Edition 2001 6251-549-2PD 9380 Preliminary Data sheet D
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9380-B21 EDDC Enhanced Deflection Controller Processor
Edition 2001 6251-549-2PD
9380
Preliminary Data sheet
Document Change Note
Date Page Changes compared previous issue
31.03.98 17.07.98 23.07.98 23.07.98 27.07.98 07.08.98 09.09.98 14.09.98 16.09.98 16.09.98 16.09.98 16.09.98 16.09.98 18.09.98 18.09.98 18.09.98 18.09.98 27.10.98 12.11.98 19.11.98 24.11.98 02.12.98 04.12.98 04.12.98 04.12.98 18.01.99 21.01.99 21.01.99 22.01.99 05.02.99 26.02.99 15.03.99 15.03.99 15.03.99 16.03.99 14,15
Version Document state corresponds silicon version block diagram changed bandwidth increased (new value MHz) Vertical component changed (not equals internal signal VBL!) configuration changed output level changed (supply voltage VDD(MC) Sequence control items changed, items added SLBLKS added control byte Detailed description item control byte Detailed description items Average beam current limit characteristics, Peak drive limit, Soft clipping Explanation items Peak dark detection border, bottom border, left border, right border KILLZIP deleted, KILLZIP function remains implemented
Description byte changed
HSWID deleted HSWMI added Positive negative polarity HSYNC allowed (int. normalization)
20.10.98 18.75 line frequency added V-blanking also programmable JMP=0 Specification V-blanking component changed MSBs control byte must instead don't care configuration changed HSAFE input voltage 31.25 specified VREFP, VREFH, VREFL internal reference voltages Input BSOIN, delay changed from lines lines Default value saturation control changed form bits NL2.NL0 Vertical sync byte control deleted Text changed because vertical noise reduction been removed Remark switching external clock mode added description changed Description Black Switch (BSO) changed VSS, SUBST total voltage differentials added Higher resolution output bit), changed LSB) Contrast setting with resolution instead Brightness setting with resolution instead NTSC/US matrix changed
Micronas
2001-05-03
9380
Preliminary Data sheet
Date
Page
Changes compared previous issue
24.03.99 29.03.99 29.03.99 30.03.99 07.04.99 12.04.99 13.04.99 19.04.99 19.04.99 19.04.99 20.04.99
output D/A: changed from +-0.5 bus: ABLTCS1, added bus: GAIN2 added, MODE changed bus: Peak drive limit, added (hidden Black stretch) Input BSOIN: hysteresis added
bus: ABLTCS1, deleted, MODE default field frequent, Tdown independent MODE, default value reg. 18.75kHz only possible with internal clock generation specification completed Hysteresis H35K, H38K adjusted PWMC data corrected case output used switch output Power-on reset thresholds added
20.04.99 default range input IBEAM changed 20.04.99 28.04.99 28.04.99 29.04.99 RDCI added switching input range Delay from outputs reduced Min. Bandwidth outputs specified Pins reference voltages VREFP, VREFL deleted
29.04.99 3,4,5,27,46 output PROTON added 29.04.99 3,4,6,30,46 output VBLO added 11.05.99 21.05.99 31.05.99 08.06.99 10.06.99 24.06.99 24.06.99 24.06.99 Application information added Nominal saturation changed Delay BG-pulse HSYNC internal clock mode changed V-blanking component corresponds with internal blanking input changed RGB/YUV1, feature added Test pins changed
Differential input RGB/YUV removed
Reset modes IIC-Registers changed, delay changed 32768
24.06.99 6,12,38,39, VREFP VREFL removed, VREFH VREFC changed 24.06.99 24.06.99 24.06.99 24.06.99 24.06.99 24.06.99 28.06.99 29.06.99 30.06.99 External capacitances quartz oscillator changed 15pF inputs bias voltages added Nominal value saturation changed outputs (E/W, D/A, VD+, VD-) changed output: black level added levels changed Text processing, diagrams black stretch soft clipping added Second paragraph changed (protection circuit) Equations Vertical compensation changed
Micronas
2001-05-03
9380
Preliminary Data sheet
Date
Page
Changes compared previous issue
30.06.99 09.07.99 09.07.99 19.07.99 16.08.99 29.09.99 29.09.99 29.09.99 26.10.99 15.11.99 18.11.99 19.11.99 19.11.99 22.11.99 22.11.99 06.12.99 06.12.99 13.12.99 17.12.99 21.01.00 26.01.00 11.02.00 11.02.00 11.02.00 10.03.00 29.03.00 29.05.00 29.05.00 29.05.00 29.05.00 29.05.00 05.07.00 05.07.00 25.08.00 18.08.00 25.08.00
Equations Horizontal compensation changed Minimum ambient temperature operating changed from position control byte must diagrams modes added control: amplitude V-parabola reduced Document state corresponds silicon version input levels HDTV added level input added High level input voltage changed 0.75*VDD(D) Second value VclampY case differential input deleted output changed open drain Tolerances black levels added (offset regulation) Tolerances supply voltages decreased bits IN1NOM IN2NOM added
moved reg. 22h, RDCI moved reg. Control item Extreme corner correction subaddress added, item moved subaddress Input leakage current inputs specified ABL: Time constants changed ABL: time constants changed exchanged output High level blanking level changed Last paragraph regarding soft start adapted Warning previous edition deleted, warning changed (now rise time supply voltages allowed Minimum value maximum output voltage changed control byte: specification V-parabola amplitude changed Document state corresponds silicon version block delay moved between blocks brightness blue stretch Min./Max. values matrices removed Min./Max. values black level stretch changed Output output HIGH value changed Circuit input changed Explanation average beam current limit added Document state corresponds silicon version Positive-going BSOIN upper threshold increased 50mV Brightness control range changed, nom. brightness removed
29.05.00 Specified H-frequency range 19kHz added
Micronas
2001-05-03
9380
Preliminary Data sheet
Date
Page
Changes compared previous issue
25.08.00 28.08.00 28.08.00 04.10.00 04.10.00 04.10.00 04.10.00 04.10.00 04.10.00 04.10.00 10.10.00 16.10.00 23.10.00 25.10.00 25.10.00 22.11.00 22.11.00 22.11.00 29.01.01 03.05.01 03.05.01 03.05.01 03.05.01 03.05.01
38.40
Nominal brightness measurement levels changed Black stretch level shift changed Foot note added Absolute maximum rating VDD(MC) Absolute maximum rating total power dissipation 1.28W Supply currents total power dissipation specified output D/A: HIGH value changed output E/W: HIGH value changed output VD+, VD-: HIGH value changed output signal amplitude changed from 1.9V nom. System overview Dig. changed schematic inserted Equations cut-off white-drive currents added Equations Vertical compensation modified Equations Horizontal compensation modified Max. input capacitance inputs specified Standby current specified Total power dissipation changed from max. 1.25W max. 1.28W Infineon logo changed Micronas BSOIN, Upper threshold decreased 25mV Output D/A, Output HIGH changed from 2.98V 3.00V Output E/W, Output changed from 0.64V 0.65V Output E/W, Output HIGH changed from 2.48V 2.50V output signal amplitude (peak-to-peak value) changed from 1.9V 1.85V
Document state
Micronas
2001-05-03
9380
Preliminary Data sheet
Data Classification Maximum Ratings Maximum ratings absolute ratings; exceeding only these values cause irreversible damage integrated circuit. Recommended Operating Conditions Under this conditions functions given circuit description fulfilled. Nominal conditions specify mean values expected over production spread proposed values interface application. stated otherwise, nominal values will apply TA=25°C nominal supply voltage Characteristics listed characteristics ensured over operating range integrated circuit.
Micronas
2001-05-03
9380
Preliminary Data sheet
Contents
General description
Features Deflection Video Block diagram. configuration description System description Functional description.
5.1.1 5.1.2 Deflection controller processing
5.5.1 5.5.2 5.5.3 5.5.4 5.5.5
Circuit description Reset modes. Frequency ranges. control
address format commands Detailed description Explanation some control items
schematic Absolute maximum ratings Recommended operating conditions Characteristics (assuming recommended operating conditions)
Application information 10.1 System overview Dig. 100Hz 10.2 System overview multisysnc deflection 10.3 Application circuit diagram Waveforms 11.1 Timing diagram H35K H38K 11.2 Black Switch-Off diagram 11.3 Power On/Off diagram 11.4 Standby mode, RESN diagram. 11.5 Function protection
Micronas
2001-05-03
9380
Preliminary Data sheet
11.6 11.7
Black Stretch diagram. Soft Clipping diagram
Package outlines
Micronas
2001-05-03
9380
Preliminary Data Sheet General description
General description
9380 highly integrated deflection controller video processor receivers with 19kHz 38kHz line frequencies. deflection component controls among others horizontal driver circuit flyback line output stage, coupled vertical saw-tooth output stage East-West raster correction circuit. adjustable output parameters controlled. Inputs HSYNC VSYNC. HSYNC signal reference internal clock system which includes the==and =control loops. processor YUV/RGB inputs input. YUV/RGB input input SVGA text/OSD with fast blanking. output stage control loops white level with halt capability vertical shrink modes. overall output adjustable delay outputs related this signal suitable scan velocity modulation circuit. supply voltages 3.3V mounted P-MQFP package with pins.
Features
Deflection
external clock needed ==PLL and==PLL chip =Standard line frequencies NTSC =18.75kHz line frequency lines/60 =Doubled line frequencies NTSC PAL, MUSE standard, standard Also suitable VGA, Macintosh (35kHz) SVGA standard (38kHz, 800*600*60Hz) =Automatic switching between 38kHz Monitor mode with digital outputs controlling analog input keep watch alignment deflection parameters =All EW-, functions =Picture width picture height compensation =Dynamic compensation (white bar) =Compensation H-phase deviation (e.g. caused white bar) =Upper/lower EW-corner correction separately adjustable =Extreme EW-corner correction (coefficient sixth order) super flat tubes =V-angle V-bow correction =Two special control items vertical zoom/shrink scroll function with absolutely correct tracking HD-output signals re-adjustment after changing vertical S-correction linearity needed =H-frequent output signal generating adjustable vertical frequent parabola constant pulse width, selectable V-blanking time adjustable =Partial overscan adjustable hide control measuring lines reduced scan modes =Self adaptation V-frequency number lines field between each possible line frequency =Selectable Black Switch-Off behaviour
Micronas
2001-05-03
9380
Preliminary Data Sheet Features
=Protection against away (X-rays protection) =Protection against missing V-deflection (CRT-protection) =D/A ouput with resolution general purpose =Digital output general purpose, controlled I2C-Bus =Selectable softstart H-output stage Video
universal YUV/RGB inputs input, YUV/RGB input with fast blanking capability fast blank input with contrast reduction capability Switchable color difference matrix PAL/SECAM, NTSC(U.S.), NTSC(Japan) HDTV Common saturation, brightness contrast control three input channels possible white level control loop Halt command white level control loop switch white level reference lines vertical shrink mode Black stretching non-standard input signals Selectable blue stretch circuit shifting white towards light blue Peak drive limiter with soft clipping, adjustable Average beam current limiter, adjustable Luminance output signal scan velocity modulation; adjustable delay from outputs
Micronas
2001-05-03
9380
Preliminary Data Sheet Block diagram
Block diagram
SWITCH VBLO HPROT VPROT PROTON
BSOIN RESN TEST FH1_2 VSYNC HSYNC
CONTROL
PROTECTION START
H-OUT
V-OUT
EW-OUT
CLEXT CLKI
HSAFE H35K H38K
PW/PH-CORR
IBEAM
AVERAGE BEAM LIMITER
CLAMP
MATRIX
BLACK STRETCH SWITCH
RGB/YUV
CLAMP
MATRIX
SATURATION CONTROL MATRIX
YUV/RGB
CLAMP
MATRIX
BRIGHTNESS CONTROL
CONTRAST CONTROL
MEASURE PULSES
VDD(A1.4) VSS(A1.4)
WHITE POINT
DELAY
VDD(D1.2) VSS(D1.2) VDD(MC) VSS(MC) SUBST
BLUE STRETCH
PEAK DRIVE LIMITER OUTPUT BUFFER
ROUT GOUT BOUT
VREFC
VREFH
VREFN
Micronas
2001-05-03
9380
Preliminary Data Sheet configuration
configuration
ROUT VDD(MC) FBL2
VSS(MC) BOUT GOUT
SWITCH
VSS(D) VDD(D)
CLKI CLEXT TEST SUBST RESN VDD(D) VSS(D) H35K H38K VSYNC
FBL1
9380
VSS(A4) VDD(A4) VREFC VREFN VBLO VREFH PROTON IBEAM BSOIN
FH1_2 VDVDD(A3) VSS(A3) VPROT HPROT HSYNC VDD(A1) VDD(A2) VSS(A2) VSS(A1) HSAFE
Micronas
2001-05-03
9380
Preliminary Data Sheet configuration
description Name
CLKI CLEXT TEST
Type
I/TTL I/TTL I/TTL
Description
Input external line locked clock Reference oscillator output, Crystal Reference oscillator input, Crystal Switching between internal external clock Switching between normal operation (TEST=L) test mode (TEST=H: pins additional test pins) Substrate pin, connected ground whenever power supply signal applied Reset input, active clock data Digital supply Digital ground Control signal output driver stage (open drain) Goes High when frequency HSYNC about 35kHz more Goes High when frequency HSYNC about 38kHz Pulse width modulated control signal output V-sync input Switching between mode mode HSYNC input (CLEXT=H: TTL; CLEXT=L: analog) Analog supply Analog ground Line flyback H-delay compensation Analog supply Analog ground Control signal output East-West raster correction Output controlled voltage Control signal output coupled V-output stage Like Analog supply Analog ground Watching external V-output stage (input V-saw-tooth from feedback resistor) Watching (input e.g. H-flyback) Watching when frequency decreased Input starting Black Switch-Off Input beam current dependent signal stabilization width, height H-phase Protection (goes High after response V-protection)
SUBST RESN VDD(D) VSS(D) H35K H38K VSYNC FH1_2 HSYNC VDD(A1) VSS(A1)
I/TTL Q/TTL Q/TTL Q/TTL I/TTL I/TTL Q/TTL
VDD(A2) VSS(A2) VDVDD(A3) VSS(A3) VPROT HPROT HSAFE BSOIN IBEAM PROTON
Micronas
2001-05-03
9380
Preliminary Data Sheet configuration
Name
VREFH VBLO VREFN VREFC VDD(A4) VSS(A4) FBL1 FBL2 VDD(MC) ROUT GOUT BOUT VSS(MC) VDD(D) VSS(D) SWITCH
Type
Q/TTL I/TTL Q/TTL
Description
Reference voltage Vertical blanking output Ground VREFH Reference current input Dark current input white level control Analog supply Luminance input signal input signal input Analog ground First input insertion First input insertion First input insertion Fast blanking input RGB1 Fast blanking input RGB2 Second input insertion Second input insertion Second input insertion Analog supply output stage output output output Blanking signal with color burst component (V-component selectable Bus) Analog ground output stage Luminance output scan velocity modulation circuit Digital supply Digital ground Disables softstart Output controlled switch (register
external clock mode used with 18.75, 33.75kHz, 35kHz 38kHz line frequency.
Micronas
2001-05-03
9380
Preliminary Data Sheet System description
System description
Functional description
5.1.1 Deflection controller
main input signals HSYNC with frequency range about 38kHz VSYNC with vertical frequencies When connecting FH1_2 with level line frequency 19kHz suitable. displaying computer signals horizontal frequencies processed. selectable Monitor mode adaptation input frequency range 31.25 38kHz done automatically. output pins (H35K H38K) controlling e.g. supply voltage line output stage indicate frequency HSYNC. When H-frequency increasing, these outputs stable until frequency HSYNC appears output (see 11.1). case decreasing H-frequency they changed immediately flag detected frequency change frequency will allowed until supply voltage H-output stage (B+) decreased. HSAFE used watch output signals control horizontal well vertical deflection stages East-West raster correction circuit. H-output signal (open drain output) compensates delays line output stage phase modulated vertical frequent remove horizontal distortions vertical raster lines (VBow, V-Angle). Time reference middle front back edge line flyback pulse. positive pulse switches line output transistor. Maximal H-shift about 2.25 µsec fH=31kHz. Picture tubes with 16:9 aspect ratio used adapting raster aspect ratio source signal. V-output saw-tooth signals controls coupled output stage disabled. Suitable blanking signals delivered East-West output signal vertical frequent parabola order, enabling extreme corner correction super flat tubes. common corner correction realised with coefficients fourth order, separately adjustable upper lower part screen. pulse width modulated horizontal frequent output signal options. vertical frequent parabolic function constant pulse width each line, selectable available. After external integration parabola used vertical dynamic focusing rsp. voltage adjustment H-offset rotation. output delivers variable signal controlled digital output available general purpose. picture width picture height compensation (PW/PH Comp) processes beam current dependent input signal IBEAM with effect outputs keep width height constant independent brightness. alignment parameter Compensation enables adjust influence input signal IBEAM horizontal phase. selectable start circuit controls energy supply H-output stage during receiver's time smooth decreasing line output transistors switching frequency down normal operating value (softstart). starts with about times line frequency converges
Micronas
2001-05-03
9380
Preliminary Data Sheet System description
within 85ms final value. high time kept constant. normal operating pulse ratio either 45/55 40/60 (selectable watch function limits increasing period max. +10%. implemented Black Switch-Off behaviour defined bits (BSO1, BSO0). When enabled signal BSOIN (e.g. supply voltage line output stage) watched. level does come defined threshold Black Swich-Off started (see 11.2). first outputs switched continuous blanking immediately vertical output signals changed about 115.120% overscan. After delay lines picture tube capacitance discharged with current some From vertical overscan rate calculated depending actual voltage BSOIN desired deflection angle. Three relations selectable I2C. After voltage BSOIN dropped down about initial value output overscan calculation stop. protection circuit watches reference saw-tooth vertical output stage. succeeds defined threshold V-deflection fails (refer 11.5) related status byte output PROTON goes High. output deactivated (H-level) immediately independent selected Black Switch-Off function. HPROT: input continuous blanking disabled operating range
VPROT:
vertical saw-tooth voltage first half V-period second half disabled
delivers composite blanking signal SCP. contains burst (Vb), H-blanking (VHBL) selectable V-blanking (control SSC). phase width H-blanking period varied I2C-Bus. timing following settings possible (default value) 1(alignment range) THBL (H-flyback time) THBL H_blanking-time TDBL (H_shift H_blanking_phase 2*H_blanking_time TVBL during V-blanking period always THBL
Micronas
2001-05-03
9380
Preliminary Data Sheet System description
BG-pulse width Delay HSYNC
internal clock: external clock:
(78-4*Internal_H-sync_phase)/ (38-4*Internal_H-sync_phase)/
Micronas
2001-05-03
9380
Preliminary Data Sheet System description
5.1.2 processing
provide accurate biasing picture tube offsets gains output stages continuously adjusted white level control loop. Leakage, white current measured each frame during vertical flyback input. position measurement lines adjustable (see page 31). reference currents white levels adjusted with parameter each output common gain parameter. Because video amplifiers part control loops, overall gain offset more adjustable this stage. proper dimensioning video amplifiers there status (CLOW), which when offset gain actuators outputs within full range. control loops switched halt mode switch measurement lines vertical shrink mode. When screen switched brightness contrast ramp soft start mode soon control loop locked. There three circuits implemented beam current limiting: -First there circuit accurate average beam current limiting. beam current measured Ibeam input limited reducing first contrast and, after half contrast reached, brightness too. parameters (limit value, gain, time constant down time constant) adjustable bus. -Second peak drive limiter circuit implemented higher frequency content video signal. reduces contrast when limit value exceeded video signals. Also parameters (limit value, time constant down time constant) adjustable bus. -Third there soft clipper very high frequency content video signal. limits video signals according diagram 11.7. Limit value slope adjustable bus. screen switched blue when video signal available. When blue stretch function activated bus, gain green output reduced amplitudes more than nominal amplitude. This shifts white towards light blue. black stretch function (switchable bus) stretches video signals with black level which higher than clamping level towards black. Therefore peak dark value video signal stored. height peak dark value determines amount stretch (diagram 11.6). screen area which peak dark detector enabled programmable bus. possible screen black borders picture (e.g. letter format) which otherwise prevent desired function black stretch. overall luminance output provided supplying circuit scan velocity modulation. delay outputs luminance output adjustable bus. proper alignment video signals current coil possible.
Micronas
5-10
2001-05-03
9380
Preliminary Data Sheet System description
Circuit description
HSYNC reference numeric PLL. This generates clock which phase locked incoming horizontal sync pulse exactly times faster than horizontal frequency. polarity external horizontal sync pulses positive (see figure below) negative. case negative polarity incoming HSYNC signal automatically inverted easier application SVGA mode.
VHSmax
VHSpp
VHSmin
Incoming signal HSYNC (internal clock)
Pulse width I2C-bus 'HSWMI'=0: 4.5µs (High level) 9.0µs (High level) Pulse width I2C-bus 'HSWMI'=1: 4.5µs (High level) 9.0µs (High level) FH1_2 High FH1_2 FH1_2 High FH1_2
(The specified pulse width depends bits INCR4.INCR0 rsp. clock frequency. above values valid INCR higher INCR values allowed pulse width decreasing proportional increasing clock frequency.) described input signal first applied converter. Conversion takes place with bits nominal frequency MHz. digital uses pass filter obtaine defined slopes further measurements (PAL/NTSC applications). addition actual high level signal well threshold value evaluated used calculate phase error between internal clock external horizontal sync pulse. means digital filtering increment gained from this. filter I2C-bus that lock-in behaviour optimal relation either mode. Moreover possible adapt nominal frequency means I2C-bus bits (INCR4.INCR0) different horizontal frequencies. additional GENMOD offers possibility frequency generator which frequency controlled INCR bits.
Micronas
5-11
2001-05-03
9380
Preliminary Data Sheet System description
Once increment been obtained, either from PI-filter I2C-bus, used operate Digital Timing Oscillator. generates saw-tooth with frequency that proportional increment. saw-tooth converted into sinusoidal clock signal means ROM's converters applied analog which multiplies frequency (for detailed explanation pinning I2C-bus description) minimizes residual jitter. this manner required line locked clock provided operate other functional parts circuit. HSYNC applied system holds momentary frequency 2040 lines following resets nominal frequency. status indicates lock state PLL. system also provides stable HS-pulse internal use. phase between this internal pulse external HSYNC adjustable bits HPHASE. shifted over range line. external clock (CLKI) provided selection (CLEXT control (SCLIIC CLEXTIIC This recommended when using 9380 with scan rate conversion system. clock frequency fHSYNC. external clock mode used with 18.75, 33.75kHz, 35kHz 38kHz line frequency. Therefore switching external clock mode only possible when INCR always allowed during operating without danger H-output stage. input signal VSYNC vertical time reference. pass window avoiding short long V-periods case distorted missing VSYNC pulses. window allows VSYNC pulse only after minimum number lines from predecessor sets artificial after maximum number lines. window size programmable I2C-bus. Values which influence shape amplitude output signals transmitted reduced binary values 9380 bus. which designed speed reasons pipe line structure calculates consideration feedback signals (e.g. IBEAM) values which exactly represent output signals. These values control after conversion external deflection raster correction circuits. firmware stored internal ROM.
Micronas
5-12
2001-05-03
9380
Preliminary Data Sheet System description
Reset modes
circuit only completely reset power-on/off (timing diagram ref. 11.3). RESN Llevel during standby operation some parts circuit affected (timing diagram ref. 11.4):
Power-On-Reset
External Reset (pin RESN=0)
Standby mode (I2C STDBY=1)
output H-protection V-protection IIC-Interface (SDA, SCL) IIC-Register 01.1C IIC-Register 1D.30h Status PONRES VREFH
High inactive inactive tristate default values default values
active active active
active active active1) ready default values affected affected inactive inactive
ready default values affected affected inactive
affected
inactive
inactive HPROT (typ. 1.5V) only read after Power-On-Reset finished
Note:
Power-On-Reset state deactivated after 32768 cycles X1/X2 oscillator clock. RESN=Low standby state deactivated after cycles clock.
Frequency ranges
15.625 15.75 18.75 kHz* 31.25 31.5 66.7 1250 1050 1125
33.75 kHz* kHz* kHz*
only with internal clock generation allowed deviation input line frequencies max. ±4.5%. number lines frame
Micronas
5-13
2001-05-03
9380
Preliminary Data Sheet System description
interlaced interlaced
(subaddr. 01/D5) number lines field selfadaptable between each specified H-frequency.
control
5.5.1 address 5.5.2 format
write:
read:
Subaddress
Data Byte
*****
Status byte
Data Byte
*****
Reading starts last write address Specification subaddress reading mode possible. Start condition Acknowledge Stop condition Acknowledge automatically address increment function implemented. After switching bits defined states.
Micronas
5-14
2001-05-03
Micronas
5.5.3 commands
9380
Control item (for deflection) Deflection control Deflection control Vertical scroll Vertical aspect Vertical shift Vertical size Vertical linearity Vertical S-correction Vertical compensation Horizontal size phase Upper corner correction Lower corner correction Extreme corner correction Horizontal compensation Horizontal shift Vertical angle Vertical compensation Vertical blanking start*) Reference pulse position*) Horizontal blanking time Horizontal blanking phase Vertical blanking end*) Guard band Vertical sync control Min. lines field Max. lines field control control control Internal H-sync phase
Subaddr.
Allowed range -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -64.+63 -128.+127 -128.+127 -32.+31 0.+15 0.+15 0.+63 -32.+31 0.+7 0.+31 0.+255 0.+255 0.+31 -128.+127
Effective range -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -128.+127 -64.+63 -128.+127 -128.+127 -32.+31 0.+15 0.+15 0.+63 -32.+31 0.+7 0.+31 0.+255 0.+255 6.+21 -96.+119
below below below below below below
Default Default Disabled Resoluvalue tion value disabled 1/CLL line line H-flyback 4/CLL 4/CLL line half line lines lines below 4/CLL
5-15
2001-05-03
Preliminary Data Sheet
System description
Micronas
9380
Control item (for RGB) control control control Video input mode Brightness Contrast Saturation Average beam current limit Average beam current limit characteristics Peak drive limit control Peak dark detection border Peak dark detection bottom border Peak dark detection left border Peak dark detection right border White control White control White control
Subaddr.
Allowed range -128.+127 -128.+127 -32.+31 -128.+127 0.+255 0.+255 0.+15 0.+15 -32.+31 -32.+31 -32.+31 -128.+127
Effective range -128.+127 -128.+127 -32.+31 -128.+127 0.+255 0.+255 0.+15 0.+15 -32.+31 -32.+31 -32.+31 -128.+127
Default value
Resolution lines lines pixels pixels
below below below below below below below
5-16
2001-05-03
5.5.5 Explanation some control items
Preliminary Data Sheet
System description
9380
Preliminary Data Sheet System description
power most data zero default otherwise specified) before transferring individual values IIC-bus. Allowed values effective range limited, e.g. Internal H-sync phase =127 limited 119. There bits (BSE, GBE) deflection control byte disabling some control items. these bits "0", value corresponding control item will ignored replaced value "default value disabled" table above.
Micronas
5-17
2001-05-03
9380
Preliminary Data Sheet System description
5.5.4 Detailed description Deflection control byte includes following bits:
VOFF STDBY SCLIIC RIBM CLEXTIIC HDDC
VOFF:
Vertical normal vertical output control items vertical saw-tooth switched off, vertical protection disabled Stand-by mode normal operation stand-by mode (all internal clocks disabled) Monitor mode (GENMOD must line frequency must defined INCR4.0 (register automatic detection line frequency Select clock select clock CLEXT select clock CLEXTIIC Input range IBEAM 0.2.7V 1.8.2.7V
STDBY:
MON:
SCLIIC:
RIBM:
CLEXTIIC:External clock selected (only effective SCLIIC internal clock selected external clock selected HDDC: duty cycle duty cycle output duty cycle output enable line switched disabled, that H-level) BSO1 BSO0 switch-off possible. line switched enabled) Default value depends SSD=Low: SSD=High:
HDE:
Micronas
5-18
2001-05-03
9380
Preliminary Data Sheet System description
Deflection control byte includes following bits:
BSO1 BSO0 NCLP
BSO1. BSO0
Black Switch-Off behaviour Black Switch-Off Black Switch-Off mode (see section 11.2) Black Switch-Off mode (see section 11.2) Black Switch-Off mode (see section 11.2) self adaptation self adaptation self adaptation clipping vertical east/west drive signals Clipping vertical east/west drive signals vertical zoom mode (vertical aspect reduce power consumption clipping vertical zoom mode (vertical aspect Guard band enable control item guard band disabled control item guard band enabled Vertical dynamic compensation influence beam current input IBEAM vertical saw-tooth static correction) influence beam current input IBEAM vertical saw-tooth dynamic correction)
NSA:
NCLP:
GBE:
VDC:
JMP:
Jump vertical drive overscan position vertical shrink mode complete reduction vertical drive shrink mode (vertical aspect reduction vertical drive shrink mode (vertical aspect during reference pulse lines Blanking select enable control items blanking times disabled control items blanking times enabled
BSE:
Micronas
5-19
2001-05-03
9380
Preliminary Data Sheet System description
Vertical sync control byte includes following bits:
SSC:
Sandcastle without output with component output without component interlace interlace depends source interlace
control byte includes following bits:
PWMC5 PWMC4 PWMC3 PWMC2 PWMC1 PWMC0 PWMS1 PWMS0
PWMS1. PWMS0: select same duty cycle each line selected (adjustable PWMC) positive V-parabola after external integration available (amplitude adjustable PWMC) negative V-parabola after external integration available (amplitude adjustable PWMC) PWMC5. PWMC0: control These bits control either duty cycle parabola amplitude depending PWMS0 according following table PWMS0 also PWMS1 defines duty cycle):
PWMC5.PWMC0 100000 110000 000000 010000 011111
Duty cycle (PWMS0 PWMS1/108 (32+PWMS1)/108 (64+PWMS1)/108 (96+PWMS1)/108
Amplitude V-parabola (ext. integration, PWMS0
0.46 (VOH -VOL) 0.58 (VOH -VOL) 0.69 (VOH -VOL) 0.81 (VOH -VOL) 0.91 (VOH -VOL)
VOH: output High level, VOL: output level
output used switching output when PWMS0 PWMC 100000 PWMS1 output Low. PWMC 011111 output continously High.
Micronas
5-20
2001-05-03
9380
Preliminary Data Sheet System description
control byte includes following bits:
INCR4 INCR3 INCR2 INCR1 INCR0
-INCR4.0:
Nominal output frequency INCR=INT((FH*55296)/FQ-64.625) (for typical values table below) specified range:6INCR21 (FQ=24.576MHz)
Application
(50Hz) NTSC (60Hz) (60Hz) (100Hz) NTSC (120Hz) MUSE Macintosh (640*480*67Hz) SVGA (800*600*60Hz)
FH[Hz]
15625 15750 18750 31250 31500 32400 33750 35000 38000
INCR
FH1_2
High High High High High High
Internal default value:
INCR INCR INCR Default value read bus: INCR
FH1_2 High FH1_2 Low, FH1_2 Low, High
control byte includes following bits:
GENMOD NOISY HSWMI TC_3RD
-GENMOD: Clock generator mode normal mode generator mode (fixed frequency output, controlled INCR.) -VCR: filter optimized mode mode
Micronas
5-21
2001-05-03
9380
Preliminary Data Sheet System description
NOISYVCR:Handling noisy input signals mode normal handling improved handling Note: this don't care mode) HSWMI: Minimum width HSYNC 1.5µs 0.8µs Third time constant slow time constant fast time constant Note: this don't care mode)
TC_3RD:
Warnings/Notes: change INCR causes changes generated clock frequency more than specified 4.5%. Switching from mode Generator mode (GENMOD) with constant INCR values does result exceeding specified frequency deviation range. H-level output signal starts immediately after power this case starting horizontal frequency 31.25kHz FH1_2 High). Starting with other frequencies requires L-level that INCR changed before enabling with HDE=1. When High FH1_2 horizontal frequency fixed 18.75 (INCR cannot changed bus. Other H-frequencies range 15.6 possible when Low. timing built-in soft start circuit (starting frequency, period, ending frequency) depends INCR. starting frequency output approx. 1.71* frequency stops defined INCR (see table previous page) total soft start takes about frequency HSYNC input signal outside lock range (+/- 4.5%), that means cannot lock, timing soft start change max. 4.5% unlocked PLL.
Micronas
5-22
2001-05-03
9380
Preliminary Data Sheet System description
control byte includes following bits:
IN2NOM IN1NOM CONTB VINP2E FBL2E VINP1E FBL1E
IN2NOM: Nominal saturation contrast video input variable saturation contrast video input (defined reg. fixed saturation contrast video input (nominal values) IN1NOM: Nominal saturation contrast video input variable saturation contrast video input (defined reg. fixed saturation contrast video input (nominal values) CONTB: Continuous blanking Blanking disable horizontal vertical blanking enabled horizontal vertical blanking disabled
VINP2E, FBLE2, VINP1E, FBL1E: Selection input signals (see table below)
VINP2E FBL2E VINP1E FBL1E
selected input signals YUV/RGB RGB/YUV when FBL1=High else YUV/RGB RGB/YUV RGB2 when FBL2=High else YUV/RGB RGB2 when FBL2=High else RGB/YUV when FBL1=High else YUV/RGB RGB2 when FBL2=High else RGB/YUV
Micronas
5-23
2001-05-03
9380
Preliminary Data Sheet System description
control byte includes following bits:
BLUES SLBLKS BLCKS CTLPD WHITD CATH2 CATH1 CATH0
BLUES: Blue stretch SLBLKS: Slow Black stretch short time constant long time constant BLCKS: Black stretch CTLPD: Control loop disable white level control loop active white level control loop inactive (halt mode) WHITD: White level control loop disable white level control loop active white level control loop inactive (halt mode) CATH2. CATH0: Cathode drive level (see 5.5.5 Explanation some control items) 100: minmum level 011: +100% (maximum level)
control byte includes following bits:
BLUEB FBL2L COR1 COR0 DELOFF SVMOFF DEL1 DEL0
BLUEB: Blue background FBL2L: FBL2 input switching level high switching levels switching levels
Micronas
5-24
2001-05-03
9380
Preliminary Data Sheet System description
COR1.0: Contrast reduction channel FBL2 DELOFF:Delay from output output delay (see below) delay (basic delay 15ns) SVMOFF:SVM output active signal output) (SVM output high) DEL1.0: Delay from output output delay 25ns delay 55ns
Video input mode includes following bits:
RGBEN1 MAT11 MAT10 RGBEN0 MAT01 MAT00
RGBEN1:RGB/YUV input input input MAT11.0:RGB/YUV input, input standard PAL/SECAM NTSC/Jap. NTSC/US HDTV RGBEN0:YUV/RGB input input input MAT01.0:YUV/RGB input, input standard PAL/SECAM NTSC/Jap. NTSC/US HDTV
Micronas
5-25
2001-05-03
9380
Preliminary Data Sheet System description
YLL:
input level NTSC matrices (black-to-white value) (black-to-white value)
Average beam current limit characteristics includes following bits:
GAIN2 GAIN1 GAIN0 TUP1 TUP0 TDOWN1 TDOWN0 MODE
GAIN2.0:
Gain adjustment 100: 0.25 101: 0.375 110: (default value) 111: 0.625 000: 0.875 001: 1.125 010: 011: Time constant increasing contrast/brightness (current contrast lower than adjusted contrast ABLIM exceeded) approximately 0.25 second approximately second approximately second approximately second
TUP1.0:
TDOWN1.0: Time constant decreasing contrast/brightness when ABLIM exceeded approximately approximately approximately approximately MODE: Updating contrast/brightness with field frequency with line frequency
Micronas
5-26
2001-05-03
9380
Preliminary Data Sheet System description
Peak drive limit register includes following bits:
PDLIM3 PDLIM2 PDLIM1 PDLIM0 PDLT1 PDLT0 PDLD
PDLIM3.0: Peak drive limit 1000: minimum level 0000: default level 0111: maximum level PDLT1.0: Peak drive limiter time constant faster fast normal (default) slow Peak drive limiter disable peak drive limiter enabled peak drive limiter disabled
PDLD:
control byte register includes following bits:
RDCI SCLEV1 SCLEV0 SCSLP1 SCSLP0
Setting output SWITCH output SWITCH L-level output SWITCH H-level Input range 0.2.7V 1.8.2.7V
RDCI:
SCLEV1.0: Soft clip level relative peak drive limit 100% 105% 110% (default) infinite SCSLP1.0: Soft clipping slope 0.125 0.375 0.625 0.875
Micronas
5-27
2001-05-03
9380
Preliminary Data Sheet System description
Status byte includes following bits:
HPON VPON H38K H35K CLOW PONRES
HPON:
H-protection normal operation line output stage upper threshold input HPROT been exceeded V-protection normal operation vertical output stage incorrect signal input VPROT been detected Coincidence H-coincidence detected H-coincidence detected line frequency line frequency detected line frequency detected line frequency line frequency detected line frequency detected Control loop window control loops inside window control loop window Power Reset after master read status byte after each detected reset
VPON:
CON:
H38K:
H35K:
CLOW:
PONRES:
Also output PROTON (pin goes High HPON=1 VPON=1.
Note!
PONRES reset after this byte been read.
Micronas
5-28
2001-05-03
9380
Preliminary Data Sheet System description
5.5.5 Explanation some control items
Vertical aspect, Vertical scroll: special control items implemented user adjust vertical height (control item: Vertical aspect) vertical position (Vertical scroll). These items stored every display mode individual height position desired. Changing these parameters automatically influences outputs VD+, VD-, E/W, such that absolutely raster distortion happens. There need user re-adjust geometry parameter. difference function Vertical size Vertical aspect following: Varying Vertical size causes linear stretching saw-tooth eliminate tolerance linear components (e.g. feedback resistor). adjusting Vertical aspect takes into consideration that more less picture height needs very more less S-correction linear relation). Therefore Vertical aspect should used changing aspect ratio (e.g. 16:9 source CRT) individual picture height desired various graphic standards. Vertical aspect -128(minimum value) results vertical reduction 37.5%. Vertical size, Vertical shift: purpose these control parameters alignment factory service adapt output signals VD+, picture tube eliminate tolerances hardware deflection yoke. Only these parameters required display modes.
Vertical linearity, Changing vertical linearity S-correction influence Vertical S-correction: E/W-geometry. That means, straight vertical lines remain straight. output signals automatically changed re-adjustment related control items needed. This feature saves time adjustment called 'smart' mode (4:3 source 16:9 CRT) Guard band: This control item useful optimizing self adaptation. Video signals with different number lines consecutive fields (e.g. search mode) must start procedure self adaptation. switching between different standards change slope vertical saw-tooth getting always same amplitude (self adaptation). avoid problems with flicker free systems which have alternating number lines field average value four consecutive fields calculated. deviation these average values (e.g. 312.5 lines half lines) less equals Guard band, adaptation takes place. When exceeds Guard band, vertical slope will changed. This item controls influence beam current dependent input signal IBEAM outputs according following equation:
Vertical_EHT_compensation VDPP IBEAM 0.59 RIBM=0) 1536 Vertical_EHT_compensation VDPP IBEAM 0.59 RIBM=1)
Vertical comp.:
VVDPP variation VD-peak-to-peak voltage
Micronas
5-29
2001-05-03
9380
Preliminary Data Sheet System description VIBEAM variation IBEAM input voltage
Vertical compensation -128 outputs independent input signal IBEAM.
Horizontal comp.:This item controls influence input signal IBEAM output according following equation:
Horizontal_EHT_compensation IBEAM 2.14 RIBM=0) Horizontal_EHT_compensation IBEAM 2.14 RIBM=1)
variation output voltage VIBEAM variation IBEAM input voltage
Horizontal compensation -128 output independent input signal IBEAM. comp.: Deviation horizontal phase caused high beam current (e.g.white bar) eliminated this control item. beam current dependent input signal IBEAM multiplied compensation. Additional control items Vertical angle, Vertical Horizontal shift, this product influences horizontal phase output according following equation:
AFC_EHT_compensation IBEAM -192 AFC_EHT_compensation IBEAM RIBM=0) RIBM=1)
variation horizontal phase output (positive values: shift left, negatives values: shift right) VIBEAM variation IBEAM input voltage (units: Volt)
Micronas
5-30
2001-05-03
9380
Preliminary Data Sheet System description
Vertical blanking start (VBS), ref. pulse pos. (RPP), Vertical blanking (VBE): control item defines position three reference pulses ref. pulse (odd field) Green ref. pulse (odd field) Blue ref. pulse (odd filed) (def. value (def. value (def. value
(Blanking Select Enable) control item replaced default value (=4). ref. pulses generated line field rsp. line even field (see diagram below). defines start well internal vertical blanking pulse output signal VBLO. internal signal defined VBE. This also applies VBLO with exception. There least line between cutoff/white level measurement line blue VBLO. vertical component signal always identical with internal vertical blanking pulse VBL. Both well VBLO synchronized with leading edge HSYNC. always starts stops beginning line never center. Therefore width line more even field than field. vertical drive signals VD+, clipped zoom mode (vertical aspect bottom screen vertical blanking pulse extended blank lines this area without additional programming. Description when JMP= Start lines before first complete line next field (def. value line (VBE (odd field) width (VBS lines (odd field)(def. value After power control also Therefore lines (odd field) will blanked before programming line (RPP (odd field) width (VBS lines (odd field) number lines between last ref. pulse defined range (VBE (VBE (minimum value) starts (point fig. below) 0.0.5 line (new field) 0.5.1 line (new even field) prior vertical flyback.
Micronas
5-31
2001-05-03
9380
Preliminary Data Sheet System description
HSYNC
VSYNC
line
VDstart even field start field
field
(default: BSE=0, VBS=0, VBE=0)
lines
lines
even field
lines
field
(BSE=0, VBS=2, VBE=0) (BSE=1, RPP=1, VBS=0,
even field
lines
field
even field
Internal vertical blanking pulse when number lines field constant
Description when JMP= Start lines before first complete line next field (def. value line (VBE (odd field) width (VBS lines (odd field)(def. value line (RPP (odd field) width (VBS lines (odd field) Note! number lines between last ref. pulse defined range (VBE (VBE
Micronas
5-32
2001-05-03
9380
Preliminary Data Sheet System description
HSYNC
VSYNC
line
VDstart even field start field
lines field
(default: BSE=0, VBS=0)
lines
even field
lines field even field
(BSE=0, VBS=2)
lines field
(BSE=0, VBS=0, VBE=1)
even field
Internal vertical blanking pulse when number lines field constant
Micronas
5-33
2001-05-03
9380
Preliminary Data Sheet System description
Min. lines field: defines minimum number lines field vertical synchronization. standard inputs VSYNC HSYNC less lines field than defined Min. lines field synchronization possible. relationship between Min. lines field minimum number lines given following table: Min. lines field minimum number lines field
Max. lines field: defines maximum number lines field vertical synchronization. standard inputs VSYNC HSYNC more lines field than defined Max. lines field synchronization possible. relationship between Max. lines field maximum number lines given following table: Max. lines maximum number field lines field
Average beam current limit: Brightness contrast reduced when average beam current limit level exceeded. beam current measured IBEAM. High voltage this input indicates beam current, voltage high beam current. limit range -128 complies voltage IBEAM 0.84V RIBM 2.63 2.08V RIBM
Micronas
5-34
2001-05-03
9380
Preliminary Data Sheet System description
Peak dark detection (PDD) border, bottom border, left border, right border: These four control items define picture area insides peak dark detector enabled. peak dark detector storing lowest level luminance signal. this value higher than clamping level luminance signal stretched towards clamping level (Black stretch function). Those parts picture with luminance signal less than nominal amplitude getting more dark. possible with these four control items screen black borders picture (e.g. letter format) which otherwise prevent desired function black stretch. following figure table show their definitions:
line
line=0
border [7:0]
peak dark detection black stretch enabled
bottom border [7:0] vertical horizontal blanking left border [3:0] right border [3:0] pixel=863
last line field pixel=0
pixel
border Width Resolution Range Default value (0.255) lines/bit line 0.510 (line
bottom border (0.255) lines/bit line 0.1020 (line 284)
left border (0.15) pixels/bit pixel 64.304 (pixel 192)
right border (0.15) pixels/bit pixel 576.816 (pixel 704)
Micronas
5-35
2001-05-03
9380
Preliminary Data Sheet System description
White control white control white control CATH[2:0]: These four control items define nominal values cut-off whitedrive currents during measurement lines. They calculated with following equations: Icut-off 0.00325 (White control RDCI Icut-off 0.00108 (White control RDCI Iwhite-drive Icut-off (CATH[2:0] White control White control register (range -32.+31) RDCI: CATH[2:0]: Resulting resistor ground input Cathode drive level (range -4.+3) register control RDCI=0) RDCI=1)
Micronas
5-36
2001-05-03
Micronas
Mode Description Characteristics Notes Vertical Vertical scroll aspect WHITD normal mode ref. pulse position line (odd field) mode after power (for source, Letterbox) V-blanking line (odd field) guard band lines with default settings normal mode ref. pulse position line (RPP (for source, Letterbox) .(RPP (odd field) with user defined settings V-blanking line (RPP (odd field) guard band Guard band/2 [lines] reference pulse position adjustable, guard band adjustable SVGA mode ref. pulse position line (odd field) Vertical scroll/Vertical aspect user defined V-position/Vwith user defined V-posi- V-blanking line (odd field) tion/V-size size, guard band lines WHITD disables white level ref. pulses shrink mode (for 16:9 source) with default settings ref. pulse position line (odd field) Vertical aspect V-blanking line (odd field) causes V-reduction 75%, guard band lines causes V-shrink incl. flyback ref. pulse positon adjust., causes V-shrink excl. flyback, WHITD disables white level ref. pulses guard band adjustable variable variable
Most important V-Deflection modes
9380
5-37
2001-05-03
shrink mode ref. pulse position line (RPP (for 16:9 source) .(RPP (odd field) with user defined settings V-blanking line (RPP (odd) start reduced V-ramp line (RPP (odd) guard band Guard band/2 [lines]
Preliminary Data Sheet
System description
Micronas
Most important V-Deflection modes 16:9
9380
Mode
Description normal mode (for 16:9 source) with default settings
Characteristics
Notes
Vertical Vertical scroll aspect
WHITD
ref. pulse position line (odd field) mode after power V-blanking line (odd field) guard band lines reference pulse position adjustable, guard band adjustable Vertical aspect controls zoom factor, clipping VD+, VD-, when NCLP above, Vertical scroll additionally used adjustment vertical position
normal mode ref. pulse position line (RPP (for 16:9 source) .(RPP (odd field) with user defined settings V-blanking line (RPP (odd field) guard band Guard band/2 [lines] zoom mode ref. pulse position line (odd field) (for source, Letterbox) V-blanking line (odd field) zoom factor Vertical aspect/2 guard band lines scroll mode (for source, Letterbox with subtitles) shrink mode (for sources) with default settings ref. pulse position line (odd field) V-blanking line (odd field) zoom factor Vertical aspect/2 guard band lines
5-38
2001-05-03
variable
ref. pulse position line (odd field) Vertical aspect V-blanking line (odd field) causes V-reduction 66%, guard band =1.5 lines causes V-shrink incl. flyback ref. pulse positon adjust., causes V-shrink excl. flyback, WHITD disables white level ref. pulses guard band adjustable
shrink mode ref. pulse position line (RPP (for sources) .(RPP (odd field) with user defined settings V-blanking line (RPP (odd) start reduced V-ramp line (RPP (odd) guard band Guard band/2 [lines] shrink mode (for 16:9 sources) with default settings
Preliminary Data Sheet
System description
ref. pulse position line (odd field) vertical aspect -102 V-blanking line (odd field) causes V-reduction 50%, guard band lines causes V-shrink incl. flyback
-102
9380
Preliminary Data Sheet schematic
schematic
ROUT, GOUT, BOUT
schematic
remark bipolar output stage, supply voltage: VDD(MC)
protection
protection
bipolar output stage, supply voltage: VDD(MC)
protection
open drain output
Micronas
6-39
2001-05-03
9380
Preliminary Data Sheet schematic
schematic
protection
remark crystal oscillator (X1: input, output)
protection
analog output
CLKI, CLEXT, TEST, RESN, SCL, SDA, H35K, H38K, PWM, VSYNC, FH1_2, HSYNC, PHI2, PROTON, VBLO, FBL1, FBL2, SWITCH
protection
digital input/ output
Micronas
6-40
2001-05-03
9380
Preliminary Data Sheet schematic
E/W, D/A, VD+, VD-, VPROT, HPROT, HSAFE, BSOIN, IBEAM, VREFH, VREFN, VREFC, DCI, Y/R0, U/G0, V/B0, Y/R1, U/G1, V/B1,
schematic
protection protection
remark analog input/ output
Micronas
6-41
2001-05-03
9380
Preliminary Data Sheet Absolute maximum ratings
Absolute maximum ratings
Parameter
Operating temperature Storage temperature Junction temperature Soldering temperature Input voltage Input voltage Output voltage Supply voltages Supply voltage Supply total voltage difference VSS, SUBST total voltage difference Total power dissipation Latch-up protection
Symbol
Unit
Remark
VSS-0.3V VSS-0.3V VSS-0.3V VDD(D) VDD(A1.4) VDD(MC) -0.3 -0.3 -0.25 -0.25
VDD+0.3V 5.5V VDD+0.3V 0.25 0.25
valid SDA, SCL, CLKI, SDA, SCL, CLKI,
between VDD(D), VDD(A1.4) between SUBST, VSS(MC), VSS(D), VSS(A1.4)
1.28 -100
inputs/outputs
Absolute Maximum Ratings those values beyond which damage device occur. Functional operation under these conditions other condition beyond those indicated operational sections this specification implied.
Micronas
7-42
2001-05-03
9380
Preliminary Data Sheet Recommended operating conditions
Recommended operating conditions
Symbol
VDD(D) VDD(A1.4) VDD(MC)
Parameter
Supply voltages Supply voltage Ambient temperature
3.45
Unit
Remark
sequence rise time 3.3V supply voltage allowed power
pins well SUBST have connected ground when applying voltage.
Inputs: VSYNC, RESN, TEST, FH1_2, CLEXT,
High-level input voltage Low-level input voltage 2.0V
Inputs: CLKI (CLEXT=High)
High-level input voltage Low-level input voltage 2.0V
Input VPROT
Threshold Threshold
Input HPROT
Threshold Threshold 2.65 2.75
Input BSOIN
Upper threshold (negative-going) Upper threshold (positive-going) Lower threshold VTHn VTHp 2.60 2.70 2.65*) 2.75*) 2.70 2.80 11.2
comparator hysteresis typ. 100mV. Input HSAFE
input voltage Full range input voltage Input voltage 31.25 Input voltage V31.25k V38k 1.225 1.24 1.26 V31.25k related V31.25k!
Micronas
8-43
2001-05-03
9380
Preliminary Data Sheet Recommended operating conditions
Parameter
Input voltage when watching HSAFE disabled
Symbol
Unit
Remark
Input IBEAM
input voltage Full range input voltage control RIBM=0 control RIBM=1 RIBM=0 RIBM=1
Reference Voltage Pins
VREFH voltage VREFN voltage VREFC resistor VREFN 1.568 1.632 tolerance tolerance
Input
Low-level input voltage High-level input voltage
2.0V
Input HSYNC (CLEXT=Low)
Input voltage range Input voltage level Input voltage High level Pulse width (HSWMI=0) VHSpp VHSmin Pulse width (HSWMI=1) FH1_2 High FH1_2 FH1_2 High FH1_2
VHSmax
High level allowed, INCR
Input HSYNC (CLEXT=High)
Low-level input voltage High-level input voltage Setup time Hold time 2.0V referred rising edge CLKI referred rising edge CLKI
Micronas
8-44
2001-05-03
9380
Preliminary Data Sheet Recommended operating conditions
Parameter Input VSYNC
Pulse width high Pulse width high Pulse width high
Symbol
Unit
Remark
1.5/fH
100/fH 100/fH 100/fH
FH1_2=1, NI=0 FH1_2=0, NI=0 NI=1
Input CLKI (external clock mode, CLEXT=high)
Input frequency
Quartz Oscillator Input Output
Crystal frequency 24.576 fundamental crystal type, e.g. Saronix 9922 00282
Crystal resonant impedance External capacitance
Inputs
input voltage (black-to-white value) VP-P 1.05 only input HDTV matrix HDTV matrix HDTV matrix
input voltage (peak-to-peak value) VP-P input voltage (peak-to-peak value) VP-P input current between clamping Input capacitance Maximum input current during clamping Internal bias during clamping Yinput Ii-clamp VclampY
1.33 1.05
1.05 1.05
Internal bias during clamping VclampUV inputs
Inputs (RGB2, RGB/YUV1 RGBEN1=1, YUV/RGB0 RGBEN0=1)
Input voltage (black-to-white value) input current between clamping Input capacitance VP-P
Micronas
8-45
2001-05-03
9380
Preliminary Data Sheet Recommended operating conditions
Parameter
Maximum input current during clamping Internal bias during clamping Difference between black level internal external signals outputs Delay difference three channels
Symbol
Ii-clamp Vclamp
Unit
Remark
Fast Blanking Input FBL1 (RGB/YUV
Input voltage data insertion Input voltage data insertion Maximum input voltage Vi-n Vi-y Vi-max MHz,
Difference between transit times signal switching signal insertion Suppression internal video signals (insertion) external video signals insertion)
Fast Blanking/Contrast Reduction Input FBL2 (RGB2)
Maximum input voltage Vi-max MHz,
Difference between transit times signal switching signal insertion Suppression internal video signals (insertion) external video signals insertion)
Fast Blanking (Control COR1.COR0
Input voltage data insertion Input voltage data insertion Vi-n Vi-y
Fast Blanking Contrast Reduction (Control COR1.COR0 01.11)
Input voltage contrast reduction internal signals Input voltage contrast reduction internal signals Contrast reduction (control COR1.COR0) Input voltage data insertion Vi-n Vicr-n Vicr-y FBL2L FBL2L FBL2L FBL2L FBL2L FBL2L
Micronas
8-46
2001-05-03
9380
Preliminary Data Sheet Recommended operating conditions
Parameter
Input voltage data insertion
Symbol
Vi-y
Unit
Remark
FBL2L FBL2L
Dark current input white level control
input voltage Full range input voltage Maximum input current Ii-DCImax Vi-DCI control RDCI=0 control RDCI=1
Input matrices PAL/SECAM mode
matrix coefficients: R=Y-V B=Y-U 0.19 0.51
NTSC/Jap mode
matrix coefficients: JurU JvrV JugU JvgV JubU
0.068 -=1.38 0.15 0.46
NTSC/US mode
matrix coefficients: AurU AvrV AugU AvgV AubU AvbV
0.12 -=1.32 0.25 0.42 -=1.08 0.035
HDTV mode (according SMPTE Standard 274M EIA-770.3-A)
matrix coefficients: HvrV HugU HvgV HubU
1.575 -=0.187 -=0.468 1.856
0.539 0.635
Internal matrices
PAL/SECAM mode
Internal colour difference matrices
PAL/SECAM mode
Micronas
8-47
2001-05-03
9380
Preliminary Data Sheet Recommended operating conditions
Parameter
Symbol
Unit
Remark
Saturation control (control B0.B5; subaddress 25h)
Saturation control range Nominal saturation B7.B2 110001 steps
Contrast control (control B7.B0; subaddress 24h)
Contrast control range Nominal contrast B7.B0 00000000 Tracking between three channels over control range steps
Brightness control (control B7.B0; subaddress 23h)
Brightness control range 0.75 steps
Black level stretch (control BLCKS; subaddress 20h)
Maximum black level shift Level shift 100% peak white Level shift peak white Level shift peak white
Peak drive limit (control byte peak drive limit, bits B7.B0; PDD) Peak detector
Peak detector level output nominal white drive relative off) bus: peak drive limit B7.B4 minimum value (range maximum value (range
Soft clipper
Starting level (relative peak detektors level) bus: peak drive limit (soft clipper off)
infinite
Micronas
8-48
2001-05-03
9380
Preliminary Data Sheet Recommended operating conditions
Parameter
Slope bus: peak drive limit B1,B0
Symbol
Unit
Remark
0.125 0.375 0.625 0.875
Blue stretch (control BLUES; subaddress 20h)
Decrease small signal gain green nominal input amplitudes nominal settings contrast brightness Percentage nominal input voltage which decrease gain begins (nominal settings contrast brightness)
(all values referred min(VIH) max(VIL))
clock frequency High-level input voltage Low-level input voltage Load capacitance Rise times SCL, Fall times SCL, Set-up time DATA Hold time DATA Spike duration inputs Fast-mode (fSCL kHz) fSCL tSU;DAT tHD;DAT 20+0.1* Cb/pF*) 20+0.1* Cb/pF*) 0.75* VDD(D) 5.25 300*)
Micronas
8-49
2001-05-03
9380
Preliminary Data Sheet Characteristics (assuming recommended operating conditions)
Characteristics (assuming recommended operating conditions)
Symbol
Parameter
Average supply current VDD(D) +VDD(A1.4) Average supply current VDD(MC) Total power dissipation Standby supply current VDD(D) +VDD(A1.4)
1.28
Unit
Remark
DEL1.0 (maximum delay)
standby mode VDD(MC)
Inputs CLKI, VSYNC, RESN, TEST, FH1_2, CLEXT,
Input leakage current |Ileak|
Input
Input leakage current |Ileak|
Input HSYNC
Input leakage current |Ileak|
Analog Inputs HPROT, VPROT, HSAFE, BSOIN, IBEAM, FBL1, FBL2
Input leakage current |Ileak|
Analog Inputs Y/R0, U/G0, V/B0, R/Y1, G/U1, B/V1,
Input leakage current |Ileak|
Input/Output
output level
Inputs SDA/SCL
Hysteresis Schmitt trigger inputs Input leakage current Vhys |Ileak|
Output Pins SWITCH, VBLO
Output level Output High level
Output PROTON
Output level HPON=0 VPON=0) Output High level HPON=1 VPON=1)
Micronas
9-50
2001-05-03
9380
Preliminary Data Sheet Characteristics (assuming recommended operating conditions)
Parameter Output
Output level Output High level Period Resolution
Symbol
Unit
Remark
TPWM
TH/108 TH/864
hor. period PWMS0=0 (subaddress PWMS0=1
Output
Output level Output BLanking level
VOHBL
VDD(MC) VDD(MC) VDD(MC) -0.6V +0.3V VDD(MC) -1.3V VDD(MC)
Output High level
Output
Resolution Output Output HIGH Load Capacitance Output Load Offset Error Gain Error 0.20 3.00 kOhm
Output
resolution output output HIGH Load capacitance Output load Zero error 0.65 2.50 kOhm output voltage 1.6V,*)
linear range: 100.900 input data input data
Micronas
9-51
2001-05-03
9380
Preliminary Data Sheet Characteristics (assuming recommended operating conditions)
Parameter
Gain error input range 100.900
Symbol
-0.2% -0.1%
0.2% 0.1%
Unit
Remark
Output VD+, VDDAC resolution output (VD-) output HIGH (VD-) output (VD-) (VD+) output HIGH (VD-) (VD+) Load capacitance Output load Zero error Gain error input range 1500.15000 -0.5% monotonous 0.5% 0.62 -1.90 1,96 kOhm (VD-)-(VD+)=0V, guaranteed design
linear range: 1500.15000 input data 1500 input data 15000 input data 1500 input data 15000
Reference Output VREFH
Output voltage 1.568 1.632 tolerance +-2%
Open Drain Output
Output level Maximum Voltage
Output H35K
Output level Output High level Positive-going threshold fHSYNC Negative-going threshold fHSYNC Hysteresis
fTH1 fTH2 fTH1 fTH2
33.9 33.3
11.1 11.1
Micronas
9-52
2001-05-03
9380
Preliminary Data Sheet Characteristics (assuming recommended operating conditions)
Parameter
Delay from positive-going threshold fHSYNC output
Symbol
Unit
Remark
int(27/12 fH0[kHz] -64))
Delay from negative-going threshold fHSYNC output
11.1
Output H38K
Output level Output High level Positive-going threshold fHSYNC Negative-going threshold fHSYNC Hysteresis Delay from positive-going threshold fHSYNC output
fTH3 fTH4 fTH3 fTH4
36.9 36.4
11.1 11.1
int(27/12 fH0[kHz] -64)) 11.1
Delay from negative-going threshold fHSYNC output
Output
Differential output resistance Maximum output current Minimum output voltage Maximum output voltage Output signal amplitude (peak-topeak value) Vo-min Vo-max Vo(p-p) VDD(MC) -1.3
nominal luminance input signal, nominal contrast white-point control
Maximum output signal amplitude (peak-to-peak value) Nominal black level voltage Control range black current stabilisation Blanking level Leakage measurement level measurement level White point measurement level
Vo(p-p)max
-0.4 -0.05 0.25 0.36
difference with nominal black level nominal contrast white point nominal brightness
Micronas
9-53
2001-05-03
9380
Preliminary Data Sheet Characteristics (assuming recommended operating conditions)
Parameter
Variation black level with temperature1) Gain range white point control loop Relative variation black level between inputs during variation Supply voltage (+-10%)1) Saturation dB)1) Contrast dB)1) Brightness (+-0.5V)1) Temperature (range °C)1) Signal-to-noise ratio output signal Bandwidth output signals inputs: Delay (DELOFF Maximum delay (DELOFF DEL1 DEL0
Symbol
Unit
mV/K
Remark
nominal controls nom. contrast white point nom. saturation white point nominal controls nominal controls V0(p-p)/RMSnoise bandwidth
Scan velocity modulation output output)
Output signal amplitude (peak-topeak value) Maximum output current Output signal black level Differential output resistance
VSVM(p-p)
Io-svm
1.85
SVMOFF
VSVM-black
Ro-svm
DELOFF
Bandwidth output signal BSVM inputs Total delay from output Dsvm0 outputs DEL0: Total delay from output Dsvm1 outputs
DELOFF (basic delay)
tested during production characterization pre-production
Micronas
9-54
2001-05-03
9380
Preliminary Data Sheet Application information
Application information
10.1 System overview Dig. 100Hz
CVBS1
9380
CVBS7
9402 PRIMUS
RGB1
Processor, Deflection Controller
H-Drive V-Drive
RGB2
10.2
System overview Multisync Deflection
HPROT VPROT
Control
HSAFE
IBEAM
BSOIN
H35K
H38K
15pF 24,576 15pF
9380
VSYNC HSYNC VDVD+
IBEAM
VPROT
Micronas
10-55
2001-05-03
9380
Preliminary Data Sheet Application information
10.3
Application circuit diagram
VSYNC HSYNC IBeam Sense Sense
+3.3
V-Sawtooth -V-Drive +V-Drive E/W-Parabola H-Flyback
+3.3 100n +3.3 100n +3.3
+3.3 100n
VDD(A1) HSYNC
HSAFE HPROT VPROT VSS(A3) VDD(A3) VDVD+
VSS(A2) VDD(A2)
VSS(A1)
FH1_2
24.576 +3.3 +3.3 100n +3.3
100n +3.3 100n
FBL1 FBL2 VDD(MC) ROUT GOUT BOUT VSS(MC)
RGBFB1
100n
100n +3.3
SWITCH
VDD(D) VSS(D)
BSOIN IBEAM PROTON VREFH VBLO VREFN VREFC VDD(A4) VSS(A4)
9380
VSYNC H38K H35K VSS(D) VDD(D) RESN SUBST TEST CLEXT CLKI
Control_1 Control_0 H-Drive
RGBFB2
SVM-Out RGB-Out Sense
Micronas
10-56
2001-05-03
9380
Preliminary Data Sheet Waveforms
Waveforms
11.1 Timing diagram H35K H38K
HSYNC
H35K H38K H-frequency detected depends decrease
11.2
Black Switch-Off diagrams
BSOIN component
overscan depends selected mode next page)
BSOIN controls VD+, mode
ROUT, BOUT, GOUT
continuously pulses until Power-On-Reset going High
tD1: 2.2.5 lines
tD2: lines
Micronas
11-57
2001-05-03
9380
Preliminary Data Sheet Waveforms
Mode (constant overscan, 01):
V-overscan (voltage BSOIN) V-overscan
V-overscan
voltage BSOIN
Mode (parabolic function, 10):
V-overscan (voltage BSOIN) V-overscan
V-overscan
voltage BSOIN
Mode (linear function, 11):
V-overscan (voltage BSOIN) V-overscan
V-overscan
voltage BSOIN
Micronas
11-58
100)
100)
100)
120.7
111.1
99.6
116.5
98.8
2001-05-03
9380
Preliminary Data Sheet Waveforms
11.3
Power On/Off diagram
Supply Voltage PowerOnReset
max. 2.6V min. 1.5V
32768 cycles
32768 cycles
SSD=0: lines SSD=1: lines SSD=0: lines SSD=1: lines
registers 01.1C programmable registers 01.1C programmable tristate ready tristate
I2C-Bus
tristate
ready
VREFH
Protection (HPROT >1.5V) I2C-Reg. 1D.30h
active inactive
default
programmable
default
programmable
default
I2C-Reg. 01.1C
default
programmable
default
programmable
default
cycles
active inactive
power
glitch
power
Micronas
11-59
2001-05-03
9380
Preliminary Data Sheet Waveforms
11.4
Standby mode, RESN diagram
Standby
RESN
cycles cycles Phi2-loop free Phi2-loop
Phi2-loop
free
active
inactive
active
VREFH
inactive
Protection (HPROT >1.5V)
active inactive
I2C-Reg. 01.1C
programmable
default values
programmable
default values
programmable
I2C-Reg. 1D.30h
programmable
Standby mode
ext. reset
Micronas
11-60
2001-05-03
9380
Preliminary Data Sheet Waveforms
11.5
Function protection
HPROT
VPROT
Mode
HPON
(IIC-Bus)
VPON
(IIC-Bus)
start
continuous blanking
operation
overvoltage
continuous blanking after
after
operation
short failure
continuous blanking after
longer failure after
continuous blanking after
after
short overvoltage
continuous blanking after
after
after
2/fv.3/fv 64/fv.128/fv 1/fv.2/fv
depends control items HPON VPON 1(off)
Micronas
11-61
2001-05-03
9380
Preliminary Data Sheet Waveforms
11.6
Black Stretch diagram
Output (IRE)
Input (IRE) maximum black stretch
11.7
Soft Clipping diagram
voltage measured output relative cut-off nominal white drive)
Output
range
Slope: soft clipping, bits
Input
Micronas
11-62
2001-05-03
9380
Preliminary Data Sheet Package outlines
Package outlines
P-MQFP-64
Micronas
12-63
2001-05-03
9380-B21
Micronas GmbH Hans-Bunte-Strasse D-79108 Freiburg (Germany) P.O. D-79008 Freiburg (Germany) Tel. +49-761-517-0 +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed Germany Order 6251-549-2PD
information data contained this data sheet without commitment, considered offer conclusion contract, shall they construed create liability. issue this data sheet invalidates previous issues. Product availability delivery exclusively subject respective order confirmation form; same applies orders based development samples delivered. this publication, Micronas GmbH does assume responsibility patent infringements other rights third parties which result from use. Further, Micronas GmbH reserves right revise this publication make changes content, time, without obligation notify person entity such revisions changes. part this publication reproduced, photocopied, stored retrieval system, transmitted without express written consent Micronas GmbH.
Micronas
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