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Edition Feb. 2001 6251-559-1 VPS/PDCPro Specification Version 3.0


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5652-2X VPS/PDCPro VPS/PDC/OSD Device VCRs
Edition Feb. 2001 6251-559-1
VPS/PDCPro Specification Version 3.00
5652-2X
Features
General Features
external component count
VSSA VDDA VDDD CVBS_IN CVBS_SLICER IREF CVBS_OUT PD2/VCO2 SECAM_BY PD1/VCO1 HT_BLANK
external crystal required Technology: CMOS P-DSO-20 package
VSSD FSC/OSC_IN OSC_OUT SYNC2 VSSD SYNC1 DAVN/EHB
Features Reception data line vertical blanking interval Complete reception BDSP packet 8/30/1 packet 8/30/2 Reception complete teletext header 400KHz interface Integrated Module
Features Display structure: rows characters rows characters characters visible frame area) characters Pixel Lines) Fringing Display start position programmable horizontal vertical direction Insertion OSDs CVBS signal (Black white) Colored full screen mode Integrated Sync-Separator Integrated SECAM switch Analog CVBS Output programmable background colors (via Look Table) Programmable flashing frequency (1.5Hz, Cursor Four size settings vertical horizontal directions
VPS/PDCPro Specification Version 3.00
5652-2X
Order Information
Type 5652-2X Package Ordering Code
General Description
PDC/OSD 5652-2X decoder chip receives 8/30 Format data together with teletext header information easy identification broadcaster. addition well known PDC/VPS decoder module with CVBS encoder integrated. synchronized CVBS signal generate complete multistandard (PAL/NTSC, 50Hz/60Hz frame rate) CVBS signal with full screen colored OSD.
VPS/PDCPro Specification Version 3.00
5652-2X
Configurations
VSSA
VDDA
VSSD
VDDD
FSC/OSC
CVBS_IN CVBS_ SLICER IREF
OSC_OUT
CVBS_ PD2/VCO2
SYNC2
VSSD
SECAM_BY
OSC_OUT
PD1/VCO1
DAVN/EHB
HT_BLANK
VPS/PDCPro Specification Version 3.00
5652-2X
Definitions Functions
Pin. P-DSO-20 3IREF 5PD2/VCO2 Symbol VSSA VSSD FSC/OSC_IN OSC_OUT SYNC2 Function Analog ground Digital ground Color Carrier Clock Serial clock input I2C-Bus. Serial data input I2C-Bus. Optional oscillator 2FSC Vertical Sync/Vertical Composite Sync (Depending definition switched either Input Output. When switched input, analog digital signals processed) internal used; should connected Vertical/Horizontal Sync (Depending definition switched either digital input output) output signals DAVN/EHB coming from VPS/PDCcircuit. Output-Pin Halftone-Blanking. Goes high halftoneblanked video-areas, non-halftoneblanked areas Connector loop filter SYSPLL. Input Secam bypass. Connector loop filter DAPLL. Composite video signal output from path. Reference current input on-chip analog circuit. Composite video signal input data slicer. source this signal must same source signal Composite video signal input path. source thsi signal must same source signal Positive supply voltage digital circuits. nom.). Positive supply voltage analog circuits nom.).
PD1/VCO1
CVBS_SLI
DAVN/EHB VSSD SYNC1 DAVN/EHB HALFTONE_BLANK PD1/VCO1 SECAM_BY PD2/VCO2 CVBS_OUT CVBS _SLICER CVBS_IN VDDD VDDA
CVBS_IN
CVBS_OUT
SECAM_BY
Sync1
Sync2
VPS/PDCPro Specification Version 3.00
5652-2X
6.Block Diagram
processing data 5652-2X works following way:
Data Sync Slicer -PLL
Data Acquisition
Acquisition Timing
Interface
Memory Sliced Data Information (512 Byte)
CVBS Encoder
Character generator
Character
Display Timing Sync /Pixelclock Generation
VPS/PDCPro Specification Version 3.00
5652-2X
Circuit Description
VPS/PDC Functions
Referring functional block diagram composite video signal with negative going sync pulses coupled CVBS through capacitor which used clamping bottom sync pulses internally fixed level. signal passed slicer, analogue circuitry separating sync data parts CVBS signal, thus yielding digital composite sync signal digital data signal further processing comparing those signals internally generated slicing levels. output this sync separator forwarded acquisition clock generator acquisition timing block which teletext related data-valid-windows generated. data slicer separates data signal from CVBS signal comparing video voltage internally generated slicing level which found averaging data signal during line mode averaging data signal during clock run-in period teletext lines during data entry window (DEW) mode. acquisition clock generator delivers system clock needed basic timing well regeneration dataclock. based phase locked loops (PLL's) parts which integrated chip with exception loop filter components. Each PLL's composed voltage controlled relaxation oscillator (VCO), phase/ frequency detector (PFD), charge pump which converts digital output signals analogue current. That current transformed control voltage off-chip loop filter. generated frequencies 13.875 mode mode, respectively. signals necessary control sync data slicing well data acquisition generated this timing block. 5652-2X operated three different modes: Depending selected operating mode, either teletext lines carrying 8/30 packages, dedicated line 16(VPS) teletext header bytes acquired. mode, only teletext rows 8/30 containing Broadcast Data Service Package (BDSP) information acquired. relevant bytes 8/30 format (8/30/1) 8/30 format 30/2) extracted. 8/30/1-bytes stored acquisition register transparent without manipulation, whereas hamming coded bytes packet 8/30/2 hamming-checked bytes with error corrected. header mode bytes headers stored. Hamming protected bytes corrected need processed external controller. order stored bytes register description. micro controller read stored bytes interface time. order achieve maximum system performance recommended start 5652-2X mode (state after power read register check whether line received. After reception data line 5652-2X switched 8/30
VPS/PDCPro Specification Version 3.00
5652-2X
mode waiting packet 8/30 data. Since data line transmitted every frame data packet 8/30 transmitted nearly every second recognition both 8/30 packets done within PDC-system constraints (about sec). differ between older (SDA5649/5650) future (SDA5652-2X/.) versions special method used chip identification: SDA5649/5650 PDC-versions writeable. First step user chooses pattern bytes writes them RAM. Second step read these bytes from RAM. comparing written bytes read bytes there correspondence not. there's correspondence present version (SDA5652-2X/.) there's correspondence older version (SDA5650/5651). addition further versions (SDA5652-2X/ could differed with special Valid-Data-Recognition: PDC/VPS-registers could read external controller. There necessity controller reading PDC/VPS-contents register-contents aren't made topical reception. There three methods identify register-contents made topical after previous reading-operation: Data-Set-Valid-Bit After reception fulfilled data-set-valid-bit from high. data-setvalid-bit high subaddress between closed stop condition data-set-valid from high low, during IIC-Read-operation datas received. DAVN-signal Pin10 signal DAVN (Data Valid active low) will available. behaviour this signal described follows: VPS-Mode: H/L-Transition (set low): L/H-Transition (set high): PDC/HTA/HTB/HTC-Mode: H/L-Transition (set high): L/H-Transition (set low): VPS/PDC-register-contents stop-condition send after read-operation been accessed addresses between register-contents from during IIC-Read-operation datas received (falling edge DAVN). reception VPS/PDC-datas during after IIC-Read-operation, will overwrite these FFh-contents. result data-reception could detected register-contents itself. line where valid data carried. beginning next field After VPS-data been received. start line
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5652-2X
Format register ACQ_CONTROL (default values brackets)
ACQ_CONTROL PDC/ FOR1/ FOR2
MABC_1 MABC_0
FOR1/FOR2:
Determines which kind data stored decoder when mode active: BDSP 8/30/2 accessible BDSP 8/30/1 header data accessible (refer description PDC/VPS mode active mode active Determines whether BDSP 8/30/1 data header data stored. BDSP 8/30/1 accessible Teletext header mode active. also Mode Header bytes accessed order Mode Header bytes accessed order Mode Header bytes accessed linear increasing order 4-45. Data valid This only read writeable. Write-operations have influence this bit. Declares when PDC/VPS-register-contents renewed after previous read-operation. allowed read content DSV-Bit (Subadr. 03h) VPS/PDC-data (subadr. 27h) within IIC-protocol. this case cleared data-registers reliable. Register-contents haven't been renewed moment this read. Register-contents renewed. datas read IIC-read-operation from byte 4-40 completly valid.
PDC/VPS:
ATTENTION: Please refer Errata-Sheet Item-No. relating VPS-Mode/Byte13
HDT:
MABC_1.0:
DSV:
VPS/PDCPro Specification Version 3.00
5652-2X
7.1.1 Format stored data bytes
Bits stored order their reception, that means first transmitted stored appropriate address. format packet 8/30 contents transmitted bytes stored register address. Hamming bits stored.
ATTENTION: Please refer errata-sheet item-no. relating VPS-Mode/Byte13
Subaddress 8/30 Format 8/30 Format
16,17 18,19 20,21 22,23 14,15 24,25 13,x
10,11 12,13
Subaddress 8/30 Format 8/30 Format
Subaddress 8/30 Format 8/30 Format
Subaddress
VPS/PDCPro Specification Version 3.00
5652-2X
8/30 Format 8/30 Format
VPS/PDCPro Specification Version 3.00
5652-2X
7.2. Functions
block consists character generator unit which reads character addresses from internal transforms them help character into pixel information. memory size Bytes. result display fixed format rows with characters. 50Hz-system rows displayed, 60Hzsystem rows. count columns defined user systems using color-carrier 4,43MHz characters should choosen, systems using 3,58MHz color-carrier characters should choosen. needed display-memorycontents from columns right side contents from last rows ignored. Bytes processed linear binary increasing order. display memory accessed dataport. Starting address (see also 7.3.2. Dataport access). character structure pixels horizontal direction lines vertical direction.
HORIZ VERTI- CHARCHARONTAL attribute_ attribute_ _SIZE _SIZE (2Bit)
(2Bit)
(2Bit)
(2Bit)
Display Memory
rows with characters
With Bits address characters character addressed. addresses characters orientated wellknown ASCII-table.
VPS/PDCPro Specification Version 3.00
5652-2X
character address used switch between attribute definitions. These attribute definitions chosen each individual. this choice each character-attribute-registers, CHAR_attribute_1 CHAR_attribute_2. CHAR-attribute_1 consists CHAR-attribute_2 consists bits. four character-definitions selected these bits. These four character-definitions made CHAR-attribute_1 four registers CHAR-definition1_1.1_4. CHAR-attribute_2 these four definitions made CHAR-definition2_1.2_4. format CHAR-definition-Registers CHAR-attribute-Registers below. Format registers CHAR-definition1_1.1_4 CHAR-definition2_1.2_4: (default value brackets):
BYTE BYTE HALFTONE FCOL_4 BL_1 FCOL_3 BL_0 FCOL_2 HS_1 FCOL_1 HS_0 FCOL_0 BK_0 BK_1
BCOL_2 BCOL_1 BCOL_0
HALFTONE:
Fullpage-Mode Display turned off: Fullpage-Mode display turned this influence. Pin11 static switched L-Level. Mixed-Mode: Switches between Halftone-Blanking off. Characters which halftone-blanking turned pin11 switched H-Level during these characters displayed. Otherwise pin11 switched L-Level. Switching Halftone-Blanking Switching Halftone-Blanking
HS_1.0:
Horizontal size multiples pixel clocks. Only used row-attribute HORIZONTAL_SIZE_SELECT bits pixel clock dot. pixel clocks dot. pixel clocks dot. pixel clocks dot. Defines blanking mode characters mixed mode. There's special fringing-mode. Fringing means, that character surrounded border. This border size pixel: Settings mixed mode: Blanking switched off. complete character (border background) visible screen. Background blanked, only foreground information
BL_1.0:
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5652-2X
character visible. Background blanked, only foreground information character including border (fringing) visible. complete characters blanked. (The character visible) full-page-mode blanking available. Fringing switched with BL_1. Settings full-page-mode: Fringing switched Fringing switched BK_1.0: Defines flashing mode period appropriate row. When flashing specified reversed characters, flashing will between normal character reversed display. Flashing switched Flashing switched period approximately 0.5/s Flashing switched period approximately 1.0/s Flashing switched period approximately 1.5/s full-page-mode: Defines background color vector. final color depends values look table (see below). mixed-mode: Defines background grey-value. final grey-value depends luminancevalue described look table (see below). Defines foreground grey-value. values between 1,4V 2,9V steps about 68mV selected full-page-mode (The values from allowed because there levels sync-area). values between 1,4V 2,9V steps about selected mixed-mode. Inverting switched Inverting switched
BCOL_2.0:
FCOL_4.0:
INV:
characters zoomed horizontal vertical direction. Characters neighboured right below zoomed character overwritten shifted. Each VERTICAL-SIZE-SELECT bits which size characters defined whole row. size zoomed vertical direction factor Each HORIZONTAL-SIZE-SELECT bits which size characters
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5652-2X
defined whole row. size zoomed horizontal direction factor HORIZONTAL_SIZE_SELECT bits each character zoomed individual char_attributes- char_definition-registers. HORIZONTAL_SIZE_SELECT bits, VERTICAL_SIZE_SELECT bits CHAR_attribute_1.2 bits stored each register ROW_ATTRIBUTE: Format register ROW_ATTRIBUTE:
HORIZO HORIZO VERTIC VERTIC CHAR_AT CHAR_AT CHAR_AT CHAR_AT NTAL_SI NTAL_SI AL_SIZE AL_SIZE TRIBUTE TRIBUTE TRIBUTE TRIBUTE _2/Bit1 _2/Bit0 _1/Bit1 _1/Bit0 ZE/Bit1 ZE/Bit0 /Bit1 /Bit0 HORIZO HORIZO VERTIC VERTIC CHAR_AT CHAR_AT CHAR_AT CHAR_AT NTAL_SI NTAL_SI AL_SIZE AL_SIZE TRIBUTE TRIBUTE TRIBUTE TRIBUTE _2/Bit1 _2/Bit0 _1/Bit1 _1/Bit0 ZE/Bit1 ZE/Bit0 /Bit1 /Bit0
HORIZO HORIZO VERTIC VERTIC CHAR_AT CHAR_AT CHAR_AT CHAR_AT NTAL_SI NTAL_SI AL_SIZE AL_SIZE TRIBUTE TRIBUTE TRIBUTE TRIBUTE _2/Bit1 _2/Bit0 _1/Bit1 _1/Bit0 ZE/Bit1 ZE/Bit0 /Bit1 /Bit0
ATTENTION: Please refer errata-sheet item-no. relating vertical horizontal zoom
Format registers VERTICAL_START_POSITION HORIZONTAL_START_POSITION: position display adjusted terms pixels lines referring horizontal vertical edge picture. position programmed register vertical_start_position horizontal_start_position. line-counter vertical-startposition during negative going flank V-Sync. pixel-counter horizontal-start-position after positive going flank H-Sync (negative flank VCS).
VERTICAL_ START_POSITION HORIZONTAL_ START_POSITION VSP_6 HSP_6 VSP_5 HSP_5 VSP_4 HSP_4 VSP_3 HSP_3 VSP_2 HSP_2 VSP_1 HSP_1 VSP_0 HSP_0
ATTENTION: Please refer errata-sheet item-no. relating horizontal vertical start-position.
VSP_6.0: Vertical start position screen. VSP_6.0 define shift screen vertical direction multiples horizontal lines.
VPS/PDCPro Specification Version 3.00
5652-2X
HSP_6.0:
Horizontal start position screen. HSP_6.0 define shift screen horizontal direction pixel clocks.
Clock-Supply pixel clock (2FSC, FSC, 2FSC/3, FSC/2) derived from system-clock (4FSC) depending horizontal-zoom-factor. system-clock(4FSC) derived from external frequency. There methods provide these external frequency. method frequency 1FSC 2FSC 4FSC Pin3. second method plug 2FSC-crystal-oscillator Pin3 Pin6. Which these methods used defined register SYNCHRONISATION. pixel clock internally synchronized horizontal- sync information discrete phase shifter. Synchronisation-modes sync information delivered external impulses, composite sync signal derived from analog CVBS-signal. free mode timing block generate composite sync signal stable display produced even external sync source available. There different synchronisation-modes mixed-mode-OSD. more information these modes, register SYNCHRONISATION figure page high-end-sync-performance mixed-mode internal HPLL used synchronisation. HPLL consist digital DTO, digital phase-detector loop-filter. There different settings loop-filter possible. high-performance recommend universal loop-filter-setting. advanced high-performance there possibility adapt loop-filter each customer-specific-VCR different replay-modes Long-Play/Short-Play).
HPLL
HPLL_3
HPLL_2
HPLL_1
HPLL_0
HPLL0:
Register justify integral filter-component 1/128 Register justify proportional filter-component Register justify proportional/integral filter-component 1/32
HPLL1:
HPLL2.3:
VPS/PDCPro Specification Version 3.00
5652-2X
1/16
universal VCR/Tuner-modes recommend: HPLL0: HPLL1: HPLL2: HPLL3: high-performance noise-surpress recommend: HPLL0: HPLL1: HPLL2: HPLL3: mixed mode display signal processing synchronized CVBSin-Signal. this Pin7 Pin9 H-synchronization V-synchronization-signals full-page-mode both pins(Pin7 Pin9) working output. this case they deliver H-sync V-sync-signals. They also switched highly impedant state. Format register SYNCHRONISATION (default values brackets):
SYNCHRONISATION
SYNC_2 SYNC_1 SYNC_0 IIC_SWI TCH(1)
DISPON OSC_SY OSC_SY S_1(0) S_0(1)
DISPON:
Switches CVBS_in-signal (Pin18) CVBS_outsignal(Pin15). This highest priority. Switching low, incoming CVBS-signal through CVBS output. CVBS_in=CVBS_out states CVBS_in=CVBS_out D/A=CVBS_out controlled charactergenerator After RELEASE-bit been from IICbus-protocol should started switch IIC-switch from this, highest noise-surpression SDA/ SCL-signals guaranteed. (see also ,,10.1 After-Reset-Start-Sequence") Defines source system-clock generation. frequency this source internally multiplied 4FSC. This frequency used color-carrier-generation full-
IIC_SWITCH:
OSC_SYS_1.0:
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5652-2X
page-mode. (Pin with ext. feedback resistor (Pin with ext. feedback resistor (Pin with ext. feedback resistor optional, external crystal-oscillator This crystal-oscillator must have resonance-frequency 2FSC. This mode also used alternative mode 2FSC (Pin3). this mode external feedback resistor longer necessary because this mode internal resistor used. oscillator-mode installed these bits long RELEASE register LEVELS_AND_CHANGE After setting RELEASE register LEVELS_AND_CHANGE oscillator-mode won't change anymore, anyway polarity these bits changed user. Next oscillator-mode-settings, OSC_SYS(0) used switch special VCS-spike-surpress-filter slicer off. recommend keep this filter switched modes. VCS-spike-filter switched VCS-spike-filter switched off. Next oscillator-mode-settings OSC_SYS(1) used switch special algorithm slicer. This special algorithm allows high noise-surpress. algorithm works signals which same length(8cycles) described inside ETSI-standard teletext. CVBS-signal processed which count CRI-cycles non-standard special algorithm should switched off. recommend start dataslicing switching special algorithm (for standardsignals high-noise-performance). this successfull recommend proceed data-slicing switching special algorithm off. this, non-standard-signals sliced with little less noise-performance. Special algorithm switched Special algorithm switched SYNC_2.0: Three MUXes inside synchronisation-signal-pathes controlled these three bits shown below figure. Pin9 Pin7 used input/output external
VPS/PDCPro Specification Version 3.00
5652-2X
chronisation. SYNC_2 switched Pin7 used output, SYNC_0 switched Pin9 used output.
Next SYNC_2.0 synchronisation-signal-path controlled bits SYNC_HIMP, HSYNC_HIGH/ LOW_DETECT VSYNC_HIGH/LOW_DETECT register LEVELS_AND_CHANGE (see also page 26/27). SYNC_HIMP used switch outputs high-impedant-state. HSYNC_HIGH/LOW_DETECT VSYNC_HIGH/LOW_DETECT used invert synchronisation-signals enabling detection both edges synchronisation-edges.
SYNC_HIMP
SYNC1 Pin9
EXOR SYNC_0 VSYNC_HIGH/ LOW_DETECT VerticalSeperation
CVBS_ Slicer Pin17
internal SyncSlicer
EXOR
dig. HPLL
DISPLAY_CONTROL/
SYNC_2
SYNC_1
LEVELS_AND_CHANGE/ HSYNC_HIGH/ LOW_DETECT
SYNC2 Pin7
EXOR
SYNC_HIMP
Figure: Signal-pathes sync-seperation-circuit
VPS/PDCPro Specification Version 3.00
5652-2X
Summary Sync-Modes (SYNC2.0):
SYNC_ SYNC_ SYNC_
HPLL
Pin9
Pin7
intern intern intern intern extern extern extern extern
extern intern extern intern intern extern intern
input input output input input output
output output output output input input input input
output
extern
output
Negative going HSync-pulses expected default. Using register LEVELS_AND_CHANGE this switched positive going syncpulses. With VSYNC_EDGE_POLARITY register LEVELS_AND_CHANGE user choose level edge-sensitive vertical synchronisation. polarity digital output-H-sync-signal positive going sync-impulses. color look-up-table capable display eight different color values picture. These eight values defined user registers color_value: assumption, that color-values given voltage values which related CVBS-Signal corresponding register-contents could derived follows: given color-value: phase chromaamplitude (peak peak luminanceamplitude above porch-level) INTEGER(
corresponding register-contents: luminance-register: U-component-register: V-component-register: Blue Phase: -38° 162mV 200mV Chromaphase Chromaamplitude (peak peak Luminanceamplitude (above Porch-Level)
example these equations solved three color-values:
luminance-register: U-component-register:
VPS/PDCPro Specification Version 3.00
5652-2X
V-component-register: Blue-Green Phase: -90° 286mV 250mV
Chromaphase Chromaamplitude (peak peak Luminanceamplitude (above Porch-Level) Chromaphase Chromaamplitude Luminanceamplitude (above Porch-Level)
luminance-register: U-component-register: V-component-register: Grey Phase: indifferent 125mV
luminance-register: U-component-register: V-component-register: 01111b 01110b 01101b 00000b 11111b 11110b 11101b 10001b
U/V-component-registers programmed two's-complement. This means:
value 10000 -16d allowed. Format eight registers color-value1.8:
LUMINANCE U-COMPONENTE V-COMPONENTE BIT5 BIT4 BIT4 BIT4 BIT3 BIT3 BIT3 BIT2 BIT2 BIT2 BIT1 BIT1 BIT1 BIT0 BIT0 BIT0
Format There leftover active video surrounding field characters. colors this border defined look-up-table described above. Next border-color, fringing color defined this register.
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BORDER_FRINGIN
BORDE
BORDE
BORDE
FRCO_2 FRCO_1 FRCO_0 BO_ON
Border switched off. Border means fullpage-mode: left part border each same color first character each set. right part border each same color last character set. upper lower part border color defined border. Border means fullpage-mode: whole border color which defined border. BO_ONOFF BORDER2.0 FRCO_2.0: Border Border Defines color border color-look-uptable (see above). fringing turned eight fringing grey-values selected. levels grey-values full-page mode 1.4V 1.9V steps about mixed mode eight levels between 1.4V 2.1V steps about 93mV selected full-page-mode.
Format register Display Control: Switching between full-page-OSD mixed-mode turning display off, etc. handled with Display-Control-Register. multi standard video output. That means, NTSC/PAL-color-systems encoded field-frequencies 50/60Hz choosen. standard-mode pixel-clock derived from color-carrier (2FSC). user free choose color-carrier which Pin3. example color-carrier 4.43MHz NTSC color-carrier 3.58MHz. pixel-clock derived from this color-carrier. suitable count character horizontal direction choosen NORM1. NTSC some PAL-derivates frame-rate 60Hz (525 lines) used. this case vertical direction character-rows produced. standard-PAL frame-rate 50Hz (625 lines) used. result vertical direction character-rows produced.
DISPLAY CONTROL DAVN/ FULLPAGE
SECAM_ SPACE SWITCH
NORM_2 NORM_1 NORM_0
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DAVN/EHB:
DAVN EHB-signals made visible output-pin10. Which these signals shown output-pin defined DAVN/EHB. shown Pin10. DAVN shown Pin10.
VCS:
Internal inverted (front porch used synchronisation). Internal inverted (back porch used synchronisation). This only used full-page-mode. NTSC This used both modes (full-page mixed-mode) characters horizontal direction characters horizontal direction This used both modes (full-page mixed-mode) 50Hz-system 60Hz-system
NORM2 NORM0
NORM0:
NORM1:
NORM2:
Following standards choosen NORM2 NORM0:
standard nominal color-carrier-frequency 4,43361875 3.57561149
NTSC(equivalent mode "10") 3,57954500 NTSC(equivalent mode "00") 3,57954500
SPACE:
SECAM_SWITCH:
FULLPAGE:
this state character-RAM displayed. this state contents character-RAM ignored space-characters displayed over screen. 0:SECAM-Switch PAL/NTSC 1:SECAM-Switch SECAM-Signals. That means current SECAM-color-frequency CVBSin-side added CVBS-out signal areas characters mixed mode. 0:Full-Page-OSD-Mode. 1:Mixed-Mode.
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Format register LEVELS_AND_CHANGE:
LEVELS_AND_CHA VSYNC_ HIGH/ LOW_ DETECT HSYNC_ HIGH/ LOW_ DETECT CHNG_ MIXED_ FULL
VSYNC_ RELEAS SYNC_ EDGE_ HIMP(1) POLAR-
CHNG_MIXED_FULL:
Next Register-Bit FULLPAGE DISPLAY_ CONTROL-Register this used switching between fullpage-mode mixed-mode. mixed-mode fullpage-mode Switching from mixed-mode fullpage-mode: first step: DISPLAY_CONTROL/Bit5 second step: CHNG_MIXED_FULL Switching from fullpage-mode mixed-mode: first step: CHNG_MIXED_FULL second step: DISPLAY_CONTROL/Bit5
HSYNC_HIGH/LOW_DETECT:Defines which polarity Hsync should used OSD-synchronization. Negative going sync-pulses expected. Positive going sync-pulses expected. VSYNC_HIGH/LOW_DETECT:Defines which edge Vsync should used OSD-synchronization. Uses rising edge Uses falling edge SYNC_HIMP: output pins switched highimpedant-state modes. output pins switched highimpedant-state modes. After power-on-reset contents synchronisationregister refer frequency which Pin9/7. After setting bits OSC_SYS1.0 Register SYNCHRONISATION contents which referring input-frequency, RELEASE switched from After switching RELEASE cannot changed anymore except IIC-bus- power-onreset. After switching RELEASE bits OSC_SYS1.0 Register SYNCHRONISATION cannot changed anymore without executing IIC-
RELEASE:
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power-on-reset. VSYNC_EDGE_POLARITY: This used, choose synchronisation-mode mixed-mode VSync. polarity choosen synchronized levels VSync. this case Vsync should have minimum-length 1line. edge choosen synchronized edge VSync. this case there special efforts Vsync-length. general it's recommended edges. synchronized VSync edges. synchronized VSYNC polarity.
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7.3.
Information exchanged between external controller 5652-2X fast asynchronous bidirectional data bus. uses connections, pins (data) (clock), operates according specifications, which limits maximum transfer rate kbit/s. interface operates slave mode: either receiver transmitter. chip address fixed 0010000X LSB. transmitted first. switches between reading-mode(1) writing-mode(0). bus-system isn't blockaded there power-supply switched SDA5652-2X
7.3.1 Protocols
following protocols supported read mode subaddress must defined previously access): Write followed read:
Please notice: Before stop-condition after reading-operation, there ACK_M allowed!!! Write followed read with stop condition:
Please notice: Before stop-condition after reading-operation, there ACK_M allowed!!! with following abbreviations: START: Start condition technical description) STOP: Stop condition technical description) ACK_S: Acknowledge slave technical description) ACK_M: Acknowledge master technical description) SL_AD: chip select address SU_AD: subaddress
7.3.2 Access modes
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There possibilities access 5652-2X. addressing direct possible subaddresses protocol. other method indirect addressing method. This must used byte from display should read written. that case dataport must used transfer (see below). Autoincrement Registers After read write access register subaddress will incremented automatically. There only exceptions: read write mode, subaddress ,,2" incremented (see also dataport access).
7.3.3 Dataport access
address pointer registers used address internal memory read write data Bus. dataport register which read written addressing with subaddress. Independent from transfer direction (read write) memory address defined address pointer registers which must defined before accessing dataport. display-RAM accessed dataport. startaddress begins address Autoincrement Dataport autoincrement dataport always switched That means, each time after dataport address accessed, contents addresspointer registers incremented. following protocols supported: Writing memory including initializing addressport:
Writing memory using previous defined addressport:
Reading memory using previous defined addressport:
Please notice: Before stop-condition after reading-operation, there more
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5652-2X
ACK_M allowed!!! with following additional abbreviations: SU_A0.2: Subaddress ADR_1.0: Addresspointer START: Start condition technical description, Falling edge STOP: ACK: Stop condition technical description, Rising edge Acknowledge technical description)
SL_AD: 7-Bit chip select address Format register ADR_POINTER (default values brackets):
ADR_POINTER_1 ADR_POINTER_0 DATA_PORT ADR_7 DAT_7 ADR_6 DAT_6 ADR_5 DAT_5 ADR_4 DAT_4 ADR_3 DAT_3 ADR_2 DAT_2 ADR_9 ADR_1 DAT_1 ADR_8 ADR_0 DAT_0
ADR_9.0
Addressport. Defines internal memory address where data should written read from. Only address valid addresses defined memory table allowed.
Format register DATA_PORT (default values brackets):
DATA_PORT DAT_7 DAT_6 DAT_5 DAT_4 DAT_3 DAT_2 DAT_1 DAT_0
DAT_7.0
Dataport. This register contains data transferred. Each time when this register read written contents addressport autoincremented internal subaddress.
VPS/PDCPro Specification Version 3.00
5652-2X
Example data port access (Beginning address 292d (124h) following data should written: 11h, 12h, 13h,
Protocol Chipadress,Write Subaddress Data, Data, Data, values Comment 5652-2X chipaddress Subaddress initialized transmitted subaddress ,,0" (Addresspointer). internal subaddress autoincremented. transmitted subaddress ,,1" (Addresspointer) Addresspointer 124h. Subaddress ,,2". Data written dataport then internally transferred address 124h. addresspointer autoincremented 125h. subaddress incremented Data written dataport then internally transferred address 125h. addresspointer autoincremented 126h. Data written dataport then internally transferred address 126h.The addresspointer autoincremented 127h. Data written dataport then internally transferred address 127h. addresspointer autoincremented 128h.
Data,
Data,
Data,
Stop
7.3.4 Subaddresses commands 7.3.4.1
above described handled with subaddresses described below. special function implemented address 255. this address submitted reset released.
4-40
Register-Name ADR_POINTER_0 ADR_POINTER_1 DATA-PORT ACQ-Control VPS/PDC-datas SYNCHRONISATION
read/write write write read/write read (only Bit5) write(excluding Bit5) read read(only OSC_SYS1.0)/ write
VPS/PDCPro Specification Version 3.00
5652-2X
LEVELS_AND_CHANGE IC-IDENTIFICATION (content:02h) RESET
write read write
7.3.4.2.
RESET-Command: 255d This command resets whole protocol which used defined follows:
START: Start condition technical description, Falling edge STOP: ACK: Stop condition technical description, Rising edge Acknowledge technical description)
SL_AD: 7-Bit chip select address (Write-Mode) 255: Reset-Command DATA: This data hasn't meaning. It's only used keep restrictions protocol.
VPS/PDCPro Specification Version 3.00
5652-2X
7.3.4.3 RAM-registers
Some register-contents stored RAM. These register-contents have accessed using Data-Port
from
content
display-RAM used IC-internal ROW_ATTRIBUTE/ROW1 ROW_ATTRIBUTE/ROW2 ROW_ATTRIBUTE/ROW3 ROW_ATTRIBUTE/ROW4 ROW_ATTRIBUTE/ROW5 ROW_ATTRIBUTE/ROW6 ROW_ATTRIBUTE/ROW7 ROW_ATTRIBUTE/ROW8 ROW_ATTRIBUTE/ROW9 ROW_ATTRIBUTE/ROW10 ROW_ATTRIBUTE/ROW11 ROW_ATTRIBUTE/ROW12 ROW_ATTRIBUTE/ROW13 ROW_ATTRIBUTE/ROW14 CHAR_definition1_1/BYTE1 CHAR_definition1_1/BYTE2 CHAR_definition1_2/BYTE1 CHAR_definition1_2/BYTE2 CHAR_definition1_3/BYTE1 CHAR_definition2_1/BYTE1 CHAR_definition2_4/BYTE2 VERTICAL_START_POSITION HORIZONTAL_START_POSITION DISPLAY_CONTROL BORDER_color COLOR_VALUE_1/LUMINANCE COLOR_VALUE_1/V_COMPONENTE
VPS/PDCPro Specification Version 3.00
5652-2X
from
content
COLOR_VALUE_1/U_COMPONENTE COLOR_VALUE_2/LUMINANCE COLOR_VALUE_2/V_COMPONENTE COLOR_VALUE_4/LUMINANCE COLOR_VALUE_4/V_COMPONENTE COLOR_VALUE_4/U_COMPONENTE COLOR_VALUE_8/LUMINANCE COLOR_VALUE_8/V_COMPONENTE COLOR_VALUE_8/U_COMPONENTE HPLL internal used internal
VPS/PDCPro Specification Version 3.00
5652-2X
Electrical Characteristics
Power-on-reset: After Power-on called Power-on-reset executed. condition power-on-reset rising VDDA from voltage value less than 0,8V voltage value least 4,5V.
Absolute Maximum Ratings
Parameter Ambient temperature Storage temperature Total power dissipation Power dissipation output Supply voltage Thermal resistance Operating Range Supply voltage Supply current Ambient temperature range VDDD VDDA Symbol min. Tstg Ptot VDDD VDDA Limit Values max. operation storage Unit Test Condition
Characteristics
Parameter Symbol min. Input Signals SDA, H-input voltage L-input voltage Input capacitance Input current Input Signal TMODE H-input voltage L-input voltage Input capacitance Input current 0.9xVDDD VDDD 0.1xVDDD 0.7xVDDD VDDD 0.3xVDDD Limit Values max. Unit Test Condition
VPS/PDCPro Specification Version 3.00
5652-2X
Characteristics (cont'd)
Parameter Symbol min. Input Signal CVBS/Output Signal mixed mode: synchron signal amplitude (bottom) Black-Porch-Level VSYNC VPORCH Limit Values max. Unit Test Condition
Resistance switch between input output-signal mixed mode:
Output Signal CVBS full page mode: Supplyvoltage used reference D/A-converter. stability voltage-values output signal depend supplyvoltage stability. Min-values related supplyvoltage 4,5V max-values related supplyvoltage 5,5V.
100% white level Synchron signal amplitude (bottom) Color burst Color burst high Black-Porch-Level Input Signal CVBS_Slicer Video input signal level peak peak Synchron signal amplitude peak peak Data amplitude peak peak
VCVBS VSYNC VBURSTL VBURSTH VPORCH
1.0(NTSC) 1.2(NTSC) 1.1(PAL) 1.3(PAL) 1.6(NTSC) 1.9(NTSC) 1.5(PAL) 1.8(PAL)
VCVBS VSYNC VDAT
0.15 0.25
Vdat=450mV VSync=300mV
VPS/PDCPro Specification Version 3.00
5652-2X
Parameter Symbol min. Limit Values max. Unit Test Condition
VCVBS
1,75 1,43 1,12
VBurstL VSync VBurstH
VPorch
Output Signals (Open-Drain-Stage) L-output voltage Permissible output voltage Open-drain-resistance (SDA) Open-drain-resistance (SCL) RSDA RSCL max. 200pF load capacity max. 200pF load capacity
PLL-Loop Filter Components Resistance PD1/VCO1 Resistance PD2/VCO2 Capacitor PD1/VCO1 Capacitor PD2/VCO2
Frequence Range Adjustment
Resistance IREF (for bias current adjustment)
68+/-5%
VPS/PDCPro Specification Version 3.00
5652-2X
Input Signal
H-input voltage L-input voltage VSyncH VSyncL 0.6xVDDD VDDD 0.2xVDDD
SECAM-bypass bandpass filter Coil CVBS_OUT Capacitor SECAM-bypass FSCin (1x/2x/4x) Amplitude FSCin-Signal peak peak Coupling Capacitor A(fSC)
Clamp components input CVBS-Slicer Capacitor Resistance 1000 kOhm
Capacitor Crystal-impedance
VPS/PDCPro Specification Version 3.00
5652-2X
Environment system with 1fsc, 2fsc 4fsc external system-clock
VDDA
VDDD
100nF(Keramik) 100nF(Keramik) 1.7kOhm 0-15pF VSSD 100kOhm 0nF-10nF SYNC2 SYNC1 DAVN/EHB VSSD 1.7kOhm VSSA IREF 3.3kOhm 68nF 10uH 120pF 3.3kOhm 100nF PD1/VCO1 HALFTONE_BLANK 470nF 270kOhm CVBS_IN CVBS_SLICER CVBS_OUT PD2/VCO2 SECAM_BY 68kOhm 100nF
Environment system with crystal-oscillator system-clock:
VDDA
VDDD
100nF(Keramik) 100nF(Keramik) 1.7kOhm 1.7kOhm VSSA 2fsc crystal SYNC2 SYNC1 DAVN/EHB VSSD VSSD IREF 3.3kOhm 68nF 10uH 120pF 3.3kOhm 100nF PD1/VCO1 HALFTONE_BLANK 470nF 270kOhm CVBS_IN CVBS_SLICER CVBS_OUT PD2/VCO2 SECAM_BY 68kOhm 100nF
VPS/PDCPro Specification Version 3.00
5652-2X
Environment system with 2fsc external system-clock oscillator-mode
VDDA
VDDD
100nF(Keramik) 100nF(Keramik) 1.7kOhm 0-15pF 0nF-10nF SYNC2 SYNC1 DAVN/EHB VSSD VSSD 1.7kOhm VSSA IREF 3.3kOhm 68nF 10uH 120pF 3.3kOhm 100nF PD1/VCO1 HALFTONE_BLANK 470nF 270kOhm CVBS_IN CVBS_SLICER CVBS_OUT PD2/VCO2 SECAM_BY 68kOhm 100nF
VPS/PDCPro Specification Version 3.00
5652-2X
Character-ROM
character-ROM shape characters defined. characters stored ROM. Each character structure 12columnsx18lines: pixel-structur characters shown figure above refer character-adresses shown table below:
VPS/PDCPro Specification Version 3.00
5652-2X
Application notes
10.1. After reset starting sequenz After reset maximum-time 50us needed which initializes itself. After this time, following registers their default-values: ADR_POINTER_0, ADR_POINTER_1, DATA_PORT, ACQ-Control SYNCHRONISATION LEVELS_AND_CHANGE. other register-values random-values must initialized with IIC-bus.
VPS/PDCPro Specification Version 3.00
5652-2X
After time 50us, first IIC-access executed. Within first IIC-bus-accesses following procedure should carried out: Procedure register-bits OSC_SYS0 OSC_SYS1 register SYNCHRONISATION have values according used external clock-source (1FSC, 2FSC, 4FSC crystal). Procedure bits OSC_SYS0 OSC_SYS1 read compared expected values which have been written procedure this assured, that there been transmissionerror there been transmission error please with procedure otherwise please back procedure Procedure Setting RELEASE register LEVELS_AND_CHANGE from high low. This will initialize internal clock-generation-circuits according settings bits OSC_SYS0 OSC_SYS1. once register-bit RELEASE cannot anymore. Setting IIC_SWITCH register SYNCHRONISATION from high low. This will assure highest IIC-bus noise-surpressing.
VPS/PDCPro Specification Version 3.00
5652-2X
Errata Sheet
Hardware Items
Item
Designation
Wrong horizontal Start-Position character-fields using zoom
Description position characters shifted left dependency -horizontal zoom-factor character zoomed modulo start-position characterfield dependencies shown following table below (Clocks clocks which characters moved left; pixel pixels which characters moved left; pixelfrequency half clock-frequency):
Affected Version
Correction Schedule
zoom
clocks
pixel clocks
pixel clocks
pixel
clocks pixel
Item
Designation
Description
Affected Version
Correction Schedule
display horizontal start-position character-field horizontal start- larger than 118, character-field will vanish position>118 there unexpected line beginning
character-field. Uncritical most applications, because such large horizontal start-positions aren't choosen practise.
display large vertical startposition
vertical start-position character-field >100, will vanish. those large vertical start-positions shouldn't visible screen normal TV-set all, this should uncritical applications.
VPS/PDCPro Specification Version 3.00
5652-2X
Item
Designation
Description
Affected Version
Correction Schedule
verti- zoom-factor used (and this zoom-factor visible screen), next character-row will allready start (instead 12). Moreover
will fail all.
PDC-Format1 Byte
Byte PDC-mode Format 8-30-1 falsely par- checked (e.g. byte hasn't parity, else
Forbidden verti- following vertical horizontal start-positions horizon- allowed (due different failures like startan offset according expected start-position): positions character-field
forbidden positions fullpage-mode: VPOS 0.16 HPOS HPOS k*4; HPOS >=116 forbidden positions mixed-mode: VPOS VPOS >100 HPOS HPOS k*4; >=120
Software/Firmware Items (optional)
Item Designation Description Affected Version Correction Schedule
Software/Firmware Items (optional)
Item
Workaround Description Following algorithm used workaround Item-No.H5: CASE MSB(byte13) byte13 (6:0) even parity THEN MSB(byte13):=0; ELSE MSB(byte13):=1; byte13 (6:0) even parity THEN MSB(byte13):=1; ELSE MSB(byte13):=0; CASE;
5652-2X
Micronas GmbH Hans-Bunte-Strasse D-79108 Freiburg (Germany) P.O. D-79008 Freiburg (Germany) Tel. +49-761-517-0 +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed Germany Order 6251-559-1
information data contained this data sheet without commitment, considered offer conclusion contract, shall they construed create liability. issue this data sheet invalidates previous issues. Product availability delivery exclusively subject respective order confirmation form; same applies orders based development samples delivered. this publication, Micronas GmbH does assume responsibility patent infringements other rights third parties which result from use. Further, Micronas GmbH reserves right revise this publication make changes content, time, without obligation notify person entity such revisions changes. part this publication reproduced, photocopied, stored retrieval system, transmitted without express written consent Micronas GmbH.
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