DVB-S Frontend (QPSK demodulation FEC) Preliminary Description CX

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DVB-S Frontend (QPSK demodulation FEC) Preliminary Description CX

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CXD1961AQ
DVB-S Frontend (QPSK demodulation FEC) Preliminary
Description CXD1961AQ single chip compliant Satellite Broadcasting Frontend including dual converter analog baseband input, QPSK demodulator, Viterbi decoder Reed-Solomon decoder Energy Dispersal descrambler. suitable Integrated Receiver Decoder. (Plastic)
Features Dual converter Absolute Maximum Rating 25°C, QPSK demodulator Power Supply -0.5 +4.6 Multi-symbol rate operation Input Voltage -0.5 Nyquist Roll filter 0.35) Output Voltage VOUT -0.5 Clock recovery circuit Voltage VI/O -0.5 Carrier recovery circuit Vcpuif -0.5 +5.5 control (PWM output) Storage Temperature Tstg +150 Viterbi decoder Constraint length Recommended Operating Condition Truncation length 75°C, monitor QPSK demodulator output Power Supply 3.15 3.45 Frame synchronization circuit Input High level Convolutional de-interleaver Input level Reed-Solomon decoder (204,188) monitor Viterbi decoder output Energy dispersal descrambler interface circuit interface input capability) Package 100pin Operating frequency 30MSPS Power consumption 750mW (@3.3V 30MSPS typical) Process 0.4µm CMOS Technology Application DVB-S (Satellite)
Sony reserves right change products specifications without prior notice. This information does convey license implication otherwise under patents other right. Application circuits shown, any, typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits.
PE97854-PS
CXD1961AQ
OPOUT
VCOEN
OPOUT
OPXIN
AVS1
AVS2
AVS4
AVD4
FSYNC
VCOC
AVD1
QSYNC
Block Diagram
AVD0
AVD2
AVS0 analog Sampling Clock VDD9 QPSK Demodulator VSS8 VDD8 Viterbi Decoder AGCPWM VSS7 VDD7 De-interleaver
VDD0 VSS0 TEST1
TEST2 TEST3 TEST4 VDD1 VSS1 SDAT/SCL SCLK SEN/SDA VDD2 VSS2 TEST6 TEST7 CK8OUT RESET VDD3 VSS3 PKTCLK BYTCLK PKTERR DATA0 DATA1
Oscillator
VSS9
AVS3 AVD3 TEST22 TEST21 TEST20 VSS6 VDD6 TEST19 TEST18
Reed-Solomon Decoder
Energy Dispersal
decoded data clock
DATA4
TEST8
VSS5
TEST12
TEST11
TEST10
Typical Block Diagram
detector SONY CXD1961AQ 479.5MHz Reference Crystal Clock QPSK Data
Micro Controller
TEST13
TEST14
TEST15
TEST16
TEST17
DATA3
DATA2
DATA5
DATA6
DATA7
TEST9
VDD4
VDD5
VSS4
CXD1961AQ
Functional Description Converters CXD1961AQ dual converters quantize analog baseband signal. sampling rate times symbol rate. input range determined external resisters. reference circuit (1). offset cancellation function setting register 1E,1F(hex). Clock Recovery Circuit CXD1961AQ operate multiple symbol rates between 30MSPS. Initial sampling clock frequency control word register (hex). This control word written numerically controlled oscillator (NCO). internal clock recovery loop feeds clock error data above provide sampling timing correction. relation between symbol rate control word (symbol rate) [23:0] Fcrystal (Hz) where [23:0] control word Fcrystal crystal frequency (Hz). clock recovery loop coefficient loop gain setting I/Fregister (hex) accordingly. reference circuit (2). recovered symbol clock monitored There three internal sub-registers save control word. setting number preset subregister, control word corresponded certain symbol rate internal NCO. Contents sub-register deleted power reset Refer explanation register (hex). Carrier Recovery Circuit carrier frequency offset which remains analog baseband input compensated internal digital costas loop. capture range ±Rs/8 (Rs: symbol rate). When carrier capture performed, QPSK lock flag QSYNC goes high. QSYNC output register (hex). QPSK synchronization, carrier offset estimation value output register (hex) [7:0]. frequency offset (carrier offset) [7:0] (Hz) where AFC7 sign that represents direction offset. Nyquist Roll Filter Nyquist roll filter each channel embedded. roll factor 0.35.
CXD1961AQ
Auto Gain Control comparing demodulated amplitude reference level which register (hex), control signal generated output polarity reversed setting register (hex). Tuner interface, reference circuit (4). Viterbi Decoder punctured decoding Viterbi decoding performed demodulated data. punctured rate programmable from 7/8. When punctured mapping performed, Viterbi lock flag register (hex) goes one. error count QPSK demodulator output estimated output register (hex) data. Frame synchronization Deinterleaver detecting MPEG2 sync word (hex), synchronization data packet achieved, convolutional deinterleaver then recovers original data order. Reed-Solomon Decoder systems, parity bytes added data bytes, that error bytes correctable Reed-Solomon decoder. there more than error bytes packet, error correction performed packet error flag PKTERR (Pin goes high during packet indicate that packet correctable. second byte uncorrectable packet also becomes one. error count Viterbi decoder output estimated output every 1280 packet (=204 1280 bit) register (hex) resolution bits. Energy Dispersal Descrambler Energy dispersal descrambling represented polynomial initial sequence loaded when inverted MPEG sync word (hex) detected. When MPEG sync word including inverted detected every bytes, lock flag whole "FSYNC" goes high. FSYNC output register (hex).
CXD1961AQ
(10) Interface CXD1961AQ interface. Serial clock serial data Slave address "1101 111" (DChex). <Write data> During write operation, second byte input sub-address start position. third byte then forms data written start register. Successive data bytes written successive subaddress registers (hex). Note that registers sub-addresses (hex) (hex) read only. Slave address 1101 address (hex) Input data sub-address (hex) Input data sub-address (hex)
STA: start condition STP: stop condition
ACK: acknowledge XACK: acknowledge
<Read operation> Before read operation, sub-address start register read input using write operation, terminated with stop condition. Read operation then begins with second byte which data start register. Data successive sub-address registers read successively following second byte. registers read. Slave address 1101 address (hex) Output data sub-address (hex)
Slave address 1101
Output data sub-address (hex)
Both have input capability.
XACK
CXD1961AQ
Configuration
OPOUT
VCOEN
OPOUT
OPXIN
AVS1
AVD2
AVS2
AVS4
AVD4
FSYNC
AVD1
VCOC
QSYNC
AVD0
AVS0 VDD0 VSS0 TEST1 TEST2 TEST3 TEST4 VDD9 VSS8 VDD8 AGCPWM VSS7 VDD7 AVS3 AVD3 TEST22 TEST21 TEST20 VSS6 VDD6 TEST19 TEST18
VDD1 VSS1 SDAT/SCL SCLK SEN/SDA VDD2 VSS2 TEST6 TEST7 CK8OUT RESET VDD3 VSS3 PKTCLK BYTCLK PKTERR DATA0 DATA1
DATA3
DATA7
VDD5
TEST12
TEST11
TEST10
TEST13
TEST14
TEST15
TEST16
DATA2
DATA5
DATA6
VSS4
TEST9
VDD4
DATA4
TEST8
VSS5
TEST17
VSS9
CXD1961AQ
List Symbol AVS0 VDD0 VSS0 TEST1 VDD1 VSS1 SDAT/SCL SCLK SEN/SDA VDD2 VSS2 TEST6 TEST7 CK8OUT RESET VDD3 VSS3 PKTCLK BYTCLK PKTERR DATA0 VDD4 VSS4 DATA5 TEST8 VDD5 VSS5 TEST13 TEST16 Analog Ref. voltage input Digital Digital CMOS input Connection Digital Digital 3-state CMOS output 3-state CMOS output with Pull Digital Digital Input with pull Input with pull CMOS input Input with pull CMOS output Input with pull Input with pull down Digital Digital 3-state CMOS output 3-state CMOS output 3-state CMOS output 3-state CMOS output Digital Digital 3-state CMOS output CMOS Digital Digital CMOS CMOS input type
CXD1961AQ
Symbol VDD6 VSS6 TEST20 AVD3 AVS3 VDD7 VSS7 AGCPWM VDD8 VSS8 VDD9 VSS9 QSYNC FSYNC AVD4 AVS4 CPOUT AVD2 VCOC OPXIN OPOUT AVS2 VCOEN AVD1 Digital Digital CMOS input input open drain Crystal Crystal Oscillator output Oscillator input CMOS CMOS Digital Digital CMOS output CMOS CMOS output Digital Digital CMOS output Digital Digital CMOS output CMOS output Analog Analog 3-state CMOS output Analog Analog input Analog input Analog output Analog CMOS input Ref. voltage input Analog
type
CXD1961AQ
Symbol AVS1 AVD0 Analog input Analog Ref. voltage input Ref. voltage input Analog Analog input
type
Note) Apply 0.1µF capacitor every power supply terminal reference voltage input (RB0, RB1, RT0, RT1).
CXD1961AQ
Explanation Converter Function Analog signal input reference level input Bottom reference level input Analog power supply (+3.3V) Analog ground reference circuit input name AVD0 AVS0 input name AVD1 AVS1
Clock Recovery 2-1. Crystal Function Crystal oscillator (output) Crystal oscillator (input) Crystal oscillator power supply (+3.3V) Crystal oscillator ground reference circuit name AVD3 AVS3
2-2. OP-Amp Function Charge Pump output Charge pump power supply (+3.3V) Charge pump ground control voltage input enable enable) OP-Amp negative input OP-Amp output OP-Amp power supply (+3.3V) OP-Amp ground reference circuit name CPOUT AVD4 AVS4 VCOC VCOEN OPXIN OPOUT AVD2 AVS2
CXD1961AQ
2-3. Clock Recovery Function Clock error output (for clock recovery VCXO) Recovered symbol clock output (switchable sampling clock output) name
Carrier Recovery Function Carrier lock flag lock) name QSYNC
Function control data (PWM output) reference circuit name AGCPWM
Viterbi Decoder Function Viterbi clock output Viterbi decoded data output name
These pins fixed ground setting register (hex).
Frame Synchronization Function Frame synchronization flag sync) name FSYNC
CXD1961AQ
Reed-Solomon Decoder/Data output Function Data output clock (parallel mode) Byte clock (Serial mode) Viterbi clock Packet clock data, parity) Uncorrectable packet flag Data output (Parallel mode) data (Serial mode) serial data (MSB first) Data output (Parallel mode) DATA7 (Serial mode) Hi-Z name BYTCLK PKTCLK PKTERR DATA0
DATA1 DATA5
Output mode (Serial Parallel) switched setting register (hex).
Interface Function serial clock input serial data name
Reset Function Reset reset/fix normal use) name RESET
Power Supply Function Digital power supply (+3.3V) name
VDD0 VSS0
Digital ground Apply 0.1µF capacitor every power supply terminal.
CXD1961AQ
Test Others Function Test mode enable (Fix normal use) Test clock (Fix normal use) Test mode Control (Fix normal use) Test input (Fix Test output (connect nothing) Test (Fix Tuner interface wire mode) Serial data output (I2C mode) Serial clock output Tuner interface wire) Clock output Tuner interface wire mode) Latch enable output (I2C mode) Serial data Clock output (crystal frequency/8) Connection name
TEST1 TEST7 TEST16 TEST20 TEST6 TEST8 TEST13 SDAT/SCL SCLK SEN/SDA CK8OUT
CXD1961AQ
Electrical Characteristics Description Symbol rate Crystal Frequency DATA0 BYTCLK falling edge (Parallel output mode PBYCK PKTCLK BYTCLK falling edge (Parallel output mode PBYCK PKTERR BYTCLK falling edge (Parallel output mode PBYCK DATA0 BYTCLK rising edge (Parallel output mode PBYCK PKTCLK BYTCLK rising edge (Parallel output mode PBYCK PKTERR BYTCLK rising edge (Parallel output mode PBYCK Serial output mode cycle time (Serial output mode) DATA0 BYTCLK hold time (Serial output mode) PKTCLK, PKTERR BYTCLK setup time (Serial output mode) PKTCLK, PKTERR BYTCLK hold time (Serial output mode) Serial clock cycle time Data setup time Data hold time Symbol Fxtal tDB0 tPB0 tEB0 tDB1 tPB1 tEB1 tSOC tDBH tPBS tEBH FscI tDSI tDHI Min.
75°C, 3.3V) Typ. Max. Unit MSPS
Timing Waveform Parallel output mode, PBYTCK
tPB0 tEB0
tPB0
tEB0
PKTCLK
PKTERR BYTCLK
DATA [0:7] tDB0 tDB0
CXD1961AQ
Parallel output mode, PBYTCK
tPB1 tEB1
tPB1
tEB1
PKTCLK
PKTERR BYTCLK
DATA [0:7] tDB1 tDB1
Serial output mode (Example 3/4)
tPBS tEBH tEBH
PKTCLK tSOC
PKTERR
BYTCLK
DATA0
tDBH
interface
0.6µs tDSI
1.3µs 1.3µs tDHI 0.6µs 0.6µs
CXD1961AQ
Interface Registers address (hex) READ REGISTER WRITE REGISTER Name INP_LEV PWM_VAL AFC_VAL bit7 INP7 PWM7 AFC7 bit6 INP6 PWM6 AFC6 QBEC6 bit5 INP5 PWM5 AFC5 bit4 INP4 PWM4 AFC4 bit3 INP3 PWM3 AFC3 QBEC3 bit2 INP2 PWM2 AFC2 QBEC2 bit1 INP1 PWM1 AFC1 QBEC1 bit0 INP0 PWM0 AFC0 QBEC0 QBEC8 VBEC0 VBEC8 VBER0 OFQ0 OFC0 SRS0
QBEC_LO QBEC7
QBEC5 QBEC4
QBEC15 QBEC14 QBEC13 QBEC12 QBEC11 QBEC10 QBEC9 VBEC6 VBEC5 VBEC4 VBEC3 VBEC2 VBEC1
QBEC_UP VBEC7 VBEC_LO
VBEC15 VBEC14 VBEC13 VBEC12 VBEC11 VBEC10 VBEC9 OFI3 OFI2 CM14 OFC6 MQS2 RATE2 DOH1Z OFI1 CM13 OFC5 MQS1 RATE1 DOPS OFI0 FSYNC CM12 OFC4 MQS0 QBER1 OFQ3 QBER0 OFQ2 VBER1 OFQ1 OFC1 SRS1
VBEC_UPR VCOLK CODE/BER DC_OFST FLAG CM_LOW CM_UPR CM15 OFC7 MQS3
VSYNC QSYNC CM11 OFC3 CM10 OFC2
RATE0 SRSAVE PPKER
CAR_OFST PBYCK MQS/CLK CODE/SRS OUT_CNT MOD_CNT AGC/RST SINV MAGC QTH5 VTH4 TUD17 TUD27 TUD37
PPKCK MBYCK VCKVDT SEL09
SYSSEL DFSKIP RSSKIP TUNSEL TUNEN MFSYNC AGCLP PAGC QTH4 VTH3 TUD16 TUD26 TUD36 TUD46 TUD56 NCO6 NCO14 NCO22 MVSYNC CKVSEL QPRST QTH3 VTH2 TUD15 TUD25 TUD35 TUD45 TUD55 NCO5 NCO13 NCO21 QTH2 VTH1 TUD14 TUD24 TUD34 TUD44 TUD54 NCO4 NCO12 NCO20 BSI0 TCAR1 QTH1 VTH0 TUD13 TUD23 TUD33 TUD43 TUD53 NCO3 NCO11 NCO19 VTRST QTH0 TVS2 TUD12 TUD22 TUD32 TUD42 TUD52 NCO2 NCO10 NCO18 RSRST VCORST TQBEC1 TQBEC0 TVS1 TUD11 TUD21 TUD31 TUD41 TUD51 NCO1 NCO9 NCO17 TVS0 TUD10 TUD20 TUD30 TUD40 TUD50 NCO0 NCO8 NCO16 BSQ0
TUN_DAT1 TUD47 TUN_DAT2 TUD57 TUN_DAT3 NCO7
TUN_DAT4 NCO15 TUN_DAT5 NCO23
SYM_RATE1 CALRST CADRST CLKRST SYM_RATE2 SYM_RATE3 BSI3 BSI2 GAIN1 TQS0 BSC6 REF6 BSI1 GAIN0
RANGE FSYSEL FSYTHD BSQ3 TCAR0 BSQ2 BSQ1
CAR_RST RSTEN N.A. DC_BIAS CAR/DC TQS1 BSC7 REF7
MOFST OFSTEN OFSTGN
FLOOP TRACK FLMOD FLSTEP QTLEV1 QTLEV0 BSC5 REF5 BSC4 REF4 BSC3 REF3 BSC2 REF2 BSC1 REF1 BSC0 REF0
Input write registers which assigned ("-").
CXD1961AQ
Description Interface Registers address (hex) INP7 INP0 (MSB) (LSB) Read INP_LEV Input level estimation
Upper analog input. (Ex.) value about (hex) when analog amplitude half input range.
address (hex) PWM7 PWM0 (MSB) (LSB) address (hex) AFC7 AFC0 (MSB) (LSB) AFC7: Sign
Read
PWM_VAL
output value
output value control.
Read
AFC_VAL
Carrier offset value
Carrier offset estimation Carrier offset (Symbol rate) [7:0] (Hz) Ex.) 20MSPS [7:0] 11110000 (bin) offset 20MHz (-16) -625kHz this case, changing tuner value -625kHz, offset cancelled. Read Read QBEC_LOW QBEC_UPR error count QPSK output error count QPSK output
address (hex) address (hex) QBEC15 QBEC0 (MSB) (LSB)
error count QPSK output bit). Measuring period TQBEC [1:0] register (hex) ratio QBEC [15:0] measuring period. QBEC [15:0] valid when QSYNC, VSYNC FSYNC High.
address (hex) address (hex) VBEC15 VBEC0 (MSB) (LSB)
Read Read
VBEC_LOW VBEC_UPR
error count Viterbi output error count Viterbi output
error count Viterbi output bit). Measuring period 1280 2,088,960. ratio VBEC [15:0] 2,088,960. VBEC [15:0] valid when QSYNC, VSYNC FSYNC High.
CXD1961AQ
address (hex)
Read
CODE/BER
Code rate
Current punctured rate (code rate) Code rate
QBER1 QBER0
level indicator QPSK output. This indicator valid when QSYNC, VSYNC FSYNC High TQBEC [1:0] (bin). TQBEC [1:0] register (hex). QBER1 QBER0 Error Rate more than 10-2 10-3 <10-2 10-4 <10-3 less than 10-4
VBER1 VBER0
level indicator Viterbi output. This indicator valid when QSYNC, VSYNC FSYNC High. VBER1 VBER0 Error Rate more than 10-2 10-3 <10-2 10-4 <10-3 less than 10-4
CXD1961AQ
address (hex) OFI3 OFI0 OFI3: Sign OFQ3 OFQ0 OFQ3: Sign
Read
DC_OFST
offset level converter
offset value channel converter.
offset value channel converter. both cases, value depend operation mode. MOFST (reg. Operating mode Offset bias mode Offset cancel mode [3:0] [3:0] Current offset value. Compensation value each converter.
Refer explanation register (hex).
address (hex)-A
Read
FLAG
Status Flag
Register (hex) irregular structure. register correspond sub-address (hex). When SEL09 register (hex) register (hex)-A selected, else register (hex)-B selected. VCOLK This become case abnormal oscillation embedded VCO.
(Tuner interface mode) This becomes case acknowledge from tuner PLL. This becomes iwhen Frame synchronization achieved.
FSYNC
VSYNC
This becomes when punctured mapping synchronization achieved.
QSYNC
This becomes when carrier lock achieved.
This always
address (hex)-B address (hex)
Read Read
CM_LOW CM_UPR
Constellation Monitor Constellation Monitor
These registers access when SEL09 register (hex) CM15 (MSB) (LSB) Monitor value QPSK constellation. This value depends reference (reg. (hex)). Refer Fig.1.
CXD1961AQ
address (hex) OFC7 OFC0 OFC7: Sign
Read
CAR_OFST
Carrier Capture offset value
Offset frequency point carrier capture (Latest offset frequency output register (hex)) (offset frequency) (Symbol rate) [7:0] 1024 (Hz) Ex.) 20MSPS [6:0] 11110000 (bin) (offset freq.) 20MHz (-16) 1024 -312.5kHz Write MQS/CLK Qsync mode/Clock recovery
address (hex) MQS3 MQS0 (MSB) (LSB)
Threshold carrier lock detection
Clock recovery loop filter coefficient Max. min. Clock recovery loop filter gain Min. Max. Clock recovery range approximately ±200ppm with (1:0)
address (hex) RATE2 RATE0
Write
CODE/SRS
Code rate select/Symbol rate select
Code rate setting RATE2 RATE1 RATE0 Code rate
SRSAVE
saving several control word registers initially, symbol rate changed setting number register which desired control word saved. There three registers.
CXD1961AQ
SRS1 SRS0
symbol rate directly without above function) SRSAVE [1:0] (1,1) control word registers (hex). save control word registers) SRSAVE register ((0, [1:0]. Then control word registers (hex). control word both clock recovery circuit selected register. symbol rate with above function) SRSAVE register control word set. control word saved register clock recovery circuit.
address (hex) PBYCK
Write
OUT_CNT
Output control polarity falling edge rising edge
BYTCLK polarity
DOH1Z
Output Hi-Z mode (PKTCLK, BYTCLK, PKTERR, DATA [7:0])
DOPS
Parallel output mode Serial output mode Refer Electric characteristics
PPKER
PKTERR polarity
PKTERR: uncorrectable packet PKTERR: uncorrectable packet
PPKCK
PKTCLK polarity
PKTCLK: data parity PKTCLK: data parity
MBYCK
BYTCLK mask mode this mode BYTCLK forced during parity data output
VCKVDT
Viterbi decode data (Pin clock (Pin output enable fixed low.
SEL09
Read register (hex)-A, selection (hex)-A selected (hex)-B selected
CXD1961AQ
address (hex) SINV
Write
MOD_CONT
Mode Control
exchange normal operation
SYSSEL
assigned. Input
DFSK1P
Nyquist roll filter bypass mode
RSSK1P
Reed-Solomon decoder bypass mode
TUNSEL
Tuner interface mode
mode wire mode
TUNEN
Tuner interface enable TUNSEL Don't care TUNEN Hi-Z clock data Hi-Z Hi-Z clock Hi-Z data Latch Enable mode wire
Refer reference circuit (5).
MFSYNC
Parameter frame synchronization protection normal operation mode powerful protection mode
AGCLP
loop filter gain normal operation large gain
CXD1961AQ
address (hex) MAGC
Write
AGC/RST
Reset
mode normal mode control mode normal mode, output controlled that (register 00hex) should become approximately equal reference level register (hex). control mode, data register (hex) directly converted output.
PAGC
tuner whose gain increases higher control voltage tuner whose gain increases lower control voltage Select mode according tuner type.
polarity
MVSYNC
Input
CKVSEL
(Pin output mode symbol clock output sampling clock output
QPRST
QPSK block reset (set normal operation) reset QPSK block, this then this again.
VTRST
Viterbi block reset (set normal operation) Reset operation same QPRST.
RSRST
Deinterleaver Reed-solomon block reset (set normal operation) Reset operation same QPRST.
VCORST
block reset (set normal operation) Reset operation same QPRST.
CXD1961AQ
address (hex) QTH5 QTH0 (MSB) (LSB)
Write
Qsync Threshold QBEC period
Threshold carrier lock detection These parameters relate QTLEV [1:0] register (hex) reference (hex). Ex.) QTLEV [1:0] (hex) [5:0] 101000
TQBEC1 TQBEC0
Count period QPSK error count TQBEC1 TQBEC0 Count period
Select TQBEC [1:0] QPSK indicator (register (hex))
address (hex) VTH4 VTH0
Write
Viterbi sync threshold period
Threshold punctured mapping synchronization 11110: Min. 00000: Max.
TVS2 TVS0
Detection period punctured mapping synchronization 110: 000: Max. code rate VTH4 VTH0, TVS2 TVS0 (hex) (hex) (hex) (hex) (hex) (hex) (hex)
CXD1961AQ
address (hex) address (hex) address (hex) address (hex) address (hex) (I2C mode)
Write Write Write Write Write
TUN_DAT1 TUN_DAT2 TUN_DAT3 TUN_DAT4 TUN_DAT5
Tuner control data Tuner control data Tuner control data Tuner control data Tuner control data
TUNSEL TUNEN register (hex). (hex): Tuner slave address (write mode) (hex): Write data (tuning parameter) starts write operation when data setting register (hex) finished. case acknowledge from tuner register (hex)-A TUNSEL TUEN register (hex). bits data (register (hex) upper 4bit register (hex)) transmitted serially. start operation, dummy data setting register (hex) needed. Refer reference circuit (5).
wire mode)
address (hex) address (hex) address (hex) NCO23 NCO0 (MSB) (LSB)
Write Write Write
SYM_RATE1 SYM_RATE2 SYM_RATE3
Control word multi-rate oscillation Control word multi-rate oscillation Control word multi-rate oscillation
relation between symbol rate control word [23:0] (symbol rate) (crystal frequency) Ex.) Symbol rate 20MSPS crystal 32MHz [23:0] 10-6 2,621,440 NCO21 NCO19 other
CXD1961AQ
address (hex) CARRST
Write
CAR_RST
Carrier loop reset
Carrier loop filter reset Reset operation same QPRST (register 10hex)
CADRST
Carrier recovery frequency loop reset Reset operation same QPRST (register 10hex)
CLKRST
Clock recovery loop reset Reset operation same QPRST (register 10hex)
RANGE
Carrier capture range
Carrier capture range ±Rs/8 Carrier capture range ±Rs/16
FSYSEL
Frame synchronization detector mode Hard decision Soft decision
FSYTHD
Frame synchronization threshold
High
address (hex)
Write Input bits.
N.A.
Assigned
address (hex)
Write
DC_BIAS
Converter DC_BIAS
offset added output converter when MOFST register (hex) BSI3 BSI0 offset channel converter. BSI3: sign Offset range from
BSQ3 BSQ0
offset channel converter. BSI3: sign Offset range from
CXD1961AQ
address (hex) RSTEN
Write
CAR/DC
Carrier recovery offset
1:Carrier loop filter reset enable (Set normal operation)
GAIN1 GAIN0
Gain setting carrier recovery loop GAIN1 GAIN0 Gain (default
TCAR1 TCAR0
Mode setting carrier recovery frequency loop: default TCAR [1:0]
MOFST
converter offset cancellation mode converter offset addition mode
OFSTEN
converter offset control (cancel add) enable converter offset control (cancel add) disable
OFSTGN
converter offset cancellation loop filter gain
CXD1961AQ
address (hex) TQS1 TQS0
Write
CAR_MODE
Carrier recovery mode
Carrier lock detection period min. max. Default [1:0]
FLOOP
Carrier recovery phase loop Carrier recovery phase frequency loop (default)
TRACK
default:
FLMOD
Carrier offset frequency [6:0]. Carrier offset frequency internal loop. (default)
FLSTEP
default:
QTLEV1 QTLEV0
Gain carrier lock detection circuit. Default QTLEV [1:0]
address (hex) BSC7 BSC0 BSC7: sign
Write
CAR_BIAS
Carrier frequency offset bias
Carrier offset frequency setting This mode good when FLMOD (Carrier offset) (Symbol rate) [7:0] 1024 (Hz)
address (hex) AGCR7 AGCR0
Write
AGC_REF
reference
Input level reference operation Refer explanation register (hex)
CXD1961AQ
Application Circuit Converter
Analog 0.1µF 0.1µF Connect AVD0 AVD1 analog +3.3V supply
Baseband input Baseband input
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
AVD0
AVS1
Analog 0.1µF AVS0 CXD1961AQ
Clock Recovery circuit
Connect AVD2 AVD4 analog +3.3V supply
Analog 2.2µF 0.1µF 100k
4.7µF
0.1µF Analog
OPOUT
AVD2
VCOC
AVS2
VCOEN
CXD1961AQ
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
CPOUT
OPXIN
AVD4
AVS4
AVD1
CXD1961AQ
Crystal
Crystal 470k AVS3 Digital
Crystal Daishinku AT-49 32.0MHz Connect AVD3 ditital +3.3V supply
AVD3 CXD1961AQ 0.1µF
This example control voltage from Power supply OP-Amp
AGCPWM
OP-Amp tuner input 5.6k
0.1µF
CXD1961AQ
Analog
Tuner Interface wire type) suitable Plessey SP5658
ENABLE DATA CLOCK SEN/SDA SP5658 CXD1961AQ SCLK SDAT/SCL
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
CXD1961AQ
Tuner Interface (I2C type) suitable Plessey SP5659 etc. bytes data written)
+3.3V SCLK SDAT/SCL
SEN/SDA SP5659 CXD1961AQ
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
CXD1961AQ
Appendix
Fig.1 Constellation monitor output
Constellation monitor output
[dB]
This figure example when AGCREF (hex). monitor output value proportional AGCREF. Monitor output [15:0] register 09-B (hex) (hex)
CXD1961AQ
Package Outline
Unit:
100PIN (PLASTIC)
23.9 20.0 0.15 0.05
14.0 17.9
15.8
0.65
0.15
0.24 0.35 2.75 0.15
0.05
0.15
DETAIL
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g

DVB-S Frontend (QPSK demodulation FEC) Preliminary Description CX

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