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SMJ320C26 DIGITAL SIGNAL PROCESSOR
100-ns Instruction Cycle Time 1568 Words Configurable On-Chip
Data/Program Words On-Chip Program 128K Words Data/Program Space Pin-for-Pin Compatible with SMJ320C25 Input Output Channels 16-Bit Parallel Interface Directly Accessible External Data Memory Space Global Data Memory Interface 16-Bit Instruction Data Words 32-Bit Accumulator Single-Cycle Multiply/Accumulate Instructions 16-Bit Scaling Shifter Manipulation Logical Instructions Instruction Support Floating-Point Operations, Adaptive Filtering, Extended-Precision Arithmetic Block Moves Data/Program Management Repeat Instructions Efficient Program Space Eight Auxiliary Registers Dedicated Arithmetic Unit Indirect Addressing Serial Port Direct Codec Interface Synchronization Input Multiprocessor Configurations Wait States Communications Slow Off-Chip Memories/Peripherals On-Chip Timer Control Operations Three External Maskable User Interrupts
68-PIN GRID ARRAY CERAMIC PACKAGE (TOP VIEW)
Assignments Table (Page Nomenclature Table (Page location description pins.
Input Polled Software Branch
Instruction Programmable Output Signalling External Devices 1.6-µm CMOS Technology Single Supply Packaging: 68-Pin Leaded Ceramic Chip Carrier Suffix) 68-Pin Leadless Ceramic Chip Carrier Suffix) 68-Pin Grid Array Ceramic Package Suffix) Military Operating Temperature Range 125°C
description
SMJ320C26 Digital Signal Processor member TMS320 family VLSI digital signal processors peripherals. TMS320 family supports wide range digital signal processing applications, such telecommunications, modems, image processing, speech processing, spectrum analysis, audio processing, digital filtering, high-speed control, graphics, other computation intensive applications.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2001, Texas Instruments Incorporated
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
description
With 100-ns instruction cycle time innovative memory configuration, SMJ320C26 performs operations necessary many real time digital signal processing algorithms. Since most instructions require only cycle, SMJ320C26 capable executing million instructions second. On-chip programmable data/program 1568 words bits, on-chip program 256-words, direct addressing 64K-words external program 64K-words data memory space, multiprocessor interface features sharing global memory minimize unnecessary data transfers take full advantage capabilities processor. SMJ320C26 scaling shifter 16-bit input connected data 32-bit output connected ALU. scaling shifter produces left shift bits input data, programmed instruction. LSBs output filled with zeroes, MSBs either filled with zeroes sign-extended, depending upon status programmed into (sign-extension mode) status register ST1.
68-PIN LEADED LEADLESS CERAMIC CHIP CARRIER PACKAGES (TOP VIEW)
MP/MC HOLD READY CLKR CLKX SYNC INT0 INT1 INT2 IACK CLKOUT1 CLKOUT2 HOLDA X2/CLKIN STRB
Assignments Table (Page Nomenclature Table (Page location description pins.
PGA/LCCC/JLCC ASSIGNMENTS
FUNCTION K1/26 K2/28 L3/29 K3/30 L4/31 K4/32 L5/33 K5/34 K6/36 L7/37 K7/38 L8/39 FUNCTION CLKOUT1 CLKOUT2 CLKR CLKX K8/40 L9/41 K9/42 L10/43 B7/68 G11/50 C11/58 D10/57 B9/64 A9/63 F1/18 E2/17 FUNCTION E1/16 D2/15 D1/14 C2/13 C1/12 B2/11 A2/9 B3/8 A3/7 B4/6 A4/5 B5/4 FUNCTION HOLD HOLDA IACK INT0 INT1 A5/3 B6/2 J1/24 K10/45 E11/54 J2/25 F10/53 A7/67 E10/55 B11/60 G1/20 G2/21 FUNCTION INT2 MP/MC READY STRB SYNC H1/22 J11/46 A6/1 C10/59 J10/47 B8/66 A8/65 H11/48 H10/49 F2/19 A10/61 B10/62 FUNCTION X2/CLKIN H2/23 L6/35 B1/10 K11/44 L2/27 D11/56 G10/51 F11/52
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
NOMENCLATURE
NAME X2/CLKIN CLKOUT1 CLKOUT2 D15-D0 A15-A0 STRB INT2, INT1, INT0 MP/MC IACK READY HOLD HOLDA SYNC CLKR CLKX I/O/Z I/O/Z supply pins. Ground pins. Output from internal oscillator crystal. Input internal oscillator from crystal external clock. Master clock output (crystal CLKIN frequency/4). second clock output signal. 16-bit data (MSB) through (LSB). Multiplexed between program, data spaces. 16-bit address (MSB) through (LSB). Program, data space select signals. Read/write signal. Strobe signal. Reset input. External user interrupt inputs. Microprocessor/microcomputer mode select pin. Microstate complete signal. Interrupt acknowledge signal. Data ready input. Asserted external logic when using slower devices indicate that current transaction complete. request signal. Asserted when SMJ320C26 requires access external global data memory space. External flag output (latched software programmable signal). Hold input. When asserted, SMJ320C26 goes into idle mode places data address control lines high-impedance state. Hold acknowledge signal. Synchronization input. Branch control input. Polled BIOZ instruction. Serial data receive input. Clock input serial port receiver. Frame synchronization pulse receive input. Serial data transmit output. Clock input serial port transmitter. DEFINITION
I/O/Z Frame synchronization pulse transmit. configured either input output. I/O/Z denotes input/output/high-impedance state.
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
functional block diagram
X2/CLKIN CLKOUT1 CLKOUT2 PROGRAM SYNC
STRB READY HOLD HOLDA IACK MP/MC INT(2-0) A15-A0 PFC(16) CONTROLLER
QIR(16) IR(16) ST0(16) ST1(16) RPTC(8) IFR(6) CLKR CLKX RSR(16) XSR(16) DRR(16) DXR(16) TIM(16) PRD(16) IMR(6) GREG(8)
MCS(16) ADDRESS PROGRAM (256 INSTRUCTION
PC(16) STACK
D15-D0
PROGRAM
DATA ARP(3) AR0(16) AR1(16) AR2(16) AR3(16) AR4(16) AR5(16) AR6(16) AR7(16) DP(9) FROM SHIFTER(0-16)
TR(16) MULTIPLIER PR(32) SHIFTER (6.0.1.4)
ARS(3)
ARAU(16)
DATA BLOCK
DATA/PROG (512 BLOCK
DATA/PROG (512 BLOCK
DATA/PROG (512 BLOCK ALU(32) ACCH(16) ACCL(16)
SHIFTERS (0-7)
DATA
LEGEND: ACCH ACCL ARAU
Accumulator high Accumulator Arithmetic logic unit Auxiliary register arithmetic unit Auxiliary register pointer buffer Auxiliary register pointer Data memory page pointer Serial port data receive register Serial port data trademark register
Interrupt flag register Interrupt mask register Instruction register Microcall stack Queue instruction register Product register Product register timer Timer Temporary register
RPTC GREG AR0-AR7 ST0,
Program counter Prefetch counter Repeat instruction counter Global memory allocation register Serial port receive shift register Serial port transmit shift register Auxiliary registers Status registers Carry
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
architecture
SMJ320C26 architecture based SMJ320C25 with different internal configuration. SMJ320C26 integrates words on-chip 1568 words on-chip compared words on-chip words on-chip SMJ320C25. SMJ320C26 compatible with SMJ320C25. Increased throughput SMJ320C26 many applications accomplished means single cycle multiply/accumulate instructions with data move option, eight auxiliary registers with dedicated arithmetic unit, faster necessary data intensive signal processing. architectural design SMJ320C26 emphasizes overall speed, communication, flexibility processor configuration. Control signals instructions provide floating point support, block memory transfers, communication slower off-chip devices, multiprocessing implementations. Three large on-chip blocks, configurable either separate program data spaces three contiguous data blocks, provide increased flexibility system design. Programs words masked into internal program ROM. remainder 64K-word program memory space located externally. Large programs execute full speed from this memory space. Programs also downloaded from slow external memory high speed on-chip RAM. data memory address space words included facilitate implementation algorithms. VLSI implementation SMJ320C26 incorporates these features well many others, including hardware timer, serial port, block data transfer capabilities. 32-bit accumulator SMJ320C26 32-bit Arithmetic Logic Unit (ALU) accumulator perform wide range arithmetic logic instructions, majority which execute single clock cycle. executes variety branch instructions dependent status single word. These instructions provide following capabilities:
Branch address specified accumulator. Normalize fixed point numbers contained accumulator. Test specified word data memory.
input always provided from accumulator, other input provided from Product Register (PR) multiplier input scaling shifter which fetched data from data bus. After performed arithmetic logical operations, result stored accumulator. 32-bit accumulator split into 16-bit segments storage data memory. Additional shifters output accumulator perform shifts while data being transferred data storage. contents accumulator remain unchanged. scaling shifter SMJ320C26 scaling shifter 16-bit input connected data 32-bit output connected ALU. scaling shifter produces left shift 16-bits input data, specified instruction word. LSBs output filled with zeroes, MSBs either filled with zeroes sign extended, depending upon value (sign extension mode) status register STO. parallel multiplier SMJ320C26 bit-hardware multiplier, which capable computing signed unsigned 32-bit product single machine cycle. multiplier following associated registers:
16-bit Temporary Register (TR) that holds operands multiplier, 32-bit Product Register (PR) that holds product.
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
parallel multiplier (continued) Incorporated into SMJ320C26 instruction single-cycle multiply/accumulate instructions that allow both operands fetched simultaneously. data these operations reside anywhere internal external memory, transferred multiplier each cycle program data buses. Four product shift modes available Product Register (PR) output that useful when performing multiply/accumulate operations, fractional arithmetic, justifying fractional products. timer SMJ320C26 provides memory mapped 16-bit timer control operations. on-chip timer (TIM) register down counter that continuously clocked CLKOUT1. timer interrupt (TINT) generated every time timer decrements zero, provided timer interrupt enabled. timer reloaded with value contained period (PRD) register within next cycle after reaches zero that interrupts programmed occur regular intervals cycles CLKOUT1. memory control SMJ320C26 provides total 1568 words on-chip RAM, divided into four separate blocks (B0, B3). 1568 words, words (block always data memory, other blocks programmable either data program memory. data memory size 1568 words allows SMJ320C26 handle data array 1536 words, while still leaving locations intermediate storage. When using program memory, instructions downloaded from external memory into on-chip RAM, then executed. When using on-chip program RAM, ROM, high speed external program memory, SMJ320C26 runs full speed without wait states. However, READY line used interface SMJ320C26 slower, less expensive external memory. Downloading programs from slow off-chip memory on-chip program speeds processing cuts overall system costs. SMJ320C26 provides three separate address spaces program memory, data memory, I/O. on-chip memory mapped into either data memory program memory space, depending upon choice memory configuration. instruction configuration (parameter) used follows configure blocks program data memory.
CONFIGURATION Data Program Program Program Data Data Program Program Data Data Data Program
Regardless configuration, user still execute from external program memory. SMJ320C26 provides words. sufficient allow programming bootstrap program interrupt handler, implement self test routines. SMJ320C26 registers that mapped into data memory space locations 0-5; serial port data receive register, serial port data transmit register, timer register, period register, interrupt mask register, global memory allocation register.
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memory control (continued)
MEMORY MAPS AFTER RESET CONF MP/MC PROGRAM (0000h) INTERRUPTS RESERVED (EXTERNAL) (0000h) (0005h) (0006h) (005Fh) (0060h) (007Fh) (0080h) (01FFh) (0200h) EXTERNAL 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 65535 (FFFFh) 65535 (FFFFh) DATA ON-CHIP MMRs RESERVED ON-CHIP BLOCK RESERVED ON-CHIP BLOCK ON-CHIP BLOCK ON-CHIP BLOCK EXTERNAL PAGE PAGE PAGE EXTERNAL
(001Fh) (0020h)
PAGE 8-11
PAGE 12-15 PAGE 16-511
MP/MC PROGRAM (0000h) (0000h) INTERRUPTS RESERVED BOOTLOAD (0005h) (0006h) (005Fh) (0060h) RESERVED 4095 (0FFFh) 4096 (1000h) (007Fh) (0080h) (01FFh) (0200h) 1023 (03FFh) 1024 (0400h) EXTERNAL 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 65535 (FFFFh) 65535 (FFFFh) DATA ON-CHIP MMRs RESERVED ON-CHIP BLOCK RESERVED ON-CHIP BLOCK ON-CHIP BLOCK ON-CHIP BLOCK EXTERNAL PAGE PAGE PAGE EXTERNAL
(00FFh) (0100h)
PAGE 8-11
PAGE 12-15 PAGE 16-511
Figure Memory Maps
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memory control (continued)
MEMORY MAPS AFTER CONF MP/MC PROGRAM (0000h) (0000h) INTERRUPTS RESERVED (EXTERNAL) (0005h) (0006h) (005Fh) (0060h) EXTERNAL (007Fh) (0080h) (01FFh) (0200h) 63999 (F9FFh) 64000 (FA00h) 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) EXTERNAL 65535 (FFFFh) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 65535 (FFFFh) DATA ON-CHIP MMRs RESERVED ON-CHIP BLOCK RESERVED DOES EXIST ON-CHIP BLOCK ON-CHIP BLOCK EXTERNAL PAGE PAGE PAGE EXTERNAL
(001Fh) (0020h)
ON-CHIP BLOCK EXTERNAL
PAGE 8-11
PAGE 12-15 PAGE 16-511
MP/MC PROGRAM (0000h) (00FFh) (0100h) 4095 (0FFFh) 4096 (1000h) INTERRUPTS RESERVED BOOTLOAD RESERVED (0000h) (0005h) (0006h) (005Fh) (0060h) (007Fh) (0080h) EXTERNAL (01FFh) (0200h) 1023 (03FFh) 1024 (0400h) ON-CHIP BLOCK EXTERNAL EXTERNAL 65535 (FFFFh) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) DATA ON-CHIP MMRs RESERVED ON-CHIP BLOCK RESERVED DOES EXIST ON-CHIP BLOCK ON-CHIP BLOCK EXTERNAL PAGE PAGE PAGE EXTERNAL
63999 (F9FFh) 64000 (FA00h) 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) 65535 (FFFFh)
PAGE 8-11
PAGE 12-15 PAGE 16-511
Figure Memory Maps
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memory control (continued)
MEMORY MAPS AFTER CONF MP/MC PROGRAM (0000h) (0000h) INTERRUPTS RESERVED (EXTERNAL) (0005h) (0006h) (005Fh) (0060h) EXTERNAL (007Fh) (0080h) RESERVED (01FFh) (0200h) 63999 (F9FFh) 64000 (FA00h) 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) 65535 (FFFFh) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 65535 (FFFFh) DOES EXIST DOES EXIST ON-CHIP BLOCK EXTERNAL DATA ON-CHIP MMRs RESERVED ON-CHIP BLOCK PAGE PAGE PAGE EXTERNAL
(001Fh) (0020h)
ON-CHIP BLOCK ON-CHIP BLOCK
PAGE 8-11
PAGE 12-15 PAGE 16-511
EXTERNAL
MP/MC PROGRAM (0000h) INTERRUPTS RESERVED BOOTLOAD RESERVED (0000h) (0005h) (0006h) (005Fh) (0060h) ON-CHIP BLOCK EXTERNAL (007Fh) (0080h) RESERVED (01FFh) (0200h) 63999 (F9FFh) 64000 (FA00h) 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) 65535 (FFFFh) 1023 (03FFh) 1024 (0400h) ON-CHIP BLOCK ON-CHIP BLOCK EXTERNAL 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) EXTERNAL 65535 (FFFFh) PAGE 16-511 DOES EXIST DOES EXIST ON-CHIP BLOCK DATA ON-CHIP MMRs RESERVED PAGE EXTERNAL
(00FFh) (0100h) 4095 (0FFFh) 4096 (1000h)
PAGE PAGE
PAGE 8-11
PAGE 12-15
Figure Memory Maps
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memory control (continued)
MEMORY MAPS AFTER CONF MP/MC PROGRAM (0000h) (0000h) INTERRUPTS RESERVED (EXTERNAL) (0005h) (0006h) (005Fh) (0060h) EXTERNAL (007Fh) (0080h) RESERVED (01FFh) (0200h) 63999 (F9FFh) 64000 (FA00h) 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) 65535 (FFFFh) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 65535 (FFFFh) DOES EXIST DOES EXIST DOES EXIST EXTERNAL DATA ON-CHIP MMRs RESERVED ON-CHIP BLOCK PAGE PAGE PAGE EXTERNAL
(001Fh) (0020h)
ON-CHIP BLOCK ON-CHIP BLOCK ON-CHIP BLOCK
PAGE 8-11
PAGE 12-15 PAGE 16-511
MP/MC PROGRAM (0000h) INTERRUPTS RESERVED BOOTLOAD RESERVED (0000h) (0005h) (0006h) (005Fh) (0060h) ON-CHIP BLOCK EXTERNAL (007Fh) (0080h) (01FFh) (0200h) 63999 (F9FFh) 64000 (FA00h) 64511 (FBFFh) 64512 (FC00h) 65023 (FDFFh) 65024 (FE00h) 65535 (FFFFh) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 65535 (FFFFh) DATA ON-CHIP MMRs RESERVED PAGE EXTERNAL
(00FFh) (0100h) 4095 (0FFFh) 4096 (1000h)
RESERVED DOES EXIST DOES EXIST DOES EXIST EXTERNAL
PAGE PAGE
ON-CHIP BLOCK ON-CHIP BLOCK ON-CHIP BLOCK
PAGE 8-11
PAGE 12-15 PAGE 16-511
Figure Memory Maps
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
interrupts subroutines SMJ320C26 three external maskable user interrupts INT2-INT0, available external devices that interrupt processor. Internal interrupts generated serial port (RINT XINT), timer (TINT), software interrupt (TRAP) instruction. Interrupts prioritized with reset (RS) having highest priority serial port transmit interrupt (XINT) having lowest priority. interrupt locations two-words boundaries that branch instructions accommodated those locations desired. built mechanism protects multicycle instructions from interrupts. interrupt occurs during multicycle instruction, interrupt processed until instruction completed. This mechanism applies both instructions that repeated become multicycle READY signal.
external interface
SMJ320C26 supports wide range system interfacing requirements. Program, data, address spaces provide interface memory I/O, thus maximizing system throughput. design simplified having treated same memory. devices mapped into address space using processor's external address data busses same manner memory-mapped devices. Interface memory devices varying speeds accomplished using READY line. When transactions made with slower devices, SMJ320C26 processor waits until other device completes function signals processor READY line, SMJ320C26 then continues execution. serial port provides communication with serial devices, such codecs, serial converters, other serial systems. interface signals compatible with codecs many other serial devices with minimum external hardware. serial port also used intercommunication between processors multiprocessing applications. serial port memory mapped registers; data transmit register (DXR) data receive register (DRR). Both registers operate either byte mode 16-bit word mode, accessed same manner other data memory location. Each register external clock, framing signal, associated shift registers. method multiprocessing implemented programming device transmit while others receive mode.
multiprocessing
flexibility SMJ320C26 allows configurations satisfy wide range system requirements. SMJ320C26 used follows:
standalone processor. multiprocessor with devices parallel. multiprocessor with global memory space. peripheral processor interfaced processor controlled signals another device.
multiprocessing applications, SMJ320C26 capability allocating global data memory space communicating with that space (bus request) READY control signals. Global memory data memory shared more than processor. Global data memory access must arbitrated. 8-bit memory mapped GREG (global memory allocation register) specifies part SMJ320C26's data memory global external memory. contents register determine size global memory space. current instruction addresses location within that space, asserted request control data bus. length memory cycle controlled READY line. SMJ320C26 supports (direct memory access) external program/data memory using HOLD HOLDA signals. Another processor take complete control SMJ320C26's external memory asserting HOLD low. This causes SMJ320C26 place address, data, control lines high impedance state, assert HOLDA.
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
addressing modes
SMJ320C26 instruction provides three memory addressing modes; direct, indirect, immediate addressing. Both direct indirect addressing used access data memory. direct addressing, seven bits instruction word concatenated with nine bits data memory page pointer form 16-bit data memory address. Indirect addressing accesses data memory through eight auxiliary registers. immediate addressing, data embedded instruction word(s). direct addressing, instruction word contains lower seven bits data memory address. This field concatenated with nine bits data memory page pointer form full 16-bit address. Thus, memory paged direct addressing mode with total pages, each page containing words. Eight auxiliary registers (AR0-AR7) provide flexible powerful indirect addressing. select specific auxiliary register, Auxiliary Register Pointer (ARP) loaded with value from through through respectively. There seven types indirect addressing: auto increment, auto decrement, post indexing either adding subtracting contents AR0, single indirect addressing with increment decrement reversal addressing (used FFTs) with increment decrement. operations performed current auxiliary register same cycle original instruction, followed update.
repeat feature
repeat feature, used with instructions such multiply/accumulates, block moves, transfers, table read/writes, allows single instruction executed times. repeat counter (RPTC) loaded with either data memory value (RPT instruction) immediate value (RPTK instruction). value this operand less than number times that next instruction executed. Those instructions that normally multicycle pipelined when using repeat feature, effectively become single-cycle instructions.
instruction
SMJ320C26 microprocessor implements comprehensive instruction that supports both numeric intensive signal processing operations well general purpose applications, such multiprocessing high speed control. maximum throughput, next instruction prefetched while current being executed. Since same data lines used communicate external data/program space, number cycles vary depending upon whether next data operand fetch from internal external program memory. Highest throughput achieved maintaining data memory on-chip using either internal fast program memory. Table lists symbols abbreviations used Table instruction summary. Table consists primarily single-cycle, single-word instructions. Infrequently used branch, I-O, CALL instructions multicycle. instruction summary arranged according function alphabetized within each functional grouping. symbol indicates instructions that included SMJ320C25 instruction set.
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instruction (continued)
Table Instruction Symbols
SYMBOL MEANING 4-bit field specifying code 2-bit field specifying compare mode Data memory address field Format status Addressing mode Immediate operand field Port address (PA0 through predefined assembler symbols equal through respectively). 2-bit field specifying register output shift code 3-bit operand field specifying auxiliary register 4-bit left-shift code Internal configuration bits 3-bit accumulator left-shift field
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instruction (continued)
Table Instruction Summary
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS MNEMONIC ADDC ADDH ADDK ADDS ADDT ADLK ANDK CMPL LACK LACT LALK NORM SACH SACL SBLK SUBB SUBC SUBH SUBK SUBS SUBT XORK ZALH ZALR ZALS Absolute value accumulator accumulator with shift accumulator with carry high accumulator accumulator short immediate accumulator with sign extension suppressed accumulator with shift specified register accumulator long immediate with shift with accumulator immediate with accumulator with shift Complement accumulator Load accumulator with shift Load accumulator immediate short Load accumulator with shift specified register Load accumulator long immediate with shift Negate accumulator Normalize contents accumulator with accumulator immediate with accumulator with shift Rotate accumulator left Rotate accumulator right Store high accumulator with shift Store accumulator with shift Subtract from accumulator long immediate with shift Shift accumulator left Shift accumulator right Subtract from accumulator with shift Subtract from accumulator with borrow Conditional subtract Subtract from high accumulator Subtract from accumulator short immediate Subtract from accumulator with sign extension suppressed Subtract from accumulator with shift specified register Exclusive-OR with accumulator Exclusive-OR immediate with accumulator with shift Zero accumulator Zero accumulator load high accumulator Zero accumulator load high accumulator with rounding Zero accumulator load accumulator with sign extension suppressed DESCRIPTION WORDS INSTRUCTION CODE
These instructions included SMJ32010 instruction set.
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instruction (continued)
Table Instruction Summary (continued)
AUXILIARY REGISTERS DATA PAGE POINTER INSTRUCTIONS MNEMONIC ADRK CMPR LARK LARP LDPK LRLK SBRK DESCRIPTION auxiliary register short immediate Compare auxiliary register with auxiliary register Load auxiliary register Load auxiliary register short immediate Load auxiliary register pointer Load data memory page pointer Load data memory page pointer immediate Load auxiliary register long immediate Modify auxiliary register Store auxiliary register Subtract from auxiliary register short immediate WORDS INSTRUCTION CODE
REGISTER, REGISTER, MULTIPLY INSTRUCTIONS MNEMONIC APAC MACD MPYA MPYK MPYS MPYU SPAC SQRA SQRS register accumulator Load high register Load register Load register accumulator previous product Load register, accumulate previous product, move data Load register store register accumulator Load register subtract previous product Multiply accumulate Multiply accumulate with data move Multiply (with register, store product register) Multiply accumulate previous product Multiply immediate Multiply subtract previous product Multiply unsigned Load accumulator with register Subtract register from accumulator Store high register Store register register output shift mode Square accumulate Square subtract previous product DESCRIPTION WORDS INSTRUCTION CODE
These instructions included SMJ32010 instruction set.
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instruction (continued)
Table Instruction Summary (continued)
BRANCH/CALL INSTRUCTIONS MNEMONIC BACC BANZ BBNZ BGEZ BIOZ BLEZ CALA CALL Branch unconditionally Branch address specified accumulator Branch auxiliary register zero Branch Branch Branch carry Branch accumulator Branch accumulator Branch status Branch accumulator Branch accumulator Branch carry Branch overflow Branch accumulator Branch overflow Branch accumulator Call subroutine indirect Call subroutine Return from subroutine DESCRITPION WORDS INSTRUCTION CODE
DATA MEMORY OPERATIONS MNEMONIC BLKD BLKP DMOV FORT RFSM RTXM SFSM STXM TBLR TBLW DESCRITPION Block move from data memory data memory Block move from program memory data memory Data move data memory Format serial port registers Input data from port Output data port Reset serial port frame synchronization mode Reset serial port transmit mode Reset external flag serial port frame synchronization mode serial port transmit mode external flag Table read Table write WORDS INSTRUCTION CODE
These instructions included SMJ32010 instruction set.
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instruction (continued)
Table Instruction Summary (concluded)
CONTROL INSTRUCTIONS MNEMONIC BITT CONF DINT EINT IDLE LST1 POPD PSHD PUSH ROVM RPTK RSXM SOVM SST1 SSXM TRAP Test Test specified register Configure blocks Data program Disable interrupt Enable interrupt Idle until interrupt Load status register Load status register operation stack accumulator stack data memory Push data memory value onto stack Push accumulator onto stack Reset carry Reset hold mode Reset overflow mode Repeat instruction specified data memory value Repeat instruction specified immediate value Reset sign-extension mode Reset test/control flag carry hold mode overflow mode Store status register Store status register sign-extension mode test/control flag Software interrupt DESCRIPTION WORDS INSTRUCTION CODE
These instructions included SMJ32010 instruction set. This instruction replaces CNFD CNFP SMJ320C25 instruction set.
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development support
Together, Texas Instruments authorized third-party suppliers offer extensive line development support products assist user aspects TMS320 second-generation-based design development. These products range from development application software complete hardware development evaluation systems. Table lists development support products second-generation TMS320 devices. System development begin with simulator, Software Development System (SWDS), emulator (XDS) along with assembler/linker. These tools give TMS320 user various means evaluation, from software simulation second-generation TMS320s (simulator) full-speed in-circuit emulation with hardware software breakpoint trace timing capabilities (XDS). Software hardware developed simultaneously using macro assembler/linker, compiler, simulator software development, hardware development, Software Development System both software development limited hardware development. Many third-party vendors offer additional development support second-generation TMS320s, including assembler/linkers, simulators, high-level languages, applications software, algorithm development tools, applications boards, software development boards, in-circuit emulators. Refer TMS320 Family Development Support Reference Guide (SPRU011A) further information about TMS320 development support products offered both Texas Instruments third-party suppliers. Additional support TMS320 products consists extensive library product applications documentation. Three-day design workshops offered Regional Technology Centers (RTCs). These workshops provide insight into architecture instruction second-generation TMS320s well hands-on training with TMS320 development tools. When technical questions arise regarding TMS320 family, contact Texas Instruments TMS320 Hotline (713) 274-2320. keep informed latest third-party development support tools accessing Bulletin Board Service (BBS) (713) 274-2323. serves 2400-, 1200-, 300-bps modems. Also, TMS320 application source code downloaded from BBS. Table gives complete list SMJ320C26 software hardware development tools.
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development support (continued)
Table Software Hardware Support
MACRO ASSEMBLER/LINKER HOST COMPUTER HOST COMPUTER HOST COMPUTER MODEL XDS/22 HOST COMPUTER Includes assembler/linker OPERATING SYSTEMS MS/PS ULTRIX UNIX COMPILER MACRO ASSEMBLER/LINKER OPERATING SYSTEMS MS/PC ULTRIX UNIX SIMULATOR OPERATING SYSTEMS MS/PC EMULATOR POWER SUPPLY INCLUDED SOFTWARE DEVELOPMENT SYSTEM OPERATING SYSTEMS MS/PC MS/PC PART NUMBER TMDX3268828 TMDX3268821 PART NUMBER TMDS3262292 PART NUMBER TMDS3242251-08 TMDS3242851-02 PART NUMBER TMDS3242255-08 TMDS3242855-02 TMDS3242265-08 TMDS3242555-08 PART NUMBER TMDS3242250-08 TMDS3242850-02 TMDS3242260-08 TMDS3242550-08
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
absolute maximum ratings over specified temperature range (unless otherwise noted)
Supply voltage range, Input voltage range Output voltage range Continuous power dissipation Storage temperature range 55°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions beyond those indicated "recommended operating conditions" section this specification implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. voltages with respect VSS.
This device contains circuits protect inputs outputs against damage high static voltages electrostatic fields. These circuits have been qualified protect this device against electrostatic discharges (ESD) according MIL-STD-883C, Method 3015; however, advised that precautions taken avoid application voltage higher than maximum-rated voltages these high-impedance circuits. During storage handling, device leads should shorted together device should placed conductive foam. circuit, unused inputs should always connected appropriated logic voltage level, preferably either ground. Specific guidelines handling devices this type contained publication Guidelines Handling (ESDS) Devices Assemblies available from Texas Instruments.
recommended operating conditions
Supply voltage Supply voltage D15-D0, High level input High-level voltage CLKIN, CLKR, CLKX others D15-D0, FSX, CLKIN, CLKR, CLKX Low-level input oltage voltage High-level output current Low-level output current Minimum operating free-air temperature Maximum operating case temperature others 3.50 3.00 UNIT
electrical characteristics over specified free-air temperature range (unless otherwise noted)
PARAMETER High-level output voltage Low-level output voltage High-impedance-state output leakage current Input current Normal Supply current Input capacitance Idle/HOLD MAX, TEST CONDITIONS MIN, MIN, UNIT
Output capacitance typical values 25°C.
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
CLOCK CHARACTERISTICS TIMING
SMJ320C26 either internal oscillator external frequency source clock.
internal clock option
internal oscillator enabled connecting crystal across X2/CLKIN (see Figure frequency CLKOUT1 one-fourth crystal fundamental frequency. crystal should either fundamental overtone mode, parallel resonant, with effective series resistance power dissipation specified load capacitance Note that overtone crystals require additional tuned circuit (see application report, Hardware Interfacing TMS320C25).
PARAMETER Input clock frequency This parameter production tested. TEST CONDITIONS -55°C 125°C 40.0 UNIT
CRYSTAL
X2/CLKIN
Figure Internal Clock Option
external clock option
external frequency source used injecting frequency directly into X2/CLKIN with left unconnected. external frequency injected must conform specifications listed table below.
switching characteristics over recommended operating conditions (see Note
PARAMETER tc(C) td(CIH-C) tf(C) tr(C) tw(CL) tw(CH) CLKOUT1/CLKOUT2 cycle time CLKIN high CLKOUT1/CLKOUT2/STRB high/low CLKOUT1/CLKOUT2/STRB fall time CLKOUT1/CLKOUT2/STRB rise time CLKOUT1/CLKOUT2 pulse duration CLKOUT1/CLKOUT2 high pulse duration 2Q-8 2Q-8 2Q+8 2Q+8 UNIT
td(C1-C2) CLKOUT1 high CLKOUT2 low, CLKOUT2 high CLKOUT1 high, etc. This parameter production tested. NOTE 1/4tc(C)
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
timing requirements over recommended operating conditions (see Note
tc(CI) tw(CIL) tw(CIH) tsu(S) CLKIN cycle time CLKIN pulse duration, tc(C) (see Note CLKIN high pulse duration, tc(CI) (see Note SYNC setup time before CLKIN UNIT
th(S) SYNC hold time from CLKIN NOTES: 1/4tc(C) CLKIN duty cycle [tr(CI) tw(CIH)]/tc(CI) must within 40-60%. CLKIN rise fall times must less than
IOH/IOL
From Output Under Test
Test Point
Figure Test Load Circuit
(MIN)
Input
(MAX)
Outputs
(MIN)
(MAX)
Figure Voltage Reference Levels
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
MEMORY PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note
PARAMETER td(C1-S) td(C2-S) tsu(A) th(A) tw(SL) tw(SH) tsu(D)W th(D)W ten(D) tdis(D) STRB from CLKOUT1 STRB present) CLKOUT2 STRB STRB present) Address setup time before STRB (see Note Address hold time after STRB high (see Note STRB pulse duration wait states, Note STRB high pulse duration (between consecutive cycles, Note Data write setup time before STRB high wait states) Data write hold time from STRB high Data starts being driven after STRB (write cycle) Data three-state after STRB high (write cycle) 2Q-20 Q-10 Q+15 Q-12 2Q-5 2Q+5 UNIT
td(MSC) valid from CLKOUT1 This parameter production tested.
timing requirements over recommended operating conditions (see Note
ta(A) tsu(D)R th(D)R td(SL-R) td(C2H-R) th(SL-R) th(C2H-R) td(M-R) Read data access time from address time (read cycle) (see Notes Data read setup time before STRB high Data read hold time from STRB high READY valid after STRB wait states) READY valid after CLKOUT2 high READY hold time after STRB wait states) READY hold after CLKOUT2 high READY valid after valid Q-22 3Q-40 UNIT
th(M-R) READY hold time after valid This parameter production tested.
INT, BIO, TIMING switching characteristics over recommended operating conditions (see Note
PARAMETER td(RS) td(IACK) td(XF) CLKOUT1 reset state entered CLKOUT1 IACK valid valid before falling edge STRB Q-12 UNIT
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
timing requirements over recommended operating conditions (see Note
tsu(IN) th(IN) tw(IN) tw(RS) INT/BIO/RS setup before CLKOUT1 high (see Note INT/BIO/RS hold after CLKOUT1 high (see Note NT/BIO pulse duration pulse duration tc(C) 3tc(C) UNIT
NOTES: 1/4tc(C) A15-A0, R/W, timings included timings referenced "address." Delays between CLKOUT1/CLKOUT2 edges STRB edges track each other, resulting tw(SL) tw(SH) being with wait states. Read data access time defined ta(A) tsu(A) tw(SL) tsu(D)R. INT, asynchronous inputs occur time during clock cycle. However, specified setup time met, exact sequence shown timing diagram will occur. INT/BIO fall time must less than
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
HOLD TIMING switching characteristics over recommended operating conditions (see Note
PARAMETER td(C1L-AL) tdis(AL-A) tdis(C1L-A) td(HH-AH) HOLDA after CLKOUT1 HOLDA address three-state Address three-state after CLKOUT1 (HOLD mode) (see Note HOLD high HOLDA high UNIT
ten(A-C1L) Address driven before CLKOUT1 (HOLD mode) (see Note This parameter production tested.
timing requirements over recommended operating conditions (see Note
td(C2H-H) HOLD valid after CLKOUT2 high NOTES: 1/4tc(C) A15-A0, STRB, timings included timings referenced "address." Q-24 UNIT
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note
PARAMETER td(CH-DX) td(FL-DX) td(CH-FS) valid after CLKX rising edge (see Note valid after falling edge (TXM (see Note valid after CLKX rising edge (TXM UNIT
timing requirements over recommended operating conditions (see Note
tc(SCK) tw(SCK) tw(SCK) tsu(FS) th(FS) tsu(DR) th(DR) Serial port frequency Serial port clock (CLKX/CLKR) cycle time Serial port clock (CLKX/CLKR) pulse duration (see Note Serial port clock (CLKX/CLKR) high pulse duration (see Note FSX/FSR setup time before CLKX/CLKR falling edge (TXM FSX/FSR hold time after CLKX/CLKR falling edge (TXM setup time before CLKR falling edge hold time after CLKR falling edge 1.25 5,000 800,000 UNIT
NOTES: 1/4tc(C) last occurrence falling CLKX rising. duty cycle serial port clock must within 40-60%. Serial port clock (CLKX/CLKR) rise fall times must less than
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
Timing measurements referenced from voltage volts high voltage volts unless otherwise noted.
tc(CI) tf(CI) tr(CI) X/2CLKIN th(S) tsu(S) SYNC td(CIH-C) CLKOUT1 td(CIH-C) tr(C) STRB td(CIH-C) CLKOUT2 td(C1-C2) td(C1-C2) td(C1-C2) tw(CH) td(C1-C2) tc(C) tw(CL) tw(CH) tf(C) tc(C) td(CIH-C) tw(CL) tw(CIL) tw(CIH)
tsu(S)
tf(C)
tr(C)
Figure Clock Timing
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
td(C1-S) CLKOUT1 td(C1-S) CLKOUT2 td(C2-S) STRB tsu(A) tw(SL) VALID ta(A) td(SL-R) READY th(SL-R) D15-D0 DATA th(D)R tsu(D)R tw(SH) th(A) td(C2-S)
A15-A0,
Figure Memory Read Timing
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
CLKOUT1 CLKOUT2 STRB tsu(A) A15-A0, VALID th(A)
READY tsu(D)W D15-D0 ten(D) DATA tdis(D) th(D)W
Figure Memory Write Timing
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
STRB A15-A0, R/W, VALID th(C2H-R) td(C2H-R) td(C2H-R) th(C2H-R)
READY D15-D0, (FOR READ OPERATION) D15-D0, (FOR WRITE OPERATION) td(MSC) td(MSC) td(M-R) th(M-R) td(M-R) th(M-R) DATA
Figure Wait-State Memory Access Timing
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
CLKOUT1 tsu(IN) tw(RS) A15-A0 FETCH LOCATION D15-D0 VALID BEGIN PROGRAM EXECUTION td(RS) tsu(IN) th(IN)
STRB CONTROL SIGNALS IACK
SERIAL PORT CONTROLS
Control signals R/W, Serial port controls FSX.
Figure Reset Timing
CLKOUT1
STRB tsu(IN) tw(N) INT2-INT0 tf(IN) A15-A0 FETCH td(IACK) IACK FETCH FETCH td(IACK) FETCH th(IN)
Figure Interrupt Timing
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
STRB FETCH BIOZ A15-A0 tsu(IN) VALID th(IN) BRANCH ADDRESS FETCH BRANCH ADDRESS FETCH NEXT INSTRUCTION
Figure Timing
CLKOUT1
STRB td(XF) A15-A0 FETCH SXF/RXF VALID VALID VALID VALID
Figure External Flag Timing
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
STRB td(C2H-H) (see note HOLD
A15-A0
VALID
VALID
tdis(C1L-A) D15-D0 tdis(AL-A) HOLDA td(C1L-AL) FETCH
EXECUTE
NOTE HOLD asynchronous input that occur time during clock cycle. specified timing met, exact sequence shown will occur; otherwise, delay CLKOUT2 cycle will occur.
Figure HOLD Timing (Part
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2 ten(A-C1L) STRB td(C2H-H) (see note
HOLD
VALID
D15-D0 td(HH-AH) HOLDA
A15-A0
FETCH
EXECUTE
NOTE HOLD asynchronous input that occur time during clock cycle. specified timing met, exact sequence shown will occur; otherwise, delay CLKOUT2 cycle will occur.
Figure HOLD Timing (Part
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
tc(SCK) tw(SCK) tr(SCK)
CLKR th(FS) th(DR) tsu(FS) tsu(DR) tf(SCK) tw(SCK)
Figure Serial Port Receive Timing
tc(SCK) tr(SCK) tw(SCK) CLKX tw(SCK) tf(SCK) td(CH-DX) (INPUT, td(FL-DX) tsu(FS) td(CH-FS) (OUTPUT, td(CH-FS) td(CH-DX)
th(FS)
tsu(FS)
Figure Serial Port Transmit Timing
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
MECHANICAL DATA package leaded chip carrier package
25,40 (1.000) 24,89 (0.980) 24,38 (0.960) 23,88 (0.940)
PARAMETER 20,52 (0.808) 20,19 (0.795) VIEW Junction-to-free-air thermal resistance Junction-to-case thermal resistance
UNIT °C/W °C/W
1,98 (0.078) 1,07 (0.042) 1,27 (0.050) NOM. 2,16 (0.085) 1,65 (0.065)
0,38 (0.015) MIN. 2,41 (0.095) 1,91 (0.075) 0,28 (0.011) 0,18 (0.007) 0,38 (0.015) 0,13(0.005) 0,58 (0.023) 0,33 (0.013) 24,13 (0.950) 23,11 (0.910)
0,81 (0.032) 0,51 (0.020)
0,51 (0.020) 0,25 (0.010)
1,27 (0.050) 0,76 (0.030)
0,89 (0.035) 0,64 (0.025)
3,43 (0.135) 2,92 (0.115)
DIMENSIONS MILLIMETERS PARENTHETICALLY INCHES.
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
MECHANICAL DATA ceramic leadless (pad) chip carrier package
(0.960) (0.940) 21,89 (0.862)
(0.960) (0.940)
VIEW
PARAMETER Junction-to-free-air thermal resistance Junction-to-case thermal resistance
39.9
UNIT °C/W °C/W
21,89 (0.862) INDEX CORNER
(0.810) (0.790)
(0.093) (0.077)
X45° CHAM
(0.028) (0.022) 1,27 (0.050)
(0.055) (0.045)
0,20 (0.008) TYP.
X45° CHAM TYP., 3PLS.
(0.050) (0.030)
(0.120) (0.082)
DIMENSIONS MILLIMETERS PARENTHETICALLY INCHES WITH INCHES GOVERNING
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(0.030) (0.010)
SMJ320C26 DIGITAL SIGNAL PROCESSOR
MECHANICAL DATA 68-pin grid array ceramic package
28,448 (1.120) 27,422 (1.080) 15,37 (0.605)
PARAMETER Junction-to-free-air thermal resistance Junction-to-case thermal resistance
UNIT °C/W °C/W VIEW 15,37 (0.605) 28,448 (1.120) 27,422 (1.080)
4,572 (0.180) 2,794 (0.110)
1,397 (0.055) 1,143 (0.045)
3,556 (0.140) 3,048 (0.120)
0,508 (0.020) 0,406 (0.016)
1,575 (0.062) 1,473 (0.058)
2,54 (0.100) T.P. 1,778 (0.070) PLACES 1,27 (0.050) BOTTOM VIEW 2,54 (1.00) T.P.
LINEAR DIMENSIONS MILLIMETERS PARENTHETICALLY INCHES
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SMJ320C26 DIGITAL SIGNAL PROCESSOR
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