Distinctive Characteristics ARCHITECTURAL ADVANTAGES 128/128
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128/128/64/32 Megabit (8/8/4/2 16-Bit) CMOS Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIOControl
Distinctive Characteristics
ARCHITECTURAL ADVANTAGES
128/128/64/32 Mbit Page Mode devices Page size words: Fast page read access from random locations within page Single power supply operation Full Voltage range: volt read, erase, program operations battery-powered applications Dual Chip Enable inputs (only PL129J) inputs control selection each half memory space Simultaneous Read/Write Operation Data continuously read from bank while executing erase/program functions another bank Zero latency switching from write read operations FlexBank Architecture (PL127J/PL064J/PL032J) separate banks, with simultaneous operations device Bank PL127J Mbit PL064J Mbit PL032J Mbit Bank PL127J Mbit PL064J Mbit PL032J Mbit Bank PL127J Mbit PL064J Mbit PL032J Mbit Bank PL127J Mbit PL064J Mbit PL032J Mbit FlexBank Architecture (PL129J) separate banks, with simultaneous operations device CE#1 controlled banks: Bank PL129J 16Mbit (4Kw 32Kw Bank PL129J 48Mbit (32Kw CE#2 controlled banks: Bank PL129J Mbit (32Kw Bank PL129J 16Mbit (4Kw 32Kw Enhanced VersatileI/O(VIO) Control Output voltage generated input voltages tolerated control inputs I/Os determined voltage options PL127J PL129J devices PL064J PL032J devices SecSi(Secured Silicon) Sector region words accessible through command sequence factory-locked words customer-lockable words Both bottom boot blocks device Manufactured process technology Data Retention: years typical Cycling Endurance: million cycles sector typical
PERFORMANCE CHARACTERISTICS
High Performance Page access times fast Random access times fast Power consumption (typical values MHz) active read current program/erase current typical standby mode current
SOFTWARE FEATURES
Software command-set compatible with JEDEC 42.4 standard Backward compatible with Am29F, Am29LV, Am29DL, AM29PDL families MBM29QM/RM, MBM29LV, MBM29DL, MBM29PDL families (Common Flash Interface) compliant Provides device-specific information system, allowing host software easily reconfigure different Flash devices Erase Suspend Erase Resume Suspends erase operation allow read program operations other sectors same bank Unlock Bypass Program command Reduces overall programming time when issuing multiple program command sequences
Publication Number S29PL127/129/064/032J_00
Revision
Amendment
Issue Date September 2004
HARDWARE FEATURES
Ready/Busy# (RY/BY#) Provides hardware method detecting program erase cycle completion Hardware reset (RESET#) Hardware method reset device reading array data WP#/ (Write Protect/Acceleration) input VIL, hardware level protection first last word sectors. VIH, allows removal sector protection VHH, provides accelerated programming factory setting Persistent Sector Protection command sector protection method lock combinations individual sectors sector groups prevent program erase operations within that sector Sectors locked unlocked in-system level
Password Sector Protection sophisticated sector protection method lock combinations individual sectors sector groups prevent program erase operations within that sector using user-defined 64-bit password Package options Standard discrete pinouts 80-ball Fine-pitch (PL127J) (VBG080) 8.15 6.15 48-ball Fine pitch (PL064J/PL032J) (VBK048) MCP-compatible pinout 11.6 64-ball Fine-pitch (PL127J) 56-ball Fine-pitch (PL064J PL032J) Compatible with pinout, allowing easy integration into existing designs 56-pin TSOP (PL127J) (TS056)
S29PL127/129/064/032J_00A6 September 2004
General Description
PL127J/PL129J/PL064J/PL032J 128/128/64/32 Mbit, volt-only Page Mode Simultaneous Read/Write Flash memory device organized 8/8/4/2 Mwords. devices offered following packages: 11mm 8mm, 80-ball Fine-pitch standalone (PL127J) 11.6mm, 64-ball Fine-pitch multi-chip compatible (PL127J) 8.15mm 6.15mm, 48-ball Fine-pitch standalone (PL064J/PL032J) 9mm, 56-ball Fine-pitch multi-chip compatible (PL064J PL032J) 20mm 14mm, 56-pin TSOP (PL127J) word-wide data (x16) appears DQ15-DQ0. This device programmed in-system standard EPROM programmers. 12.0 required write erase operations. device offers fast page access times with corresponding random access times respectively, allowing high speed microprocessors operate without wait states. eliminate contention device separate chip enable (CE#), write enable (WE#) output enable (OE#) controls. Note: Device PL129J chip enable inputs (CE1#, CE2#).
Simultaneous Read/Write Operation with Zero Latency
Simultaneous Read/Write architecture provides simultaneous operation dividing memory space into banks, which considered four separate memory arrays certain operations concerned. device improve overall system performance allowing host system program erase bank, then immediately simultaneously read from another bank with zero latency (with simultaneous operations operating time). This releases system from waiting completion program erase operation, greatly improving system performance. device organized both bottom sector configurations. banks organized follows: Bank PL127J Sectors Mbit Mbit Mbit Mbit PL064J Sectors Mbit Mbit Mbit Mbit PL032J Sectors Mbit Mbit Mbit Mbit
Bank
PL129J Sectors Mbit Mbit Mbit Mbit
Control CE1# CE1# CE2# CE2#
September 2004 S29PL127/129/064/032J_00A6
Page Mode Features
page size words. After initial page access accomplished, page mode operation provides fast read access speed random locations within that page.
Standard Flash Memory Features
device requires single volt power supply (2.7 both read write functions. Internally generated regulated voltages provided program erase operations. device entirely command compatible with JEDEC 42.4 single-power-supply Flash standard. Commands written command register using standard microprocessor write timing. Register contents serve inputs internal state-machine that controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from other Flash EPROM devices. Device programming occurs executing program command sequence. Unlock Bypass mode facilitates faster programming times requiring only write cycles program data instead four. Device erasure occurs executing erase command sequence. host system detect whether program erase operation complete reading (Data# Polling) (toggle) status bits. After program erase cycle been completed, device ready read array data accept another command. sector erase architecture allows memory sectors erased reprogrammed without affecting data contents other sectors. device fully erased when shipped from factory. Hardware data protection measures include detector that automatically inhibits write operations during power transitions. hardware sector protection feature disables both program erase operations combination sectors memory. This achieved in-system programming equipment. Erase Suspend/Erase Resume feature enables user erase hold period time read data from, program data sector that selected erasure. True background erase thus achieved. read needed from SecSi Sector area (One Time Program area) after erase suspend, then user must proper command sequence enter exit this region. device offers power-saving features. When addresses have been stable specified amount time, device enters automatic sleep mode. system also place device into standby mode. Power consumption greatly reduced both these modes. device electrically erases bits within sector simultaneously Fowler-Nordheim tunneling. data programmed using electron injection.
S29PL127/129/064/032J_00A6 September 2004
TABLE CONTENTS
General Description
Simultaneous Read/Write Operation with Zero Latency Page Mode Features Standard Flash Memory Features
Persistent Sector Protection
Persistent Protection (PPB) Persistent Protection Lock (PPB Lock) Dynamic Protection (DYB) Persistent Sector Protection Mode Locking
Ordering Information Product Selector Guide Block Diagram Simultaneous Read/Write Block Diagram Simultaneous Read/Write Block Diagram (PL129J) Connection Diagrams
80-Ball Fine-pitch Special Package Handling Instructions 64-Ball Fine-pitch BGA-MCP Compatible Special Package Handling Instructions 48-Ball Fine-pitch
Password Protection Mode
Password Password Mode Locking 64-bit Password Write Protect (WP#) Persistent Protection Lock High Voltage Sector Protection
Figure In-System Sector Protection/Sector Unprotection Algorithms.
Temporary Sector Unprotect
Figure Temporary Sector Unprotect Operation
Connection Diagram (PL064J PL032J)
56-pin TSOP Configuration (PL127J) Special Package Handling Instructions
SecSi(Secured Silicon) Sector Flash Memory Region Factory-Locked Area words) Customer-Lockable Area words) SecSi Sector Protection Bits
Figure SecSi Sector Protect Verify
Description Logic Symbol Device Operations
Table PL127J Device Operations Table PL129J Device Operations
Hardware Data Protection Write Inhibit Write Pulse "Glitch" Protection Logical Inhibit Power-Up Write Inhibit
Requirements Reading Array Data Random Read (Non-Page Read) Page Mode Read
Table Page Select
Common Flash Memory Interface (CFI)
Table Query Identification String Table System Interface String Table Device Geometry Definition Table Primary Vendor-Specific Extended Query
Simultaneous Read/Write Operation
Table Bank Select
Command Definitions
Reading Array Data Reset Command Autoselect Command Sequence Enter SecSiSector/Exit SecSi Sector Command Sequence Word Program Command Sequence Unlock Bypass Command Sequence
Figure Program Operation
Writing Commands/Command Sequences Accelerated Program Operation Autoselect Functions Automatic Sleep Mode RESET#: Hardware Reset Output Disable Mode
Table PL127J Sector Architecture Table PL064J Sector Architecture Table PL032J Sector Architecture Table S29PL129J Sector Architecture Table SecSiSector Addresses
Chip Erase Command Sequence Sector Erase Command Sequence
Figure Erase Operation
Autoselect Mode
Table Autoselect Codes (High Voltage Method) Table Autoselect Codes PL129J Table PL127J Boot Sector/Sector Block Addresses Protection/Unprotection Table PL129J Boot Sector/Sector Block Addresses Protection/Unprotection Table PL064J Boot Sector/Sector Block Addresses Protection/Unprotection Table PL032J Boot Sector/Sector Block Addresses Protection/Unprotection
Erase Suspend/Erase Resume Commands Command Definitions Tables
Table Memory Array Command Definitions Table Sector Protection Command Definitions
Write Operation Status
DQ7: Data# Polling
Figure Data# Polling Algorithm
DQ6: Toggle
Figure Toggle Algorithm
Selecting Sector Protection Mode
Table Sector Protection Schemes
DQ2: Toggle Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limits DQ3: Sector Erase Timer
Table Write Operation Status
Sector Protection
Persistent Sector Protection Password Sector Protection Hardware Protection Selecting Sector Protection Mode
Absolute Maximum Ratings
Figure Maximum Overshoot Waveforms
Operating Ranges
Industrial Devices
September 2004 S29PL127/129/064/032J_00A6
Extended Devices Supply Voltages
Figure
Protect/Unprotect
Table Temporary Sector Unprotect Figure Temporary Sector Unprotect Timing Diagram Figure Sector/Sector Block Protect Unprotect Timing Diagram
Characteristics
Table CMOS Compatible
Characteristic
Test Conditions
Figure Test Setups. Table Test Specifications
Controlled Erase Operations
Table Alternate Controlled Erase Program Operations Figure Alternate Controlled Write (Erase/Program) Operation Timings. Table CE1#/CE2# Timing (S29PL129J only) Figure Timing Diagram Alternating Between CE1# CE2# Control. Table Erase Programming Performance
Switching Waveforms
Table Switching Waveforms Figure Input Waveforms Measurement Levels.
RampRate Read Operations
Table Read-Only Operations Figure Read Operation Timings Figure Page Read Operation Timings
Reset
Table Hardware Reset (RESET#) Figure Reset Timings.
Capacitance Physical Dimensions
VBG080-80-Ball Fine-pitch Ball Grid Array Package (PL127J) VBH064-64-Ball Fine-pitch Ball Grid Array 11.6 package (PL127J) VBK048-48-Ball Fine-pitch Ball Grid Array 8.15 6.15 package (PL127J) TLC056-56-Ball Fine-pitch package (PL064J PL032J) .101 TS056-20 56-pin TSOP (PL127J) .102
Erase/Program Operations
Table Erase Program Operations
Timing Diagrams
Figure Program Operation Timings Figure Accelerated Program Timing Diagram Figure Chip/Sector Erase Operation Timings Figure Back-to-back Read/Write Cycle Timings Figure Data# Polling Timings (During Embedded Algorithms). Figure Toggle Timings (During Embedded Algorithms)
Revision Summary
S29PL127/129/064/032J_00A6 September 2004
Ordering Information
order number (Valid Combination) formed following: S29PL127J
PACKING TYPE
Tray Tube Tape Reel Tape Reel 3.0V 1.8V 3.0V 3.0V 3.0V 3.0V VIO, VIO, VIO, VIO, VIO, VIO, 80-ball 80-ball 64-ball 48-ball 56-ball 56-ball FBGA (VBG080) FBGA (VBG080) 11.6 FBGA (VBH064) FBGA (VBK048) TSOP (TS056) FBGA (TLC056)
MODEL NUMBER (ADDITIONAL ORDERING OPTIONS)
TEMPERATURE RANGE
Wireless (-25°C +85°C) Industrial (-40°C +85°C)
Fine-Pitch Grid Array (FBGA) Lead (Pb)- free compliant Fine-Pitch Grid Array (FBGA) Lead (Pb)- free Thin Small Outline Package (TSOP) Standard Pinout Lead (Pb)- free compliant Thin Small Outline Package (TSOP) Standard Pinout Lead (Pb)- free
PACKAGE TYPE
CLOCK SPEED
(Contact factory availability)
DEVICE NUMBER/DESCRIPTION
Megabit 16-Bit), Megabit 16-Bit), Megabit 16-Bit) CMOS Flash Memory, Simultaneous Read/Write, Page Mode Flash Memory, Volt-only Read, Program, Erase
Valid Combinations Valid Combination configuration planned supported this device.
September 2004 S29PL127/129/064/032J_00A6
Products Based Floating Gate Technology Valid FBGA Package Combinations S29PL127J55BAI00 S29PL127J55BFI00 S29PL127J55BAW00 S29PL127J55BFW00 S29PL127J60BAI00 S29PL127J60BFI00 S29PL127J60BAW00 S29PL127J60BFW00 S29PL127J65BAI00 S29PL127J65BFI00 S29PL127J65BAW00 S29PL127J65BFW00 S29PL127J70BAI00 S29PL127J70BFI00 S29PL127J70BAW00 S29PL127J70BFW00 S29PL127J65BAI01 S29PL127J65BFI01 S29PL127J65BAW01 S29PL127J65BFW01 S29PL127J70BAI01 S29PL127J70BFI01 S29PL127J70BAW01 S29PL127J70BFW01 Package Marking PL127J55BAI00 PL127J55BFI00 PL127J55BAW00 PL127J55BFW00 PL127J60BAI00 PL127J60BFI00 PL127J60BAW00 PL127J60BFW00 PL127J65BAI00 PL127J65BFI00 PL127J65BAW00 PL127J65BFW00 PL127J70BAI00 PL127J70BFI00 PL127J70BAW00 PL127J70BFW00 PL127J60BAI01 PL127J60BFI01 PL127J60BAW01 PL127J60BFW01 PL127J70BAI01 PL127J70BFI01 PL127J70BAW01 PL127J70BFW01 Temperature Speed Configuration Package Type
(-40 (Note) (-25
(-40 (-25 (-40 (-25 ball FBGA Standalone Package (-40 (-25 VBG080 Single
(-40 (-25 (-40 (-25 Single
S29PL127/129/064/032J_00A6 September 2004
Products Based Floating Gate Technology Valid FBGA Package Combinations S29PL127J55BAI02 S29PL127J55BFI02 S29PL127J55BAW02 S29PL127J55BFW02 S29PL127J60BAI02 S29PL127J60BFI02 S29PL127J60BAW02 S29PL127J60BFW02 S29PL127J65BAI02 S29PL127J65BFI02 S29PL127J65BAW02 S29PL127J65BFW02 S29PL127J70BAI02 S29PL127J70BFI02 S29PL127J70BAW02 S29PL127J70BFW02 S29PL127J55TAI13 S29PL127J55TFI13 S29PL127J55TAW13 S29PL127J55TFW13 S29PL127J60TAI13 S29PL127J60TFI13 S29PL127J60TAW13 S29PL127J60TFW13 S29PL127J70TAI13 S29PL127J70TFI13 S29PL127J70TAW13 S29PL127J70TFW13 S29PL127J55TFI13 S29PL127J55TFW13 S29PL127J60TFI13 S29PL127J60TFW13 S29PL127J70TFI13 S29PL127J70TFW13 Package Marking PL127J55BAI02 PL127J55BFI02 PL127J55BAW02 PL127J55BFW02 PL127J60BAI02 PL127J60BFI02 PL127J60BAW02 PL127J60BFW02 PL127J65BAI02 PL127J65BFI02 PL127J65BAW02 PL127J65BFW02 PL127J70BAI02 PL127J70BFI02 PL127J70BAW02 PL127J70BFW02 PL127J55TAI13 PL127J55TFI13 PL127J55TAW13 PL127J55TFW13 PL127J60TAI13 PL127J60TFI13 PL127J60TAW13 PL127J60TFW13 PL127J70TAI13 PL127J70TFI13 PL127J70TAW13 PL127J70TFW13 PL127J55TFI13 PL127J55TFW13 S29PL127J60TFI13 PL127J60TFW13 PL127J70TFI13 PL127J70TFW13 Temperature Speed Configuration Package Type
(-40 (Note) (-25
(-40 (-25 (-40 (-25 Single 11.6 ball FBGA MCP-Compatible VBH064
(-40 (-25
(-40 (Note) (-25
(-40 (-25 Single 56-pin TSOP TS056
(-40 (-25 (Note)
(-40 (-25 (-40 (-25 (-40 (-25
Single
56-pin TSOP TS056
September 2004 S29PL127/129/064/032J_00A6
Products Based Floating Gate Technology Valid Combinations Packages S29PL064J55BAI12 S29PL064J55BFI12 S29PL064J55BAW12 S29PL064J55BFW12 S29PL064J60BAI12 S29PL064J60BFI12 S29PL064J60BAW12 S29PL064J60BFW12 S29PL064J70BAI12 S29PL064J70BFI12 S29PL064J70BAW12 S29PL064J70BFW12 S29PL064J55BAI15 S29PL064J55BFI15 S29PL064J55BAW15 S29PL064J55BFW15 S29PL064J60BAI15 S29PL064J60BFI15 S29PL064J60BAW15 S29PL064J60BFW15 S29PL064J70BAI15 S29PL064J70BFI15 S29PL064J70BAW15 S29PL064J70BFW15 Package Marking PL064J55BAI12 PL064J55BFI12 PL064J55BAW12 PL064J55BFW12 PL064J60BAI12 PL064J60BFI12 PL064J60BAW12 PL064J60BFW12 PL064J70BAI12 PL064J70BAFI12 PL064J70BAW12 PL064J70BFW12 PL064J55BAI15 PL064J55BFI15 PL064J55BAW15 PL064J55BFW15 PL064J60BAI15 PL064J60BFI15 PL064J60BAW15 PL064J60BFW15 PL064J70BAI15 PL064J70BFI15 PL064J70BAW15 PL064J70BFW15 Temperature (-40 (Note) (-25 Speed Package Type
(-40 (-25
48-ball Standalone Package VBK048
(-40 (-25
(-40 (Note) (-25
(-40 (-25
56-ball MCP-Compatible TLC056
(-40 (-25
S29PL127/129/064/032J_00A6 September 2004
Products Based Floating Gate Technology Valid Combinations Packages S29PL032J55BAI12 S29PL032J55BFI12 S29PL032J55BAW12 S29PL032J55BFW12 S29PL032J60BAI12 S29PL032J60BFI12 S29PL032J60BAW12 S29PL032J60BFW12 S29PL032J70BAI12 S29PL032J70BFI12 S29PL032J70BAW12 S29PL032J70BFW12 S29PL032J55BAI15 S29PL032J55BFI15 S29PL032J55BAW15 S29PL032J55BFW15 S29PL032J60BAI15 S29PL032J60BFI15 S29PL032J60BAW15 S29PL032J60BFW15 S29PL032J70BAI15 S29PL032J70BFI15 S29PL032J70BAW15 S29PL032J70BFW15 Package Marking PL032J55BAI12 PL032J55BFI12 PL032J55BAW12 PL032J55BFW12 PL032J60BAI12 PL032J60BFI12 PL032J60BAW12 PL032J60BFW12 PL032J70BAI12 PL032J70BFI12 PL032J70BAW12 PL032J70BFW12 PL032J55BAI15 PL032J55BFI15 PL032J55BAW15 PL032J55BFW15 PL032J60BAI15 PL032J60BFI15 PL032J60BAW15 PL032J60BFW15 PL032J70BAI15 PL032J70BFI15 PL032J70BAW15 PL032J70BFW15 Temperature (-40 Speed Package Type
(Note)
(-25
(-40 (-25
48-ball Standalone Package VBK048
(-40 (-25
(-40 (Note) (-25
(-40 (-25
56-ball MCP-Compatible TLC056
(-40 (-25
September 2004 S29PL127/129/064/032J_00A6
Valid Combinations Packages Order Number (note PL129J, PL127J PL064J, PL032J PL129J, PL127J PL064J, PL032J PL129J, PL127J PL064J, PL032J PL129J, PL127J PL064J, PL032J PL129J, PL127J PL129J, PL127J
Notes: Please contact factory PL129J availability. Please contact factory availability.
Speed (note
Range
2.7-3.6 1.65-1.95
Valid Combinations Packages Order Number PL127J Speed 2.7-3.6 Range
S29PL127/129/064/032J_00A6 September 2004
Product Selector Guide
Part Number VCC,VIO 2.7-3.6 Speed Option 2.7-3.6 1.65-1.95 (PL127J PL129J only) Access Time, (tACC) Access, (tCE) Page Access, (tPACC) Access, (tOE) Note: Contact factory availability (Note) (Note)
(Note)
Block Diagram
DQ15-DQ0 RY/BY# (See Note) Sector Switches
RESET# Erase Voltage Generator State Control Command Register Voltage Generator
Input/Output Buffers
Chip Enable Output Enable Logic
Data Latch
Y-Decoder Detector Timer
Address Latch
Y-Gating
Amax-A3
X-Decoder
Cell Matrix
A2-A0
Notes: RY/BY# open drain output. Amax (PL127J), (PL129J PL064J), (PL032J) PL129J there (CE1# CE2#)
September 2004 S29PL127/129/064/032J_00A6
Simultaneous Read/Write Block Diagram
Amax-A0
Bank Address
Bank
Y-gate
X-Decoder
A22-A0
RY/BY#
Bank Address
Bank X-Decoder
DQ15-DQ0
Amax-A0 RESET# WP#/ACC STATE CONTROL COMMAND REGISTER Status
DQ15-DQ0
DQ15-DQ0 Control
DQ15-DQ0
DQ0-DQ15
A22-A0
Bank Address
X-Decoder Bank
Y-gate
X-Decoder Amax-A0
Bank Address
Bank
Note: Amax (PL127J), (PL064J), (PL032J)
S29PL127/129/064/032J_00A6 September 2004
DQ15-DQ0
Simultaneous Read/Write Block Diagram (PL129J)
CE1#=L CE2#=H A21-A0
Bank Address
Bank
Y-gate
X-Decoder
A21-A0
RY/BY#
Bank Address
Bank X-Decoder
A21-A0 RESET# CE1# CE2# WP#/ACC STATE CONTROL COMMAND REGISTER CE1#=H CE2#=L DQ0-DQ15 X-Decoder Status
DQ15-DQ0
DQ15-DQ0
DQ15-DQ0 Control
A21-A0
X-Decoder A21-A0
Bank Address
Bank
Notes: Amax (PL129J)
September 2004 S29PL127/129/064/032J_00A6
DQ15-DQ0
Bank Address
Bank
Y-gate
DQ15-DQ0
Connection Diagrams
80-Ball Fine-pitch
80-Ball Fine-pitch (PL127J) View, Balls Facing Down
RESET#
DQ14 DQ12 DQ10
DQ15 DQ13 DQ11
RY/BY# WP#/ACC
Note: Pinout shown PL127J.
Special Package Handling Instructions
Special handling required Flash Memory products molded packages (TSOP, BGA, PDIP, SSOP, PLCC). package and/or data integrity compromised package body exposed temperatures above 150°C prolonged periods time.
S29PL127/129/064/032J_00A6 September 2004
64-Ball Fine-pitch BGA-MCP Compatible
64-Ball Fine-pitch BGA-MCP Compatible (PL127J) View, Balls Facing Down
CE#f1 DQ10 VCCf DQ11 VCCf DQ13 DQ12 DQ15 DQ14 CE2#
WP#/ACC
RESET#
RY/BY
Note: Pinout shown PL127J.
Special Package Handling Instructions
Special handling required Flash Memory products molded packages (TSOP, BGA, PDIP, SSOP, PLCC). package and/or data integrity compromised package body exposed temperatures above 150°C prolonged periods time.
September 2004 S29PL127/129/064/032J_00A6
48-Ball Fine-pitch
48-Ball Fine-pitch (PL064J/PL032J) View, Balls Facing Down
RESET#
DQ14 DQ12 DQ10
DQ15 DQ13 DQ11
RY/BY# WP#/ACC
Note: Pinout shows PL064J. PL032J, C4(A21)
S29PL127/129/064/032J_00A6 September 2004
Connection Diagram (PL064J PL032J)
56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
CE1#f CE1#s
DQ10
WP#/ACC RST# RY/BY#
CE2s
DQ15 DQ14
VCCf DQ11
VCCs
DQ13 DQ12
Special Handling Instructions FBGA Package
Special handling required Flash Memory products FBGA packages. Flash memory devices FBGA packages damaged exposed ultrasonic cleaning methods. package and/or data integrity compromised package body exposed temperatures above 150°C prolonged periods time.
September 2004 S29PL127/129/064/032J_00A6
56-pin TSOP Configuration (PL127J)
RESET# RY/BY# VSSQ VCCQ WP#/ACC DQ15 DQ14 DQ13 DQ12 VSSQ VCCQ DQ11 DQ10
56-pin TSOP
this family products, single multi-chip compatible package offered each density allow both standalone multi-chip qualification using single, adaptable package. This methodology allows package standardization resulting faster development. multi-chip compatible package includes pins required standalone device operation verification. addition, extra pins included insertion common data storage logic devices used multi-chip products. standalone device required, extra multi-chip specific pins connected standalone device operates normally. multi-chip compatible package sizes were chosen serve largest number combinations possible. There only cases where larger package size would required accommodate multi-chip combination. This multi-chip compatible package does allow direct package migration from Am29BDS128H, Am29BDS128G, Am29BDS640G products, which legacy standalone packages.
Special Package Handling Instructions
Special handling required Flash Memory products molded packages (TSOP, BGA, PDIP, SSOP, PLCC). package and/or data integrity compromised package body exposed temperatures above 150°C prolonged periods time.
S29PL127/129/064/032J_00A6 September 2004
Description
Amax-A0 DQ15-DQ0 RY/BY# Address 16-bit data inputs/outputs/float Chip Enable Inputs Output Enable Input Write Enable Device Ground Connected Internally Ready/Busy output open drain. When RY/BY#= VIH, device ready accept read operations commands. When RY/BY#= VOL, device either executing embedded algorithm device executing hardware reset operation. Write Protect/Acceleration Input. When WP#/ACC= VIL, highest lowest 4K-word sectors write protected regardless other sector protection configurations. When WP#/ACC= VIH, these sector unprotected unless programmed. When WP#/ACC= 12V, program erase operations accelerated. Input/Output Buffer Power Supply (1.65 1.95 (for PL127J PL129J) (for PLxxxJ devices)) Chip Power Supply (2.7 Hardware Reset Chip Enable Inputs. CE1# controls 64Mb Banks CE2# controls Banks (Only PL129J)
WP#/ACC
RESET# CE1#, CE2#
Notes: Amax (PL127J), (PL129J PL064J), (PL032J)
Logic Symbol
max+1 Amax-A0 WP#/ACC RESET# RY/BY# DQ15-DQ0
(VCCQ)
September 2004 S29PL127/129/064/032J_00A6
Device Operations
This section describes requirements device operations, which initiated through internal command register. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. contents register serve inputs internal state machine. state machine outputs dictate function device. Table lists device operations, inputs control levels they require, resulting output. following subsections describe each these operations further detail.
Table
Operation Read Write Standby Output Disable Reset Temporary Sector Unprotect (High Voltage)
PL127J Device Operations
RESET# WP#/ACC (Note (Note Addresses (Amax-A0) DQ15- DOUT High-Z High-Z High-Z
VIO±
Table
Operation Read CE1# VIO±
PL129J Device Operations
RESET# WP#/ACC (Note Addresses (A21-A0) DQ15- DOUT
CE2#
Write Standby Output Disable Reset Temporary Sector Unprotect (High Voltage)
High-Z High-Z High-Z
Legend: Logic VIL, Logic High VIH, 11.5-12.5 8.5-9.5 Don't Care, Sector Address, Address Data DOUT Data Notes: sector protect sector unprotect functions also implemented programming equipment. "High Voltage Sector Protection" section section. WP#/ACC must high when writing upper lower sectors.
S29PL127/129/064/032J_00A6 September 2004
Requirements Reading Array Data
read array data from outputs, system must drive appropriate pins (For PL129J CE1#/CE2# pins) VIL. PL129J, CE1# CE2# power control select lower (CE1#) upper (CE2#) halves device. power control. output control gates array data output pins. should remain VIH. internal state machine reading array data upon device power-up, after hardware reset. This ensures that spurious alteration memory content occurs during power transition. command necessary this mode obtain array data. Standard microprocessor read cycles that assert valid addresses device address inputs produce valid data device data outputs. Each bank remains enabled read access until command register contents altered. Refer Table timing specifications Figure timing diagram. ICC1 Characteristics table represents active current specification reading array data.
Random Read (Non-Page Read)
Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time (tCE) delay from stable addresses stable valid data output inputs. output enable access time delay from falling edge valid data output inputs (assuming addresses have been stable least tACC-tOE time).
Page Mode Read
device capable fast page mode read compatible with page mode Mask read operation. This mode provides faster read access speed random locations within page. Address bits Amax-A3 select word page, address bits A2-A0 select specific word within that page. This asynchronous operation with microprocessor supplying specific word location. random initial page access tACC subsequent page read accesses long locations specified microprocessor falls within that page) equivalent tPACC. When (CE1# CE#2 PL129J) deasserted (=VIH), reassertion (CE1# CE#2 PL129J) subsequent access access time tACC tCE. Here again, (CE1# /CE#2 PL129J)selects device output control should used gate data output inputs device selected. Fast page mode accesses obtained keeping Amax-A3 constant changing A2-A0 select specific word within that page.
Table Page Select
Word Word Word Word Word Word Word
September 2004 S29PL127/129/064/032J_00A6
Table
Word Word
Page Select (Continued)
Simultaneous Read/Write Operation
addition conventional features (read, program, erase-suspend read, erase-suspend program), device capable reading data from bank memory while program erase operation progress another bank memory (simultaneous operation). bank selected bank addresses (PL127J: A22-A20, PL129J PL064J: A21-A19, PL032J: A20-A18) with zero latency. simultaneous operation execute multi-function mode same bank.
Table
Bank Select PL127J: A22-A20 PL064J: A21-A19 PL032J: A20-A18
001, 010, 100, 101,
Bank Bank Bank Bank Bank
Bank Bank Bank Bank Bank
CE1#
CE2#
PL129J: A21-A20
Writing Commands/Command Sequences
write command command sequence (which includes programming data device erasing sectors memory), system must drive (CE1# CE#2 PL129J) VIL, VIH. device features Unlock Bypass mode facilitate faster programming. Once bank enters Unlock Bypass mode, only write cycles required program word, instead four. "Word Program Command Sequence" section details programming data device using both standard Unlock Bypass command sequences. erase operation erase sector, multiple sectors, entire device. Table indicates address space that each sector occupies. "bank address" address bits required uniquely select bank. Similarly, "sector address" refers address bits required uniquely select sector. "Command Definitions" section details erasing sector entire chip, suspending/resuming erase operation.
S29PL127/129/064/032J_00A6 September 2004
ICC2 Characteristics table represents active current specification write mode. timing specification tables timing diagrams "Reset" section write operations.
Accelerated Program Operation
device offers accelerated program operations through function. This function primarily intended allow faster manufacturing throughput factory. system asserts this pin, device automatically enters aforementioned Unlock Bypass mode, temporarily unprotects protected sectors, uses higher voltage reduce time required program operations. system would two-cycle program command sequence required Unlock Bypass mode. Removing from WP#/ACC returns device normal operation. Note that must asserted WP#/ACC operations other than accelerated programming, device damage result. addition, WP#/ACC should raised when use. That WP#/ACC should left floating unconnected; inconsistent behavior device result.
Autoselect Functions
system writes autoselect command sequence, device enters autoselect mode. system then read autoselect codes from internal register (which separate from memory array) DQ15-DQ0. Standard read cycle timings apply this mode. Refer "SecSiSector Addresses" section "Autoselect Command Sequence" section more information.
Standby Mode
When system reading writing device, place device standby mode. this mode, current consumption greatly reduced, outputs placed high impedance state, independent input. device enters CMOS standby mode when (CE1#,CE#2 PL129J) RESET# pins both held (Note that this more restricted voltage range than VIH.) (CE1#,CE#2 PL129J) RESET# held VIH, within device will standby mode, standby current will greater. device requires standard access time (tCE) read access when device either these standby modes, before ready read data. device deselected during erasure programming, device draws active current until operation completed. ICC3 Characteristics" represents CMOS standby current specification.
Automatic Sleep Mode
automatic sleep mode minimizes Flash device energy consumption. device automatically enables this mode when addresses remain stable tACC automatic sleep mode independent CE#, WE#, control signals. Standard address access timings provide data when addresses changed. While sleep mode, output data latched always available system. Note that during automatic sleep mode, must before device reduces current stated sleep mode specification. ICC5 Characteristics" represents automatic sleep mode current specification.
September 2004 S29PL127/129/064/032J_00A6
RESET#: Hardware Reset
RESET# provides hardware method resetting device reading array data. When RESET# driven least period tRP, device immediately terminates operation progress, tristates output pins, ignores read/write commands duration RESET# pulse. device also resets internal state machine reading array data. operation that interrupted should reinitiated once device ready accept another command sequence, ensure data integrity. Current reduced duration RESET# pulse. When RESET# held VSS±0.3 device draws CMOS standby current (ICC4). RESET# held within VSS±0.3 standby current will greater. RESET# tied system reset circuitry. system reset would thus also reset Flash memory, enabling system read boot-up firmware from Flash memory. RESET# asserted during program erase operation, RY/BY# remains (busy) until internal reset operation complete, which requires time tREADY (during Embedded Algorithms). system thus monitor RY/BY# determine whether reset operation complete. RESET# asserted when program erase operation executing (RY/BY# "1"), reset operation completed within time tREADY (not during Embedded Algorithms). system read data after RESET# returns VIH. Refer Characteristic" section tables RESET# parameters timing diagram.
Output Disable Mode
When input VIH, output from device disabled. output pins (except RY/BY#) placed highest Impedance state
S29PL127/129/064/032J_00A6 September 2004
Table
Bank Sector
SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 Bank SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
PL127J Sector Architecture
Sector Size (Kwords)
Sector Address (A22-A12)
00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 00000100XXX 00000101XXX 00000110XXX 00000111XXX 00001000XXX 00001001XXX 00001010XXX 00001011XXX 00001100XXX 00001101XXX 00001110XXX 00001111XXX 00010000XXX 00010001XXX 00010010XXX 00010011XXX 00010100XXX 00010101XXX 00010110XXX 00010111XXX 00011000XXX 00011001XXX 00011010XXX 00011011XXX 00011100XXX 00011101XXX 00011110XXX 00011111XXX
Address Range (x16)
000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh
September 2004 S29PL127/129/064/032J_00A6
Table PL127J Sector Architecture (Continued)
Bank Sector
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78
Sector Address (A22-A12)
00100000XXX 00100001XXX 00100010XXX 00100011XXX 00100100XXX 00100101XXX 00100110XXX 00100111XXX 00101000XXX 00101001XXX 00101010XXX 00101011XXX 00101100XXX 00101101XXX 00101110XXX 00101111XXX 00110000XXX 00110001XXX 00110010XXX 00110011XXX 00110100XXX 00110101XXX 00110110XXX 00110111XXX 00111000XXX 00111001XXX 00111010XXX 00111011XXX 00111100XXX 00111101XXX 00111110XXX 00111111XXX 01000000XXX 01000001XXX 01000010XXX 01000011XXX 01000100XXX 01000101XXX 01000110XXX 01000111XXX
Sector Size (Kwords)
Address Range (x16)
100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh
S29PL127/129/064/032J_00A6 September 2004
Table PL127J Sector Architecture (Continued)
Bank Sector
SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 Bank SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
Sector Address (A22-A12)
01001000XXX 01001001XXX 01001010XXX 01001011XXX 01001100XXX 01001101XXX 01001110XXX 01001111XXX 01010000XXX 01010001XXX 01010010XXX 01010011XXX 01010100XXX 01010101XXX 01010110XXX 01010111XXX 01011000XXX 01011001XXX 01011010XXX 01011011XXX 01011100XXX 01011101XXX 01011110XXX 01011111XXX 01100000XXX 01100001XXX 01100010XXX 01100011XXX 01100100XXX 01100101XXX 01100110XXX 01100111XXX 01101000XXX 01101001XXX 01101010XXX 01101011XXX 01101100XXX 01101101XXX 01101110XXX 01101111XXX
Sector Size (Kwords)
Address Range (x16)
240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh
September 2004 S29PL127/129/064/032J_00A6
Table PL127J Sector Architecture (Continued)
Bank Sector
SA119 SA120 SA121 SA122 SA123 SA124 SA125 Bank SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 Bank SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158
Sector Address (A22-A12)
01110000XXX 01110001XXX 01110010XXX 01110011XXX 01110100XXX 01110101XXX 01110110XXX 01110111XXX 01111000XXX 01111001XXX 01111010XXX 01111011XXX 01111100XXX 01111101XXX 01111110XXX 01111111XXX 10000000XXX 10000001XXX 10000010XXX 10000011XXX 10000100XXX 10000101XXX 10000110XXX 10000111XXX 10001000XXX 10001001XXX 10001010XXX 10001011XXX 10001100XXX 10001101XXX 10001110XXX 10001111XXX 10010000XXX 10010001XXX 10010010XXX 10010011XXX 10010100XXX 10010101XXX 10010110XXX 10010111XXX
Sector Size (Kwords)
Address Range (x16)
380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh 400000h-407FFFh 408000h-40FFFFh 410000h-417FFFh 418000h-41FFFFh 420000h-427FFFh 428000h-42FFFFh 430000h-437FFFh 438000h-43FFFFh 440000h-447FFFh 448000h-44FFFFh 450000h-457FFFh 458000h-45FFFFh 460000h-467FFFh 468000h-46FFFFh 470000h-477FFFh 478000h-47FFFFh 480000h-487FFFh 488000h-48FFFFh 490000h-497FFFh 498000h-49FFFFh 4A0000h-4A7FFFh 4A8000h-4AFFFFh 4B0000h-4B7FFFh 4B8000h-4BFFFFh
S29PL127/129/064/032J_00A6 September 2004
Table PL127J Sector Architecture (Continued)
Bank Sector
SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 Bank SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198
Sector Address (A22-A12)
10011000XXX 10011001XXX 10011010XXX 10011011XXX 10011100XXX 10011101XXX 10011110XXX 10011111XXX 10100000XXX 10100001XXX 10100010XXX 10100011XXX 10100100XXX 10100101XXX 10100110XXX 10100111XXX 10101000XXX 10101001XXX 10101010XXX 10101011XXX 10101100XXX 10101101XXX 10101110XXX 10101111XXX 10110000XXX 10110001XXX 10110010XXX 10110011XXX 10110100XXX 10110101XXX 10110110XXX 10110111XXX 10111000XXX 10111001XXX 10111010XXX 10111011XXX 10111100XXX 10111101XXX 10111110XXX 10111111XXX
Sector Size (Kwords)
Address Range (x16)
4C0000h-4C7FFFh 4C8000h-4CFFFFh 4D0000h-4D7FFFh 4D8000h-4DFFFFh 4E0000h-4E7FFFh 4E8000h-4EFFFFh 4F0000h-4F7FFFh 4F8000h-4FFFFFh 500000h-507FFFh 508000h-50FFFFh 510000h-517FFFh 518000h-51FFFFh 520000h-527FFFh 528000h-52FFFFh 530000h-537FFFh 538000h-53FFFFh 540000h-547FFFh 548000h-54FFFFh 550000h-557FFFh 558000h-15FFFFh 560000h-567FFFh 568000h-56FFFFh 570000h-577FFFh 578000h-57FFFFh 580000h-587FFFh 588000h-58FFFFh 590000h-597FFFh 598000h-59FFFFh 5A0000h-5A7FFFh 5A8000h-5AFFFFh 5B0000h-5B7FFFh 5B8000h-5BFFFFh 5C0000h-5C7FFFh 5C8000h-5CFFFFh 5D0000h-5D7FFFh 5D8000h-5DFFFFh 5E0000h-5E7FFFh 5E8000h-5EFFFFh 5F0000h-5F7FFFh 5F8000h-5FFFFFh
September 2004 S29PL127/129/064/032J_00A6
Table PL127J Sector Architecture (Continued)
Bank Sector
SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 Bank SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230
Sector Address (A22-A12)
11000000XXX 11000001XXX 11000010XXX 11000011XXX 11000100XXX 11000101XXX 11000110XXX 11000111XXX 11001000XXX 11001001XXX 11001010XXX 11001011XXX 11001100XXX 11001101XXX 11001110XXX 11001111XXX 11010000XXX 11010001XXX 11010010XXX 11010011XXX 11010100XXX 11010101XXX 11010110XXX 11010111XXX 11011000XXX 11011001XXX 11011010XXX 11011011XXX 11011100XXX 11011101XXX 11011110XXX 11011111XXX
Sector Size (Kwords)
Address Range (x16)
600000h-607FFFh 608000h-60FFFFh 610000h-617FFFh 618000h-61FFFFh 620000h-627FFFh 628000h-62FFFFh 630000h-637FFFh 638000h-63FFFFh 640000h-647FFFh 648000h-64FFFFh 650000h-657FFFh 658000h-65FFFFh 660000h-667FFFh 668000h-66FFFFh 670000h-677FFFh 678000h-67FFFFh 680000h-687FFFh 688000h-68FFFFh 690000h-697FFFh 698000h-69FFFFh 6A0000h-6A7FFFh 6A8000h-6AFFFFh 6B0000h-6B7FFFh 6B8000h-6BFFFFh 6C0000h-6C7FFFh 6C8000h-6CFFFFh 6D0000h-6D7FFFh 6D8000h-6DFFFFh 6E0000h-6E7FFFh 6E8000h-6EFFFFh 6F0000h-6F7FFFh 6F8000h-6FFFFFh
S29PL127/129/064/032J_00A6 September 2004
Table PL127J Sector Architecture (Continued)
Bank Sector
SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 Bank SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
Sector Address (A22-A12)
11100000XXX 11100001XXX 11100010XXX 11100011XXX 11100100XXX 11100101XXX 11100110XXX 11100111XXX 11101000XXX 11101001XXX 11101010XXX 11101011XXX 11101100XXX 11101101XXX 11101110XXX 11101111XXX 11110000XXX 11110001XXX 11110010XXX 11110011XXX 11110100XXX 11110101XXX 11110110XXX 11110111XXX 11111000XXX 11111001XXX 11111010XXX 11111011XXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111
Sector Size (Kwords)
Address Range (x16)
700000h-707FFFh 708000h-70FFFFh 710000h-717FFFh 718000h-71FFFFh 720000h-727FFFh 728000h-72FFFFh 730000h-737FFFh 738000h-73FFFFh 740000h-747FFFh 748000h-74FFFFh 750000h-757FFFh 758000h-75FFFFh 760000h-767FFFh 768000h-76FFFFh 770000h-777FFFh 778000h-77FFFFh 780000h-787FFFh 788000h-78FFFFh 790000h-797FFFh 798000h-79FFFFh 7A0000h-7A7FFFh 7A8000h-7AFFFFh 7B0000h-7B7FFFh 7B8000h-7BFFFFh 7C0000h-7C7FFFh 7C8000h-7CFFFFh 7D0000h-7D7FFFh 7D8000h-7DFFFFh 7E0000h-7E7FFFh 7E8000h-7EFFFFh 7F0000h-7F7FFFh 7F8000h-7F8FFFh 7F9000h-7F9FFFh 7FA000h-7FAFFFh 7FB000h-7FBFFFh 7FC000h-7FCFFFh 7FD000h-7FDFFFh 7FE000h-7FEFFFh 7FF000h-7FFFFFh
September 2004 S29PL127/129/064/032J_00A6
Table
Bank Sector
Bank SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 Bank SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47
PL064J Sector Architecture
Sector Size (Kwords)
Sector Address (A22-A12)
0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX 0100000XXX 0100001XXX 0100010XXX 0100011XXX 0100100XXX 0100101XXX 0100110XXX 0100111XXX 0101000XXX
Address Range (x16)
000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh
S29PL127/129/064/032J_00A6 September 2004
Table
Bank Sector
SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 Bank SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 Bank SA90 SA91 SA92 SA93 SA94 SA95
PL064J Sector Architecture (Continued)
Sector Address (A22-A12)
0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX 1001000XXX 1001001XXX 1001010XXX 1001011XXX 1001100XXX 1001101XXX 1001110XXX 1001111XXX 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX
Sector Size (Kwords)
Address Range (x16)
148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh
September 2004 S29PL127/129/064/032J_00A6
Table
Bank Sector
SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 Bank SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 Bank SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
PL064J Sector Architecture (Continued)
Sector Address (A22-A12)
1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX 1111000XXX 1111001XXX 1111010XXX 1111011XXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111
Sector Size (Kwords)
Address Range (x16)
2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh
S29PL127/129/064/032J_00A6 September 2004
Table
Bank Sector
Bank SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 Bank SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
PL032J Sector Architecture
Sector Size (Kwords)
Sector Address (A22-A12)
000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001XXX 000010XXX 000011XXX 000100XXX 000101XXX 000110XXX 000111XXX 001000XXX 001001XXX 001010XXX 001011XXX 001100XXX 001101XXX 001110XXX 001111XXX 010000XXX 010001XXX 010010XXX 010011XXX 010100XXX 010101XXX 010110XXX 010111XXX 011000XXX 011001XXX 011010XXX 011011XXX 011100XXX 011101XXX 011110XXX 011111XXX
Address Range (x16)
000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh
September 2004 S29PL127/129/064/032J_00A6
Table PL032J Sector Architecture (Continued)
Bank Sector
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 Bank SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 Bank SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77
Sector Address (A22-A12)
100000XXX 100001XXX 100010XXX 100011XXX 100100XXX 100101XXX 100110XXX 100111XXX 101000XXX 101001XXX 101010XXX 101011XXX 101100XXX 101101XXX 101110XXX 101111XXX 110000XXX 110001XXX 110010XXX 110011XXX 110100XXX 110101XXX 110110XXX 110111XXX 111000XXX 111001XXX 111010XXX 111011XXX 111100XXX 111101XXX 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111
Sector Size (Kwords)
Address Range (x16)
100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh
S29PL127/129/064/032J_00A6 September 2004
Table
Bank Sector
SA1-0 SA1-1 SA1-2 SA1-3 SA1-4 SA1-5 SA1-6 SA1-7 SA1-8 SA1-9 SA1-10 SA1-11 SA1-12 SA1-13 SA1-14 SA1-15 SA1-16 SA1-17 Bank SA1-18 SA1-19 SA1-20 SA1-21 SA1-22 SA1-23 SA1-24 SA1-25 SA1-26 SA1-27 SA1-28 SA1-29 SA1-30 SA1-31 SA1-32 SA1-33 SA1-34 SA1-35 SA1-36 SA1-37 SA1-38
S29PL129J Sector Architecture
CE2#
CE1#
Sector Address (A21-A12)
0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX
Sector Size (Kwords)
Address Range (x16)
000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh
September 2004 S29PL127/129/064/032J_00A6
Table S29PL129J Sector Architecture (Continued)
Bank Sector
SA1-39 SA1-40 SA1-41 SA1-42 SA1-43 SA1-44 SA1-45 SA1-46 SA1-47 SA1-48 SA1-49 SA1-50 SA1-51 SA1-52 SA1-53 SA1-54 SA1-55 SA1-56 SA1-57 SA1-58 Bank SA1-59 SA1-60 SA1-61 SA1-62 SA1-63 SA1-64 SA1-65 SA1-66 SA1-67 SA1-68 SA1-69 SA1-70 SA1-71 SA1-72 SA1-73 SA1-74 SA1-75 SA1-76 SA1-77 SA1-78 SA1-79 SA1-80 SA1-81 SA1-82
CE1#
CE2#
Sector Address (A21-A12)
0100000XXX 0100001XXX 0100010XXX 0100011XXX 0100100XXX 0100101XXX 0100110XXX 0100111XXX 0101000XXX 0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX 1001000XXX 1001001XXX 1001010XXX 1001011XXX
Sector Size (Kwords)
Address Range (x16)
100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh
S29PL127/129/064/032J_00A6 September 2004
Table S29PL129J Sector Architecture (Continued)
Bank Sector
SA1-83 SA1-84 SA1-85 SA1-86 SA1-87 SA1-88 SA1-89 SA1-90 SA1-91 SA1-92 SA1-93 SA1-94 SA1-95 SA1-96 SA1-97 SA1-98 SA1-99 SA1-100 SA1-101 SA1-102 Bank SA1-103 SA1-104 SA1-105 SA1-106 SA1-107 SA1-108 SA1-109 SA1-110 SA1-111 SA1-112 SA1-113 SA1-114 SA1-115 SA1-116 SA1-117 SA1-118 SA1-119 SA1-120 SA1-121 SA1-122 SA1-123 SA1-124 SA1-125 SA1-126
CE1#
CE2#
Sector Address (A21-A12)
1001100XXX 1001101XXX 1001110XXX 1001111XXX 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX 1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX
Sector Size (Kwords)
Address Range (x16)
260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh
September 2004 S29PL127/129/064/032J_00A6
Table S29PL129J Sector Architecture (Continued)
Bank Sector
SA1-127 SA1-128 Bank SA1-129 SA1-130 SA1-131 SA1-132 SA1-133 SA1-134 SA2-0 SA2-1 SA2-2 SA2-3 SA2-4 SA2-5 SA2-6 SA2-7 SA2-8 SA2-9 SA2-10 SA2-11 SA2-12 SA2-13 SA2-14 SA2-15 Bank SA2-16 SA2-17 SA2-18 SA2-19 SA2-20 SA2-21 SA2-22 SA2-23 SA2-24 SA2-25 SA2-26 SA2-27 SA2-28 SA2-29 SA2-30 SA2-31 SA2-32 SA2-33 SA2-34 SA2-35
CE1#
CE2#
Sector Address (A21-A12)
1111000XXX 1111001XXX 1111010XXX 1111011XXX 1111100XXX 1111101XXX 1111110XXX 1111111XXX 0000000XXX 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX 0100000XXX 0100001XXX 0100010XXX 0100011XXX
Sector Size (Kwords)
Address Range (x16)
3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh
S29PL127/129/064/032J_00A6 September 2004
Table S29PL129J Sector Architecture (Continued)
Bank Sector
SA2-36 SA2-37 Bank SA2-38 SA2-39 SA2-40 SA2-41 SA2-42 SA2-43 SA2-44 SA2-45 SA2-46 SA2-47 SA2-48 SA2-49 SA2-50 SA2-51 SA2-52 SA2-53 SA2-54 SA2-55 SA2-56 SA2-57 SA2-58 SA2-59 Bank SA2-60 SA2-61 SA2-62 SA2-63 SA2-64 SA2-65 SA2-66 SA2-67 SA2-68 SA2-69 SA2-70 SA2-71 SA2-72 SA2-73 SA2-74 SA2-75 SA2-76 SA2-77 SA2-78 SA2-79
CE1#
CE2#
Sector Address (A21-A12)
0100100XXX 0100101XXX 0100110XXX 0100111XXX 0101000XXX 0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX 1001000XXX 1001001XXX 1001010XXX 1001011XXX 1001100XXX 1001101XXX 1001110XXX 1001111XXX
Sector Size (Kwords)
Address Range (x16)
120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh
September 2004 S29PL127/129/064/032J_00A6
Table S29PL129J Sector Architecture (Continued)
Bank Sector
SA2-80 SA2-81 SA2-82 SA2-83 SA2-84 SA2-85 Bank SA2-86 SA2-87 SA2-88 SA2-89 SA2-90 SA2-91 SA2-92 SA2-93 SA2-94 SA2-95 SA2-96 SA2-97 SA2-98 SA2-99 SA2-100 SA2-101 SA2-102 SA2-103 SA2-104 SA2-105 SA2-106 SA2-107 Bank SA2-108 SA2-109 SA2-110 SA2-111 SA2-112 SA2-113 SA2-114 SA2-115 SA2-116 SA2-117 SA2-118 SA2-119 SA2-120 SA2-121 SA2-122 SA2-123
CE1#
CE2#
Sector Address (A21-A12)
1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX 1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX 1111000XXX 1111001XXX 1111010XXX 1111011XXX
Sector Size (Kwords)
Address Range (x16)
280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh
S29PL127/129/064/032J_00A6 September 2004
Table S29PL129J Sector Architecture (Continued)
Bank Sector
SA2-124 SA2-125 SA2-126 SA2-127 Bank SA2-128 SA2-129 SA2-130 SA2-131 SA2-132 SA2-133 SA2-134
CE1#
CE2#
Sector Address (A21-A12)
1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111
Sector Size (Kwords)
Address Range (x16)
3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh
Table
SecSiSector Addresses
Sector Size Address Range 000000h-00003Fh 000040h-00007Fh
Factory-Locked Area Customer-Lockable Area
words words
Autoselect Mode
autoselect mode provides manufacturer device identification, sector protection verification, through identifier codes output DQ7-DQ0. This mode primarily intended programming equipment automatically match device programmed with corresponding programming algorithm. However, autoselect codes also accessed in-system through command register. When using programming equipment, autoselect mode requires address Address pins must shown Table Table addition, when verifying sector protection, sector address must appear appropriate highest order address bits (see Table Table Table show remaining address bits that don't care. When necessary bits have been required, programming equipment then read corresponding identifier code DQ7-DQ0. However, autoselect codes also accessed in-system through command register, instances when device erased programmed system without access high voltage pin. command sequence illustrated Table Note that Bank Address (BA) address bits PL127J: A22-A20, PL129J PL064J: A21-A19, PL032J: A20-A18) asserted during third write cycle autoselect command, host system read autoselect data that bank then immediately read array data from other bank, without exiting autoselect mode. access autoselect codes in-system, host system issue autoselect command command register, shown Table This method does require VID. Refer "Autoselect Command Sequence" section more information.
September 2004 S29PL127/129/064/032J_00A6
Table
Autoselect Codes (High Voltage Method)
DQ15 0001h
Description Manufacturer Spansion products Read Cycle Device Read Cycle Read Cycle Sector Protection Verification SecSi Indicator (DQ7, DQ6)
Amax
227Eh 2220h (PL127J) 2202h (PL064J) 220Ah (PL032J) 2200h (PL127J) 2201h (PL064J) 2201h (PL032J) 0001h (protected), 0000h (unprotected) DQ7=1 (factory locked), DQ6=1 (factory customer locked)
Table
Autoselect Codes PL129J
DQ15 0001h
Description Manufacturer Spansion products Read Cycle Device Read Cycle Read Cycle Sector Protection Verification SecSi Indicator (DQ7, DQ6)
CE1# CE2#
227Eh
2221h
2200h 0001h (protected), 0000h (unprotected) DQ7=1 (factory locked), DQ6=1 (factory customer locked)
Legend: Logic VIL, Logic High VIH, Bank Address, Sector Address, Don't care. Note: autoselect codes also accessed in-system command sequences
S29PL127/129/064/032J_00A6 September 2004
Table
Sector SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130
PL127J Boot Sector/Sector Block Addresses Protection/Unprotection
A22-A12 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 000001XXXXX 000010XXXXX 000011XXXXX 000100XXXXX 000101XXXXX 000110XXXXX 000111XXXXX 001000XXXXX 001001XXXXX 001010XXXXX 001011XXXXX 001100XXXXX 001101XXXXX 001110XXXXX 001111XXXXX 010000XXXXX 010001XXXXX 010010XXXXX 010011XXXXX 010100XXXXX 010101XXXXX 010110XXXXX 010111XXXXX 011000XXXXX 011001XXXXX 011010XXXXX 011011XXXXX 011100XXXXX 011101XXXXX 011110XXXXX Sector/ Sector Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords Sector SA131-SA134 SA135-SA138 SA139-SA142 SA143-SA146 SA147-SA150 SA151-SA154 SA155-SA158 SA159-SA162 SA163-SA166 SA167-SA170 SA171-SA174 SA175-SA178 SA179-SA182 SA183-SA186 SA187-SA190 SA191-SA194 SA195-SA198 SA199-SA202 SA203-SA206 SA207-SA210 SA211-SA214 SA215-SA218 SA219-SA222 SA223-SA226 SA227-SA230 SA231-SA234 SA235-SA238 SA239-SA242 SA243-SA246 SA247-SA250 SA251-SA254 SA255-SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 A22-A12 011111XXXXX 100000XXXXX 100001XXXXX 100010XXXXX 100011XXXXX 100100XXXXX 100101XXXXX 100110XXXXX 100111XXXXX 101000XXXXX 101001XXXXX 101010XXXXX 101011XXXXX 101100XXXXX 101101XXXXX 101110XXXXX 101111XXXXX 110000XXXXX 110001XXXXX 110010XXXXX 110011XXXXX 110100XXXXX 110101XXXXX 110110XXXXX 110111XXXXX 111000XXXXX 111001XXXXX 111010XXXXX 111011XXXXX 111100XXXXX 111101XXXXX 111110XXXXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 Sector/ Sector Block Size (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
September 2004 S29PL127/129/064/032J_00A6
Table
PL129J Boot Sector/Sector Block Addresses Protection/Unprotection
CE1# Control CE2# Control Sector/Sector Block Size
Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords
Sector Group
SA1-0 SA1-1 SA1-2 SA1-3 SA1-4 SA1-5 SA1-6 SA1-7 SA1-8 SA1-9 SA1-10 SA1-11 SA1-14 SA1-15 SA1-18 SA1-19 SA1-22 SA1-23 SA1-26 SA1-27 SA1-30 SA1-31 SA1-34 SA1-35 SA1-38 SA1-39 SA1-42 SA1-43 SA1-46 SA1-47 SA1-50 SA1-51 SA1-54 SA1-55 SA1-58 SA1-59 SA1-62 SA1-63 SA1-66 SA1-67 SA1-70 SA1-71 SA1-74 SA1-75 SA1-78 SA1-79 SA1-82 SA1-83 SA1-86 SA1-87 SA1-90 SA1-91 SA1-94 SA1-95 SA1-98 SA1-99 SA1-102 SA1-103 SA1-106 SA1-107 SA1-110 SA1-111 SA1-114 SA1-115 SA1-118 SA1-119 SA1-122 SA1-123 SA1-126 SA1-127 SA1-130 SA1-131 SA1-134
A21-12
0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 11111XXXXX
Sector Group
SA2-0-SA2-3 SA2-4-SA2-7 SA2-8-SA2-11 SA2-12-SA2-15 SA2-16-SA2-19 SA2-20-SA2-23 SA2-24-SA2-27 SA2-28-SA2-31 SA2-32-SA2-35 SA2-36-SA2-39 SA2-40-SA2-43 SA2-44-SA2-47 SA2-48-SA2-51 SA2-52-SA2-55 SA2-56-SA2-59 SA2-60-SA2-63 SA2-64-SA2-67 SA2-68-SA2-71 SA2-72-SA2-75 SA2-76-SA2-79 SA2-80-SA2-83 SA2-84-SA2-87 SA2-88-SA2-91 SA2-92-SA2-95 SA2-96-SA2-99 SA2-100-SA2-103 SA2-104-SA2-107 SA2-108-SA2-111 SA2-112-SA2-115 SA2-116-SA2-119 SA2-120-SA2-123 SA2-124 SA2-125 SA2-126 SA2-127 SA2-128 SA2-129 SA2-130 SA2-131 SA2-132 SA2-133 SA2-134
A21-12
00000XXXXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111
Sector/Sector Block Size
(4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
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Table
Sector
SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
PL064J Boot Sector/Sector Block Addresses Protection/Unprotection
A21-A12
0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111
Sector/Sector Block Size
Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
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Table
Sector
SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77
PL032J Boot Sector/Sector Block Addresses Protection/Unprotection
A21-A12
000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001XXX 000010XXX 000011XXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX 0110XXXXX 0111XXXXX 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX 1110XXXXX 111100XXX 111101XXX 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111
Sector/Sector Block Size
Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords (4x32) Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
Selecting Sector Protection Mode
device shipped with sectors unprotected. Optional Spansion programming services enable programming protecting sectors factory prior shipping device. Contact your local sales office details. possible determine whether sector protected unprotected. "SecSiSector Addresses" section details.
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Table
Lock
Sector Protection Schemes
Sector State Unprotected-PPB changeable Unprotected-PPB changeable, changeable
Protected-PPB changeable
Protected-PPB changeable, changeable
Sector Protection
PL127J, PL129J, PL064J, PL032J features several levels sector protection, which disable both program erase operations certain sectors sector groups:
Persistent Sector Protection
command sector protection method that replaces controlled protection method.
Password Sector Protection
highly sophisticated protection method that requires password before changes certain sectors sector groups permitted
Hardware Protection
write protect that prevent program erase operations sectors SA1-133, SA1-134, SA2-0 SA2-1. Hardware Protection feature always available, independent software managed protection method chosen.
Selecting Sector Protection Mode
parts default operate Persistent Sector Protection mode. customer must then choose Persistent Password Protection method most desirable. There one-time programmable non-volatile bits that define which sector protection method will used. Persistent Sector Protection method desired, programming Persistent Sector Protection Mode Locking permanently sets device Persistent Sector Protection mode. Password Sector Protection method desired, programming Password Mode Locking permanently sets device Password Sector Protection mode. possible switch between protection modes once locking been set. modes must selected when device first programmed. This prevents program virus from later setting Password Mode Locking Bit, which would cause unexpected shift from default Persistent Sector Protection Mode into Password Protection Mode.
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device shipped with sectors unprotected. Optional Spansion programming services enable programming protecting sectors factory prior shipping device. Contact your local sales office details. possible determine whether sector protected unprotected. Autoselect Mode details.
Persistent Sector Protection
Persistent Sector Protection method replaces controlled protection method previous flash devices. This method provides three different sector protection states: Persistently Locked-The sector protected cannot changed. Dynamically Locked-The sector protected changed simple command. Unlocked-The sector unprotected changed simple command. achieve these states, three types "bits" used: Persistent Protection Persistent Protection Lock Persistent Sector Protection Mode Locking
Persistent Protection (PPB)
single Persistent (non-volatile) Protection assigned maximum four sectors (see sector address tables specific sector protection groupings). Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) greater flexibility. Each individually modifiable through Write Command. device erases PPBs parallel. requires erasure, device must instructed preprogram sector PPBs prior erasure. Otherwise, previously erased sector PPBs potentially over-erased. flash device does have built-in means preventing sector PPBs over-erasure.
Persistent Protection Lock (PPB Lock)
Persistent Protection Lock (PPB Lock) global volatile bit. When "1", PPBs cannot changed. When cleared ("0"), PPBs changeable. There only Lock device. Lock cleared after power-up hardware reset. There command sequence unlock Lock.
Dynamic Protection (DYB)
volatile protection assigned each sector. After power-up hardware reset, contents DYBs "0". Each individually modifiable through Write Command. When parts first shipped, PPBs cleared, DYBs cleared, Lock defaulted power cleared state meaning PPBs changeable. When device first powered DYBs power cleared (sectors protected). Protection State each sector determined logical related that sector. sectors that have PPBs cleared, DYBs control whether sector protected unprotected. issuing Write command sequences, DYBs will cleared, thus placing each sector protected unprotected state. These
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so-called Dynamic Locked Unlocked states. They called dynamic states because very easy switch back forth between protected unprotected conditions. This allows software easily protect sectors against inadvertent changes does prevent easy removal protection when changes needed. DYBs maybe cleared often needed. PPBs allow more static, difficult change, level protection. PPBs retain their state across power cycles because they non-volatile. Individual PPBs with command must cleared group through complex sequence program erasing commands. PPBs also limited erase cycles. Lock adds additional level protection. Once PPBs programmed desired settings, Lock "1". Setting Lock disables program erase commands non-volatile PPBs. effect, Lock locks PPBs into their current state. only clear Lock through power cycle. System boot code determine changes needed; example, allow system code downloaded. changes needed then boot code Lock disable further changes PPBs during system operation. WP#/ACC write protect adds final level hardware protection sectors SA1-133, SA1-134, SA2-0 SA2-1. When this possible change contents these sectors. These sectors generally hold system boot code. WP#/ACC prevent changes boot code that could override choices made while setting sector protection during system initialization. customers concerned about malicious viruses there another level security persistently locked state. persistently protect given sector sector group, PPBs associated with that sector need "1". Once PPBs programmed desired settings, Lock should "1". Setting Lock automatically disables program erase commands Non-Volatile PPBs. effect, Lock "freezes" PPBs into their current state. only clear Lock through power cycle. possible have sectors that have been persistently locked, sectors that left dynamic state. sectors dynamic state unprotected. there need protect some them, simple Write command sequence that necessary. write command dynamic sectors switch DYBs signify protected unprotected, respectively. there need change status persistently locked sectors, more steps required. First, Lock must disabled either putting device through power-cycle, hardware reset. PPBs then changed reflect desired settings. Setting lock once again will lock PPBs, device operates normally again. best protection achieved executing lock command early boot code, protect boot code holding WP#/ACC VIL. Table contains possible combinations DYB, PPB, lock relating status sector. summary, set, lock set, sector protected protection removed until next power cycle clears lock. cleared, sector dynamically locked unlocked. then controls whether sector protected unprotected.
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user attempts program erase protected sector, device ignores command returns read mode. program command protected sector enables status polling approximately before device returns read mode without having modified contents protected sector. erase command protected sector enables status polling approximately after which device returns read mode without having erased protected sector. programming DYB, PPB, lock given sector verified writing DYB/PPB/PPB lock verify command device. There alternative means reading protection status. Take RESET# hold VIH.(The high voltage Autoselect Mode also works reading status PPBs). Scanning addresses (A18-A11) while (A6, will produce logical code device output protected sector unprotected sector. this mode, other addresses don't cares. Address location with reserved autoselect manufacturer device codes.
Persistent Sector Protection Mode Locking
Like password mode locking bit, Persistent Sector Protection mode locking exists guarantee that device remain software sector protection. Once set, Persistent Sector Protection locking prevents programming password protection mode locking bit. This guarantees that hacker could place device password protection mode.
Password Protection Mode
Password Sector Protection Mode method allows even higher level security than Persistent Sector Protection Mode. There main differences between Persistent Sector Protection Password Sector Protection Mode: When device first powered comes reset cycle, Lock locked state, rather than cleared unlocked state. only means clear Lock writing unique 64-bit Password device. Password Sector Protection method otherwise identical Persistent Sector Protection method. 64-bit password only additional tool utilized this method. Once Password Mode Locking set, password permanently with means read, program, erase password used clear Lock bit. Password Unlock command must written flash, along with password. flash device internally compares given password with pre-programmed password. they match, Lock cleared, PPBs altered. they match, flash device does nothing. There built-in delay each "password check." This delay intended thwart efforts program that tries possible combinations order crack password.
Password Password Mode Locking
order select Password sector protection scheme, customer must first program password. password correlated unique Electronic Serial Number (ESN) particular flash device. Each different every
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flash device; therefore each password should different every flash device. While programming password region, customer perform Password Verify operations. Once desired password programmed customer must then Password Mode Locking Bit. This operation achieves objectives: Permanently sets device operate using Password Protection Mode. possible reverse this function. Disables further commands password region. program, read operations ignored. Both these objectives important, carefully considered, lead unrecoverable errors. user must sure that Password Protection method desired when setting Password Mode Locking Bit. More importantly, user must sure that password correct when Password Mode Locking set. fact that read operations disabled, there means verify what password afterwards. password lost after setting Password Mode Locking Bit, there will clear Lock bit. Password Mode Locking Bit, once set, prevents reading 64-bit password further password programming. Password Mode Locking erasable. Once Password Mode Locking programmed, Persistent Sector Protection Locking disabled from programming, guaranteeing that changes protection scheme allowed.
64-bit Password
64-bit Password located memory space accessible through Password Program Verify commands (see "Password Verify Command"). password function works conjunction with Password Mode Locking Bit, which when set, prevents Password Verify command from reading contents password pins device.
Write Protect (WP#)
Write Protect feature provides hardware method protecting upper lower sectors without using VID. This function provided overrides previously discussed "High Voltage Sector Protection" section method. system asserts WP#/ACC pin, device disables program erase functions outermost Kword sectors both ends flash array independent whether previously protected unprotected. system asserts WP#/ACC pin, device reverts upper lower sectors whether they were last protected unprotected. That sector protection unprotection these sectors depends whether they were last protected unprotected using method described "High Voltage Sector Protection" section. Note that WP#/ACC must left floating unconnected; inconsistent behavior device result.
Persistent Protection Lock
Persistent Protection (PPB) Lock volatile that reflects state Password Mode Locking after power-up reset. Password Mode Lock also after hardware reset (RESET# asserted) power-up reset, ONLY means clearing Lock Password Protection Mode issue
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Password Unlock command. Successful execution Password Unlock command clears Lock Bit, allowing sector PPBs modifications. Asserting RESET#, taking device through power-on reset, issuing Lock command sets Lock when Password Mode Lock set. Password Mode Locking set, including Persistent Protection Mode, Lock cleared after power-up hardware reset. Lock issuing Lock command. Once only means clearing Lock issuing hardware power-up reset. Password Unlock command ignored Persistent Protection Mode.
High Voltage Sector Protection
Sector protection unprotection also implemented using programming equipment. procedure requires high voltage (VID) placed RESET# pin. Refer Figure details this procedure. Note that sector unprotect, unprotected sectors must first protected prior first sector write cycle.
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START PLSCNT RESET# Wait Protect sectors: indicated portion sector protect algorithm must performed unprotected sectors prior issuing first sector unprotect address
START PLSCNT RESET# Wait
Temporary Sector Unprotect Mode
First Write Cycle 60h? sector address Sector Protect: Write sector address with A7-A0 00000010 Wait Verify Sector Protect: Write sector address with A7-A0 00000010 Read from sector address with A7-A0 00000010
First Write Cycle 60h? sectors protected? first sector address
Temporary Sector Unprotect Mode
Sector Unprotect: Write sector address with A7-A0 01000010 Reset PLSCNT Wait Verify Sector Unprotect: Write sector address with A7-A0 00000010
Increment PLSCNT
PLSCNT Remove from RESET# Data 01h?
Increment PLSCNT
Read from sector address with A7-A0 00000010 next sector address
Protect another sector? Remove from RESET#
PLSCNT 1000? Remove from RESET#
Data 00h?
Write reset command
Sector Protect complete Write reset command Device failed
Last sector verified? Remove from RESET#
Write reset command Sector Unprotect complete
Sector Protect complete
Sector Protect Algorithm
Write reset command Device failed Sector Unprotect complete
Sector Unprotect Algorithm
Figure In-System Sector Protection/Sector Unprotection Algorithms
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Temporary Sector Unprotect
This feature allows temporary unprotection previously protected sectors change data in-system. Sector Unprotect mode activated setting RESET# VID. During this mode, formerly protected sectors programmed erased selecting sector addresses. Once removed from RESET# pin, previously protected sectors protected again. shows algorithm, shows timing diagrams, this feature. While lock set, device cannot enter Temporary Sector Unprotection Mode.
START
RESET# (Note Perform Erase Program Operations
RESET#
Temporary Sector Unprotect Completed (Note
Notes: protected sectors unprotected WP#/ACC VIL, upper lower sectors will remain protected). previously protected sectors protected once again
Figure
Temporary Sector Unprotect Operation
SecSi(Secured Silicon) Sector Flash Memory Region
SecSi (Secured Silicon) Sector feature provides Flash memory region that enables permanent part identification through Electronic Serial Number (ESN) 128-word SecSi sector divided into factory-lockable words that programmed locked customer. SecSi sector located addresses 000000h-00007Fh both Persistent Protection mode Password Protection mode. Indicator bits used indicate factory-locked customer locked status part. system accesses SecSi Sector through command sequence (see "Enter SecSiSector/Exit SecSi Sector Command Sequence" section). After system written Enter SecSi Sector command sequence, read SecSi Sector using addresses normally occupied boot sectors. This mode operation continues until system issues Exit SecSi Sector command sequence, until power removed from device. power-up, following hardware reset, device reverts sending commands normal address space. Note that function unlock bypass modes available when SecSi Sector enabled.
Factory-Locked Area words)
factory-locked area SecSi Sector (000000h-00003Fh) locked when part shipped, whether area programmed factory.
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SecSi Sector Factory-locked Indicator (DQ7) permanently "1". Optional Spansion programming services program factory-locked area with random ESN, customer-defined code, combination two. Because only Spansion program protect factory-locked area, this method ensures security once product shipped field. Contact your local sales office details using Spansion's programming services. Note that function unlock bypass modes available when SecSi sector enabled.
Customer-Lockable Area words)
customer-lockable area SecSi Sector (000040h-00007Fh) shipped unprotected, which allows customer program optionally lock area appropriate application. SecSi Sector Customer-locked Indicator (DQ6) shipped permanently locked issuing SecSi Protection Program Command. SecSi Sector read number times, programmed locked only once. Note that accelerated programming (ACC) unlock bypass functions available when programming SecSi Sector. Customer-lockable SecSi Sector area protected using following procedures: Write three-cycle Enter SecSi Sector Region command sequence, then follow in-system sector protect algorithm shown Figure except that RESET# either VID. This allows in-system protection SecSi Sector Region without raising device high voltage. Note that this method only applicable SecSi Sector. verify protect/unprotect status SecSi Sector, follow algorithm shown Figure Once SecSi Sector locked verified, system must write Exit SecSi Sector Region command sequence return reading writing remainder array. SecSi Sector lock must used with caution since, once locked, there procedure available unlocking SecSi Sector area none bits SecSi Sector memory space modified way.
SecSi Sector Protection Bits
SecSi Sector Protection Bits prevent programming SecSi Sector memory area. Once set, SecSi Sector memory area contents non-modifiable.
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START RESET# Wait Write address data 00h, SecSi Sector unprotected. data 01h, SecSi Sector protected.
Remove from RESET#
Write SecSi Sector address with Read from SecSi Sector address with
Write reset command SecSi Sector Protect Verify complete
Figure
SecSi Sector Protect Verify
Hardware Data Protection
command sequence requirement unlock cycles programming erasing provides data protection against inadvertent writes. addition, following hardware data protection measures prevent accidental erasure programming, which might otherwise caused spurious system level signals during power-up power-down transitions, from system noise.
Write Inhibit
When less than VLKO, device does accept write cycles. This protects data during power-up power-down. command register internal program/erase circuits disabled, device resets read mode. Subsequent writes ignored until greater than VLKO. system must provide proper signals control pins prevent unintentional writes when greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses less than (typical) OE#, CE#, (CE1#, CE2# PL129J) initiate write cycle.
Logical Inhibit
Write cycles inhibited holding VIL, (CE1# CE2# PL129J)= VIH. initiate write cycle, (CE1# CE2# PL129J) must logical zero while logical one.
Power-Up Write Inhibit
(CE1#, CE2# PL129J) during power device does accept commands rising edge WE#. internal state machine automatically reset read mode power-up.
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Common Flash Memory Interface (CFI)
Common Flash Interface (CFI) specification outlines device host system software interrogation handshake, which allows specific vendor-specified software algorithms used entire families devices. Software support then device-independent, JEDEC ID-independent, forward- backward-compatible specified flash device families. Flash vendors standardize their existing interfaces long-term compatibility. This device enters Query mode when system writes Query command, 98h, address 55h, time device ready read array data. system read information addresses given Tables 17-20. terminate reading data, system must write reset command. Query mode accessible when device executing Embedded Program embedded Erase algorithm. system also write query command when device autoselect mode. device enters query mode, system read data addresses given Tables 17-20. system must write reset command return device reading array data. further information, please refer Specification Publication 100. Contact your local sales office copies these documents.
Table
Addresses Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
Query Identification String
Description
Query Unique ASCII string "QRY"
Primary Command Address Primary Extended Table Alternate Command (00h none exists) Address Alternate Extended Table (00h none exists)
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Table
Addresses Data 0027h 0036h 0000h 0000h 0003h 0000h 0009h 0000h 0004h 0000h 0004h 0000h
System Interface String
Description
Min. (write/erase) D7-D4: volt, D3-D0: millivolt Max. (write/erase) D7-D4: volt, D3-D0: millivolt Min. voltage (00h present) Max. voltage (00h present) Typical timeout single byte/word write Typical timeout Min. size buffer write (00h supported) Typical timeout individual block erase Typical timeout full chip erase (00h supported) Max. timeout byte/word write times typical Max. timeout buffer write times typical Max. timeout individual block erase times typical Max. timeout full chip erase times typical (00h supported)
Table Device Geometry Definition
Addresses Data 0018h (PL127J) 0018h (PL129J) 0017h (PL064J) 0016h (PL032J) 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh (PL127J) 00FDh (PL129J) 007Dh (PL064J) 003Dh (PL032J) 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Device Size byte Description
Flash Device Interface description (refer publication 100) Max. number byte multi-byte write (00h supported) Number Erase Block Regions within device Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
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Table Primary Vendor-Specific Extended Query
Addresses Data 0050h 0052h 0049h 0031h 0033h Query-unique ASCII string "PRI" Major version number, ASCII (reflects modifications silicon) Minor version number, ASCII (reflects modifications table) Address Sensitive Unlock (Bits 1-0) Required, Required Silicon Revision Number (Bits 7-2) 0002h 0001h 0001h 0007h (PLxxxJ) 00E7h (PL127J) 00E7h (PL129J) 0077h (PL064J) 003Fh (PL032J) 0000h 0002h (PLxxxJ) 0085h 0095h Erase Suspend Supported, Read Only, Read Write Sector Protect Supported, Number sectors group Sector Temporary Unprotect Supported, Supported Sector Protect/Unprotect scheme Advanced Sector Protection Simultaneous Operation Supported, Number Sectors excluding Bank Burst Mode Type Supported, Supported Page Mode Type Supported, Word Page, Word Page (Acceleration) Supply Minimum Supported, D7-D4: Volt, D3-D0: (Acceleration) Supply Maximum Supported, D7-D4: Volt, D3-D0: Top/Bottom Boot Sector Flag Uniform device, Both bottom boot with write protect, Bottom Boot Device, Boot Device, Both Bottom Program Suspend supported, Supported Bank Organization Data zero, Number Banks Bank Region Information Number Sectors Bank Description
0001h
0001h 0004h 0027h (PL127J) 0027h (PL129J) 0017h (PL064J) 000Fh (PL032J) 0060h (PL127J) 0060h (PL129J) 0030h (PL064J) 0018h (PL032J)
Bank Region Information Number Sectors Bank
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Table Primary Vendor-Specific Extended Query (Continued)
Addresses Data 0060h (PL127J) 0060h (PL129J) 0030h (PL064J) 0018h (PL032J) 0027h (PL127J) 0027h (PL129J) 0017h (PL064J) 000Fh (PL032J) Bank Region Information Number Sectors Bank Description
Bank Region Information Number Sectors Bank
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Command Definitions
Writing specific address data commands sequences into command register initiates device operations. Table defines valid register command sequences. Writing incorrect address data values writing them improper sequence place device unknown state. reset command then required return device reading array data. addresses latched falling edge (CE1# CE2# PL129J), whichever happens later. data latched rising edge (CE1# CE2# PL129J), whichever happens first. Refer Characteristic" section section timing diagrams.
Reading Array Data
device automatically reading array data after device power-up. commands required retrieve data. Each bank ready read array data after completing Embedded Program Embedded Erase algorithm. After device accepts Erase Suspend command, corresponding bank enters erase-suspend-read mode, after which system read data from non-erase-suspended sector within same bank. system read array data using standard read timing, except that reads address within erase-suspended sectors, device outputs status data. After completing programming operation Erase Suspend mode, system once again read array data with same exception. "Erase Suspend/Erase Resume Commands" section section more information. system must issue reset command return bank read erase-suspend-read) mode goes high during active program erase operation, bank autoselect mode. next section, "Reset Command" section, more information. also "Requirements Reading Array Data" section "Device Operations" section section more information. Characteristic" section table provides read parameters, Figure shows timing diagram.
Reset Command
Writing reset command resets banks read erase-suspend-read mode. Address bits don't cares this command. reset command written between sequence cycles erase command sequence before erasing begins. This resets bank which system writing read mode. Once erasure begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles program command sequence before programming begins. This resets bank which system writing read mode. program command sequence written bank that Erase Suspend mode, writing reset command returns that bank erase-suspend-read mode. Once programming begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles autoselect command sequence. Once autoselect mode, reset command must written return read mode. bank entered autoselect mode while Erase Suspend mode, writing reset command returns that bank erase-suspend-read mode.
September 2004 S29PL127/129/064/032J_00A6
goes high during program erase operation, writing reset command returns banks read mode erase-suspend-read mode that bank Erase Suspend).
Autoselect Command Sequence
autoselect command sequence allows host system access manufacturer device codes, determine whether sector protected. autoselect command sequence written address within bank that either read erase-suspend-read mode. autoselect command written while device actively programming erasing other bank. autoselect command sequence initiated first writing unlock cycles. This followed third write cycle that contains bank address autoselect command. bank then enters autoselect mode. system read number autoselect codes without reinitiating command sequence. Table shows address data requirements. determine sector protection information, system must write appropriate bank address (BA) sector address (SA). Table shows address range bank number associated with each sector. system must write reset command return read mode erase-suspend-read mode bank previously Erase Suspend).
Enter SecSiSector/Exit SecSi Sector Command Sequence
SecSi Sector region provides secured data area containing random, eight word electronic serial number (ESN). system access SecSi Sector region issuing three-cycle Enter SecSi Sector command sequence. device continues access SecSi Sector region until system issues four-cycle Exit SecSi Sector command sequence. Exit SecSi Sector command sequence returns device normal operation. SecSi Sector accessible when device executing Embedded Program embedded Erase algorithm. Table shows address data requirements both command sequences. also "SecSi(Secured Silicon) Sector Flash Memory Region" further information. Note that function unlock bypass modes available when SecSi Sector enabled.
Word Program Command Sequence
Programming four-bus-cycle operation. program command sequence initiated writing unlock write cycles, followed program set-up command. program address data written next, which turn initiate Embedded Program algorithm. system required provide further controls timings. device automatically provides internally generated program pulses verifies programmed cell margin. Table shows address data requirements program command sequence. Note that SecSi Sector, autoselect, functions unavailable when [program/erase] operation progress. When Embedded Program algorithm complete, that bank then returns read mode addresses longer latched. system determine status program operation using DQ7, DQ6, RY/BY#. Refer "Write Operation Status" section section information these status bits. commands written device during Embedded Program Algorithm ignored. Note that hardware reset immediately terminates program
S29PL127/129/064/032J_00A6 September 2004
operation. program command sequence should reinitiated once that bank returned read mode, ensure data integrity. Note that SecSi Sector, autoselect functions unavailable when SecSi Sector enabled. Programming allowed sequence across sector boundaries. cannot programmed from back "1." Attempting cause that bank cause status bits indicate operation successful. However, succeeding read will show that data still "0." Only erase operations convert "1."
Unlock Bypass Command Sequence
unlock bypass feature allows system program data bank faster than using standard program command sequence. unlock bypass command sequence initiated first writing unlock cycles. This followed third write cycle containing unlock bypass command, 20h. That bank then enters unlock bypass mode. two-cycle unlock bypass program command sequence that required program this mode. first cycle this sequence contains unlock bypass program command, A0h; second cycle contains program address data. Additional data programmed same manner. This mode dispenses with initial unlock cycles required standard program command sequence, resulting faster total programming time. Table shows requirements command sequence. During unlock bypass mode, only Unlock Bypass Program Unlock Bypass Reset commands valid. exit unlock bypass mode, system must issue two-cycle unlock bypass reset command sequence. (See Table device offers accelerated program operations through WP#/ACC pin. When system asserts WP#/ACC pin, device automatically enters Unlock Bypass mode. system then write two-cycle Unlock Bypass program command sequence. device uses higher voltage WP#/ACC accelerate operation. Note that WP#/ACC must operation other than accelerated programming, device damage result. addition, WP#/ACC must left floating unconnected; inconsistent behavior device result. illustrates algorithm program operation. Refer "Erase/Program Operations" section table Characteristics section parameters, Figure timing diagrams.
September 2004 S29PL127/129/064/032J_00A6
START
Write Program Command Sequence
Embedded Program algorithm progress
Data Poll from System
Verify Data?
Increment Address
Last Address?
Programming Completed
Note: Table program command sequence.
Figure Program Operation
Chip Erase Command Sequence
Chip erase cycle operation. chip erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed chip erase command, which turn invokes Embedded Erase algorithm. device does require system preprogram prior erase. Embedded Erase algorithm automatically preprograms verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. Table shows address data requirements chip erase command sequence. When Embedded Erase algorithm complete, that bank returns read mode addresses longer latched. system determine status erase operation using DQ7, DQ6, DQ2, RY/BY#. Refer "Write Operation Status" section section information these status bits. commands written during chip erase operation ignored. Note that SecSi Sector, autoselect, functions unavailable when [program/erase] operation progress. However, note that hardware reset immediately terminates erase operation. that occurs, chip erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity.
S29PL127/129/064/032J_00A6 September 2004
illustrates algorithm erase operation. Refer "Erase/Program Operations" section tables Characteristics section parameters, Figure section timing diagrams.
Sector Erase Command Sequence
Sector erase cycle operation. sector erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock cycles written, then followed address sector erased, sector erase command. Table shows address data requirements sector erase command sequence. device does require system preprogram prior erase. Embedded Erase algor
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