SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SC
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
REJ03B0132-0100Z Rev.1.00 2001
DESCRIPTION
M3727GM6/M8-XXXSP/FP single-chip microcomputers designed with CMOS silicon gate technology. They have OSD, data slicer, I2C-BUS interface, useful channel selection system with closed caption decoder. features M37272E8SP/FP similar those M3727GM6/M8-XXXSP/FP except that these chips have built-in PROM which written electrically. difference between M3727GM6-XXXSP/FP M3727GM8-XXXSP/FP size size. Accordingly, following descriptions will M3727GM6-XXXSP/FP.
FEATURES
Number basic instructions Memory size bytes (M3727GM6-XXXSP/FP) bytes (M3727GM8-XXXSP/FP, M37272E8SP/FP) 1024 bytes (M3727GM6-XXXSP/FP) 1152 bytes (M3727GM8-XXXSP/FP, M37272E8SP/FP) (*ROM correction memory included) Minimum instruction execution time oscillation frequency) Power source voltage Subroutine nesting levels (Max.) Interrupts types, vectors 8-bit timers Programmable ports (Ports P30, P31) Input ports (Ports P50, P51) Output ports (Ports P52-P55) drive ports Serial 8-bit channel Multi-master I2C-BUS interface systems) comparator (6-bit resolution) channels output circuit 8-bit Power dissipation high-speed mode 137.5 5.5V, oscillation frequency, Data slicer low-speed mode 0.33 5.5V, oscillation frequency) correction function vectors Closed caption data slicer
function Display characters characters lines possible display lines more software) Kinds characters kinds Character display area mode: dots mode: dots Kinds character sizes mode: kind mode: kinds Kinds character colors colors Coloring unit character, character background, raster Display position Horizontal: levels Vertical: levels Attribute mode: smooth italic, underline, flash, automatic solid space mode: border Smoth roll-up Window function
APPLICATION
with closed caption decoder
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
TABLE CONTENTS
DESCRIPTION FEATURES APPLICATION CONFIGURATION FUNCTIONAL BLOCK DIAGRAM PERFORMANCE OVERVIEW DESCRIPTION FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) MEMORY INTERRUPTS TIMERS SERIAL MULTI-MASTER I2C-BUS INTERFACE OUTPUT FUNCTION COMPARATOR CORRECTION FUNCTION 8.10 DATA SLICER 8.11 FUNCTIONS 8.11.1 Display Position 8.11.2 Size 8.11.3 Clock 8.11.4 Field Determination Display 8.11.5 Memory 8.11.6 Character color 8.11.7 Character background color 8.11.8 OUT1, OUT2 signals 8.11.9 Attribute 8.11.10 Multiline Display 8.11.11 Automatic Solid Space Function 8.11.12 Window Function 8.11.13 Output Control 8.11.14 Raster Coloring Function 8.12 SOFTWARE RUNAWAY DETECT FUNCTION 8.13. RESET CIRCUIT 8.14 CLOCK GENERATING CIRCUIT 8.15 DISPLAY OSCILLATION CIRCUIT 8.16 AUTO-CLEAR CIRCUIT 8.17 ADDRESSING MODE 8.18 MACHINE INSTRUCTIONS PROGRAMMING NOTES ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRIC CHARACTERISTICS CONVERTER CHARACTERISTICS MULTI-MASTER I2C-BUS LINE CHARACTERISTICS PROM PROGRAMMING METHOD DATA REQUIRED MASK ORDERS TIME PROM VERSION M37272E8SP/FP MARKING APPENDIX PACKAGE OUTLINE
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
CONFIGURATION
P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/AD4 P07/INT1 P23/TIM3 P24/TIM2
P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P17/AD3 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT
M3727GM6/M8-XXXSP M37272E8SP
.M37272E8SP
VHOLD CVIN CNVSS XOUT
Outline 42P4B
Note: Only 14th M3727GM6/ M8-XXXSP. This AVcc M37272E8SP. M3727GM6/M8-XXXSP connect inside apply Vcc.
Fig. Configuration (Top View)
P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/AD4 P07/INT1 P23/TIM3 P24/TIM2
P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P17/AD3 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT
M3727GM6/M8-XXXFP M37272E8FP
.M37272E8FP
VHOLD CVIN CNVSS XOUT
Outline 42P2R-A/E
Note: Only 14th M3727GM6/ M8-XXXFP. This AVcc M37272E8FP. M3727GM6/M8-XXXFP connect inside apply Vcc.
Fig. Configuration (Top View)
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Clock input Clock output Pins data slicer CVIN VHOLD
XOUT
Reset input (AVCC) ).M37272E8SP/FP CNVSS RESET
ports P26, Clock input Clock output OSD/ OSD/sub-clock input sub-clock output OSC1/XCIN OSC2/XCOUT
INT1 INT2 INT3
SDA2 SDA1 SCL2 SCL1
SCLK SOUT
PWM5 PWM4
PWM3
PWM2 PWM1 PWM0
AD1-6
port port
port
ports P30,
Output ports P52-P55 Output display Input ports P50, Synchronous signal input
OUT1 VSYNC HSYNC
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Data slicer TIM2 TIM3 Timer count source selection circuit
Program counter
Clock generating circuit
Fig. Functional Block Diagram M3727G
Timer Timer Timer Timer Control signal
Index register
Data
FUNCTIONAL BLOCK DIAGRAM
M3727GM6/M8-XXXSP/FP M37272E8SP/FP
page
Instruction register Stack pointer Timer Timer Instruction decoder circuit
Multi-master I2C-BUS interface
Progam counter
correction circuit
Address
8-bit arithmetic logical unit
Accumulator
Processor status register
Index register
comparator SI/O
OUT2
M3727GM6/M8-XXXSP/FP M37272E8SP/FP
PERFORMANCE OVERVIEW
Table Performance Overview Parameter Number basic instructions Instruction execution time Clock frequency Memory size Functions (the minimum instruction execution time, oscillation frequency) (maximum) bytes bytes 1024 bytes (ROM correction memory included) 1152 bytes (ROM correction memory included) bytes bytes 8-bit (N-channel open-drain output structure, used output pins, input pins, input pin) 8-bit (CMOS input/output structure, however, N-channel open-drain output structure, when P11-P14 used multi-master I2C-BUS interface, used output pin, input pins, input pin, multimaster I2C-BUS interface) 8-bit CMOS input/output structure, however, N-channel opendrain output structure when used serial output, used serial input/output pins, timer external clock input pins, clock input/output pin, sub-clock input/output pins) 2-bit (CMOS input/output N-channel open-drain output structure, used input pins) 2-bit (can used input pins) 4-bit (CMOS output structure, used output pins) 8-bit systems) channels (6-bit resolution) 8-bit 8-bit timer vectors levels (maximum) types> external interrupt Internal timer interrupt Serial interrupt interrupt Multi-master I2C-BUS interface interrupt Data slicer interrupt f(XIN)/4096 interrupt VSYNC interrupt instruction interrupt reset built-in circuits (externally connected ceramic resonator quartzcrystal oscillator) Built-in
Input/Output ports
M3727GM6-XXXSP/FP M3727GM8-XXXSP/FP, M37272E8SP/FP M3727GM6-XXXSP/FP M3727GM8-XXXSP/FP, M37272E8SP/FP P10-P17
P20-P27
P30, P50, P52-P55 Serial Multi-master I2C-BUS interface comparator output circuit Timers correction function Subroutine nesting Interrupt
Input Output
Clock generating circuit Data slicer
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
Table Performance Overview (Continued) Parameter Number display characters structure Kinds characters Kinds character sizes screen Character font coloring Display position Power source voltage Power high-speed dissipation mode low-speed mode stop mode Operating temperature range Device structure M3727GM6/M8-XXXSP, M37272E8FP Package M3727GM6/M8-XXXSP, M37272E8FP Data slicer Data slicer Data slicer Functions characters lines mode: dots (character display area dots) mode: dots kinds mode: kinds mode: kinds screen: kinds (per character unit) Horizontal: levels, Vertical: levels 137.5mW typ. oscillation frequency f(XIN) MHz, fOSC MHz) <165mW typ. When M37272E8SP/FP 55mW typ. oscillation frequency f(XIN) MHz) <82.5mW typ. When M37272E8SP/FP 0.33 typ. oscillation frequency f(XCIN) kHz, f(XIN) stopped) 0.055 maximum CMOS silicon gate process 42-pin plastic molded 42-pin plastic molded SSOP
function
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
DESCRIPTION
Table Description Name Input/ Output
Only M37272E8SP/FP
Functions Apply voltage (typical) (AVCC), VSS. This connected VSS.
VCC, (AVCC) Power source CNVSS
CNVSS Reset input Input
RESET
enter reset state, reset input must kept more (under normal conditions). more time needed quartz-crystal oscillator stabilize, this condition should maintained required time. This chip internal clock generating circuit. control generating frequency, external ceramic resonator quartz-crystal oscillator connected between pins XOUT. external clock used, clock source should connected XOUT should left open. Port 8-bit port with direction register allowing each individually programmed input output. reset, this port input mode. output structure N-channel open-drain output. (See note Pins P00-P05 also used output pins PWM0-PWM5 respectively. output structure N-channel open-drain output. Pins also used external interrupt input pins INT2 INT1 respectively. also used analog input AD4. Port 8-bit port basically same functions port output structure CMOS output. (See note Pins also used output OUT2. output structure CMOS output. Pins P11-P14 used SCL1, SCL2, SDA1 SDA2 respectively, when multi-master I2C-BUS interface used. output structure N-channel open-drain output. Pins P10, P15-P17 also used analog input AD8, AD1-AD3 respectively. also used external interrupt input INT3. Port 8-bit port basically same functions port output structure CMOS output. (See note also used serial synchronous clock input/output SCLK. output structure N-channel open-drain output. also used serial data output SOUT. output structure open-drain output. also used serial data input SIN. Pins also used timer external clock input pins TIM3 TIM2 respectively. also used clock input OSC1. (See note also used clock input OSC2. output structure CMOS output. (See note also used sub-clock input XCIN. also used sub-clock output XCOUT.
XOUT
Clock input Clock output
Input Output
P00/PWM0- port P05/PWM5, P06/INT2/AD4, P07/INT1 output External interrupt input Analog input P10/OUT2, port P11/SCL1, P12/SCL2, output P13/SDA1, P14/SDA2, P15/AD1/INT3, P16/AD2, P17/AD3 P20/SCLK, P21/SOUT, P22/SIN, P23/TIM3, P24/TIM2, P25, P26/OSC1/ XCIN, P27/OSC2/ XCOUT Multi-master I2C-BUS interface Analog input External interrupt input port Serial synchronous clock input/output port Serial data output Serial data input External clock input timer Clock input Clock output Sub-clock input Sub-clock output
Output Input Input Output Input Input Input Input Input Output Input Output
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
Table Description (continued) P30/AD5, P31/AD6 Name port Input/ Output Functions Ports 2-bit port basically same functions port output structure selected either CMOS output N-channel open-drain output structure. (See notes Pins also used analog input pins respectively. 2-bit input ports. also used HSYNC input. This horizontal synchronous signal input OSD. also used VSYNC input. This vertical synchronous signal input OSD. Ports P52-P55 4-bit output port. output structure CMOS output. Pins P52-P55 also used output pins OUT1 respectively. output structure CMOS output. Input composite video signal through capacitor. Connect capacitor between VHOLD Vss. Connect filter using capacitor resistor between Vss.
Analog input P50/HSYNC, Input port P51/VSYNC P52/R, P53/G, P54/B, P55/OUT1 CVIN VHOLD HSYNC input VSYNC input Output port output data slicer
Input Input Input Input Output Output Input Input
Notes Port port direction register which used program each input ("0") output ("1"). pins programmed direction register output pins. When pins programmed "0," they input pins. When pins programmed output pins, output data written into port latch then output. When data read from output pins, output level read data port latch read. This allows previously-output value read correctly even output voltage risen, example, because light emitting diode directly driven. input pins floating state, values pins read. When data written into input pin, written only into port latch, while remains floating state. switch output functions, raster color register control register. When pins used clock input/output pins, corresponding bits port direction register (input mode). switch output structures, bits port direction register, When "0," CMOS output when "1," N-channel open-drain output.
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
Ports P00-P07
N-channel open-drain output
Direction register
Ports P00-P07
Data
Port latch
Note Each port also used follows 0-P05 PWM0-PWM5 INT2/AD4 INT1
Fig. Block Diagram
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
Ports P30,
Direction register
CMOS output Ports P30,
Data
Port latch
Notes Each port also used follows SCLK OUT2 SOUT SCL1 SCL2 TIM3 SDA15 TIM2 SDA2 AD1/INT3 output structure ports selected either CMOS output N-channel opendrain output structure (when selecting N-channel open-drain, same with P00-P07). output structure ports P11-P14 N-channel open-drain output when using multi-master I2C-BUS interface (when selecting N-channel open-drain, same with P00-P07). output structure ports N-channel open-drain output when using serial output (when selecting N-channel open-drain, same with P00-P07).
P50,
P52-P55
CMOS input
Internal circuit
Ports P50,
Internal circuit
CMOS output Ports P52-P55 Note Each also used follows OUT1
Note Each also used follows HSYNC VSYNC
Fig. Block Diagram
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses standard Family instruction set. Refer table Family addressing modes machine instructions SERIES <Software> User's Manual details instruction set. Machine-resident Family instructions follows: FST, instruction cannot used. MUL, DIV, instructions used.
8.1.1 Mode Register
mode register contains stack page selection internal system clock selection bit. mode register allocated address 00FB16.
Mode Register
mode register (CM) [Address 00FB16] Name Processor mode bits (CM0, CM1) Functions
After reset
Single-chip mode available
Stack page selection (CM2) (See note)
page page
these bits "1." XCOUT drivability selection (CM5) Main Clock (XIN-XOUT) stop (CM6) Internal system clock selection (CM7) drive HIGH drive Oscillating Stopped XIN-XOUT selected (high-speed mode) XCIN-XCOUT selected (high-speed mode)
Note: This after reset release.
Fig. 8.1.1 Mode Register
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
MEMORY 8.2.1 Special Function Register (SFR) Area
special function register (SFR) area zero page contains control registers such ports timers.
8.2.6 Interrupt Vector Area
interrupt vector area contains reset interrupt vectors.
8.2.7 Zero Page
bytes from addresses 000016 00FF16 called zero page area. internal special function registers (SFR) allocated this area. zero page addressing mode used specify memory register addresses zero page area. Access this area with only bytes possible zero page addressing mode.
8.2.2
used data storage stack area subroutine calls interrupts.
8.2.3
used storing user programs well interrupt vector area.
8.2.8 Special Page
bytes from addresses FF0016 FFFF16 called special page area. special page addressing mode used specify memory addresses special page area. Access this area with only bytes possible special page addressing mode.
8.2.4
display used specifying character codes colors display.
8.2.5
display used storing character data.
8.2.9 Correction Vector
This used program jump destination addresses correction.
M3727GM6/M8-XXXSP/FP, M37272E8SP/FP
000016 00BF16 00C016 00FF16 010016 01FF16 020016 020F16 030016 032016 053F16 05BF16 used (128 bytes) 080016 087F16 used (10K bytes) 140016 3BFF16 Zero page SFR1 area
M3727GM6XXXSP/FP, M37272E8SP/FP (1152 bytes)
M3727GM8XXXSP/FP (1024 bytes)
SFR2 area used correction function Vector address 030016 Vector address 0320
M3727GM6XXXSP/FP (24K bytes) M3727GM8XXXSP/FP M37272E8SP/FP (32K bytes)
used
800016 A00016 FF0016 FFDE16 FFFF16 Interrupt vector area
Special page
Note: Refer Table 8.11.3 RAM.
Fig. 8.2.1 Memory (M3727GM6/M8-XXXSP/FP, M37272E8SP/FP)
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
SFR1 Area (addresses C016 DF16)
<Bit allocation> <State immediately after reset> immediately after reset Function immediately after reset Indeterminate immediately after reset
Name
function this write "1") this write "0")
Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16
Register
allocation
State immediately after reset 0016 0016 0016 0016 0016 0016 0016 0016 4016 0016 0016 0016 0016
Port (P0) Port direction register (D0) Port (P1) Port direction register (D1) Port (P2) Port direction register (D2) Port (P3) Port direction register (D3)
T3SC P31CP30C P31D P30D
Port (P5) port control register (PF)
0016
Caption data register (CD3) Caption data register (CD4) control register (OC) Horizontal position register (HP) Block control register (BC1) Block control register (BC2) Vertical position register (VP1) Vertical position register (VP2) Window register (WN1) Window register (WN2) polarity control register (PC) Raster color register (RC)
CDL27 CDL26 CDL25 CDL24 CDL23CDL22 CDL21 CDL20
BC17 BC16 BC15 BC14 BC13BC12 BC11 BC10 BC27 BC26 BC25 BC24 BC23BC22 BC21 BC20 VP17 VP16 VP15 VP14 VP13 VP12 VP11 VP10 VP27 VP26 VP25 VP24 VP23 VP22 VP21 VP20
WN17 WN16 WN15 WN14 WN13WN12 WN11 WN10 WN27 WN26 WN25 WN24 WN23WN22 WN21 WN20
Interrupt input polarity control register (RE)
INT3 INT2 INT1
0016 0016 0016
Fig. 8.2.2 Memory Special Function Register (SFR1)
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
SFR1 Area (addresses E016 FF16)
<Bit allocation> <State immediately after reset> immediately after reset Function immediately after reset Indeterminate immediately after reset
Name
function this write "1") this write "0")
Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16
Register
allocation
DSC20
State immediately after reset 0016 0016 0016 0016 0916 0016 0016 0016 0016 0016 0716 FF16 FF16 0716 FF16 0716 0016 0016 0016 0016 0016 3C16 0016 0016 0016 0016
Data slicer control register (DSC1) Data slicer control register (DSC2) Caption data register (CD1) Caption data register (CD2) Clock run-in detect register (CRD) Data clock position register (DPS) Caption position register (CPS) Data slicer test register Data slicer test register
DSC12DSC11DSC10
DSC25 DSC24 DSC23
CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10
CRD7 CRD6 CRD5 CRD4 CRD3 DPS7 DPS6 DPS5 DPS4 DPS3
CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
Synchronous signal counter register (HC) Serial register (SIO) Serial mode register (SM) control register (AD1) control register (AD2) Timer (T5) Timer (T6) Timer (T1) Timer (T2) Timer (T3) Timer (T4) Timer mode register (TM1) Timer mode register (TM2) data shift register (S0) address register (S0D) status register (S1) control register (S1D) clock control register (S2)
ADC14
ADC12 ADC11 ADC10
ADC25 ADC24 ADC23 ADC22ADC21 ADC20
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
BSEL1 BSEL0 10BIT FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE
mode register (CPUM) IN3R VSCR OSDRTM4R TM3R TM2R TM1R Interrupt request register (IREQ1)
Interrupt request register (IREQ2) Interrupt control register (ICON1) Interrupt control register (ICON2)
TM56RIICR IN2R IN1R
IN3E VSCEOSDE TM4E TM3E TM2E TM1E
TM56CTM56E
IICE IN2E IN1E
Fig. 8.2.3 Memory Special Function Register (SFR1)
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SFR2 Area (addresses 20016 20F16)
<Bit allocation> <State immediately after reset> immediately after reset Function immediately after reset Indeterminate immediately after reset
Name
function this write this write
Address 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16
Register
allocation
tate immediately after reset
PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM5 register (PWM5)
0016 0016
mode register (PM1) mode register (PM2) correction address (high-order) correction address (low-order) correction address (high-order) correction address (low-order) correction enable register (RCR)
RCR1 RCR0
PM13 PM10
0016 0016 0016 0016 0016 0016
PM25
Fig. 8.2.4 Memory Special Function Register (SFR2)
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
<Bit allocation>
<State immediately after reset>
Name
Function
immediately after reset immediately after reset Indeterminate immediately after reset
function
this write "1") this write "0") Register
Processor status register (PS) Program counter (PCH) Program counter (PCL)
allocation
State immediately after reset
Contents address FFFF16 Contents address FFFE16
Fig. 8.2.5 Internal State Processor Status Register Program Counter Reset
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
INTERRUPTS
Interrupts caused different sources consisting external, internal, software, reset. Interrupts vectored interrupts with priorities shown Table 8.3.1. Reset also included table because operation similar interrupt. When interrupt accepted, contents program counter processor status register automatically stored into stack. interrupt disable flag corresponding interrupt request "0." jump destination address stored vector address enters program counter. Other interrupts disabled when interrupt disable flag "1." interrupts except instruction interrupt have interrupt request interrupt enable bit. interrupt request bits interrupt request registers interrupt enable bits interrupt control registers Figures 8.3.2 8.3.6 show interrupt-related registers. Interrupts other than instruction interrupt reset accepted when interrupt enable "1," interrupt request "1," interrupt disable flag "0." interrupt request program, "1." interrupt enable program. Reset treated non-maskable interrupt with highest priority. Figure 8.3.1 shows interrupt control.
8.3.1 Interrupt Causes VSYNC, interrupts
VSYNC interrupt interrupt request synchronized with vertical sync signal. interrupt occurs after character block display completed.
INT1 INT3 external interrupts
INT1 INT3 interrupts external interrupt inputs, system detects that level changes from HIGH from HIGH LOW, generates interrupt request. input active edge selected bits interrupt input polarity register (address 00DC16) when this "0," change from HIGH detected; when "1," change from HIGH detected. Note that both bits cleared reset.
Timers interrupts
interrupt generated overflow timers
Table 8.3.1 Interrupt Vector Addresses Priority Priority Interrupt Source Reset interrupt INT1 external interrupt Data slicer interrupt Serial interrupt Timer interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer interrupt Timer interrupt Timer interrupt INT3 external interrupt INT2 external interrupt Multi-master I2C-BUS interface interrupt Timer interrupt instruction interrupt Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFE316, FFE216 FFDF16, FFDE16 Remarks Non-maskable Active edge selectable
Active edge selectable Active edge selectable Source switch software (see note) Non-maskable
Note: Switching source during program causes unnecessary interrupt. Therefore, source initializing program.
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
Serial interrupt
This interrupt request from clock synchronous serial function.
f(XIN)/4096 interrupt
(XIN)/4096 interrupt occurs regularly with f(XIN)/4096 period. mode register "0."
Interrupt request Interrupt enable
Data slicer interrupt
interrupt occurs when slicing data completed.
Interrupt disable flag
Multi-master
I2C-BUS
interface interrupt
instruction Reset
Interrupt request
This interrupt request related multi-master I2C-BUS interface.
Timer interrupt
interrupt generated overflow timer Their priorities same, switched software. Fig. 8.3.1 Interrupt Control
instruction interrupt
This software interrupt least significant priority. does have corresponding interrupt enable bit, affected interrupt disable flag (non-maskable).
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M3727GM6/M8-XXXSP/FP M37272E8SP/FP
Interrupt Request Register
Interrupt request register (IREQ1) [Address 00FC16] Name Functions
After reset
interrupt request issued Timer interrupt request (TM1R) Interrupt request issued Timer interrupt interrupt request issued request (TM2R) Interrupt request issued interrupt request issued Timer interrupt request (TM3R) Interrupt request issued interrupt request issued Timer interrupt request (TM4R) Interrupt request issued interrupt request interrupt request issued Interrupt request issued (OSDR) VSYNC interrupt interrupt request issued request (VSCR) Interrupt request issued INT3 external interrupt interrupt request issued request (VSCR) Interrupt request issued Nothing assigned. This write disable bit. When this read out, value "0."
software, cannot set.
Fig. 8.3.2 Interrupt Request Register
Interrupt Request Register
Interrupt request register (IREQ2) [Address 00FD16] Name INT1 external interrupt request (INIR) Data slicer interrupt request (DSR) Functions interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued
After reset
Serial interrupt request (S1R) f(XIN)/4096 interrupt request (CKR) INT2 external interrupt request (IN2R) Multi-master I2C-BUS interrupt request (IICR) Timer interrupt request (TM56R) this "0."
software, cannot set.
Fig. 8.3.3 Interrupt Request Register
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Interrupt Control Register
Interrupt control register (ICON1) [Address 00FE16] Name Timer interrupt enable (TM1E) Timer interrupt enable (TM2E) Timer interrupt enable (TM3E) Timer interrupt enable (TM4E) interrupt enable (OSDE) VSYNC interrupt enable (VSCE) INT3 external interrupt enable (IN3E) Functions Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled
After reset
Nothing assigned. This write disable bit. When this read out, value "0."
Fig. 8.3.4 Interrupt Control Register
Interrupt Control Register
Interrupt control register (ICON2) [Address 00FF16] Name INT1 external interrupt enable (IN1E) Data slicer interrupt enable (DSE) Serial interrupt enable (S1E) f(XIN)/4096 interrupt enable (CKE) INT2 external interrupt enable (IN2E) Functions Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Timer Timer
After reset
Multi-master I2C-BUS interface interrupt enable (IICE) Timer interrupt enable (TM56E) Timer interrupt switch (TM56C)
Fig. 8.3.5 Interrupt Control Register
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Interrupt Input Polarity Register
Interrupt input polarity register (RE) [Address 00DC
Name INT1 polarity switch (INT1) INT2 polarity switch (INT2) INT3 polarity switch (INT3)
Functions Positive polarity Negative polarity Positive polarity Negative polarity Positive polarity Negative polarity
After reset
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.3.6 Interrupt Input Polarity Register
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TIMERS
This microcomputer timers: timer timer timer timer timer timer timers 8-bit timers with 8-bit timer latch. timer block diagram shown Figure 8.4.3. timers count down their divide ratio 1/(n+1), where value timer latch. writing count value corresponding timer latch (addresses 00F016 00F316 timers addresses 00EE16 00EF16 timers value also timer, simultaneously. count value decremented timer interrupt request timer overflow next count pulse, after count value reaches "0016".
8.4.5 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 Timer overflow signal Timer overflow signal count source timer selected setting timer mode register (address 00F416) timer mode register (address 00F516). When overflow timer count source timer either timer functions 8-bit prescaler. Either f(XIN) f(XCIN) selected mode register. Timer interrupt request occurs timer overflow.
8.4.6 Timer 8.4.1 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 f(XIN)/4096 f(XCIN)/4096 External clock from TIM2 count source timer selected setting bits timer mode register (address 00F416). Either f(XIN) f(XCIN) selected mode register. Timer interrupt request occurs timer overflow. Timer select following count sources: f(XIN)/16 f(XCIN)/16 Timer overflow signal count source timer selected setting timer mode register (address 00F416). Either f(XIN) f(XCIN) selected mode register. When timer overflow signal count source timer timer functions 8-bit prescaler. Timer interrupt request occurs timer overflow. reset, timers connected hardware "FF16" automatically timer "0716" timer f(XIN) selected timer count source. internal reset released timer overflow this state internal clock connected. execution instruction, timers connected hardware "FF16" automatically timer "0716" timer However, f(XIN) selected timer count source. both timer mode register (address 00F516) address 00C716 before execution instruction (f(XIN) selected timer count source). internal state released timer overflow this state internal clock connected. result above procedure, program start under stable clock. When mode register (CM7) "1," f(XIN) becomes f(XCIN). timer-related registers shown Figures 8.4.1 8.4.2.
8.4.2 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 Timer overflow signal External clock from TIM2 count source timer selected setting bits timer mode register (address 00F416). Either f(XIN) f(XCIN) selected mode register. When timer overflow signal count source timer timer functions 8bit prescaler. Timer interrupt request occurs timer overflow.
8.4.3 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 f(XCIN) External clock from TIM3 count source timer selected setting timer mode register (address 00F516) address 00C716. Either f(XIN) f(XCIN) selected mode register. Timer interrupt request occurs timer overflow.
8.4.4 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 f(XIN)/2 f(XCIN)/2 f(XCIN) count source timer selected setting bits timer mode register (address 00F516). Either f(XIN) f(XCIN) selected mode register. When timer overflow signal count source timer timer functions 8bit prescaler. Timer interrupt request occurs timer overflow.
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Timer Mode Register
Timer mode register (TM1) [Address 00F4 Name Timer count source selection (TM10) Timer count source selection (TM11) Timer count stop (TM12) Timer count stop (TM13) Timer count source selection (TM14) Timer count source selection (TM15) Timer count source selection (TM16) Timer internal count source selection (TM17)
After reset Functions f(XIN)/16 CIN)/16 (See note) Count source selected
Count source selected External clock from TIM2 Count start Count stop Count start Count stop f(XIN)/16 CIN)/16 (See note) Timer overflow f(XIN)/4096 CIN)/4096 (See note) External clock from TIM2 Timer overflow Timer overflow f(XIN)/16 CIN)/16 (See note) Timer overflow
Note: Either CIN) selected mode register.
Fig. 8.4.1 Timer Mode Register
Timer Mode Register
Timer mode register (TM2) [Address 00F5 Name Timer count source selection (TM20) Functions address 00C7 Timer count source selection bits (TM21, TM24) IN)/16 CIN)/16 (See note) CIN) External clock from TIM3 Timer overflow signal IN)/16 CIN)/16 (See note) IN)/2 CIN)/2 (See note) CIN)
After reset
Timer count stop (TM22) Timer count stop (TM23) Timer count stop (TM25) Timer count stop (TM26) Timer count source selection (TM27)
Count start Count stop Count start Count stop Count start Count stop Count start Count stop f(XIN)/16 CIN)/16 (See note) Count source selected
Note: Either CIN) selected mode register.
Fig. 8.4.2 Timer Mode Register
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Data
TM15 1/4096 Timer latch
TM10 TM12 TM14
Timer
Timer interrupt request
Timer latch
TIM2 TM11 TM13
Timer
Timer interrupt request
FF16 T3SC Timer latch
Reset instruction
TIM3 TM20 TM22
Timer
Timer interrupt request
TM21
Timer latch
Timer TM21 TM24 TM23 TM16 Selection gate: Connected black side reset Timer mode register Timer mode register T3SC Timer count source switch (address 00C7 mode register TM27 TM25
Timer interrupt request
Timer latch
Timer
Timer interrupt request
Timer latch
Timer TM17 TM26
Timer interrupt request
Notes HIGH pulse width external clock inputs TIM2 TIM3 needs machine cycles more. When external clock source selected, timers counted rising edge input signal. stop mode wait mode, external clock inputs TIM2 TIM3 cannot used.
Fig. 8.4.3 Timer Block Diagram
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SERIAL
This microcomputer built-in serial which either transmit receive 8-bit data serially clock synchronous mode. serial block diagram shown Figure 8.5.1. synchronous clock (SCLK), data output (SOUT) also function port data input (SIN) also functions port P20-P22. serial mode register (address 00EB16) selects whether synchronous clock supplied internally externally (from SCLK pin). When internal clock selected, bits select whether f(XIN) f(XCIN) divided serial I/O, corresponding port direction register (address 00C516) "0."
operation serial described below. operation serial differs depending clock source; external clock internal clock.
XCIN
Synchronous circuit
Data Frequency divider
1/16
Selection gate: Connect black side reset.
Latch SCLK Latch SOUT (See note) Serial shift register Serial counter
mode register Serial mode register Serial interrupt request
Note When data serial register (address 00EA 16), register functions serial shift register.
Fig. 8.5.1 Serial Block Diagram
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Internal clock serial counter during write cycle into serial register (address 00EA16), transfer clock goes HIGH forcibly. each falling edge transfer clock after write cycle, serial data output from SOUT pin. Transfer direction selected serial mode register. each rising edge transfer clock, data input from data serial register shifted bit. After transfer clock counted times, serial counter becomes transfer clock stops HIGH. this time interrupt request "1."
External clock external clock selected clock source, interrupt request after transfer clock been counted counts. However, transfer operation does stop, clock should controlled externally. external clock less with duty cycle 50%. serial timing shown Figure 8.5.2. When using external clock transfer, external clock must held HIGH initializing serial counter. When switching between internal clock external clock, switch during transfer. Also, sure initialize serial counter after switching.
Notes programming, note that serial counter writing serial register with managing instructions, such CLB. When external clock used synchronous clock, write transmit data serial register when transfer clock input level HIGH.
Synchronous clock
Transfer clock Serial register write signal (Note) Serial output SOUT Serial input
Interrupt request Note When internal clock selected, SOUT high-impedance after transfer completed.
Fig. 8.5.2 Serial Timing (for first)
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Serial Mode Register
Serial mode register (SM) [Address 00EB16] Name Internal synchronous clock selection bits (SM0, SM1) After reset Functions f(XIN)/4 f(XCIN)/4 f(XIN)/16 f(XCIN)/16 f(XIN)/32 f(XCIN)/32 f(XIN)/64 f(XCIN)/64
Synchronous clock selection (SM2) Port function selection (SM3)
External clock Internal clock P20, SCLK, SOUT
this "0." Transfer direction selection (SM5) first first
Transfer clock input Input signal from selection (SM6) Input signal from SOUT this "0."
Fig. 8.5.3 Serial Mode Register
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MULTI-MASTER I2C-BUS INTERFACE
multi-master I2C-BUS interface serial communications circuit, conforming Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection synchronous functions, useful multi-master serial communications. Figure 8.6.1 shows block diagram multi-master I2C-BUS interface Table 8.6.1 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists address register, data shift register, clock control register, control register, status register other control circuits.
Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Function conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 MHz)
Format
Communication mode
clock frequency
System clock f(XIN)/2
Note responsible third party's infringement patent rights other rights attributable control function (bits control register address 00F916) connections between I2C-BUS interface ports (SCL1, SCL2, SDA1, SDA2).
address register (S0D)
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
Address comparator Serial data
(SDA)
Noise elimination circuit
Data control circuit
data shift register
circuit
Internal data
status register (S1)
circuit
Serial clock
(SCL)
Noise elimination circuit
Clock control circuit
BSEL1 BSEL0 10BIT
FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE
clock control register (S2) Clock division
control register (S1D) counter
System clock
Fig. 8.6.1 Block Diagram Multi-master I2C-BUS Interface
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8.6.1 Data Shift Register
data shift register address 00F616) 8-bit shift register store receive data write transmit data. When transmit data written into this register, transferred outside from synchronization with clock, each time one-bit data output, data this register shifted left. When data received, input this register from synchronization with clock, each time one-bit data input, data this register shifted left. data shift register write enable status only when control register (address 00F916) "1." counter reset write instruction data shift register. When both status register (address 00F816) "1," output write instruction data shift register. Reading data from data shift register always enabled regardless value.
Note: write data into data shift register after setting (slave mode), keep interval machine cycles more.
Data Shift Register
data shift register1(S0) [Address 00F616]
Name
Functions This 8-bit shift register store receive data write transmit data.
After reset
Indeterminate
Note: write data into data shift register after setting (slave mode), keep interval machine cycles more.
Fig. 8.6.2 Data Shift Register
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8.6.2 Address Register
address register (address 00F716) consists 7-bit slave address read/write bit. addressing mode, slave address written this register compared with address data received immediately after START condition detected.
read/write (RBW)
used when comparing addresses, 7-bit addressing mode. 10-bit addressing mode, first address data received compared with contents (SAD6 SAD0 RBW) address register. cleared automatically when stop condition detected.
Bits slave address (SAD0-SAD6)
These bits store slave addresses. Regardless 7-bit addressing mode 10-bit addressing mode, address data transmitted from master compared with contents these bits.
Address Register
address register (S0D) [Address 00F716]
Name
Read/write (RBW)
Functions
<Only 10-bit addressing slave) mode> last significant address data compared. Wait first byte slave address after START condition (read state) Wait first byte slave address after RESTART condition (write state)
After reset
Slave address both modes> (SAD0 SAD6) address data compared.
Fig. 8.6.3 Address Register
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8.6.3 Clock Control Register
clock control register (address 00FA16) used control, mode frequency.
clock (ACK)
This specifies mode acknowledgment which acknowledgment response data transmission. When this "0," clock mode set. this case, clock occurs after data transmission. When "1," clock mode master generates clock upon completion each 1-byte data transmission.The device transmitting address data control data releases occurrence clock (make HIGH) receives generated data receiving device.
Note: write data into clock control register during transmission. data written during transmission, clock generator reset, that data cannot transmitted normally.
Bits frequency control bits (CCR0-CCR4)
These bits control frequency.
mode specification (FAST MODE)
This specifies mode. When this "0," standard clock mode set. When "1," high-speed clock mode set.
(ACK BIT)
This sets status when clock generated. When this "0," return mode goes occurrence clock. When "1," non-return mode set. held HIGH status occurrence clock. However, when slave address matches address data reception address data "0," automatically made (ACK returned). there mismatch between slave address address data, automatically made HIGH (ACK returned). clock: Clock acknowledgement
Clock Control Register
clock control register address 00FA
Name
Functions
After reset
frequency control Setup value Standard clock High speed CCR4- mode clock mode bits CCR0 (CCR0 CCR4) Setup disabled Setup disabled
Setup disabled Setup disabled
(See note)
83.3 17.2 16.6 16.1
34.5 33.3 32.3
500/CCR value 1000/CCR value
mode specification (FAST MODE) (ACK BIT) clock (ACK)
MHz, unit kHz) Standard clock mode High-speed clock mode returned. returned. clock clock
Note: 4000kHz high-speed clock mode, duty below period period other cases, duty below. period period
Fig. 8.6.4 Address Register
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8.6.4 Control Register
control register (address 00F916) controls data communication format.
data format selection (ALS)
This decides whether recognize slave addresses. When this "0," addressing format selected, that address data recognized. When match found between slave address address data result comparison when general call (refer "8.6.5 Status Register," received, transmission processing performed. When this "1," free data format selected, that slave addresses recognized.
Bits counter (BC0-BC2)
These bits decide number bits next 1-byte data transmitted. interrupt request signal occurs immediately after number bits specified with these bits transmitted. When START condition received, these bits become "0002" address data always transmitted received bits.
interface enable (ESO)
This enables usage multimaster interface. When this "0," disable status provided, become high-impedance. When "1," interface enabled. When "0," following performed. "1," (they bits status register address 00F816 Writing data data shift register (address 00F616) disabled.
addressing format selection (10BIT SAD)
This selects slave address specification format. When this "0," 7-bit addressing format selected. this case, only high-order bits (slave address) address register (address 00F716) compared with address data. When this "1," 10-bit addressing format selected, bits address register compared with address data.
Bits connection control bits between C-BUS interface ports (BSEL0, BSEL1)
These bits controls connection between ports ports (refer Figure 8.6.5).
BSEL0 SCL/P11 Multi-master I2C-BUS interface BSEL1 SCL2/P12 BSEL0 SDA1/P13 BSEL1 SDA2/P14
Note: corresponding direction register port multi-master I2C-BUS interface.
Fig. 8.6.5 Connection Port Control BSEL0 BSEL1
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Control Register
control register (S1D address 00F916)
Name
counter (Number transmit/recieve bits) (BC0 BC2)
Functions
After reset
I2C-BUS interface enable (ESO) Data format selection bit(ALS) Addressing format selection (10BIT SAD)
Disabled Enabled Addressing mode Free data format 7-bit addressing format 10-bit addressing format Connection port (See note) None SCL1, SDA1 SCL2, SDA2 SCL1, SDA1 SCL2, SDA2
Connection control bits between I2C-BUS interface ports
Note: When using ports P11-P14 I2C-BUS interface, output structure changes automatically from CMOS output N-channel open-drain output.
Fig. 8.6.6 Control Register
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8.6.5 Status Register
status register (address 00F816) controls I2C-BUS interface status. low-order bits read-only bits highorder bits read written
I2C-BUS interface interrupt request (PIN)
This generates interrupt request signal. Each time 1-byte data transmitted, state changes from "0." same time, interrupt request signal sent CPU. synchronization with falling edge last clock (including clock) internal clock interrupt request signal occurs synchronization with falling edge bit. When detecting STOP condition slave, multi-master I2C-BUS interface interrupt request (IR) (interrupt request) regardless falling bit. When "0," kept state clock generation disabled. Figure 8.6.8 shows interrupt request signal generating timing chart. following conditions. Writing Executing write instruction data shift register (address 00F616). (See note) When reset
Note: takes BCLK cycles more until become after write instructions executed these registers.
last receive (LRB)
This stores last value received data also used receive confirmation. returned when clock occurs, "0." returned, this "1." Except mode, last value received data input. state this changed from executing write instruction data shift register (address 00F616).
general call detecting flag (AD0)
This when general call whose address data received slave mode. general call master device, every slave device receives control data after general call. detecting STOP condition START condition. General call: master transmits general call address "0016" slaves.
slave address comparison flag (AAS)
This flag indicates comparison result address data. slave receive mode, when 7-bit addressing format selected, this following conditions. address data immediately after occurrence START condition matches slave address stored high-order bits address register (address 00F716). general call received. slave reception mode, when 10-bit addressing format selected, this with following condition. When address data compared with address register bits consists slave address RBW), first bytes match. state this changed from executing write instruction data shift register (address 00F616).
conditions which shown below: Immediately after completion 1-byte data transmission (including when arbitration lost detected) Immediately after completion 1-byte data reception slave reception mode, with immediately after completion slave address general call address reception slave reception mode, with immediately after completion address data reception
busy flag (BB)
This indicates status system. When this "0," this system busy START condition generated. When this "1," this system busy occurrence START condition disabled START condition duplication prevention function (See note). This flag written software only master transmission mode. other modes, this detecting START condition detecting STOP condition. When control register (address 00F916) reset, flag kept state.
arbitration lost detecting flag (AL)
master transmission mode, when device other than microcomputer sets "L,", arbitration judged have been lost, that this "1." same time, "0," that immediately after transmission byte whose arbitration lost completed, "0." When arbitration lost during slave address transmission, reception mode set. Consequently, becomes possible receive recognize slave address transmitted another master device. Arbitration lost: status which communication master disabled.
communication mode specification (transfer direction specification bit: TRX)
This decides direction transfer data communication. When this "0," reception mode selected data transmitting device received. When "1," transmission mode selected address data control data output into synchronization with clock generated SCL. When control register (address 00F916) slave reception mode selected, (trans_ mit) least significant (R/W bit) address data transmit_ master "1." When "0," cleared (receive). cleared following conditions. When arbitration lost detected. When STOP condition detected. When occurence START condition disabled START condition duplication prevention function (Note). With when START condition detected. With when non-return detected. reset
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Communication mode specification (master/slave specification bit: MST)
This used master/slave specification data communication. When this "0," slave specified, that START condition STOP condition generated master received, data communication performed synchronization with clock generated master. When this "1," master specified START condition STOP condition generated, also clocks required data communication generated SCL. cleared following conditions. Immediately after completion 1-byte data transmission when arbitration lost detected When STOP condition detected. When occurence START condition disabled START condition duplication preventing function (Note). reset
Note: START condition duplication prevention function disables START condition generation, reset counter reset, output, when following condition satisfied: START condition another master device.
Status Register
status register (S1) [Address 00F816]
Name
Last receive (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request (PIN) busy flag (BB)
Functions
Last Last (See note)
After reset
Indeterminate
general call detected General call detected (See note) Address mismatch Address match detected Detected (See note)
(See note) Interrupt request issued interrupt request issued
free busy Slave recieve mode Slave transmit mode Master recieve mode Master transmit mode
Communication mode specification bits (TRX, MST)
Note These bits flags read out, cannnot written.
Fig. 8.6.7 Status Register
IICIRQ
Fig. 8.6.8 Interrupt Request Signal Generation Timing
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8.6.6 START Condition Generation Method
When control register (address 00F916) "1," execute write instruction status register (address 00F816) MST, bits "1." START condition will then generated. After that, counter becomes "0002" byte output. START condition generation timing timing different standard clock mode highspeed clock mode. Refer Figure 8.6.9 START condition generation timing diagram, Table 8.6.2 START condition/ STOP condition generation timing table.
status register write signal flag Setup time Hold time
time flag
Fig. 8.6.9 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
When control register (address 00F916) "1," execute write instruction status register (address 00F816) setting "0". STOP condition will then generated. STOP condition generation timing flag reset timing different standard clock mode high-speed clock mode. Refer Figure 8.6.10 STOP condition generation timing diagram, Table 8.6.2 START condition/STOP condition generation timing table.
status register write signal flag Setup time Hold time
Reset time flag
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Timing Table Item Standard Clock Mode Setup time cycles) (START condition) Setup time 4.25 cycles) (STOP condition) cycles) Hold time Set/reset time cycles) flag High-speed Clock Mode cycles) 1.75 cycles) cycles) cycles)
Note: Absolute time MHz. value parentheses denotes number cycles.
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8.6.8 START/STOP Condition Detect Conditions
START/STOP condition detect conditions shown Figure 8.6.11 Table 8.6.3. Only when conditions Table 8.6.3 satisfied, START/STOP condition detected.
Note: When STOP condition detected slave mode (MST interrupt request signal "IICIRQ" generated CPU.
8.6.9 Address Data Communication
There address data communication formats, namely, 7-bit addressing format 10-bit addressing format. respective address communication formats described below.
7-bit addressing format
meet 7-bit addressing format, 10BIT control register (address 00F916) "0." first 7-bit address data transmitted from master compared with high-order 7-bit slave address stored address register (address 00F716). time this comparison, address comparison address register (address 00F716) made. data transmission format when 7-bit addressing format selected, refer Figure 8.6.12, (2).
release time (START condition) (STOP condition) Setup time Setup time Hold time
10-bit addressing format
Hold time meet 10-bit addressing format, 10BIT control register (address 00F916) "1." address comparison made between first-byte address data transmitted from master 7-bit slave address stored address register (address 00F716). time this comparison, address comparison between address register (address 00F716) which last address data transmitted from master made. 10-bit addressing mode, which last address data only specifies direction communication control data also processed address data bit. When first-byte address data matches slave address, status register (address 00F816) "1." After second-byte address data stored into data shift register (address 00F616), make address comparison between second-byte data slave address software. When address data bytes matches slave address, address register (address 00F716) software. This processing match 7-bit slave address data, which received after RESTART condition detected, with value address register (address 00F716). data transmission format when 10-bit addressing format selected, refer Figure 8.6.12, (4).
Fig. 8.6.11 START Condition/STOP Condition Detect Timing Diagram
Table 8.6.3 START Condition/STOP Condition Detect Conditions Standard Clock Mode cycles) release time 3.25 cycles) Setup time 3.25 cycles) Hold time High-speed Clock Mode cycles) release time cycles) Setup time cycles) Hold time
Note: Absolute time MHz. value parentheses denotes number cycles.
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8.6.10 Example Master Transmission
example master transmission standard clock mode, frequency return mode shown below. slave address high-order bits address register (address 00F716) bit. return mode setting "8516" clock control register (address 00FA16). "1016" status register (address 00F816) hold HIGH. communication enable status setting "4816" control register (address 00F916). address data destination transmission highorder bits data shift register (address 00F616) least significant bit. "F016" status register (address 00F816) generate START condition. this time, byte clock automatically occurs. transmit data data shift register (address 00F616). this time, clock automatically occurs. When transmitting control data more than byte, repeat step "D016" status register (address 00F816). After this, returned transmission ends, STOP condition will generated.
8.6.11 Example Slave Reception
example slave reception high-speed clock mode, frequency kHz, non-return mode, using addressing format, shown below. slave address high-order bits address register (address 00F716) bit. clock mode setting "2516" clock control register (address 00FA16). "1016" status register (address 00F816) hold HIGH. communication enable status setting "4816" control register (address 00F916). When START condition received, address comparison made. transmitted address are"0" (general call): status register (address 00F816) "1"and interrupt request signal occurs. transmitted addresses match address status register (address 00F816) interrupt request signal occurs. cases other than above: status register (address 00F816) interrupt request signal occurs. dummy data data shift register (address 00F616). When receiving control data more than byte, repeat step When STOP condition detected, communication ends.
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Slave address
Data
Data
bits bits bits master-transmitter transmits data slave-receiver
Slave address
Data
Data
bits bits bits master-receiver receives data from slave-transmitter Slave address bits Slave address byte
Data
Data
bits bits bits bits master-transmitter transmits data slave-receiver with 10-bit address Slave address bits Slave address byte Slave address bits
Data
Data bits
bits bits bits bits master-receiver receives data from slave-transmitter with 10-bit address START condition Restart condition STOP condition Read/Write From master slave From slave master
Fig. 8.6.12 Address Data Communication Format
8.6.12 Precautions when using multi-master I2C-BUS interface Read-modify-write instruction
precautions when raead-modify-write instruction such SEB, etc. executed each register multi-master I2C-BUS interface described below. data shift register (S0) When executing read-modify-write instruction this register during transfer, data become value intended. address register (S0D) When read-modify-write instruction executed this register detecting STOP condition, data become value intended. because hardware changes read/write (RBW) above timing. status register (S1) execute read-modify-write instruction this register because bits this register changed hardware. control register (S1D) When read-modify-write instruction executed this register detecting START condition completing byte transfer, data become value intended. Because hardware changes counter (BC0-BC2) above timing. clock control register (S2) read-modify-write instruction executed this register.
START condition generating procedure using multi-master
Procedure example (The necessary conditions generating procedure described following
5,S1,BUSBUSY BUSFREE: #$F0, BUSBUSY:
(Taking slave address value) (Interrupt disabled) flag confirming branch process) (Writing slave address value) (Trigger START condition generating) (Interrupt enabled)
(Interrupt enabled)
"STA," "STX" "STY" zero page addressing instruction writing slave address value data shift register. "LDM" instruction setting trigger START condition generating. Write slave address value above trigger START condition generating above continuously shown above procedure example. Disable interrupts during following three process steps: flag confirming Writing slave address value Trigger START condition generating When condition flag busy, enable interrupts immediately.
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RESTART condition generating procedure
Procedure example (The necessary conditions generating procedure described following Execute following procedure when "0." #$00, #$F0, Select slave receive mode when "0." write bit. Neither specified writing bit. becomes released. released writing slave address value data shift register. "STA," "STX" "STY" zero page addressing instruction writing. "LDM" instruction setting trigger RESTART condition generating. Write slave address value above trigger RESTART condition generating above continuously shown above procedure example. Disable interrupts during following process steps: Writing slave address value Trigger RESTART condition generating
STOP condition generating procedure
Procedure example (The necessary conditions generating procedure described following
(Select slave receive mode) (Taking slave address value) (Interrupt disabled) (Writing slave address value) (Trigger RESTART condition generating) (Interrupt enabled)
#$C0, #$D0,
(Interrupt disabled) (Select master transmit mode) (Set NOP) (Trigger STOP condition generating) (Interrupt enabled)
Write when master transmit mode select. Execute "NOP" instruction after setting master transmit mode. Also, trigger STOP condition generating within cycles after selecting master trasmit mode. Disable interrupts during following process steps: Select master transmit mode Trigger STOP condition generating
Writing status register
execute instruction from instruction bits from simultaneously. because enter state that released released after about machine cycle. execute instruction bits from simultaneously when "1." because become same above.
Process after STOP condition generating
write data data shift register status register until busy flag becomes after generating STOP condition master mode. because STOP condition waveform might normally generated. Reading above registers have problem.
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OUTPUT FUNCTION
This microcomputer equipped with 8-bit PWMs (PWM0- PWM5). PWM0-PWM5 have same circuit structure 8-bit resolution with minimum resolution width (for f(XIN) MHz) repeat period 1024 (for f(XIN) MHz). Figure 8.7.1 shows block diagram. timing generating circuit applies individual control signals PWM0-PWM5 using f(XIN) divided reference signal.
8.7.1 Data Setting
When outputting PWM0-PWM5, 8-bit output data PWMi register means addresses 020016 020516).
8.7.2 Transmitting Data from Register circuit
Data transfer from 8-bit register 8-bit circuit executed writing data register. signal output from 8-bit output corresponds contents this register.
8.7.3 Operating 8-bit
following explains operation. First, mode register (address 020816) reset, already automatically), that count source supplied. PWM0-PWM5 also used pins P00-P05. corresponding bits port direction register (output mode). select each output polarity mode register (address 020816). Then, bits mode register (address 020916) (PWM output). waveform output from output pins setting these registers. Figure shows 8-bit timing. cycle composed (28) segments. kinds pulses relative weight each (bits output inside circuit during cycle. Refer Figure (a). 8-bit outputs waveform which logical (OR) pulses corresponding contents bits 8-bit register. Several examples shown Figure (b). kinds output (HIGH area: 0/256 255/256) selected changing contents register. length entirely HIGH cannot output, i.e. 256/256.
8.7.4 Output after Reset
reset, output ports P00-P05 high-impedance state, contents register circuit undefined. Note that after reset, output undefined until setting register.
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Data PM10 PWM0 register (Address 0200
timing generating circuit
PM13 8-bit circuit
PM20 PM21 PM22 PM23 PM24 PM25
PWM0
PWM1
PWM1 register (Address 0201
PWM2
PWM2 register (Address 0202
PWM3
PWM3 register (Address 0203
PWM4
PWM4 register (Address 0204
PWM5
PWM5 register (Address 0205
Selection gate: Connected black side reset. Inside same contents with others.
mode register (address 0208 mode register (address 0209 Port register (address 00C0 Port direction register (address 00C1
Fig. 8.7.1 Block Diagram
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Fig. 8.7.2 Timing
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Pulses showing weight each output 1024 f(XIN) Example 8-bit
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0016
0116
1816 (24)
FF16 (255)
M3727GM6/M8-XXXSP/FP M37272E8SP/FP
Mode Register
mode register (PM1) [Address 020816] Name counts source selection (PM10) Functions Count source supply Count source stop After reset
Nothing assigned. These bits write disable bits. Indeterminate When these bits read out, values "0." output polarity selection (PM13) Positive polarity Negative polarity
Nothing assigned. These bits write disable bits. Indeterminate When these bits read out, values "0."
Fig. 8.7.3 Mode Register
Mode Register
mode register (PM2) [Address 0209 Name P00/PWM0 output selection (PM20) P01/PWM1 output selection (PM21) P02/PWM2 output selection (PM22) P03/PWM3 output selection (PM23) P04/PWM4 output selection (PM24) P05/PWM5 output selection (PW25) Functions output PWM0 output output PWM1 output output PWM2 output output PWM3 output output PWM4 output output PWM5 output After reset
these bits "0."
Fig. 8.7.4 Mode Register
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COMPARATOR
comparator consists 6-bit converter comparator. comparator block diagram shown Figure 8.8.1. reference voltage "Vref" conversion bits control register (address 00ED16). comparison result analog input voltage reference voltage "Vref" stored control register (address 00EC16). comparison, corresponding bits direction register ports analog input pins. Write data select analog input pins bits control register write digital value corresponding Vref compared bits control register voltage comparison starts writing control register completed after machine cycles (NOP instruction
Data
control register
Bits
Comparator control
control register Analog signal switch Comparator
control register
Switch tree
Resistor ladder
Fig. 8.8.1 Comparator Block Diagram
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Control Register
control register (AD1) [Address 00EC16]
Name
Analog input selection bits (ADC10 ADC12)
Functions
set.
After reset
This write disable bit. When this read out, value "0." Storage comparison result (ADC14) Input voltage reference voltage Input voltage reference voltage
Indeterminate
Nothing assigned. This bits write disable bits. When these bits read out, values "0."
Fig. 8.8.2 Control Register
Control Register
control register (AD2) [Address 00ED
Name converter bits (ADC20 ADC25)
Functions 1/128Vcc 3/128Vcc 5/128Vcc
After reset
123/128Vcc 125/128Vcc 127/128Vcc
Nothing assigned. These bits write disable bits. When these bits reed out, values
Fig. 8.8.3 Control Register
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CORRECTION FUNCTION
This correct program data ROM. addresses corrected, program correction stored correction vector address. correction vectors vectors. Vector address 030016 Vector address 032016 address data corrected into correction address register. When value counter matches data address correction vector address, main program branches correction program stored memory correction. return from correction program main program, code operand instruction (total bytes) necessary correction program. correction function controlled correction enable register.
Notes instruction correction address. instruction (total bytes) return from correction program main program. same correction address vectors
correction address (high-order) correction address (low-order) correction address (high-order) correction address (low-order)
020A 020B 020C 020D
Fig. 8.9.1 Correction Address Registers
Correction Enable Register
correction enable register (RCR) [Address 020E
Name
Vector enable (RC0) Vector enable (RC1)
Functions
Disabled Enabled Disabled Enabled
After reset
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.9.2 Correction Enable Register
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8.10 DATA SLICER
This microcomputer includes data slicer function closed caption decoder (referred CCD). This function takes caption data superimposed vertical blanking interval composite video signal. composite video signal which makes sync chip's polarity negative input CVIN pin.
When data slicer function used, data slicer circuit timing signal generating circuit setting data slicer control register (address 00E016) "0." These settings realize low-power dissipation.
Composite video signal
Sync pulse counter register (address 00E9
HSYNC
Synchronizing signal counter Clamping circuit Low-pass filter Sync slice circuit
Synchronizing separation circuit
Data slicer control register (address 00E1
Data slicer control register (address 00E0 Timing signal generating circuit
Data slicer ON/OFF
Reference voltage generating 1000 circuit
VHOLD
Comparator
Clock run-in determination circuit
Data slice line specification circuit
Clock run-in defect register (address 00E4
Start detecting circuit
External circuit Note Make length wiring which connected HOLD HLF, short possible that leakage current generated when mounting resistor capacitor each pin.
Caption position register (address 00E6
Data clock generating circuit Data clock position register (address 00E5 16-bit shift register Interrupt request generating circuit
high-order low-order Caption data register (address 00E216)
Data slicer interrupt request
Caption data register (address 00E316)
Caption data register (address 00CF16)
Caption data register (address 00CE16)
Data
Fig. 8.10.1 Data Slicer Block Diagram
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8.10.1 Notes When Using Data Slicer
When data slicer control register (address 00E016) "0," terminate pins shown Figure 8.10.2.
<When data slicer circuit timing signal generating circuit state>
(Apply
same voltage AVCC pin.)
(AVCC)
Leave open.
Open Open
VHOLD CVIN
Leave HOLD open. Pull-down through resistor more.
more
M37272E8SP/FP
Fig. 8.10.2 Termination Data Slicer Input/Output Pins when Data Slicer Circuit Timing Generating Circuit State When both bits data slicer control register (address 00E016) "1," terminate pins shown Figure 8.10.3.
<When using reference clock generated timing signal generating circuit clock>
(Apply
same voltage AVCC pin.)
(AVCC)
Connect same external circuit when using data slicer pin. Leave HOLD open. Pull-up through resistor more.
200pF
Open
VHOLD
more
M37272E8SP/FP
CVIN
Fig. 8.10.3 Termination Data Slicer Input/Output Pins when Timing Signal Generating Circuit State
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Figures 8.10.4 8.10.5 data slicer control registers.
Data Slicer Control Register
Data slicer control register 1(DSC1) [Address 00E016] Name Functions Stopped Operating Video signal HSYNC signal After reset
Data slicer timing signal generating circuit control (DSC10) Selection data slice reference voltage generating field (DSC11) Reference clock source selection (DSC12) these bits "0." these bits "1." this "0."
Definition fields Hsep Vsep Hsep Vsep
Fig. 8.10.4 Data Slicer Control Register
Data Slicer Control Register
Data slicer control register (DSC2) [Address 00E116]
Name Caption data latch completion flag (DSC20)
Functions
After reset
Data latched Indeterminate clock-run-in determined. Data latched clock-run-in determined. Read-only Method Method Match Mismatch
this "1." Test Field determination flag(DSC23) Vertical synchronous signal (Vsep) generating method selection (DSC24) V-pulse shape determination flag (DSC25) this "o." Test Read-only
Indeterminate Indeterminate
Indeterminate
Indeterminate
Definition fields Hsep Vsep Hsep Vsep
Fig. 8.10.5 Data Slicer Control Register
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8.10.2 Clamping Circuit Low-pass Filter
clamp circuit clamps sync chip part composite video signal input from CVIN pin. low-pass filter attenuates noise clamped composite video signal. CVIN which composite video signal input requires capacitor (0.1 coupling outside. Pull down CVIN with resistor hundreds kiloohms addition, recommend install externally simple lowpass filter using resistor capacitor CVIN (refer Figure 8.10.1). Composite Measure period Timing signal
8.10.3 Sync Slice Circuit
This circuit takes composite sync signal from output signal low-pass filter.
Vsep signal
8.10.4 Synchronous Signal Separation Circuit
This circuit separates horizontal synchronous signal vertical synchronous signal from composite sync signal taken sync slice circuit. (1)Horizontal Synchronous Signal (Hsep) one-shot horizontal synchronizing signal Hsep generated falling edge composite sync signal. (2)Vertical Synchronous Signal (Vsep) Vsep signal generating method, possible select following methods using data slicer control register (address 00E116). level width composite sync signal measured. this width exceeds certain time, Vsep signal generated synchronization with rising timing signal immediately after this level. level width composite sync signal measured. this width exceeds certain time, detected whether falling composite sync signal exits level period timing signal immediately after this level. falling exists, Vsep signal generated synchronization with rising timing signal (refer Figure 8.10.6). Figure 8.10.6 shows Vsep generating timing. timing signal shown figure generated from reference clock which timing generating circuit outputs. Reading data slicer control register permits determinating shape V-pulse portion composite sync signal. shown Figure 8.10.7, when level matches level, this "0." case mismatch, "1."
Vsep signal generated rising timing signal immediately after level width composite sync signal exceeds certain time.
Fig. 8.10.6 Vsep Generating Timing (method
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8.10.5 Timing Signal Generating Circuit
This circuit generates reference clock which times large horizontal synchronous signal frequency. also generates various timing signals basis reference clock, horizontal synchronous signal vertical synchronizing signal. circuit operates setting data slicer control register (address 00E016) "1." reference clock used display clock function addition data slicer. HSYNC signal used count source instead composite sync signal. However, when HSYNC signal selected, data slicer cannot used. count source reference clock selected data slicer control register (address 00E016). pins HLF, connect resistor capacitor shown Figure 8.10.1. Make length wiring which connected these pins short possible that leakage current generated.
Note: takes tens milliseconds until reference clock becomes stable after data slicer timing signal generating circuit started. this period, various timing signals, Hsep signals Vsep signals become unstable. this reason, take stabilization time into consideration when programming.
DSC2 Composite sync signal
Fig. 8.10.7 Determination V-pulse Waveform
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8.10.6 Data Slice Line Specification Circuit Specification data slice line
This circuit decides line which caption data superimposed. line (fixed), appropriate line period field (total line period field), both fields sliced their data. caption position register (address 00E616) used each setting (refer Table 8.10.1). counter reset falling edge Vsep incremented every Hsep pulse. When counter value matched value specified bits caption position register, this Hsep sliced. values "0016" "1F16" caption position register setting only appropriate line). Figure 8.10.8 shows signals vertical blanking interval. Figure 8.10.9 shows structure caption position register.
Field determination
field determination flag read data slicer control register This flag charge falling edge Vsep.
Specification line slice voltage
reference voltage slicing (slice voltage) generated clock run-in pulse particular line (refer Table 8.10.1). field generate slice voltage specified data slicer control register line generate slice voltage field specified bits caption position register (refer Table 8.10.1).
Video signal
Vertical blanking interval
Composite video signal Vsep
appropriate line caption position register Line (when setting line
Hsep
Count value caption position register ("0F this case)
Magnified drawing
Hsep Clock run-in Start 16-bit data
Composite video signal Window deteminating clock-run-in
Start
Fig. 8.10.8 Signals Vertical Blanking Interval
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Caption Position Register
Caption Position Register (CPS) [Address 00E616]
Name Caption position bits(CPS0 CPS4) Caption data latch completion flag (CPS5)
Functions
After reset
Data latched Indeterminate clock-run-in determined. Data latched clock-run-in determined. Refer corresponding Table (Table 8.10.1).
Slice line mode specification bits field) (CPS6, CPS7)
Fig. 8.10.9 Caption Position Register
Table 8.10.1 Specification Data Slice Line Field Line Sliced Data Both fields Line line specified bits (total lines) (See note Both fields line specified bits (total line) (See note Both fields Line (total line) Both fields Line line specified bits (total lines) (See note Field Line Generate Slice Voltage Field specified DSC1 Line (total line) Field specified DSC1 line specified bits (total line) (See note Field specified DSC1 Line (total line) Field specified DSC1 Line line specified bits (total lines) (See note
Notes DSC1 data slicer control register caption position register. "0016" "1016" bits CPS. "0016" "1F16" bits CPS.
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8.10.7 Reference Voltage Generating Circuit Comparator
composite video signal clamped clamping circuit input reference voltage generating circuit comparator.
8.10.8 Start Detecting Circuit
This circuit detects start line decided data slice line specification circuit. detection start described below. sampling clock generated dividing reference clock output timing signal. clock run-in pulse detected sampling clock. After detection pulse, start pattern detected from comparator output.
Reference voltage generating circuit
This circuit generates reference voltage (slice voltage) using amplitude clock run-in pulse line specified data slice line specification circuit. Connect capacitor between VHOLD pin, make length wiring short possible that leakage current generated.
8.10.9 Clock Run-in Determination Circuit
This circuit determinates clock run-in counting number pulses window composite video signal. reference clock count value pulse cycle stored bits clock run-in detect register (address 00E416). Read these bits after occurrence data slicer interrupt (refer "8.10.12 Interrupt Request Generating Circuit"). Figure 8.10.10 shows structure clock run-in detect register.
Comparator
comparator compares voltage composite video signal with voltage (reference voltage) generated reference voltage generating circuit, converts composite video signal into digital value.
Clock Run-in Detect Register
Clock run-in detect register (CRD) [Address 00E4
Test bits
Name Read-only
Functions
After reset
Clock run-in detection (CRD3 CRD7)
Number reference clocks counted clock run-in pulse period.
Fig. 8.10.10 Clock Run-in Detect Register
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8.10.10 Data Clock Generating Circuit
This circuit generates data clock synchronized with start detected start detecting circuit. data clock stores caption data 16-bit shift register. When 16-bit data been stored clock run-in determination circuit determines clock run-in, caption data latch completion flag set. This flag reset falling vertical synchronous signal (Vsep).
Data Clock Position Register
Data clock position register (DPS) [Address 00E516]
Name this "0." this "1." this "0." Data clock position bits (DPS3 DPS7)
Functions
After reset
Fig. 8.10.11 Data Clock Position Register
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8.10.11 16-bit Shift Register
caption data converted into digital value comparator stored into 16-bit shift register synchronization with data clock. contents high-order bits stored caption data obtained reading data register (address 00E316) data register (address 00CF16). contents low-order bits obtained reading data register (address 00E216) data register (address 00CE16), respectively. These registers reset falling Vsep. Read data registers after occurrence data slicer interrupt (refer "8.10.12 Interrupt Request Generating Circuit").
8.10.12 Interrupt Request Generating Circuit
interrupt requests shown Table 8.10.3 generated combination following bits; bits caption position register (address 00E616). Read contents data registers contents bits clock run-in detect register after occurrence data slicer interrupt request.
Table 8.10.2 Contents Caption Data Latch Completion Flag 16-bit Shift Register Slice Line Specification Mode Contents Caption Data Latch Completion Flag Completion Flag (bit DSC2) Line line specified bits Line Line Completion Flag (bit CPS) line specified bits Invalid Invalid line specified bits Contents 16-bit Shift Register Caption Data Registers 16-bit data line 16-bit data line specified bits 16-bit data line 16-bit data line Caption Data Registers 16-bit data line specified bits Invalid Invalid 16-bit data line specified bits
CPS: Caption position register DSC2: Data slicer control register
Table 8.10.3 Occurence Sources Interrupt Request Caption position register Occurence Souces Interrupt Request Data Slice Line After slicing line After line specified bits After slicing line After slicing line
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8.10.13 Synchronous Signal Counter
synchronous signal counter counts composite sync signal taken from video signal data slicer circuit vertical synchronous signal Vsep count source. count value certain time time) generated f(XIN)/213 f(XIN)/213 stored into 5-bit latch. Accordingly, latch value changes cycle time. When count value exceeds "1F16," "1F16" stored into latch.
latch value obtained reading sync pulse counter register (address 00E916). count source selected sync pulse counter register. synchronous signal counter used when mode register (address 020816). Figure 8.10.12 shows structure sync pulse counter Figure 8.10.13 shows synchronous signal counter block diagram.
Sync Pulse Counter Register
Sync pulse counter register (HC) [Address 00E916]
Name Count value (HC0 HC4)
Functions
After reset
Count source (HC5)
HSYNC signal Composite sync signal
Nothing assigned. These bits write disable bits. When these bits read out, values
Fig. 8.10.12 Sync Pulse Counter Register
f(XIN)/213
Composite sync signal HSYNC signal
Reset 5-bit counter Counter
Latch bits)
Sync pulse counter register
Selection gate connected black side when reset.
Data
Fig. 8.10.13 Synchronous Signal Counter Block Diagram
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8.11 FUNCTIONS
Table 8.11.1 outlines functions. This microcomputer incorporates circuit characters lines. also, there display modes they selected block unit. display modes selected bits block control register features each mode described below.
Table 8.11.1 Features Each Display Mode
Display mode Parameter mode (Closed caption mode) characters lines dots (Character display area dots) kinds kinds (fixed) 1/2H Smooth italic, under line, flash kinds 1/2H, Border (black) dots mode (Border OFF) (On-screen display mode)
Number display characters structure Kinds characters Kinds character sizes Pre-divide ratio (See note) size Attribute Character font coloring Character background coloring output Raster coloring Function
screen kinds (per character unit) screen kinds (per character unit) Possible (per character unit) Auto solid space function Window function
Display position Display expansion (multiline display)
Horizontal: levels, Vertical: levels Possible
Notes divide ratio frequency divider (the pre-divide circuit) referred "pre-divide ratio" hereafter. character size specified with size pre-divide ratio (refer 8.11.2 Size).
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circuit extended display mode. This mode allows multiple lines lines more) displayed screen interrupting display each time line displayed rewriting data block which display terminated software. Figure 8.11.1 shows configuration character. Figure 8.11.2 shows block diagram circuit. Figure 8.11.3 shows control register. Figure 8.11.4 shows block control register
mode mode
dots dots Blank area
dots
dots dots
Underline area Blank area Displayed only mode.
Fig. 8.11.1 Configuration Character Display Area
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Clock OSC1 OSC2 HSYNC VSYNC
Data slicer clock
Display oscillation circuit
Control registers Control circuit control register Horizontal position register Block control register Vertical position register Window register polarity control register Raster color register (address 00D016) (address 00D116) (addresses 00D216, 00D316) (addresses 00D416, 00D516) (addresses 00D616, 00D716) (address 00D816) (address 00D916)
bytes characters lines
dots dots characters
Shift register 16-bit Output circuit
OUT1
OUT2
Data
Fig. 8.11.2 Block Diagram Circuit
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Control Register
control register (OC) [Address 00D016] Name control (OC0) (See note) Automatic solid space control (OC1) Window control (OC2) mode clock selection (OC3) Functions All-blocks display All-blocks display Data slicer clock Clock from OSC1 Data slicer clock Clock from OSC1
After reset
mode clock selection (OC4) OSC1 clock selection (OC5, OC6)
oscillating set. oscillating, Ceramic oscillating set.
this
Note: Even this switched during display, display screen remains unchanged until rising (falling) next SYNC.
Fig. 8.11.3 Control Register
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Block Control register
Block control register (BCi) (i=1, [Addresses 00D2 Name
00D3
After reset
Functions
Display mode selection bits (BCi0, BCi1) (See note size selection bits (BCi2, BCi3)
Display mode mode (Border OFF) mode (Border
Pre-divide Ratio Size
Indeterminate
Indeterminate
Pre-divide ratio selection (BCi4)
1/2H 1/2H Indeterminate
OUT1/OUT2 output control OUT1 output control OUT2 output control (BCi5) (See note Vertical display start position control (BCi6) Window top/bottom boundary control (BCi7) BC16: Block BC26: Block
BC17: Window boundary BC27: Window bottom boundary
Indeterminate Indeterminate
Indeterminate
Notes controls OUT1 output when "0." controls OUT2 output when "1." clock cycle divided pre-divide circuit. HSYNC.
Fig. 8.11.4 Block Control Register
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8.11.1 Display Position
display positions characters specified units called "block." There blocks, blocks characters displayed each block (refer "8.11.5 Memory OSD"). display position each block both horizontal vertical directions software. display start position horizontal direction selected blocks common from 128-step display positions units 4TOSC (TOSC oscillation cycle). display start position vertical direction each block selected from 512-step display positions units HSYNC cycle).
Blocks displayed conformance with following rules: When display position block overlapped with that block (Figure 8.11.5 (b)), block displayed front. When another block display position appears while block displayed (Figure 8.11.5 (c)), block with larger value vertical display start position displayed.
(HP) Block Block Example when each block separated
(HP) Block (Block displayed) Example when block overlaps with block
(HP) Block Block Example when block overlaps process block
Note: indicates vertical display start position display block
Fig. 8.11.5 Display Position
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vertical display start position determined counting horizontal sync signal (HSYNC). this time, when VSYNC HSYNC positive polarity (negative polarity), starts count rising edge (falling edge) HSYNC signal from after fixed cycle rising edge (falling edge) VSYNC signal. interval from rising edge (falling edge) VSYNC signal rising edge (falling edge) HSYNC signal needs enough time machine cycles more) avoiding jitter. polarity HSYNC VSYNC signals select with polarity control register (address 00D816).
machine cycles more VSYNC signal input 0.25 0.50 [µs] f(XIN) 8MHz) VSYNC control signal microcomputer Period counting HSYNC signal HSYNC signal input machine cycles more
(See note
count When bits polarity control register (address 00D816) (negative polarity) Notes vertical position determined counting falling edge HSYNC signal after rising edge VSYNC control signal microcomputer. generate falling edge HSYNC signal near rising edge VSYNC control signal microcomputer avoid jitter. pulse width VSYNC HSYNC needs machine cycles more.
Fig. 8.11.6 Supplement Explanation Display Position
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vertical display start position each block steps (where each step (TH: HSYNC cycle)) values "0016" "FF16" vertical position register (addresses 00D416 00D516) values block control register (addresses 00D216 00D316). vertical position registers shown Figure 8.11.7.
Vertical Position Register
Vertical position register (VPi) [Addresses 00D416, 00D516]
Name Vertical display start position control bits (VPi0 VPi7) (See note) Functions Vertical display start position (BCi6 setting value, HSYNC cycle, BCi6: block control register After reset
Inderterminate
Note: values except "0016" when BCi6 "0."
Fig. 8.11.7 Vertical Position Register
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horizontal display start position common blocks, steps (where step 4TOSC, TOSC being oscillation cycle) values "0016" "FF16" bits horizontal position register (address 00D116). horizontal position register shown Figure 8.11.8.
Horizontal Position Register
Horizontal position register (HP) [Address 00D1 Functions Horizontal display start positions steps step OSC) Nothing assigned. This write disable bit. When this read out, value "0." Name After reset
Horizontal display start position control bits (HP0 HP6)
Note: setting value synchronizes with SYNC.
Fig. 8.11.8 Horizontal Position Register
Notes clock cycle divided pre-divide circuit) occurs between horizontal display start position horizontal position register most left block. Accordingly, when blocks have different pre-divide ratios, their horizontal display start position will match. horizontal start position based clock source cycle selected each block. Accordingly, when blocks have different clock source cycles, their horizontal display start position will match. When setting "0016" horizontal position register, needs approximately 62TOSC Tdef) interval from rising edge (when negative polarity selected) HSYNC signal horizontal display start position.
HSYNC Note Tdef 4TOSC
Block (Pre-divide ratio clock source data slicer clock)
Block (Pre-divide ratio clock source data slicer clock)
Tdef' 4TOSC'
Note
Block (Pre-divide ratio clock source OSC1)
TOSC Tdef Value horizontal position register (decimal notation) clock cycle divided pre-divide circuit oscillation cycle
Fig. 8.11.9 Notes Horizontal Display Start Position
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8.11.2 Size
size selected block unit. size vertical direction determined dividing HSYNC vertical size control circuit. size horizontal determined dividing following clock horizontal size control circuit clock gained dividing clock source (data slicer clock, OSC1) pre-divide circuit. clock cycle divided pre-divide circuit defined 1TC. size each block specified bits block control register Refer Figure 8.11.4 (the structure block control register). block diagram size control circuit shown Figure 8.11.10.
OSC1
Synchronous
circuit
Cycle
Clock cycle
Data slicer clock
BCi4 Cycle
Horizontal size control circuit
Pre-divide circuit HSYNC Vertical size control circuit control circuit Note: data slicer clock, data slicer control register "1."
Fig. 8.11.10 Block Diagram Size Control Circuit
1/2H
Scanning line F1(F2) Scanning line F2(F1)
Fig. 8.11.11 Definition Sizes
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8.11.3 Clock
clock display used OSD, possible select following types. Data slicer clock output from data slicer (approximately MHz) OSC1 clock supplied from pins OSC1 OSC2 Clock from ceramic resonator oscillator from pins OSC1 OSC2 This clock each block selected following bits raster color register (address 00D916), bits clock source control register (addresses 00D016). variety character sizes obtained combining sizes with clocks. When using pins OSC1 OSC2 clock pins, pins used sub-clock pins port
Table 8.11.2 Setting P26/OSC1/XCIN, P27/OSC2/XCOUT Function Register raster color register control register clock Sub-clock Port
Data slicer circuit
Data slicer clock (See note)
mode block
mode block
Ceramic "10"
OSC1 clock
OC6,
Oscillating mode
Note data slicer clock, data slicer control register "1."
Fig. 8.11.12 Block Diagram Selection Circuit
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8.11.4 Field Determination Display
display block with vertical size 1/2H, whether even field field determined through differences synchronizing signal waveform interlacing system. line (refer Figure 8.11.14) corresponding field displayed alternately. following, field determination standard case where both horizontal sync signal vertical sync signal negative-polarity inputs will explained. field determination determined detecting time from falling edge horizontal sync signal until falling edge VSYNC control signal (refer Figure 8.11.6) microcomputer then comparing this time with time previous field. When time longer than comparing time, regarded even field. When time shorter, regarded field contents this field read field determination flag (bit polarity control register address 00D816). line specified polarity control register (refer Figure 8.11.14). However, field determination flag read from fixed even field field, regardless
Polarity Control Register
polarity control register (PC) [Address 00D8
Name HSYNC input polarity switch (PC0) VSYNC input polarity switch (PC1) output polarity switch (PC2) OUT1 output polarity switch (PC3) OUT2 output polarity switch (PC4) Display line selection (PC5) (See note)
Functions Positive polarity input Negative polarity input Positive polarity input Negative polarity input Positive polarity output Negative polarity output Positive polarity output Negative polarity output Positive polarity output Negative polarity output even field field even field field
After reset
Field determination flag (PC6) this "0."
Even field field
Note: Refer corresponding figure (8.11.14).
Fig. 8.11.13 Polarity Control Register
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Both SYNC signal SYNC signal negative-polarity input Field Display line determination selection flag(Note)
HSYNC
Field
Display line
VSYNC VSYNC control signal microcomputer Upper VSYNC signal Lower VSYNC control signal microcomputer
field (Odd-numbered)
0.25 0.50[µs] f(XIN)
field (Even-numbered) Even
line line
field (Odd-numbered)
line
line
When using field determination flag, sure mode register (address 0208 mode mode
"0."
When display line selection "0," font displayed even field, font displayed field. polarity control register read field determination flag read field, read even field.
font configuration diagram
Note field determination flag changes rising edge SYNC control signal (negative-polarity input) microcomputer.
Fig. 8.11.14 Relation between Field Determination Flag Display Font
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8.11.5 Memory
There types memory used store character data used specify characters colors displayed. <M3727GM6/M8-XXXSP/FP, M37272E8SP/FP> addresses 140016 3BFF16 addresses 080016 087F16
(addresses 140016 3BFF16)
pattern data characters stored ROM. specify kinds character font, necessary write character code into RAM. Data character font specified shown Figure 8.11.15.
address character font data
address AD16 AD15 AD14 AD13 AD12 AD11 AD10 Font
Line number/character code/font
Line number
haracter code
0A16 1D16 Line number Character code 0016 FF16 7F16 8016 cannot used) Left area Font Right area
Line number
Left area
Right area
Data
000016 7FF016 7FF816 601C16 600C16 600C16 600C16 600C16 601C16 7FF816 7FF016 630016 638016 61C016 60E016 607016 603816 601C16 600C16 000016
Character font
Fig. 8.11.15 Character Font Data Storing Address
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Notes 80-byte addresses corresponding character code "7F16" "8016" test data storing area. data area follows. <Test data storing area> M37272M6/M8-XXXSP/FP, M37272E8SP/FP addresses 100016 10016 FE16 100016 10016 0116 (1)Mask version (M3727GM6/M8-XXXSP/FP) "FF16" area stores test data this area different data from "FF16" stored actual products.) When using font editor, test data written automatically. (2)EPROM version (M37272E8SP/FP) test data area. When using font editor, test data written automatically.
M37272E8SP/FP <"FF16"> address (test data)
<"8016"> address (test data)
14FE16 (0916), 14FF16 (5116) 16FE16 (0016), 16FF16 (5216) 18FE16 (1216), 18FF16 (5316) 1AFE16 (0016), 1AFF16 (5416) 1CFE16 (2416), 1CFF16 (5516) 1EFE16 (0016), 1EFF16 (5616) 20FE16 (8816), 20FF16 (5716) 22FE16 (0016), 22FF16 (5816) 24FE16 (9016), 24FF16 (5916) 26FE16 (4816), 26FF16 (5A16) 28FE16 (2416), 28FF16 (5B16) 2AFE16 (0016), 2AFF16 (5C16) 2CFE16 (2416), 2CFF16 (5D16) 2EFE16 (4816), 2EFF16 (5E16) 30FE16 (0016), 30FF16 (5F16) 32FE16 (4816), 32FF16 (5016) 34FE16 (9016), 34FF16 (5116) 36FE16 (0016), 36FF16 (5216) 38FE16 (0116), 38FF16 (5316) 3AFE16 (8016), 3AFF16 (5416)
150016 (9016), 150116 (A116) 170016 (0016), 170116 (A216) 190016 (4816), 190116 (A316) 1B0016 (0016), 1B0116 (A416) 1D0016 (2416), 1D0116 (A516) 1F0016 (0016), 1F0116 (A616) 210016 (1216), 210116 (A716) 230016 (0016), 230116 (A816) 250016 (0916), 250116 (A916) 270016 (0016), 270116 (AA16) 290016 (8116), 290116 (AB16) 2B0016 (1816), 2B0116 (AC16) 2D0016 (0016), 2D0116 (AD16) 2F0016 (4216), 2F0116 (AE16) 310016 (2416), 310116 (AF16) 330016 (0016), 330116 (B016) 350016 (8116), 350116 (B116) 370016 (0C16), 370116 (B216) 390016 (0616), 390116 (B316) 3B0016 (0016), 3B0116 (B416)
character code "0916" used "transparent space" when displaying Closed Caption. Therefore, "0016" 40-byte addresses corresponding character code "0916." <Transparent space font data storing area> M3727GM6/M8-XXXSP/FP, M37272E8SP/FP addresses 100016 10016 1216 100016 10016 1316
addresses 141216 141316 addresses 161216 161316 addresses 381216 381316 addresses 3A1216 3A1316
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allocated addresses 080016 087F16, divided into display character code specification part, color code specification part, color code specification part each block. Table 8.11.3 shows contents RAM. example, display character position (the left edge) block write character code address 080016, write color code 082016. structure shown Figure 8.11.16.
Table 8.11.3 Contents Display Position (from left) Block character character character Block 30th character 31st character 32nd character character character character Block 30th character 31st character 32nd character
Character Code Specification 080016 080116 080216 081D16 081E16 081F16 084016 084116 084216 085D16 085E16 085F16
Color Code Specification 082016 082116 082216 083D16 083E16 083F16 086016 086116 086216 087D16 087E16 087F16
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Blocks
(See note
Color code mode Control character color Control character color Control character color OUT1/OUT2 control Flash control Underline control Italic control (See note Flash Flash Underline Underline Italic Italic
Notes Read value bits color code "0." OUT1/OUT2 control, refer "8.11.8 OUT1/OUT2 signal." "7F16" "8016" cannot used character code.
Character code (See note mode
name
Function
name
Function
Character code
Character code
Character code
Character code
Color signal output Color signal output
Control character color Control character color Control character color OUT1/OUT2 control Control background color Control background color Control background color
Color signal output Color signal output
(See note Color signal output Color signal output
Fig. 8.11.16 structure
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8.11.6 Character color
color each character displayed color code. kinds> Specified bits (R), (G), color code
8.11.7 Character background color
character background color displayed character display area only mode. character background color each character specified color code. kinds> Specified bits (R), (G), color code
Note character background color displayed following part (character display area)-(character font)-(border). Accordingly, character background color does with these color signal.
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8.11.8 OUT1, OUT2 signals
OUT1, OUT2 signals used control luminance video signal. output waveform OUT1, OUT2 signals controlled display mode, block control register (refer Figure 8.11.4) RAM. setting values
controlling OUT1, OUT2 corresponding output waveform shown Figure 8.11.17.
Note When OUT2 signal output, port control register (refer Figure 8.11.28) "1."
Block Control OUT1/OUT2 Register Display Control Mode OUT1/OUT2 Output Control (b5) (OUT1 output controlled RA3) (OUT2 output controlled RA3)
Output Waveform (A-A')
OUT1 FONT/BORDER OUT2 OUT1 AREA OUT2 OUT1 FONT/BORDER OUT2 OUT1 FONT/BORDER OUT2 AREA OUT1 FONT
(OUT1 output controlled RA3) (OUT2 output controlled RA3)
OUT2 OUT1 AREA OUT2 OUT1 FONT OUT2 OUT1 FONT
OUT2 AREA
Notes FONT/BORDER.In mode (Border ON), OUT1 outputs area font border. mode (Border OFF), OUT1 outputs only font area. AREA. OUT1/OUT2 outputs entire display area character. FONT. mode, OUT1 outputs font area. When automatic solid space function mode, AREA outputs according color code. When solid space automatically output character code regardless RA3.
Fig. 8.11.17 Setting Value Controlling OUT1, OUT2 Corresponding Output Waveform
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8.11.9 Attribute
attributes (border, flash, underline, italic) controlled character font. attributes controlled different depending each mode. mode Flash, underline, italic (per character unit) mode Border (per character unit)
Under line
underline output 23th 24th dots vertical direction only mode. underline controlled RAM. color underline same color that character font.
Flash
character font underline flashed only mode. flash controlled RAM. character font part, character output part flashed, character background part flashed. flash cycle bases VSYNC count. VSYNC cycle display VSYNC cycle display OFF)
Italic
italic made slanting font stored right only mode. italic controlled
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