Available Texas Instruments NanoStar NanoFree Packages Supports Operat

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SN74LVC2G34 DUAL BUFFER GATE
Available Texas Instruments NanoStar NanoFree Packages Supports Operation Inputs Accept Voltages Power Consumption, 10-µA ±24-mA Output Drive Typical VOLP (Output Ground Bounce) <0.8 25°C Typical VOHV (Output Undershoot) 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds JESD Class Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
PACKAGE (TOP VIEW)
YEA, YEP, YZA, PACKAGE (BOTTOM VIEW)
description/ordering information
This dual buffer gate designed 1.65-V 5.5-V operation. SN74LVC2G34 performs Boolean function positive logic. NanoStar NanoFree package technology major breakthrough packaging concepts, using package. ORDERING INFORMATION
PACKAGE NanoStar WCSP (DSBGA) 0.17-mm Small Bump NanoFree WCSP (DSBGA) 0.17-mm Small Bump (Pb-free) NanoStar WCSP (DSBGA) 0.23-mm Large Bump -40°C 85°C NanoFree WCSP (DSBGA) 0.23-mm Large Bump (Pb-free) (SOT (SOT-23) (SC-70) Reel 3000 Reel Reel 3000 Reel ORDERABLE PART NUMBER SN74LVC2G34YEAR SN74LVC2G34YZAR Reel 3000 SN74LVC2G34YEPR SN74LVC2G34YZPR SN74LVC2G34DBVR SN74LVC2G34DBVT SN74LVC2G34DCKR SN74LVC2G34DCKT C34_ _C9_ TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. DBV/DCK: actual top-side marking additional character that designates assembly/test site. YEA/YZA,YEP/YZP: actual top-side marking three preceding characters denote year, month, sequence code, following character designate assembly/test site. Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. NanoStar NanoFree trademarks Texas Instruments.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G34 DUAL BUFFER GATE
description/ordering information (continued)
This device fully specified partial-power-down applications using Ioff. Ioff circuitry disables outputs, preventing damaging current backflow through device when powered down.
FUNCTION TABLE (each gate) INPUT OUTPUT
logic diagram (positive logic)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high-impedance power-off state, (see Note -0.5 Voltage range applied output high state, (see Notes -0.5 Input clamp current, Output clamp current, Continuous output current, Continuous current through ±100 Package thermal impedance, (see Note package 165°C/W package 259°C/W YEA/YZA package 143°C/W YEP/YZP package 123°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input negative-voltage output voltage ratings exceeded input output current ratings observed. value provided recommended operating conditions table. package thermal impedance calculated accordance with JESD 51-7.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G34 DUAL BUFFER GATE
recommended operating conditions (see Note
Supply voltage Operating Data retention only 1.65 1.95 1.65 1.95 1.65 High-level output current 1.65 Low-level output current 0.15 Input transition rise fall rate 1.65 0.65 0.35 ns/V UNIT
High-level High level input voltage
Low-level level input voltage
Input voltage Output voltage
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G34 DUAL BUFFER GATE
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER -100 Ioff inputs GND, input Other inputs TEST CONDITIONS 1.65 1.65 1.65 1.65 1.65 VCC-0.1 0.45 0.55 0.55 UNIT
typical values 25°C.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) 0.15 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G34 DUAL BUFFER GATE
PARAMETER MEASUREMENT INFORMATION
VLOAD Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD
From Output Under Test (see Note
LOAD CIRCUIT INPUTS 0.15 tr/tf VCC/2 VCC/2 VCC/2 VLOAD
0.15 0.15
Timing Input Input VOLTAGE WAVEFORMS PULSE DURATION Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS Output Waveform (see Note Output Control tPZL tPZH Data Input
VOLTAGE WAVEFORMS SETUP HOLD TIMES tPLZ VLOAD/2 tPHZ
Output Waveform VLOAD (see Note
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd. parameters waveforms applicable devices.
Figure Load Circuit Voltage Waveforms
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MECHANICAL DATA
MPDS026D FEBRUARY 1997 REVISED FEBRUARY 2002
(R-PDSO-G6)
PLASTIC SMALL-OUTLINE
0,95
0,50 0,25
0,20
1,70 1,50
3,00 2,60
0,15
3,00 2,80
Gage Plane
0,25 0°-8° 0,55 0,35
Seating Plane 1,45 0,95 0,05 0,10
4073253-5/G 01/02
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion. Leads wider than leads package orientation.
POST OFFICE 655303
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MECHANICAL DATA
MPDS114 FEBRUARY 2002
(R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,15
0,10
1,40 1,10
2,40 1,80
0,13
2,15 1,85
Gage Plane
0,15 0°-8° 0,46 0,26
Seating Plane 1,10 0,80 0,10 0,00 0,10
4093553-3/D 01/02 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion. Falls within JEDEC MO-203
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MXBG003A NOVEMBER 2001 REVISED 2002
(R-XBGA-N6)
DIE-SIZE BALL GRID ARRAY
0,50 0,95 0,85 0,25
1,00 0,50
1,45 1,35
0,35
0,50
NOTES:
linear dimensions millimeters. This drawing subject change without notice. NanoStar package configuration. Package complies JEDEC MO-211 variation This package tin-lead (SnPb). Refer package (drawing 4204151) lead-free.
INDEX AREA 0,19 0,15 0,05 0,05
0,05 SEATING PLANE 0,15 0,10
4203167-3/C 04/2002
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MXBG005A JANUARY 2002 REVISED APRIL 2002
(R-XBGA-N6)
DIE-SIZE BALL GRID ARRAY
0,50 0,95 0,85 0,25
1,00 0,50 Index Area 0,19 0,15 0,05 0,05
1,45 1,35
0,35
0,05 0,50 Seating Plane 0,15 0,10
4204151-3/B 03/2002 NOTES: linear dimensions millimeters. This drawing subject change without notice. NanoFree package configuration. Package complies JEDEC MO-211 variation This package lead-free. Refer package (drawing 4203167) tin-lead (SnPb).
NanoFree trademark Texas Instruments.
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MXBG019 OCTOBER 2002
(R-XBGA-N6)
DIE-SIZE BALL GRID ARRAY
0,50 0,95 0,85 0,25
1,00 0,50 Index Area 0,25 0,20 0,05 0,05
1,45 1,35
0,05 0,50 Seating Plane 0,20 0,15
4204741-3/A 10/2002 NOTES: NOTES: linear dimensions millimeters. This drawing subject change without notice. NanoFree package configuration. This package lead-free. Refer package (drawing 4204725) tin-lead (SnPb).
NanoFree trademark Texas Instruments.
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MXBG022 OCTOBER 2002
(R-XBGA-N6)
DIE-SIZE BALL GRID ARRAY
0,50 0,95 0,85 0,25
1,00 0,50 Index Area 0,25 0,20 0,05 0,05
1,45 1,35
0,05 0,50 Seating Plane 0,20 0,15
4204725-3/A 10/2002 NOTES: linear dimensions millimeters. This drawing subject change without notice. NanoFree package configuration. This package tin-lead (SnPb). Refer package (drawing 420741) lead-free.
NanoFree trademark Texas Instruments.
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements.
Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated

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