FPD3000P100 DESCRIPTION APPLICATIONS FPD3000P100 packaged AlGaAs/

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FPD3000P100 DESCRIPTION APPLICATIONS FPD3000P100 packaged AlGaAs/

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PACKAGED POWER PHEMT FEATURES 32.5 Linear Output Power Power Gain Maximum Stable Gain Output Power-Added Efficiency
FPD3000P100
DESCRIPTION APPLICATIONS FPD3000P100 packaged AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (PHEMT), featuring 0.25 3000 Schottky barrier gate, defined highresolution stepper-based photolithography. recessed offset Gate structure minimizes parasitics optimize performance. epitaxial structure processing have been optimized reliable high-power applications. FPD3000P100 also features Si3N4 passivation also available form cost plastic SOT89 plastic package. Typical applications include commercial other narrowband broadband high-performance amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, medium-haul digital radio transmitters.
ELECTRICAL SPECIFICATIONS 22°C
Parameter Power Gain Compression Power Gain P1dB Maximum Stable Gain (S21/S12) Symbol P1dB G1dB Test Conditions IDSS IDSS IDSS Power-Added Efficiency Output Third-Order Intercept Point (from below P1dB) Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Drain Breakdown Voltage Thermal Resistivity (see Notes) IDSS IMAX IGSO |VP| |VBDGD| IDSS; POUT P1dB IDSS Matched optimal power 14.5 16.0 1110 °C/W 20.5 21.5 31.0 16.5 32.5 17.0 Units UNLESS OTHERWISE NOTED, SPECIFICATIONS MEASURED USING SIGNAL
Phone: 850-5790 Fax: 850-5766
Released: 6/27/05 Email: sales@filcsi.com
PACKAGED POWER PHEMT RECOMMENDED BIAS CONDITIONS: Drain-Source Voltage: Drain-Source Current: IDSS ABSOLUTE MAXIMUM RATINGS1
Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current Input Power
FPD3000P100
Symbol TSTG PTOT Comp.
Test Conditions Forward reverse current Under acceptable bias state Under acceptable bias state Non-Operating Storage De-Rating Note below Under bias conditions more Max. Limits
IDSS
Units
Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression Simultaneous Combination Limits
Users should avoid exceeding more Limits simultaneously
TAmbient 22°C unless otherwise noted
Max. Input Limit must further limited input VSWR 2.5:1
Notes: Operating conditions that exceed Absolute Maximum Ratings could result permanent damage device. Thermal Resitivity specification assumes Au/Sn eutectic attach onto Au-plated copper heatsink rib. Power Dissipation defined PTOT (PDC PIN) POUT, where PDC: Bias Power PIN: Input Power POUT: Output Power Absolute Maximum Power Dissipation de-rated follows above 22°C: PTOT= 5.3W (0.042W/°C) where heatsink ambient temperature above 22°C Example: 85°C heatsink temperature: PTOT 5.3W (0.042 22)) 2.65
HANDLING PRECAUTIONS avoid damage devices care should exercised during handling. Proper Electrostatic Discharge (ESD) precautions should observed stages storage, handling, assembly, testing. These devices should treated Class 250V) JESD22-A114-B, Human Body Model, Class 200V) JESD22-A115-A, Machine Model.
Phone: 850-5790 Fax: 850-5766
Released: 6/27/05 Email: sales@filcsi.com
PACKAGED POWER PHEMT APPLICATIONS NOTES DESIGN DATA Applications Notes available from your local Filtronic Sales Representative directly from factory. Complete design data, including S-parameters, noise data, large-signal models available Filtronic site. RECOMMENDED BIASING GUIDELINES: most applications, dual-bias circuit required amount quiescent current drawn FPD3000P100. Source discrete pHEMT device wire-bonded package flange, therefore self-biasing (using bypassed Source resistor Gate-Source voltage) practical. dual-bias circuit will require regulated filtered negative Gate supply well positive Drain supply. Typical Gate bias voltages will about -0.4V. Active bias circuits employed dissipation Drain current sense resistor acceptable, these cases bias voltages must sequenced that negative Gate voltage established final value before Drain voltage reached, prevent device self-oscillation.
FPD3000P100
information specifications subject change without notice.
Phone: 850-5790 Fax: 850-5766
Released: 6/27/05 Email: sales@filcsi.com

FPD3000P100 DESCRIPTION APPLICATIONS FPD3000P100 packaged AlGaAs/

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