Baudrate Synthesizer baudrate 1/64 clock speed dedicated clock freq. B

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Baudrate Synthesizer baudrate 1/64 clock speed dedicated clock freq. B

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iniUART innovative, flexible implementation UART (Universal Asynchronous Receiver Transmitter). iniUART implements RS-232 serial protocol, provides interface between microprocessor serial port between system standard serial port. features: core contains highly accurate programmable baud rate generator, which allows generate baudrate independently 1/64) system clock speed. point input sampling glitch rejection implemented serial receiver. iniUART core used data link layer with parallel interfaces event communication. Application-specific blocks (e.g., interrupt controller, special interfaces, status reporting circuits) then built around iniUART without modification iniUART. offers also complete UART modules, please refer webpage. MDS's in-depth know serial communication frequency synthesizers gives best benefit UART your needs. offers structural VHDL UART simulation/synthesis model target technology your choice. iniUART Structure
Baudrate Synthesizer baudrate 1/64 clock speed dedicated clock freq. Bits Data No/Odd/Even Parity Error Detection Stop Bits Format Check 3-Point Input Sampling Parallel Interface with Event Control
Smart UART Technology
iniUART
Config
Baudrate Synthesizer
Data Ctrl
Receive Unit
Format Analyzer
serial
Data Ctrl
Transmit Unit
serial
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Memec Inicore Mattenstrasse CH-2555 Switzerland e-mail: ask_us@inicore.ch http://www.inicore.ch
iniUART
Version Last modification 16.01.2002
Document change without further notice
Table Content
2.2.1 Overview Event communication. description General inputs Configuration. Baudrate. Serial interface Transmitter interface Receiver interface
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Overview
iniUART core generally used data link layer with parallel interfaces event communication. Microprocessor specific interfaces built around iniUART, well queues, interrupt controllers status reporting circuits1. following picture shows inputs outputs:
reset_n
iniUART
uart_tx_busy
uart_tx_data uart_tx_we
Unit
uart_tx_pin
uart_tx_pin
uart_rx_data
Unit
uart_rx_ready uart_par_error uart_form_error
uart_config.data_78 uart_config.par_ebl uart_config.par_pol uart_config.stop_12 uart_config.tx_run uart_config.rx_run uart_config.baudrate
Configuration
Event communication
communicating events, iniUART core uses produces active pulses, which activated only cycle. inactive state, they remain with respect rising edge, glitches occur. communicating over clock domains, these events must synchronized first!
event event input tsetup thold
event output
parameters tsetup, thold technology dependent must determined according chosen technology.
complete UART solutions, please check iniUART datasgeet. Page
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description
following part lists input output ports iniUART core gives short overview their functionality.
General inputs
These pins used clock initialize whole iniUART core. There other clocks this core. name reset_n type description system clock, rising edge used only, must least times higher than maximum baudrate asynchronous system reset, active low, goes flip flops
Configuration
configuration pins used bitrate, timing output format. They're static inputs. used both receiver transmitter common. name type uart_config.baudrate[15:0] uart_config.data_78 uart_config.par_ebl uart_config.par_pol description Defines baudrate. 2.2.1, Baudrate more details Transmit receive data size: `0': data `1': data Parity enable: `0': parity check, parity transmitted received `1': parity check, parity inserted checked Parity polarity: `0': even parity2 `1': parity This parameter ignored when par_ebl inactive! Transmit receive stop number: `0': check stop `1': check stop bits Transmit control: `0': transmitter off, ignores inputs, outputs inactive `1': transmitter working Receive control: `0': receiver off, ignores inputs, outputs inactive `1': receiver working
uart_config.stop_12 uart_config.tx_run uart_config.rx_run
2.2.1
Baudrate
baudrate generator simple prescaler, innovative (digitally controlled oscillator) which allows generating baudrates from system clock within certain range. There special clock frequency needed that purpose that you're free choose system clock iniUART, which simplifies considerably clock structure. configurate baudrate, 16bit value calculated according following formula:
Baudrate
respective
Baudrate
where Baudrate transmitting speed bits second fclk system clock speed 16bit value programmed
number ones byte, including parity even Page
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Examples: 8Mhz clock 64kbps, 33554(dec), accuracy better than 13ppm, 10Mhz clock 1200bps, 503(dec), accuracy better than 600ppm. Limitations: Values lower than 100(dec) should used, otherwise accuracy below e.g. 8MHz clock, possible baudrates with accuracy better than range from 190bps 125kbps. Accuracy: worst case accuracy calculated simply inversing value Therefore, value larger than will guarantee accuracy better than values larger than 1000 produce results better than 0.1%. Jitter: faster baudrate, better accuracy, more relative jitter added. Maximum absolute jitter always equal 1/fclk.
Serial interface
serial interface includes receive transmit path separately. full duplex solution, receive transmit possible same time. name rx_pin tx_pin type description incoming stream. inactive state logic outgoing stream. inactive state logic
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Transmitter interface
transmitting data, parallel event controlled interface used. efficient embed iniUART systems well connecting simple complex specific interfaces, including queues etc., name uart_tx_data[7:0] uart_tx_we uart_tx_busy type description 8bit data transmitted. 7bit configuration, bit[7] ignored. Data must valid stable when uart_tx_we active. Event storing tx_data transmit shift register start transmission. It's system activate this input when iniUART busy. When transmitter sending byte, this status output remains active (logic `1') until ready send byte. While uart_tx_busy `1', uart_tx_we mustn't activated.
following diagram shows typical case: uart_tx_we start sending uart_tx_busy uart_tx_pin uart_tx_data valid data change ready next byte
transmitter path stores incoming byte shift register means uart_tx_we signal starts transmitting activity. uart_tx_busy goes high also remains high until data sent.
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Receiver interface
receiving data, similar type interface used transmitter path. name uart_rx_data[7:0] type description 8bit data that been received. 7bit configuration, bit[7] ignored. data will stable only during active phase uart_rx_ready. buffer register data should remain stable until reception next character. Event (active `1') signalling, that byte arrived uart_rx_data valid now. Event (active `1') signalling, that byte with wrong parity been received aborted (it's visible rx_ready) This signal always inactive when par_ebl deactivated. Event (active `1') signalling, that byte with wrong format been received aborted (it's visible rx_ready)
uart_rx_ready uart_par_error uart_form_error
This normal case, where correct byte arrives. byte received uart_rx_ready uart_rx_data uart_form_error uart_par_error data change valid data change
when parity form error occurs transmission, byte aborted uart_rx_ready uart_rx_data uart_form_error uart_par_error invalid data
receiver path contains several checks special features. First, level uart_rx_pin watched. When falling edge detected, receiver started. reception started only when start after falling edge detected low. parity enabled, checked eventual failures reported uart_par_error. Missing stop bits (level zero) reported format checks. error cases, data byte aborted error reason reported. Please note that uart_rx_ready asserted when error reporting done.
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Baudrate Synthesizer baudrate 1/64 clock speed dedicated clock freq. B

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