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4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC DESCRIPTI


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MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC DESCRIPTION
MH64S72VJG 67108864 word 72-bit nchronous DRAM module. This consist eighteen industry standard nchronous DRAMs TSOP. TSOP card edge dual in-line package prov ides application where high densities large quantities memory required. This socket-ty memory odule ,suitable easy interchange addition module.
85pin
1pin
FEATURES
Max. Frequency Access Time from [component level]
94pin 95pin
10pin 11pin
133MHz 133MHz
5.4ns Latch mode) 5.4ns Latch mode)
Utilizes industry standard Synchronous DRAMs TSOP package industry standard Resistered buffer TSSOP package,industry standard TSSOP package Single 3.3V 0.3V supply Max.Clock frequency 133MHz forFully synchronous operation referenced clock rising edge 4-bank operation controlled BA0,BA1(Bank Address) /CAS latency -2/3(programmable,at buffer mode) LVTTL Interface Burst length 1/2/4/8/Full Page(programmable) Burst type- Sequential interleave burst (programmable) Random column access Burst rite Single rite(programmable) Auto precharge bank precharge controlled Auto refresh Self refresh 8192 refresh cycles every 64ms
124pin 125pin
40pin 41pin
Discrete module design conform PC133 specification.
APPLICATION
Main memory graphic memory computer systems
168pin
84pin
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
NAME DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB0 DQMB1
NAME DQMB2 DQMB3 DQ16 DQ17 DQ18 DQ19 DQ20 CKE1 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
NAME DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS DQMB4 DQMB5 /RAS
NAME CKE0 DQMB6 DQMB7 DQ48 DQ49 DQ50 DQ51 DQ52 REGE DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Connection
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
CKE0 /S0,2 DQM0-7 /RAS /CAS
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
RCKE0 R/S0,2 RDQM0-7
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57
REGE
DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
From
RCKE0 R/S0 R/S2
SERIAL
Terminated
D0-17 D0-4,9-13 D5-8,14-17
RDQM RDQM RDQM RDQM RDQM RDQM RDQM RDQM
D0-1 D2-4 D5-6 D7-8 D9-10 D11-13 D14-15 D16-17
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
FUNCTION
Input Master Clock:All other inputs referenced rising edge Clock Enable:CKE controls internal clock.When low,internal clock following cycle ceased. also used select auto self refresh. After self refresh mode started, becomes asynchronous input.Self refresh maintained long low. Chip Select: When high,any command means Operation. Combination /RAS,/CAS,/W defines basic commands. A0-12 specify Row/Column Address conjunction with BA.The Address specified A0-12.The Column Address specified A0-9,11.A10 also used indicate precharge option.When high read write command, auto precharge performed. When high precharge command, both banks precharged. Bank Address:BA0,1 specifies four bank which command applied.BA must with ,PRE ,READ ,WRITE commands
CKE0
Input
/S0,2 /RAS,/CAS,/W
Input Input
A0-12
Input
BA0-1 DQ0-63 CB0-7 DQM0-7 Vdd,Vss
Input
Data Data referenced rising edge Input/Output Mask/Output Disable:When DQMB high burst write.Din current cycle masked.When DQMB high Input burst read,Dout disabled next cycle. Power Supply memory mounted Power Supply module. Input Register enable:When REGE low,All control ignals address buffered. (Buffer mode) When REGE high,All control address latched. (Latch mode)
REGE
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
BASIC FUNCTIONS
MH64S72VJG provides basic read write, bank(row)precharge,and auto self refresh. Each command defined control signals /RAS,/CAS rising edge. addition signals,/S,CKE used chip select,refresh option,and precharge option,respectively. know detailed definition commands please command truth table.
/RAS /CAS
Chip Select L=select, H=deselect Command Command Command resh Option @ref resh command Precharge Option @precharge read/write command basic commands
Activate(ACT) [/RAS /CAS command activates idle bank indicated Read(READ) [/RAS =H,/CAS READ command starts burst read from active bank indicated BA.First output data appears after /CAS latency. When this command,the bank deactivated after burst read(auto-precharge,READA). Write(WRITE) [/RAS /CAS WRITE command starts burst write active bank indicated Total data length written burst length. When this command, bank deactivated after burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS /CAS =H,/WE command deactivates active bank indicated This command also term inates burst read write operation. When this command, both banks deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =CKE REFA command starts auto-refresh cycle. Refresh address including bank address generated internally. After this command, banks precharged automatically.
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
COMMAND TRUTH TABLE
COMMAND Deselect Operation Adress Entry Bank Activate Single Bank Precharge Precharge Bank Column Address Entry Write Column Address Entry Write with AutoPrecharge Column Address Entry Read Column Address Entry Read with Auto Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register MNEMONIC DESEL PREA WRITE /RAS /CAS BA0,1 A0-9
WRITEA
READ
READA REFA REFS REFSX TERM
=High Level, Level, Valid, Don't Care, cycle number NOTE: 1.A11-12= A0-9 Mode Address
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE
Current State IDLE READ /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 Address Command DESEL TBST PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA DESEL TBST ILLEGAL*2 Bank Active,Latch NOP*4 Auto-Refresh*5 Mode Register Set*5 Begin Read,Latch Determine Auto-Precharge Begin Write,Latch Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) Terminate Burst Terminate Burst,Latch READ/READA Begin Read,Determine Auto-Precharge*3 Terminate Burst,Latch BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 BA,RA BA,A10 Op-Code, Mode-Add PRE/PREA REFA Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL Action
READ/WRITE ILLEGAL*2
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE(continued)
Current State WRITE /RAS /CAS Address BA,CA,A10 Action DESEL NOP(Continue Burst END) NOP(Continue Burst END) TBST Terminate Burst Terminate Burst,Latch READ/READA Begin Read,Determine AutoPrecharge*3 READ with PRECHARGE WRITE with PRECHARGE BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add WRITE/ WRITEA PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA Terminate Burst,Latch Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL Command
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE(continued)
Current State CHARGING ACTIVATING WRITE RECOVERING /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add Address Command DESEL TBST PRE/PREA REFA DESEL TBST PRE/PREA REFA DESEL TBST PRE/PREA REFA Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING MODE REGISTER SETTING /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add Address Command DESEL TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ/WRITE ILLEGAL PRE/PREA REFA DESEL TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ/WRITE ILLEGAL PRE/PREA REFA ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: Hige Level, Level, Don't Care Bank Address, Address, Column Address, Operation NOTES: entries assume that High during preceding clock cycle current clock cycle. ILLEGAL bank specified state; function legal bank indicated depending state that bank. Must satisfy contention, turn around, write recovery requirements bank precharging idle state.May precharge bank indicated ILLEGAL bank idle. ILLEGAL Device operation date-integrity guaranteed.
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE
Current State SELF REFRESH*1 POWER DOWN BANKS IDLE*2 STATE other than listed above /RAS /CAS INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down Idle NOP(Maintain Self-Refresh) Refer Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer Current State Power Down Refer Function Truth Table Begin Suspend Next Cycle*3 Exit Suspend Next Cycle*3 Maintain Suspend Action
ABBREVIATIONS: High Level, Level, Don't Care NOTES: High transition will re-enable other inputs asynchronously. minimum setup time must satisfied before command other than EXIT. Power-Down Self-Refresh entered only from banks idle State. Must legal command.
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
POWER SEQUENCE
Before tarting normal operation, following power sequence necessary prevent SDRAM from damaged malfunctioning. Apply power start clock. Attempt maintain high, DQMB0-7 high condition inputs. Maintain stable power, stable clock, input conditions minimum 100us. Issue precharge commands banks. (PRE PREA) After banks become idle state (after tRP), issue more auto-refresh commands. Issue mode register command initialize mode register. After these sequence, SDRAM idle state ready normal operation.
MODE REGISTER
Burs Length, Burst Type /CAS Latency programmed setting mode register(MRS). mode register stores these date until next command, which issue when both banks idle state. After tRSC from command, SDRAM ready command.
/RAS /CAS LTMODE BA0,1 A12-0 SEQUENTIAL INTERLEAVED
LATENCY MODE*1
/CAS LATENCY BURST SINGLE BURST LENGTH
BURST TYPE
WRITE MODE
R:Reserved Future Full Page
*1:This alue components mode, case latch mode(REGE="H"), latency should added
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Command Address /CAS Latency
Read Write
Burst Length
Burst Type
Burst Length
Initial Address Sequential
Column Addressing Interleaved
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
ABSOLUTE AXIMUM RATINGS
Symbol Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25°C Condition with respect with respect with respect Ratings -0.5 -0.5 -0.5 Unit
RECOM ENDED OPERATING CONDITION
(Ta=0 70°C, unless otherwise noted) Limits Symbol VIH*1 VIL*2 Parameter Supply Voltage Supply Voltage High-Level Input Voltage inputs Low-Level Input Voltage inputs Min. -0.3 Typ. Max. Vdd+0.3 Unit
CAPACITANCE
(Ta=0 70°C, 0.3V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address Input Capacitance, control Input Capacitance, Input Capacitance, 1MHz, 1.4V bias 200mV swing Test Condition Limits(max.) Unit
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
AVERAGE SUPPLY CURRENT from
(Ta=0 ~70°C, 0.3V, unless otherwise noted)
Limits (max)
operating current bank activ (discrete)
Parameter
Symbol
Test Condition tRC=min.tCLK=min, BL=1
Unit Note
1935 2295 3555
Icc1 Icc2P
2295 2295 3555
precharge stanby current power-down mode precharge stanby current power-down mode active stanby current power-down mode
bank activ (discrete)
CKE<VILmax,tCLK=min CKE<VILmax,tCLK=infinity Icc2PS Icc2N CKE>VIHmin,tCLK=min Icc2NS CKE>VIHmin,tCLK=infinity Icc3N Icc3NS Icc4 Icc5 Icc6 CKE>VIHmin,tCLK=min CKE>VIHmin,tCLK=infinity
tCLK=min, BL=4, gapless data
burst current auto-refresh current self-refresh current
tRC=min, tCLK=min <VILmax
Notes addresses changed times during only 1bank activ other banks idle banks idle input signals changed time during 3xtCLK input signals stable banks activ
OPERATING CONDITIONS CHARACTERISTICS
(Ta=0 70°C, 0.3V, unless otherwise noted)
Limits Unit Min. Max. VOH(DC) High-Level Output Voltage(DC) IOH=-2mA VOL(DC) Low-Level Output Voltage(DC) IOL=2mA Off-stare Output Current floating VO=0 Input Current VIH=0 Vdd+0.3V Symbol Parameter Test Condition
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
REQUIREMENTS (Components)
(Ta=0 70°C, 0.3V, unless otherwise noted) Input Pulse Levels: 0.8V 2.0V Input Timing Measurement Level: 1.4V LATCH MODE Limits Symbol Parameter tCLK tRFC tRCD tRAS tRRD tRSC tREF cycle High pulse width pulse width Transition time Input Setup time(all inputs Input Hold time(all inputs) Cycle time Refresh Cycle time Column Delay Active time Precharge Write Recovery time Deley time Mode Register Cycle time Refresh Interval time CL=3 CL=4 Min.
67.5
Max. Min.
67.5
Max.
Unit
120K
120K
1.4V
Signal
1.4V
referenced input signal crossing through 1.4V.
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
BUFFER MODE
Limits Symbol Parameter tCLK tRFC tRCD tRAS tRRD tRSC tREF cycle High pulse width pulse width Transition time Input Setup time(all inputs Input Hold time(all inputs) Cycle time Refresh Cycle time Column Delay Active time Precharge Write Recovery time Deley time Mode Register Cycle time Refresh Interval time CL=2 CL=3 Min.
67.5
Max. Min.
67.5
Max.
Unit
120K
120K
SWITCHING CHARACTERISTICS
(Ta=0 70°C, 0.3V, unless otherwise noted) LATCH MODE Limits Symbol Parameter Access time from Output Hold from Delay time, output impedance from Delay time, output high impedance from CL=3 CL=4 CL=3 CL=4 CL=3 CL=4 tOLZ tOHZ Min. Max. Min. Max. Unit
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
BUFFER MODE
Limits Symbol Parameter Access time from Output Hold from Delay time, output impedance from Delay time, output high impedance from CL=2 CL=3 CL=2 CL=3 CL=2 CL=3 tOLZ tOHZ Min. Max. Min. Max. Unit
Output Load Condition
1.4V
Ext.CL=50pF Output Timing Measurement erence Point
1.4V
1.4V
tOLZ
tOHZ
1.4V
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst WRITE (single bank) BL=4,Buffer mode(REGE="L")
tRAS
/RAS
tRCD tRCD
/CAS
A0-9
BA0,1 REGE
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.200119
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst WRITE (multi bank) BL=4,Buffer mode(REGE="L")
tRRD tRRD
tRAS
tRCD
/RAS
tRCD
/CAS
A0-9
BA0,1 REGE
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst WRITE (single bank) BL=4,Lacth mode(REGE="H")
tRAS
/RAS
tRCD tRCD
/CAS
A0-9 BA0,1
REGE
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst WRITE (multi bank) BL=4,Latch mode(REGE="H")
tRRD tRRD
tRAS
tRCD
/RAS
tRCD
/CAS
A0-9 BA0,1 REGE
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst READ (single bank) BL=4,CL=3,Buffer mode(REGE="L")
tRAS
/RAS
tRCD tRCD
/CAS
read latency
A0-9
BA0,1 REGE
CL=3
ACT#0 READ#0
PRE#0
ACT#0
READ#0
READ allows full data
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst READ (multi bank) BL=4,CL=3,Buffer mode(REGE="L")
tRRD tRAS tRCD tRRD
/RAS
tRCD
/CAS
read latency
A0-9 BA0,1
REGE
CL=3 CL=3
ACT#0 READ#0 ACT#1
PRE#0 READ#1
ACT#0 READ#0 PRE#1 ACT#2
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst READ (single bank) BL=4, CL=4,Latch mode(REGE="H")
tRAS
/RAS
tRCD tRCD
/CAS
read latency
A0-9
BA0,1 REGE
CL=4
ACT#0 READ#0
PRE#0
ACT#0
READ#0
READ allows full data
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst READ (multi bank) BL=4,CL=4,Latch mode(REGE="H")
tRRD tRAS tRRD
/RAS
tRCD tRCD
/CAS
read latency
A0-9
BA0,1
REGE
CL=4 CL=4
ACT#0 READ#0 ACT#1
PRE#0 READ#1
ACT#0 READ#0 PRE#1 ACT#2
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.200126
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4,Buffer mode(REGE="L")
tRRD tRRD
/RAS
tRCD tRCD BL-1+ BL-1+ tRCD
/CAS A0-9
BA0,1
REGE
ACT#0 ACT#1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4,Latch mode(REGE="H")
tRRD tRRD
/RAS
tRCD tRCD BL-1+ BL-1+ tRCD
/CAS
A0-9 BA0,1
REGE
ACT#0 ACT#1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst READ (multi bank) with AUTO-PRECHARGE BL=4,CL=3 Buffer mode(REGE="L")
tRRD tRRD
/RAS
tRCD tRCD BL+tRP BL+tRP tRCD
/CAS
read latency
A0-9
BA0,1
REGE
CL=3 CL=3
CL=3
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Burst READ (multi bank) with AUTO-PRECHARGE BL=4,CL=4 Latch mode(REGE="H")
tRRD tRRD
/RAS
tRCD tRCD BL+tRP BL+tRP tRCD
/CAS
read latency
A0-9
BA0,1 REGE
CL=4
CL=4
CL=4
ACT#0 ACT#1 READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Page Mode Burst Write (multi bank)
BL=4,Buffer mode(REGE="L")
tRRD
/RAS
tRCD
/CAS
A0-9
BA0,1 REGE
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Page Mode Burst Write (multi bank) BL=4,Latch mode(REGE="H")
tRRD
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Page Mode Burst Read (multi bank) BL=4,CL=3 Buffer mode(REGE="L")
tRRD
/RAS
tRCD
/CAS
read latency=2
A0-9
BA0,1 REGE
CL=3
CL=3
CL=3
ACT#0 READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Page Mode Burst Read (multi bank) BL=4,CL=4 Latch mode(REGE="H")
tRRD
/RAS
tRCD
/CAS
read latency=3
A0-9
BA0,1 REGE
CL=4
CL=4
CL=4
ACT#0 READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Write Interrupted Write Read BL=4,Buffer mode(REGE="L")
tRRD
/RAS
tRCD tCCD
/CAS A0-9
BA0,1 REGE
CL=3
ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write interrupted Write Read active bank. Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.200135
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Write Interrupted Write Read BL=4,Latch mode(REGE="H")
tRRD
/RAS
tRCD tCCD
/CAS A0-9
BA0,1 REGE
CL=4
ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write interrupted Write Read active bank. Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Read Interrupted Read Write BL=4,CL=3 Buffer mode(REGE="L")
tRRD
/RAS
tRCD
/CAS
read latency=2
A0-9
BA0,1 REGE
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank prevent contention
Burst Read interrupted Read Write active bank. Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Read Interrupted Read Write BL=4,CL=4 Latch mode(REGE="H")
tRRD
/RAS
tRCD
/CAS
read latency=3
A0-9
BA0,1 REGE
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 blank prevent contention ACT#1 READ#1
Burst Read interrupted Read Write active bank. Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Write Interrupted Precharge BL=4,Buffer mode(REGE="L")
tRRD
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write interrupted Precharge other bank.
Burst Write interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Write Interrupted Precharge BL=4,Latch mode(REGE="H")
tRRD
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write interrupted Precharge other bank.
Burst Write interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Read Interrupted Precharge BL=4,CL=3 Buffer mode(REGE="L")
tRRD
/RAS
tRCD tRCD
/CAS
read latency=2
A0-9
BA0,1 REGE
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read interrupted Precharge other bank.
Burst Read interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Read Interrupted Precharge BL=4,CL=4 Latch mode(REGE="H")
tRRD
/RAS
tRCD tRCD
/CAS
read latency=3
A0-9
BA0,1 REGE
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read interrupted Precharge other bank.
Burst Read interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Mode Register Setting
tRSC
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
Auto-Ref (last cycles)
Mode ACT#0 WRITE#0 Register Setting Italic parameter indicates minimum case
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Auto-Refresh @BL=4
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
Auto-Refresh Before Auto-Refresh, banks must idle state.
ACT#0
WRITE#0
After from Auto-Refresh, banks idle state. Italic parameter indicates minimum case
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Self-Refresh
stopped tRC+1
/RAS /CAS
tSRX
must maintain Self-Refresh
A0-9
BA0,1 REGE
Self-Refresh Entry Before Self-Refresh Entry, banks must idle state.
Self-Refresh Exit
ACT#0
After from Self-Refresh Exit, banks idle state. Italic parameter indicates minimum case
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Write Mask
BL=4,Buffer mode(REGE="L")
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
masked
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Write Mask
BL=4,Latch mode(REGE="H")
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
masked
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Read Mask
BL=4, CL=3 Buffer mode(REGE="L")
/RAS
tRCD
/CAS
read latency=2
A0-9
BA0,1 REGE
masked
masked
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Read Mask
BL=4,CL=4 Latch mode(REGE="H")
/RAS
tRCD
/CAS A0-9
read latency=3
BA0,1 REGE
masked
masked
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Power Down
/RAS /CAS A0-9
Standby Power Down latency=1 Active Power Down
BA0,1 REGE
Precharge
ACT#0
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Suspend
BL=4,CL=3 Buffer mode(REGE="L")
/RAS
tRCD
/CAS
latency=1 latency=1
A0-9
BA0,1 REGE
ACT#0
WRITE#0 READ#0 suspended
suspended
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Suspend
BL=4,CL=4 Latch mode(REGE="H")
/RAS
tRCD
/CAS
latency=2 latency=2
A0-9
BA0,1 REGE
ACT#0
WRITE#0
READ#0 suspended
suspended
Italic parameter indicates minimum case MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Serial Presence Detect Table
Byte Function described Serial Bytes Written during Production Total Bytes device Fundamental memory type Addresses this assembly Column Addresses this assembly Module Banks this assembly Data Width this assembly. Data Width continuation Voltage interface standard this assembly
SDRAM Cycletime Max. Supported Latency (CL).
enrty data Bytes SDRAM A0-A12 A0-A9,11 1BANK LVTTL 7.5ns 7.5ns 5.4ns 5.4ns
DATA(hex)
Cycle time CL=3 SDRAM Access from Clock CL=3 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
self refresh(7.8uS) 1/2/4/8/Full 4bank
buffered,registered with
Precharge All,Auto precharge Write1/Read Burst
Minimum Clock Delay,Back Back Random Column Addresses
Burst Lengths Supported Banks Each SDRAM device CAS# Latency Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes:General SDRAM Cycle time(2nd highest latency) Cycle time CL=2
7.5ns 10ns 5.4ns
SDRAM Access form Clock(2nd highest latency)
CL=2 SDRAM Cycle time(3rd highest latency)
SDRAM Access form Clock(3rd highest latency)
Precharge Active Minimum
15ns 20ns 15ns 15ns 15ns 20ns 45ns 45ns
Active Active Min.
Delay
Active Precharge
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Serial Presence Detect Table
36-61 Checksum bytes 0-62 64-71 Manufactures Jedec code JEP-108E Manufacturing location Density each bank module Command Address signal input setup time Command Address signal input hold time Data signal input setup time Data signal input hold time Superset Information (may used future) Revision MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany 73-90 91-92 93-94 95-98 99-125 128+ Manufactures Part Number Revision Code Manufacturing date Assembly Serial Number Manufacture Specific Data Intetl specification frequency Intel specification CAS# Latency support Unused storage locations MH64S72VJG-5 MH64S72VJG-6 revision year/week code serial number option CL=2/3,AP,CK0 open 512MByte 1.5ns 0.8ns 1.5ns 0.8ns option JEDEC2 1CFFFFFFFFFFFFFF
rrrr yyww ssssssss
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC EEPROM Components A.C. D.C. Characteristics
Symbol Parameter Supply Voltage Supply Voltage Input High Voltage Input Voltage Output Voltage Min. Vddx0.7 -0.3 Limits Typ. Max. Vccx0.3 Units
EEPROM A.C.Timing Parameters (Ta=0 70°C
Symbol fSCL TBUF Parameter Clock Frequency Noise Supression Time Constant SCL, inputs Data Valid
Time Must Free before ransmission Start
Limits Min. Max.
Units
THD:STA Start Condition Hold Time TLOW THIGH TSU:STA Clock Time Clock High Time Start Condition Setup Time
THD:DAT Data Hold Time TSU:DAT TSU:STO Data Setup Time Rise Time Fall Time Stop Condition Setup Time Data Hold Time Write Cycle Time
time from valid stop condition write sequence EEPROM internal erase/program cycle.
HIGH
SU:STO SU:STA HD:STA HD:DAT SU:DAT
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
133.35
8.89 11.43
6.35 36.83 24.495 42.18
6.35 54.61 127.35
1.27
43.18
3.9Max
1.27
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001
MH64S72VJG-5,-6
4,831,838,208-BIT 67,108,864-WORD 72-BIT Synchronous DYNAMIC
Keep safety first your circuit designs!
Mitsubishi Electric Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap.
Notes regarding these materials
1.These materials intended reference assist customers selection Mitsubishi semiconductor product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Mitsubishi Electric Corporation third party. 2.Mitsubishi Electric Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts, programs, algorithms, circuit application examples contained these materials. 3.All information contained these materials, including product data, diagrams, charts, programs algorithms represents information products time publication these materials, subject change Mitsubishi Electric Corporation without notice product improvements other reasons. therefore recommended that customers contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor latest product information before purchasing product listed herein. information described here contain technical inaccuracies typographical errors. Mitsubishi Electric Corporation assumes responsibility damage, liability, other loss rising from these inaccuracies errors. Please also attention information published Mitsubishi Electric Corporation various means, including Mitsubishi Semiconductor home page 4.When using information contained these materials, including product data, diagrams, charts, programs algorithms, please sure evaluate information total system before making final decision applicability information products. Mitsubishi Electric Corporation assumes responsibility damage, liability other loss resulting from information contained herein. 5.Mitsubishi Electric Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. 6.The prior written approval Mitsubishi Electric Corporation necessary reprint reproduce whole part these materials. 7.If these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. 8.Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor further details these materials products contained therein.
MIT-DS-0385-1.2
MITSUBISHI ELECTRIC
20.Sep.2001

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