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Kbit Parallel EEPROM With Software Data Protection Fast Access Ti


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M28C64
Kbit Parallel EEPROM With Software Data Protection
Fast Access Time: VCC=5 M28C64 M28C64-A VCC=3 M28C64-xxW
Single Supply Voltage: M28C64 M28C64-A M28C64-xxW
Power Consumption Fast BYTE PAGE WRITE Bytes) VCC=4.5 M28C64-A VCC=4.5 M28C64 VCC=2.7 M28C64-xxW
PDIP28 (BS)
PLCC32 (KA)
Enhanced Write Detection Monitoring: Ready/Busy Open Drain Output Data Polling Toggle Page Load Timer Statu1
JEDEC Approved Bytewide Pin-Out Software Data Protection 100000 Erase/Write Cycles (minimum) Data Retention (minimum): Years M28C64 M28C64-xxW Years M28C64-A
SO28 (MS) width
TSOP28 (NS) 13.4
Figure Logic Diagram
Table Signal Name13
A0-A12 DQ0-DQ7 Address Input Data Input Output Write Enable Chip Enable Output Enable Ready Busy Supply Voltage
DQ0-DQ7
A0-A12
M28C64
Ground
AI01350C
March 1999
1/21
M28C64
Figure ConnectionRB M28C64
AI01351C
Figure ConnectionVCC M28C64
AI01353C
Note: Connected
Note: Connected
Figure PLLC ConnectionRB
Figure TSOP ConnectionG
M28C64
M28C64
AI01354C
AI01352D
Note: Connected
Note: Connected
DESCRIPTION M28C64 devices consist 8192x8 bits power, parallel EEPROM, fabricated with STMicroelectronics' proprietary single polysilicon CMOS technology. devices offer fast access time, with power dissipation, require single voltage supply depending option chosen). device been designed offer flexible microcontroller interface, featuring both hardware
software handshaking, with Ready/Busy, Data Polling Toggle Bit. device supports byte Page Write operation. Software Data Protection (SDP) also supported, using standard JEDEC algorithm.
2/21
M28C64
Table Absolute Maximum Ratings
Symbol VESD Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Input Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model) Value -0.3 VCC+1 -0.6 VCC+0.6 -0.3 4000 Unit
Note: Except rating "Operating Temperature Range", stresses above those listed Table "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, operation device these other conditions above those indicated Operating sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also SURE Program other relevant quality documents. MIL-STD-883C, 3015.7 (100 1500
Figure Block Diagram
RESET
CONTROL LOGIC
DECODE
A6-A12 (Page Address)
ADDRESS LATCH
ARRAY
A0-A5
ADDRESS LATCH
DECODE
SENSE DATA LATCH
BUFFERS
PAGE LOAD TIMER STATUS TOGGLE DATA POLLING
AI01355
DQ0-DQ7
3/21
M28C64
Table Operating Modes
Mode Stand-by Output Disable Write Disable Read Write Chip Erase DQ0-DQ7 Hi-Z Hi-Z Hi-Z Data Data Hi-Z
Note: 0=VIL; 1=VIH; VIL; V=12V
SIGNAL DESCRIPTION external connections device summarized Table their Table Addresses (A0-A12). address inputs used select byte from memory array during read write operation. Data In/Out (DQ0-DQ7). contents data byte written read from, memory array through Data pins. Chip Enable (E). chip enable input must held enable read write operations. When Chip Enable high, power consumption reduced. Output Enable (G). Output Enable input controls data output buffers, used initiate read operations. Write Enable (W). Write Enable input controls whether addressed location read, from written
Ready/Busy (RB). Ready/Busy open drain output that used detect internal write cycle. DEVICE OPERATION order prevent data corruption inadvertent write operations, internal comparator inhibits Write operations voltage lower than (see Table Table 4B). Once voltage applied goes over threshold (VCC>VWI), write access memory allowed after time-out tPUW, specified Table Table Further protection against data corruption offered pass filters: glitch, inputs, with pulse width less than (typical) internally filtered prevent inadvertent write operations memory.
Table Power-Up Timing1 M28C64 range)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Min. Max. Unit
Note: Sampled only, 100% tested.
Table Power-Up Timing1 M28C64-xxW range)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Min. Max. Unit
Note: Sampled only, 100% tested.
4/21
M28C64
Read device accessed like static RAM. When low, high, contents addressed location presented pins. Otherwise, when either high, pins revert their high impedance state. Write Write operations initiated when both high. device supports both W-controlled E-controlled write cycles shown Figure Figure 12). address latched during falling edge (which ever occurs later) data latched rising edge (which ever occurs first). After delay, tWLQ5H, that cannot shorter than value specified Table Table 10B, internal write cycle starts. continues, under internal timing control, until write operation complete. commencement this period detected reading Page Load Timer Status DQ5. cycle detected reading status Data Polling Toggle functions DQ6. Page Write Page Write mode allows bytes written single page single This achieved through series successive Write operations, which separated more than WLQ5H value specified Table Table 10B). page write initiated during byte write operation. Following first byte write instruction host send another address data with minimum data transfer rate 1/tWLQ5H. internal write cycle start instant after tWLQ5H. Once initiated, write operation internally timed, continues, uninterrupted, until completion. bytes must located same page address (A12-A6 must same bytes). Otherwise, Page Write operation executed. with single byte Write operation, described above, DQ5, lines used detect beginning internally controlled phase Page Write cycle. Software Data Protection (SDP) device offers software-controlled write-protection mechanism that allows user inhibit write operations device. This useful protecting memory from inadvertent write cycles that occur during periods instability (uncontrolled conditions when excessive noise detected, when power supply levels outside their specified values). default, device shipped "unprotected" state: memory contents freely changed user. Once Software Data Protection Mode enabled, write commands
Figure Software Data Protection Enable Algorithm Memory Write
Write Address 1555h Page Write Timing (see note Page Write Timing (see note Write Address 1555h
Write Address 0AAAh
Write Address 0AAAh
Write Address 1555h
Write Address 1555h Write enabled Physical Page Write Instruction Page Write bytes)
Enable Algorithm
Write Memory When
AI01356C
Note: most significant address bits (A12 differ during these specific Page Write operations.
5/21
M28C64
Figure Software Data Protection Disable Algorithm
Write Address 1555h
Write Address 0AAAh
Page Write Timing
Write Address 1555h
Write Address 1555h
Write Address 0AAAh
Write Address 1555h
Unprotected State
AI01357B
ignored, have effect memory contents. device remains this mode until valid Software Data Protection disable sequence received. device reverts "unprotected" state. status Software Data Protection (enabled disabled) represented non-volatile latch, remembered across periods power being off. Software Data Protection Enable command consists writing three specific data bytes three specific memory locations (each location being different page), shown Figure Similarly disable Software Data Protection, user write specific data bytes into different locations, shown Figure This complex series operations protects against chance inadvertent enabling disabling Software Data Protection mechanism. When enabled, memory array still have data written sequence more complex (and hence better protected from inadvertent use). sequence shown Figure This consists unlock key, enable write action, which continues enabled. This allows enabled, data written, within single Write cycle WC).
Software Chip Erase Using this function, available M28C64 M28C64-A M28C64-xxW, contents entire memory erased (set FFh) holding Chip Enable low, holding Output Enable CC+7.0V. chip cleared when pulse applied Write Enable signal (see Figure Table details). Status Bits devices provide three status bits (DQ7, DQ5), output (RB), during write operations. These allow application write time latency device getting with other work. These signals available
Figure Status Assignment
PLTS
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PLTS Hi-Z
Data Polling Toggle Page Load Timer Status High impedance
AI02815
6/21
M28C64
Figure Chip Erase Waveforms (M28C64 M28C64-xxW)
tWHEH
tGLWH tELWL tWLWH2 tWHRH
AI01484B
Table Chip Erase Characteristics1 M28C64 M28C64-xxW
Symbol tELWL tWHEH tWLWH2 tGLWH tWHRH Parameter Chip Enable Write Enable Write Enable High Chip Enable High Write Enable Write Enable High Output Enable Write Enable High Write Enable High Write Enable Test Condition Min. Max. Unit
Note: Sampled only, 100% tested.
port bits DQ7, (but only during programming cycle, once byte more been latched into memory) continuously output pin. Data Polling (DQ7). internally timed write cycle starts after tWLQ5H (defined Table Table 10B) elapsed since previous byte latched memory. value this last byte, used signal throughout this write operation: inverted while internal write operation underway, inverted back original value once operation complete. Toggle (DQ6). device offers another determining when internal write cycle completed. During internal Erase/Write cycle, toggles from (the first read value being '0') subsequent attempts read byte memory. When internal write cycle complete, toggling stopped, values read DQ7-DQ0 those addressed memory byte. This indicates that
device again available Read Write operations. Page Load Timer Status (DQ5). internal timer used measure period between successive Write operations, tWLQ5H (defined Table Table 10B). line held show when this timer running (hence showing that device received write operation, waiting next). line held high when counter overflowed (hence showing that device starting internal write memory array). Ready/Busy pin. open drain output that held during erase/write cycle, that released (allowed float) completion programming cycle.
7/21
M28C64
Table Read Mode Characteristics M28C64 M28C64-A range)
Symbol ICC1 ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (TTL inputs) Supply Current (CMOS inputs) Supply Current (Stand-by) Supply Current (Stand-by) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage -400 Test Condi tion VOUT VIL, VIL, 0.3V -0.3 Min. Max. Unit
Note: inputs outputs open circuit.
Table Read Mode Characteristics M28C64-xxW range)
Symbol ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS inputs) VIL, MHz, 3.6V Supply Current (Stand-by) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage -400 0.3V -0.3 Test Condi tion VOUT VIL, MHz, 3.3V Min. Max. Unit
Note: inputs outputs open circuit.
8/21
M28C64
Table Input Output Parameters1 MHz)
Symbol Parameter Input Capacitance Output Capacitance Test Condition VOUT Min. Max. Unit
Note: Sampled only, 100% tested.
Table Measurement ConditionInput Rise Fall Times Input Pulse Voltages (M28C64, M28C64-A) Input Pulse Voltages (M28C64-xxW) Input Output Timing Reference Voltages (M28C64, M28C64-A) Input Output Timing Reference Voltages (M28C64-xxW) VCC-0.3V
Figure Testing Input Output Waveform4.5V 5.5V Operating Voltage 2.4V 2.0V 0.8V
Figure Testing Equivalent Load Circuit
0.4V
DEVICE UNDER TEST 100pF
2.7V 3.6V Operating Voltage 0.3V
AI02101B
includes capacitance
AI02102B
Table Read Mode Characteristics M28C64 M28C64-A range)
Symbol Alt. Parameter Test Condi VIL, VIL, M28C64 Unit
tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX
tACC
Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition
Note: Output Hi-Z defined point which data longer driven.
9/21
M28C64
Table Read Mode Characteristics M28C64-xxW range)
Symbol Alt. Parameter Test Condit =VIL, =VIL, M28C64-xxW Unit
tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX
tACC
Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition
Note: Output Hi-Z defined point which data longer driven.
Figure Read Mode Waveforms (with Write Enable, high)
A0-A12 tAVQV tGLQV tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA Hi-Z
AI00749B
Note: Write Enable
10/21
M28C64
Table 10A. Write Mode Characteristics M28C64 M28C64-A range)
M28C64 Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H Alt. tCES tOES tOES tWES tCEH tOEH tOEH tWEH tWPH tBLC Parameter Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Write Enable Input Valid Chip Enable Input Valid Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Time-out after last byte write (M28C64) Time-out after last byte write (M28C64-A) Write Cycle Time (M28C64) Write Cycle Time (M28C64-A) Write Enable High Ready/Busy Chip Enable High Ready/Busy Data Valid before Write Enable High Data Valid before Chip Enable High Note Note VIL, VIH, 1000 Test Condit VIL, VIH, Unit
tQ5HQ5X tWHRL tEHRL tDVWH tDVEH
Note: With pull-up resistor.
11/21
M28C64
Table 10B. Write Mode Characteristics M28C64-xxW range)
M28C64-xxW Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tQ5HQ5X tWHRL tEHRL tDVWH tDVEH Alt. tCES tOES tOES tWES tCEH tOEH tOEH tWEH tWPH tBLC Parameter Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Write Enable Input Valid Chip Enable Input Valid Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Time-out after last byte write Write Cycle Time Write Enable High Ready/Busy Chip Enable High Ready/Busy Data Valid before Write Enable High Data Valid before Chip Enable High Note Note VIL, VIH, 1000 Test Condit VIL, VIH, 1000 Unit
Note: With pull-up resistor.
12/21
M28C64
Figure Write Mode Waveforms (Write Enable, controlled)
A0-A12 tAVWL tELWL tGHWL tWLDV DQ0-DQ7 DATA tDVWH tWHRL
AI01126
VALID tWLAX
tWHEH
tWLWH
tWHGL
tWHWL
tWHDX
Figure Write Mode Waveforms (Chip Enable, controlled)
A0-A12 tAVEL tGHEL tWLEL tELDV DQ0-DQ7 DATA tDVEH tEHRL
AI00751
VALID tELAX
tELEH
tEHGL
tEHWH
tEHDX
13/21
M28C64
Figure Page Write Mode Waveforms (Write Enable, controlled)
A0-A12 Addr Addr Addr Addr
tWHWL tWLWH DQ0-DQ7 (in) Byte Byte Byte Byte
(out) tWHRL
AI00752D
tWLQ5H tQ5HQ5X
Figure Software Protected Write Cycle WaveformG
tWLWH tAVEL A0-A5 tWHDX A6-A12 1555h 0AAAh 1555h Page Address tWLAX Byte Address tWHWL
tDVWH DQ0-DQ7 Byte Byte Byte
AI01358B
Note: must specify same page address during each high-to-low transition must high only when both low.
14/21
M28C64
Figure Data Polling Sequence WaveformA0-A12 Address last byte Page Write instruction
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI00753C
Figure Toggle Sequence WaveformA0-A12
LAST WRITE
TOGGLE INTERNAL WRITE SEQUENCE
READY
AI00754D
Note: Toggle first `0'.
15/21
M28C64
Table Ordering Information Scheme
Example: M28C64
Write Time blank 4.5V 5.5V; 2.7V 3.6V 4.5V 5.5V
Option Tape Reel Packing
Speed
Temperature Range
Package PDIP28 PLCC32 SO28 (300 width) TSOP28 13.4
Operating Voltage blank
Note:
Available only with speed (-12), operating range (-blank), temperature range (-6). Available M28C64 only. Available range (-xxW) only. available write time option (-A).
ORDERING INFORMATION Devices shipped from factory with memory content `1's (FFh). notation used device number shown Table list available options (speed, package, etc.) further information aspect this device, please contact Sales Office nearest you.
16/21
M28C64
Table PDIP28 Plastic DIP, mils width
Symb. Typ. 2.54 Min. 3.94 0.38 3.56 0.38 1.14 0.20 34.70 14.80 12.50 15.20 3.05 1.02 Max. 5.08 1.78 4.06 0.56 1.78 0.30 37.34 16.26 13.97 17.78 3.82 2.29 0.100 Typ. Min. 0.155 0.015 0.140 0.015 0.045 0.008 1.366 0.583 0.492 0.598 0.120 0.040 Max. 0.200 0.070 0.160 0.021 0.070 0.012 1.470 0.640 0.550 0.700 0.150 0.090 inche
Figure PDIP28 (BS)
PDIP
Note: Drawing scale.
17/21
M28C64
Table PLCC32 lead Plastic Leaded Chip Carrier, rectangular
Symbol 0.89 1.27 Typ. Min. 2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 0.00 0.10 Max. 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 0.25 0.035 0.050 Typ. inches Min. 0.100 0.060 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 0.000 0.004 Max. 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 0.010
Figure PLCC (KA)
0.51 (.020)
D2/E2
1.14 (.045)
PLCC
Note: Drawing scale.
18/21
M28C64
Table SO28 lead Plastic Small Outline, mils body width
Symb. Typ. 1.27 Min. 2.46 0.13 2.29 0.35 0.23 17.81 7.42 10.16 0.61 0.10 Max. 2.64 0.29 2.39 0.48 0.32 18.06 7.59 10.41 1.02 0.050 Typ. Min. 0.097 0.005 0.090 0.014 0.009 0.701 0.292 0.400 0.024 0.004 Max. 0.104 0.011 0.094 0.019 0.013 0.711 0.299 0.410 0.040 inche
Figure SO28 wide (MS)
SO-b
Note: Drawing scale.
19/21
M28C64
Table TSOP28 lead Plastic Thin Small Outline, 13.4
Symb. Typ. 0.55 0.95 0.17 0.10 13.20 11.70 7.90 0.50 0.10 Min. Max. 1.25 0.20 1.15 0.27 0.21 13.60 11.90 8.10 0.70 0.022 0.037 0.007 0.004 0.520 0.461 0.311 0.020 0.004 Typ. Min. Max. 0.049 0.008 0.045 0.011 0.008 0.535 0.469 0.319 0.028 inche
Figure TSOP28 (NS)
TSOP-a
Note: Drawing scale.
20/21
M28C64
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express writt approval STMicroelectronics. 1999 STMicroelectronics Rights Reserved logo registered trademark STMicroelectronics. other names property their respective owners. STMicroelectronics GROUP COMPANIES Australia Brazil China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A. http:// www.st.com
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