960JX provides high performance low-cost 32-bit embedded applications.

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960JX provides high performance low-cost 32-bit embedded applications.

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960JX provides high performance low-cost 32-bit embedded applications. 960JX features generous instruction cache, data cache, data RAM. also fast interrupt mechanism, dual programmable timer units, instructions. processor combines important peripherals: timer unit interrupt controller. These other hardware resources programmed through memorymapped control registers. timer unit offers independent 32-bit timers real-time system clocks general-purpose system timing. These operate either single-shot auto-reload mode generate interrupts. interrupt controller unit (ICU) flexible, lowlatency means processing handling interrupts. provides full programmability interrupt sources into priority levels takes advantage cached priority table optional routine caching minimize interrupt latency. ICU, independent from core, compares priorities posted interrupts with current process priority. also supports integrated timer interrupts. When using memory subsystems low-cost embedded applications, substantial wait-state penalties often required. 960JX integrates considerable storage resources on-chip decouple execution from external bus. Both instruction cache data cache included 960JX configured different sizes. details, please refer Figure next page. 32-bit multiplexed burst provides high-speed interface system memory I/O. full complement control signals makes connection 960JX external components easier. user programs physical logical memory attributes through memorymapped control registers (MMRs). Physical logical configuration registers enable processor operate with multiple combinations width byte ordering. processor supports homogeneous byte ordering model. halt mode included support applications where power consumption critical. halt instruction enables shutdown instruction execution, which results power savings 90%. 960JX's testability features, which include ONCE* (on-circuit emulation) mode boundary scan (JTAG), provide powerful environment design debug fault diagnosis.
960JX Embedded 32-Bit RISC Processor
Features
Functionally equivalent Intel 80960JA/JF embedded 32-bit microprocessor High-performance embedded architecture High-speed interrupt controller on-chip timers Two-way associative instruction cache Direct mapped data cache On-chip stack frame cache On-chip data High bandwidth burst Halt mode low-power operation
IEEE 1149.1 (JTAG) boundary-scan compatibility
Samples available system emulation: 132-pin, plastic, bumpered quad flat pack (BQFP)
ONCE trademark Intel Corporation.
Figure shows main blocks 960JX.
Lucent Technologies Inc.
Silicon Suite ISDN Products Services Overview
960JX Embedded 32-Bit RISC Processor (continued)
Description (continued)
CONTROL
CONTROL UNIT CLKIN CLOCKS, POWER MANAGEMENT INSTRUCTION CACHE TWO-WAY ASSOCIATIVE Kbyte, Kbyte, Kbyte) BOUNDARY-SCAN CONTROLLER REQUEST QUEUES 32-bit TIMERS PROGRAMMABLE INTERRUPT CONTROLLER MEMORY-MAPPED REGISTER INTERFACE MULTIPLY UNIT DIVIDE UNIT EXECUTION ADDRESS GENERATION UNIT DEST SRC1 SRC2 MEMORY INTERFACE UNIT 32-bit ADDR 32-bit DATA DEST SRC1 SRC2 DEST DEST SRC1 SRC2 SRC1
PHYSICAL REGION CONFIGURATION
ADDR/ DATA
INSTRUCTION SEQUENCER CONSTANTS CONTROL
PORT
GLOBAL REGISTER
LOCAL REGISTER SETS DEST SRC1 SRC2
Kbyte DATA
DIRECT-MAPPED DATA CACHE (512 byte, Kbyte, Kbyte) THREE INDEPENDENT 32-bit SRC1, SRC2, DEST BUSES
Figure 960JX Embedded 32-Bit RISC Processor Block Diagram
Lucent Technologies Inc.

960JX provides high performance low-cost 32-bit embedded applications.

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