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80C32/87C52 CMOS single-chip 8-bit microcontrollers
Product specification IC20 Data Handbook 1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DESCRIPTION
Philips 80C32/87C52 high-performance microcontroller fabricated with Philips high-density CMOS technology. Philips CMOS technology combines high speed density characteristics HMOS with power attributes CMOS. Philips epitaxial substrate minimizes latch-up sensitivity. 87C52 contains EPROM 80C32 ROMless. Both contain RAM, lines, three 16-bit counter/timers, six-source, two-priority level nested interrupt structure, serial port either multi-processor communications, expansion full duplex UART, on-chip oscillator clock circuits. addition, 80C32/87C52 software selectable modes power reduction-idle mode power-down mode. idle mode freezes while allowing RAM, timers, serial port, interrupt system continue functioning. power-down mode saves contents freezes oscillator, causing other chip functions inoperative. 80C52/80C54/80C58 datasheet device specifications.
CONFIGURATIONS
P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 CERAMIC PLASTIC DUAL IN-LINE PACKAGE P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/V ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
FEATURES
80C51 based architecture 8032 compatible
EPROM (87C52) ROMless (80C32) Three 16-bit counter/timers Full duplex serial channel Boolean processor
WR/P3.6 RD/P3.7 XTAL2 XTAL1
SU00060
Memory addressing capability
Power control modes:
Idle mode Power-down mode
CMOS compatible Three speed ranges:
16MHz 24MHz 33MHz
Five package styles Extended temperature ranges package available
1996
853-1562 17195
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
ORDERING INFORMATION
ROMless P80C32EBP P80C32EBA EPROM1 P87C52EBP P87C52EBA P87C52EBF P87C52EBL P80C32EBB P80C32EFP P80C32EFA P87C52EBB P87C52EFP P87C52EFA P87C52EFF P80C32EFB P80C32IBP P80C32IBA P80C32IBB P87C52IBF P87C52IBL P80C32IFP P80C32IFA P80C32IFB P87C52IFF P80C32NBA P80C32NBP P80C32NBB P80C32NFA P80C32NFP P80C32NFB P87C52IFP P87C52IFA P87C52EFB P87C52IBP P87C52IBA TEMPERATURE RANGE PACKAGE +70, Plastic Dual In-line Package +70, Plastic Leaded Chip Carrier +70, Ceramic Dual In-line Package +70, Ceramic Leaded Chip Carrier +70, Plastic Quad Flat Pack +85, Plastic Dual In-line Package +85, Plastic Leaded Chip Carrier +85, Ceramic Dual In-line Package +85, Plastic Quad Flat Pack +70, Plastic Dual In-line Package +70, Plastic Leaded Chip Carrier +70, Plastic Quad Flat Pack +70, Ceramic Dual In-line Package +70, Ceramic Leaded Chip Carrier +85, Plastic Dual In-line Package +85, Plastic Leaded Chip Carrier +85, Plastic Quad Flat Pack +85, Ceramic Dual In-line Package +70, Plastic Leaded Chip Carrier +70, Plastic Dual In-line Package +70, Plastic Quad Flat Pack +85, Plastic Leaded Chip Carrier +85, Plastic Dual In-line Package +85, Plastic Quad Flat Pack FREQ DRAWING NUMBER SOT129-1 SOT187-2 0590B 1472A SOT307-2 SOT129-1 SOT187-2 0590B SOT307-2 SOT129-1 SOT187-2 SOT307-2 0590B 1472A SOT129-1 SOT187-2 SOT307-2 0590B SOT187-2 SOT129-1 SOT307-2 SOT187-2 SOT129-1 SOT307-2
NOTE: Time Programmable EPROM. erasable EPROM 33MHz 80C52 operation, 80C52/80C54/80C58 data sheet.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
CERAMIC PLASTIC LEADED CHIP CARRIER FUNCTIONS
PLASTIC QUAD FLAT PACK FUNCTIONS
PQFP
Function T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 Function T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
Function P2.7/A15 PSEN ALE/PROG EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 Function P1.5 P1.6 P1.7 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1
Function P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA/VPP P0.7/AD7
Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4
CONNECT
SU00061
CONNECT
SU00062
LOGIC SYMBOL
XTAL1 PORT ADDRESS DATA
XTAL2 T2EX EA/VPP PSEN SECONDARY FUNCTIONS ALE/PROG INT0 INT1 PORT PORT
PORT
ADDRESS
SU00063
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT DRIVERS ADDR REGISTER PORT LATCH
PORT DRIVERS
PORT LATCH
ROM/ EPROM
REGISTER
STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
PCON T2CON
SCON
TMOD
TCON RCAP2H
BUFFER
RCAP2L SBUF
INTERRUPT, SERIAL PORT TIMER BLOCKS
INCREMENTER
PROGRAM COUNTER PSEN TIMING CONTROL INSTRUCTION REGISTER
DPTR
PORT LATCH
PORT LATCH
OSCILLATOR PORT DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT DRIVERS
P3.0-P3.7
SU00064
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Table
SYMBOL ACC* DPTR:
8XC52 Special Function Registers
DESCRIPTION Accumulator register Data pointer bytes) Data pointer high Data pointer DIRECT ADDRESS, SYMBOL, ALTERNATIVE PORT FUNCTION ADDRESS xx000000B 0x000000B RESET VALUE
Interrupt enable
Interrupt priority
Port
Port
T2EX
Port
PCON1 Port Power control SMOD
INT1
INT0
0xxxxxxxB
PSW* RCAP2H# RCAPL# SBUF Program status word Capture high Capture Serial data buffer SCON* Serial controller Stack pointer TCON* Timer control
xxxxxxxxB
T2CON*# TH2# TL2# Timer control Timer high Timer high Timer high Timer Timer Timer
EXF2
RCLK
TCLK
EXEN2
C/T2
CP/RL2
TMOD Timer mode GATE GATE addressable SFRs modified from added 80C51 SFRs. Bits GF1, GF0, PCON register implemented NMOS 8XC52.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DESCRIPTION
MNEMONIC P0.0-0.7 39-32 43-36 37-30 TYPE NAME FUNCTION Ground: reference. Power Supply: This power supply voltage normal, idle, power-down operation. Port Port open-drain, bidirectional port. Port pins that have written them float used high-impedance inputs. Port also multiplexed low-order address data during accesses external program data memory. this application, uses strong internal pull-ups when emitting Port also outputs code bytes during program verification 87C52. External pull-ups required during program verification. Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally pulled will source current because internal pull-ups. (See Electrical Characteristics: IIL). Pins P1.0 P1.1 also. Port also receives low-order address byte during program memory verification. Port also serves alternate functions timer (P1.0): Timer/counter external count input. T2EX (P1.1): Timer/counter trigger input. Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally being pulled will source current because internal pull-ups. (See Electrical Characteristics: IIL). Port emits high-order address byte during fetches from external program memory during accesses external data memory that 16-bit addresses (MOVX @DPTR). this application, uses strong internal pull-ups when emitting During accesses external data memory that 8-bit addresses (MOV @Ri), port emits contents special function register. Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally being pulled will source current because pull-ups. (See Electrical Characteristics: IIL). Port also serves special features 80C51 family, listed below: (P3.0): Serial input port (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt (P3.4): Timer external input (P3.5): Timer external input (P3.6): External data memory write strobe (P3.7): External data memory read strobe Reset: high this machine cycles while oscillator running, resets device. internal diffused resistor permits power-on reset using only external capacitor VCC. Address Latch Enable/Program Pulse: Output pulse latching byte address during access external memory. normal operation, emitted constant rate oscillator frequency, used external timing clocking. Note that pulse skipped during each access external data memory. This also program pulse input (PROG) during EPROM programming. Program Store Enable: read strobe external program memory. When device executing code from external program memory, PSEN activated twice each machine cycle, except that PSEN activations skipped during each access external data memory. PSEN activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: must externally held enable device fetch code from external program memory locations 0000H 1FFFH. held high, device executes from internal program memory unless program counter contains address greater than 1FFFH. This also receives 12.75V programming supply voltage (VPP) during EPROM programming. Crystal Input inverting oscillator amplifier input internal clock generator circuits. Crystal Output from inverting oscillator amplifier.
P1.0-P1.7
40-44
P2.0-P2.7 21-28
24-31
18-25
P3.0-P3.7
10-17
13-19
7-13
ALE/PROG
PSEN
EA/VPP
XTAL1 XTAL2
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DIFFERENCES FROM 80C51 Special Function Registers
special function register space same 80C51 except that 80C32/87C52 contains additional special function registers T2CON, RCAP2L, RCAP2H, TL2, TH2. Since standard 80C51 on-chip functions identical 8XC52, locations, locations, operation likewise identical. only exceptions interrupt mode interrupt priority SFRs (see Table
transition external input T2EX will also trigger 16-bit reload EXF2. auto-reload mode illustrated Figure baud rate generation mode selected RCLK and/or TCLK will described conjunction with serial port.
Serial Port
serial port 8XC52 identical that 80C51 except that counter/timer used generate baud rates. 8XC52, Timer selected baud rate generator setting TCLK and/or RCLK T2CON (see Figure Note that baud rate transmit receive simultaneously different. Setting RCLK and/or TCLK puts Timer into baud rate generator mode, shown Figure baud rate generator mode similar auto-reload mode, that rollover causes Timer registers reloaded with 16-bit value registers RCAP2H RCAP2L, which preset software. Now, baud rates Modes determined Timer overflow rate follows: Modes Baud Rate Timer Overflow Rate timer configured either "timer" "counter" operation. most typical applications, configured "timer" operation (C/T2 "Timer" operation little different Timer when it's being used baud rate generator. Normally, timer would increment every machine cycle (thus 1/12 oscillator frequency). baud rate generator, however, increments every state time (thus oscillator frequency). that case baud rate given formula: Modes Baud Rate Oscillator Frequency [65536 (RCAP2H, RCAP2L)]
Timer/Counters
addition timer/counters 80C51, 80C32/87C52 contains timer/counter Like timers timer operate either event timer event counter. This selected C/T2 special function register T2CON (see Figure three operating modes: capture, auto-load, baud rate generator, which selected bits T2CON shown Table Capture Mode there options which selected EXEN2 T2CON. EXEN2 then Timer 16-bit timer counter which upon overflowing sets TF2, Timer overflow bit, which used generate interrupt. EXEN2 then Timer still does above, with added feature that 1-to-0 transition external input T2EX causes current value Timer registers, TH2, captured into registers RCAP2L RCAP2H, respectively. (RCAP2L RCAP2H special function registers 80C52.) addition, transition T2EX causes EXF2 T2CON set, EXF2 like generate interrupt. Capture Mode illustrated Figure auto-reload mode, there again options, which selected EXEN2 T2CON. EXEN2 then when Timer rolls over only sets also causes Timer registers reloaded with 16-bit value registers RCAP2L RCAP2H, which preset software. EXEN2 then Timer still does above, with added feature that 1-to-0
where (RCAP2H, RCAP2L) content RCAP2H RCAP2L taken 16-bit unsigned integer.
(MSB) Symbol EXF2 Position T2CON.7 T2CON.6 EXF2 RCLK TCLK EXEN2 C/T2
(LSB) CP/RL2
Name Significance Timer overflow flag Timer overflow must cleared software. will when either RCLK TCLK Timer external flag when either capture reload caused negative transition T2EX EXEN2 When Timer interrupt enabled, EXF2 will cause vector Timer interrupt routine. EXF2 must cleared software. Receive clock flag. When set, causes serial port Timer overflow pulses receive clock modes RCLK causes Timer overflow used receive clock. Transmit clock flag. When set, causes serial port Timer overflow pulses transmit clock modes TCLK causes Timer overflows used transmit clock. Timer external enable flag. When set, allows capture reload occur result negative transition T2EX Timer being used clock serial port. EXEN2 causes Timer ignore events T2EX. Start/stop control Timer logic starts timer. Timer counter select. (Timer Internal timer (OSC/12) External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur negative transitions T2EX EXEN2 When cleared, auto-reloads will occur either with Timer overflows negative transitions T2EX when EXEN2 When either RCLK TCLK this ignored timer forced auto-reload Timer overflow.
RCLK TCLK EXEN2
T2CON.5 T2CON.4 T2CON.3
C/T2
T2CON.2 T2CON.1
CP/RL2
T2CON.0
SU00065
Figure Timer/Counter (T2CON) Control Register
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
C/T2 (8-bits) C/T2 (8-bits)
Control
Transition Detector
Capture Timer Interrupt RCAP2L RCAP2H
T2EX
EXF2
Control
EXEN2
SU00066
Figure Timer Capture Mode
C/T2 (8-BITS) C/T2 (8-BITS)
CONTROL
RELOAD
TRANSITION DETECTOR
RCAP2L
RCAP2H TIMER INTERRUPT
T2EX
EXF2
CONTROL
EXEN2
SU00067
Figure Timer Auto-Reload Mode
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Timer Overflow
NOTE: OSC. Freq. divided C/T2 (8-bits) C/T2 Control (8-bits)
SMOD RCLK
Reload
Clock
TCLK
Transition Detector
RCAP2L
RCAP2H
Clock
T2EX
EXF2
Timer Interrupt
Control EXEN2 Note availability additional external interrupt.
SU00068
Figure Timer Baud Rate Generator Mode
Table
Timer Operating Modes
CP/RL2 16-bit Auto-reload 16-bit Capture Baud rate generator (off) MODE
RCLK TCLK
Timer baud rate generator shown Figure This figure valid only RCLK TCLK T2CON. Note that rollover does TF2, will generate interrupt. Therefore, Timer interrupt does have disabled when Timer baud rate generator mode. Note too, that EXEN2 set, 1-to-0 transition T2EX will EXF2 will cause reload from (RCAP2H, RCAP2L) (TH2, TL2). Thus when Timer baud rate generator, T2EX used extra external interrupt, desired. should noted that when Timer running (TR2 "timer" function baud rate generator mode, should read write TL2. Under these conditions timer being incremented every state time, results read write accurate. RCAP registers read, should written because write might overlap reload cause write and/or reload errors. Turn timer (clear TR2) before accessing Timer RCAP registers, this case.
Timer/Counter Set-up
Except baud rate generator mode, values given T2CON include setting bit. Therefore, must set, separately, turn timer Table set-up timer timer. Table set-up timer counter.
Using Timer/Counter Generate Baud Rates
this purpose, Timer must used baud rate generating mode. Timer being clocked through (P1.0) baud rate Baud Rate Timer Overflow Rate being clocked internally, baud rate Baud Rate Oscillator Frequency [65536 (RCAP2H, RCAP2L)]
obtain reload value RCAP2H RCA02L, above equation rewritten RCAP2H, RCAP2L 65536 Oscillator Frequency Baud Rate
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Interrupts
80C32/87C52 interrupt sources. except EXF2 identical sources those 80C51. Interrupt Enable Register Interrupt Priority Register modified include additional 80C32/87C52 interrupt sources. operation these registers identical 80C51. 80C32/87C52, Timer Interrupt generated logical EXF2. Neither these flags cleared hardware when service routine vectored fact, service routine have determine whether EXF2 that generated interrupt, will have cleared software. bits that generate interrupts cleared software, with same result though been cleared
hardware. That interrupts generated pending interrupts canceled software. interrupt vector addresses interrupt priority requests same priority level given following: Vector Priority Within Address Level 0003H (highest) 000BH 0013H 001BH 0023H EXF2 002BH (lowest) Source
Note that they identical those 80C51 except addition Timer (TF1 EXF2) interrupt 002BH lowest priority within level.
Table
Timer Timer
MODE INTERNAL CONTROL (Note T2CON EXTERNAL CONTROL (Note
16-bit Auto-Reload 16-bit Capture Baud rate generator receive transmit same baud rate Receive only Transmit only
Table
Timer Counter
MODE INTERNAL CONTROL (Note 16-bit TMOD EXTERNAL CONTROL (Note
Auto-Reload NOTES: Capture/reload occurs only timer/counter overflow. Capture/reload occurs timer/counter overflow 1-to-0 transition T2EX (P1.1) except when timer used baud rate generator mode.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
OSCILLATOR CHARACTERISTICS
XTAL1 XTAL2 input output, respectively, inverting amplifier. pins configured on-chip oscillator, shown Logic Symbol, page drive device from external clock source, XTAL1 should driven while XTAL2 left unconnected. There requirements duty cycle external clock signal, because input internal clock circuitry through divide-by-two flip-flop. However, minimum maximum high times specified data sheet must observed.
special function registers remain intact during this mode. idle mode terminated either enabled interrupt which time process picked interrupt service routine continued), hardware reset which starts processor same manner power-on reset.
POWER-DOWN MODE
power-down mode, oscillator stopped instruction invoke power-down last instruction executed. Only contents on-chip preserved. hardware reset only terminate power-down mode. control bits reduced power modes special function register PCON.
RESET
reset accomplished holding high least machine cycles oscillator periods), while oscillator running. insure good power-up reset, must high long enough allow oscillator time start (normally milliseconds) plus machine cycles.
DESIGN CONSIDERATIONS
power-on, voltage must come same time proper start-up. Table shows state ports during current operating modes. precaution coming unexpected power down, INT0 INT1 should disabled prior enterring power down.
IDLE MODE
idle mode, puts itself sleep while on-chip peripherals stay active. instruction invoke idle mode last instruction executed normal operating mode before idle mode activated. contents, on-chip RAM,
Table External Status During Idle Power-Down Modes
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External PSEN PORT Data Float Data Float PORT Data Data Data Data PORT Data Address Data Data PORT Data Data Data Data
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Electrical Deviations from Commercial Specifications Extended Temperature Range (87C52) parameters included here same commercial temperature range table.
ELECTRICAL CHARACTERISTICS
Tamb -40°C +85°C, ±10%, TEST SYMBOL VIL1 VIH1 PARAMETER Input voltage, except Input voltage Input high voltage, except XTAL1, Input high voltage XTAL1, Logical input current, ports Logical 1-to-0 transition current, ports Power supply current: Active mode Idle mode Power-down mode 0.45V 2.0V 4.5-5.5V, Frequency range 16MHz CONDITIONS -0.5 0.2VCC+1 0.7VCC+0.1 LIMITS 0.2VCC-0.15 0.2VCC-0.35 VCC+0.5 VCC+0.5 -750 UNIT
ABSOLUTE MAXIMUM RATINGS1,
PARAMETER Operating temperature under bias Storage temperature range Voltage EA/VPP Voltage other Maximum Power dissipation (based package heat transfer limitations, device power consumption) RATING +150 +13.0 -0.5 +6.5 UNIT
NOTES: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these conditions other than those described Electrical Characteristics section this specification implied. This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maxima. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C, ±10%, (87C52) Tamb +70°C -40°C +85°C, ±10%, (80C32) TEST SYMBOL VIL1 VIH1 VOL1 PARAMETER Input voltage, except Input voltage RST7 CONDITIONS -0.5 0.2VCC+0.9 0.7VCC 1.6mA2 3.2mA2 -60µA, -25µA -10µA -800µA, -300µA -80µA 0.45V note note Tamb 70°C Tamb +85°C 11.5 0.75VCC 0.9VCC 0.75VCC 0.9VCC -650 LIMITS TYP1 0.2VCC-0.1 0.2VCC-0.3 VCC+0.5 VCC+0.5 0.45 0.45 UNIT
Input high voltage, except XTAL1, Input high voltage, XTAL1, RST7
Output voltage, ports Output voltage, port ALE, PSEN9 Output high voltage, ports ALE, PSEN3
VOH1
Output high voltage (port external mode)
Logical input current, ports Logical 1-to-0 transition current, ports Input leakage current, port Power supply current:7 Active mode 16MHz5 Idle mode 16MHz Power-down mode
RRST
Internal reset pull-down resistor capacitance10
NOTES: Typical ratings guaranteed. values listed room temperature, Capacitive loading ports cause spurious noise superimposed VOLs ports noise external capacitance discharging into port port pins when these pins make 1-to-0 transitions during operations. worst cases (capacitive loading 100pF), noise pulse exceed 0.8V. such cases, desirable qualify with Schmitt Trigger, address latch with Schmitt Trigger STROBE input. exceed these conditions provided that single output sinks more than more than outputs exceed test conditions. Capacitive loading ports cause PSEN momentarily fall below 0.9VCC specification when address bits stabilizing. Pins ports source transition current when they being externally driven from transition current reaches maximum value when approximately ICCMAX other frequencies given Active mode: ICCMAX FREQ 8.0: Idle mode: ICCMAX 0.14 FREQ +2.31, where FREQ external oscillator frequency MHz. ICCMAX given Figure Figures through test conditions. These values apply only Tamb +70°C. Tamb -40°C +85°C, table previous page. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Under steady state (non-transient) conditions, must externally limited follows: 15mA (*NOTE: This 85°C specification.) Maximum port pin: 26mA Maximum 8-bit port: 67mA Maximum total outputs: exceeds test condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions. This limit plastic packages. ceramic packages, maximum limit 20pF.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C, ±10%, (87C52)1, 16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX Serial port clock cycle time Output data setup clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 12tCLCL 10tCLCL-133 2tCLCL-117 pulse width pulse width valid data Data hold after Data float after valid data Address valid data Address valid Data valid transition Data hold after Data valid high address float high high High time time Rise time Fall time tCLCL-40 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 7tCLCL-150 tCLCL+40 tCLCL-tCLCX tCLCL-tCHCX 2tCLCL-60 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 FIGURE PARAMETER Oscillator frequency Speed versions pulse width Address valid Address hold after valid instruction PSEN PSEN pulse width PSEN valid instruction Input instruction hold after PSEN Input instruction float after PSEN Address valid instruction PSEN address float tCLCL-25 5tCLCL-105 tCLCL-30 3tCLCL-45 3tCLCL-105 VARIABLE CLOCK 2tCLCL-40 tCLCL-40 tCLCL-30 4tCLCL-100 UNIT
External Clock
tXHDV Clock rising edge input data valid 10tCLCL-133 NOTES: Parameters valid over operating temperature range unless otherwise specified. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Interfacing 80C32/52 devices with float times 45ns permitted. This limited contention will cause damage Port drivers. application note AN457 external memory interface.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C, ±10%, 0V1, 24MHz CLOCK SYMBOL 1/tCLCL FIGURE PARAMETER Oscillator frequency Speed versions pulse width Address valid Address hold after valid instruction PSEN PSEN pulse width PSEN valid instruction Input instruction hold after PSEN Input instruction float after PSEN Address valid instruction PSEN address float pulse width pulse width valid data Data hold after Data float after valid data Address valid data Address valid Data valid transition Data hold after Data valid high address float high high High time time Rise time Fall time Serial port clock cycle time Output data setup clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 12tCLCL 10tCLCL-133 2tCLCL-80 tCLCL-25 3tCLCL-50 4tCLCL-75 tCLCL-30 tCLCL-25 7tCLCL-130 tCLCL+25 tCLCL-tCLCX tCLCL-tCHCX 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-90 tCLCL-25 5tCLCL-80 tCLCL-25 3tCLCL-45 3tCLCL-60 VARIABLE CLOCK 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 33MHz CLOCK UNIT
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX
External Clock
tXHDV Clock rising edge input data valid 10tCLCL-133 NOTES: Parameters valid over operating temperature range unless otherwise specified. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Interfacing 8XC52 devices with float times 45ns permitted. This limited contention will cause damage Port drivers. Variable clock specified oscillator frequencies greater than 16MHz 33MHz. frequencies equal less than 16MHz, 16MHz Electrial Characteristics", page 1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
EXPLANATION SYMBOLS
Each timing symbol five characters. first character always time). other characters, depending their positions, indicate name signal logical status that signal. designations are: Address Clock Input data Logic level high Instruction (program memory contents) Logic level low, PSEN Output data signal Time Valid signal longer valid logic level Float Examples: tAVLL Time address valid low. tLLPL= Time PSEN low.
tLHLL
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR
tLLAX
tPXIZ
PORT
A0-A7
A0-A7
tAVIV
PORT A0-A15 A8-A15
SU00006
Figure External Program Memory Read Cycle
tWHLH
PSEN
tLLDV tLLWL
tRLRH
tAVLL
PORT
tLLAX tRLAZ
A0-A7 FROM
tRLDV tRHDX
DATA
tRHDZ
A0-A7 FROM
INSTR
tAVWL tAVDV
PORT P2.0-P2.7 A8-A15 FROM A0-A15 FROM
SU00025
Figure External Data Memory Read Cycle
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
tWHLH
PSEN
tLLWL
tWLWH
tAVLL
PORT
tLLAX
tQVWX
tWHQX
A0-A7 FROM
DATA
A0-A7 FROM
INSTR
tAVWL
PORT
P2.0-P2.7 A8-A15 FROM
A0-A15 FROM
SU00069
Figure External Data Memory Write Cycle
INSTRUCTION
tXLXL
CLOCK
tQVXH
OUTPUT DATA WRITE SBUF
tXHQX
tXHDV
INPUT DATA VALID CLEAR VALID
tXHDX
VALID VALID VALID VALID VALID VALID
SU00027
Figure Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure External Clock Drive
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
VCC-0.5
0.2VCC+0.9 0.2VCC-0.1
0.45V
NOTE: inputs during testing driven -0.5 logic 0.45V logic `0'. Timing measurements made logic logic `0'.
SU00010
Figure Testing Input/Output
VLOAD+0.1V VLOAD VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
NOTE: timing purposes, port longer floating when 100mV change from load voltage occurs, begins float when 100mV change from loaded VOH/VOL level occurs. IOH/IOL ±20mA.
SU00011
Figure Float Waveform
ACTIVE MODE ICCMAX FREQ.
ACTIVE MODE
IDLE MODE IDLE MODE 4MHz 8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz FREQ XTAL1
SU00070B
Figure FREQ Valid only within frequency specifications device under test
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
(NC) CLOCK SIGNAL XTAL2 XTAL1 (NC) CLOCK SIGNAL XTAL2 XTAL1
SU00719
SU00720
Figure Test Condition, Active Mode other pins disconnected
Figure Test Condition, Idle Mode other pins disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure Clock Signal Waveform Tests Active Idle Modes tCLCH tCHCL
(NC) XTAL2 XTAL1
SU00016
Figure Test Condition, Power Down Mode other pins disconnected. 5.5V
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
EPROM CHARACTERISTICS
87C52 programmed using modified Quick-Pulse Programmingalgorithm. differs from older methods value used (programming supply voltage) width number ALE/PROG pulses. 87C52 contains signature bytes that read used EPROM programming system identify device. signature bytes identify device 87C52 manufactured Philips. Table shows logic levels reading signature byte, programming program memory, encryption table, security bits. circuit configuration waveforms quick-pulse programming shown Figures Figure shows circuit configuration normal program memory verification.
Program Verification security been programmed, on-chip program memory read program verification. address program memory locations read applied ports shown Figure other pins held `Verify Code Data' levels indicated Table contents address location will emitted port External pull-ups required port this operation. encryption table been programmed, data presented port will exclusive program byte with encryption bytes. user will have know encryption table contents order correctly decode verification data. encryption table itself cannot read out. Reading Signature Bytes signature bytes read same procedure normal verification locations 030H 031H, except that P3.6 P3.7 need pulled logic low. values are: (030H) indicates manufactured Philips (031H) indicates 87C52
Quick-Pulse Programming
setup microcontroller quick-pulse programming shown Figure Note that 87C52 running with 6MHz oscillator. reason oscillator needs running that device executing internal address program data transfers. address EPROM location programmed applied ports shown Figure code byte programmed into that location applied port RST, PSEN pins ports specified Table held `Program Code Data' levels indicated Table ALE/PROG pulsed times shown Figure program encryption table, repeat pulse programming sequence addresses through 1FH, using `Pgm Encryption Table' levels. forget that after encryption table programmed, verification cycles will produce only encrypted data. program security bits, repeat pulse programming sequence using `Pgm Security Bit' levels. After security programmed, further programming code memory encryption table disabled. However, other security still programmed. Note that EA/VPP must allowed above maximum specified level amount time. Even narrow glitch above that voltage cause permanent damage device. source should well regulated free glitches overshoot.
Program/Verify Algorithms
algorithm agreement with conditions listed Table which satisfies timing specifications, suitable.
Erasure Characteristics
Erasure EPROM begins occur when chip exposed light with wavelengths shorter than approximately 4,000 angstroms. Since sunlight fluorescent lighting have wavelengths this range, exposure these light sources over extended time (about week sunlight, years room level fluorescent lighting) could cause inadvertent erasure. this secondary effects, recommended that opaque label placed over window. elevated temperature environments where solvents being used, apply Kapton tape Fluorglas part number 2345-5, equivalent. recommended erasure procedure exposure ultraviolet light 2537 angstroms) integrated dose least 15W-s/cm2. Exposing EPROM ultraviolet lamp 12,000µW/cm2 rating minutes, distance about inch, should sufficient. Erasure leaves array state.
Table EPROM Programming Modes
MODE Read signature Program code data Verify code data encryption table security security PSEN ALE/PROG EA/VPP P2.7 P2.6 P3.7 P3.6
NOTES: Valid that pin, valid high that pin. 12.75V ±0.25V. 5V±10% during programming verification. *ALE/PROG receives programming pulses while held 12.75V. Each programming pulse 100µs (±10µs) high minimum 10µs. TMTrademark phrase Intel Corporation. 1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
A0-A7 P3.6 P3.7 XTAL2 4-6MHz XTAL1 87C52 DATA +12.75V 100µs PULSES GROUND A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00071
Figure Programming Configuration
ALE/PROG:
PULSES
ALE/PROG:
10µs
100µs+10
SU00018
Figure PROG Waveform
A0-A7 P3.6 P3.7 XTAL2 4-6MHz XTAL1 87C52 DATA ENABLE A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00072
Figure Program Verification
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
EPROM PROGRAMMING VERIFICATION CHARACTERISTICS
Tamb 21°C +27°C, 5V±10%, (See Figure SYMBOL 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL Programming supply voltage Programming supply current Oscillator frequency Address setup PROG Address hold after PROG Data setup PROG Data hold after PROG P2.7 (ENABLE) high setup PROG hold after PROG PROG width Address data valid ENABLE data valid Data float after ENABLE PROG high PROG 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL PARAMETER 12.5 13.0 UNIT
PROGRAMMING* P1.0-P1.7 P2.0-P2.4 ADDRESS
VERIFICATION* ADDRESS
tAVQV
PORT DATA DATA
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC EA/VPP LOGIC
LOGIC
tEHSH
P2.7 ENABLE
tELQV
tEHQZ
SU00020
NOTE: PROGRAMMING VERIFICATION FIGURE
VERIFICATION CONDITIONS FIGURE
Figure EPROM Programming Verification
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DIP40: plastic dual in-line package; leads (600 mil)
SOT129-1
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
PLCC44: plastic leaded chip carrier; leads
SOT187-2
1996
0590B
1996
NOTE 0.098 (2.49) 0.040 (1.02)
CMOS single-chip 8-bit microcontrollers
853-0590B 06688
0.098 (2.49) 0.040 (1.02)
NOTES: Controlling dimension: Inches. Millimeters shown parentheses. Dimension tolerancing ANSI Y14. 5M-1982. "T", "D", reference datums body include allowance glass overrun meniscus seal line, base mismatch. These dimensions measured with leads constrained perpendicular plane numbers start with continue counterclockwise when viewed from top. Denotes window location EPROM products.
0.598 (15.19) 0.571 (14.50)
2.087 (53.01) 2.038 (51.77)
0.100 (2.54)
40-PIN (600 mils wide) CERAMIC DUAL IN-LINE PACKAGE (WITH WINDOW (FA) PACKAGE)
0.225 (5.72) MAX. 0.175 (4.45) 0.145 (3.68) 0.165 (4.19) 0.125 (3.18) 0.055 (1.40) 0.020 (0.51) 0.010 (0.254) 0.015 (0.38) 0.010 (0.25)
0.070 (1.78) 0.050 (1.27)
0.620 (15.75) 0.590 (14.99) (NOTE
SEATING PLANE
0.600 (15.24) (NOTE 0.695 (17.65) 0.600 (15.24)
0.023 (0.58) 0.015 (0.38)
80C32/87C52
Product specification
1472A
1996
3.05 (0.120) 2.29 (0.090) 0.38 (0.015)
CMOS single-chip 8-bit microcontrollers
853-1472A 05854
1.02 (0.040) CHAMFER
17.65 (0.695) 17.40 (0.685) 16.89 (0.665) 16.00 (0.630)
NOTES: dimensions tolerances conform ANSI Y14.5-1982. window optional. Dimensions include glass protrusion. Glass protrusion 0.005 inches maximum each side. Controlling dimension millimeters. dimensions tolerances include lead trim offset lead plating finish. Backside solder relief optional dimensions reference only.
0.51 (0.02) 17.65 (0.695) 17.40 (0.685) 16.89 (0.665) 16.00 (0.630)
44-PIN CERQUAD J-BEND PACKAGE
0.63 (0.025) MIN.
4.83 (0.190) 3.94 (0.155)
SEATING PLANE
0.73 0.08 (0.029 0.003) 1.27 (0.050) TYP. 0.25 (0.010) MIN. 1.52 (0.060) REF. TYP. PLACES 0.15 (0.006) MIN.
1.02 0.25 (0.040 0.010) DETAIL 0.482 (0.019 0.002) SEATING PLANE BASE PLANE
17.65 (0.656) 17.40 (0.685)
1.27 (0.050)
0.076 (0.003) MIN.
4.83 (0.190) 3.94 (0.155)
SEATING PLANE
DETAIL
12.7 (0.500) NOMINAL
0.25 (0.010) 0.15 (0.006)
0.508 (0.020) MIN.
8.13 (0.320) 7.37 (0.290)
8.13 (0.320) 7.37 (0.290)
DETAIL TYP. SIDES mm/(inch)
DETAIL mm/(inch)
80C32/87C52
Product specification
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
QFP44: plastic quad flat package; leads (lead length mm); body 1.75
SOT307-2
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
NOTES
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative Design
Definition
This data sheet contains design target goal specifications product development. Specifications change manner without notice. This data sheet contains preliminary data, supplementary data will published later date. Philips Semiconductors reserves right make changes time without notice order improve design supply best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves right make changes time without notice, order improve design supply best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors Philips Electronics North America Corporation reserve right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified. Applications that described herein these products illustrative purposes only. Philips Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors Philips Electronics North America Corporation Products designed life support appliances, devices, systems where malfunction Philips Semiconductors Philips Electronics North America Corporation Product reasonably expected result personal injury. Philips Semiconductors Philips Electronics North America Corporation customers using selling Philips Semiconductors Philips Electronics North America Corporation Products such applications their risk agree fully indemnify Philips Semiconductors Philips Electronics North America Corporation damages resulting from such improper sale. Philips Semiconductors East Arques Avenue P.O. 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors Philips Electronics North America Corporation register eligible circuits under Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 rights reserved. Printed U.S.A.
80C52/80C54/80C58 CMOS single-chip 8-bit microcontrollers
Product specification IC20 Data Handbook 1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DESCRIPTION
80C52/80C54/80C58 Single-Chip 8-Bit Microcontroller manufactured advanced CMOS process derivative 80C51 microcontroller family. 80C52/80C54/80C58 same instruction 80C51. This device provides architectural enhancements that make applicable variety applications general control systems. 80C52 contains memory, 80C54 contains memory, 80C58 contains memory, volatile read/write data memory, four 8-bit ports, three 16-bit timer/event counters, multi-source, four-priority-level, nested interrupt structure, enhanced UART on-chip oscillator timing circuits. systems that require extra capability, 80C52/54/58 expanded using standard compatible memories logic. added features make even more powerful microcontroller applications that require pulse width modulation, high-speed up/down counting capabilities such motor control. also more versatile serial channel that facilitates multiprocessor communications. 87C52/80C32 87C54/87C58 data sheets EPROM ROMless devices.
CONFIGURATIONS
T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 DUAL IN-LINE PACKAGE P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
FEATURES
80C51 central processing unit Full static operation ROM: 80C52;
ROM: 80C54; ROM: 80C58; capable addressing external memory bytes level program security system byte encryption array
SU00740
RAM, expandable externally bytes Speed range 33MHz Operating voltage ±10% Three 16-bit timer/counters
up/down counter
interrupt sources level priority Four 8-bit ports Full-duplex enhanced UART
Framing error detection Automatic address recognition
Power control modes
Idle mode Power-down mode
Once Circuit Emulation) Mode Five package styles Programmable clock (Inhibit ALE) Second DPTR register Asynchronous port reset
1996 853-1470 17196
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
ORDERING INFORMATION
P80C52EBPN P80C52EBAA P80C52EBBB P80C52EFP P80C52EFA P80C52EFB P80C52IBP P80C52IBA P80C52IBB P80C52IFP P80C52IFA P80C52IFB P80C52NBAA P80C52NBPN P80C52NBBB P80C52NFA P80C52NFPN P80C52NFBB P80C54EBPN P80C54EBAA P80C54EBBB P80C54EFP P80C54EFA P80C54EFB P80C54IBP P80C54IBA P80C54IBB P80C54IFP P80C54IFA P80C54IFB P80C54NBAA P80C54NBPN P80C54NBBB P80C54NFA P80C54NFPN P80C54NFBB P80C58EBPN P80C58EBAA P80C58EBBB P80C58EFP P80C58EFA P80C58EFB P80C58IBP P80C58IBA P80C58IBB P80C58IFP P80C58IFA P80C58IFB P80C58NBAA P80C58NBPN P80C58NBBB P80C58NFA P80C58NFPN P80C58NFBB TEMPERATURE RANGE PACKAGE +70, Plastic Dual In-line Package +70, Plastic Leaded Chip Carrier +70, Plastic Quad Flat Pack +85, Plastic Dual In-line Package +85, Plastic Leaded Chip Carrier +85, Plastic Quad Flat Pack +70, Plastic Dual In-line Package +70, Plastic Leaded Chip Carrier +70, Plastic Quad Flat Pack +85, Plastic Dual In-line Package +85, Plastic Leaded Chip Carrier +85, Plastic Quad Flat Pack +70, Plastic Leaded Chip Carrier +70, Plastic Dual In-line Package +70, Plastic Quad Flat Pack +85, Plastic Leaded Chip Carrier +85, Plastic Dual In-line Package +85, Plastic Quad Flat Pack FREQ DRAWING NUMBER SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT187-2 SOT129-1 SOT307-2 SOT187-2 SOT129-1 SOT307-2
LOGIC SYMBOL
XTAL1 PORT ADDRESS DATA
XTAL2 T2EX PSEN SECONDARY FUNCTIONS INT0 INT1 PORT PORT
PORT
ADDRESS
SU00732
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT DRIVERS ADDR REGISTER PORT LATCH
PORT DRIVERS
PORT LATCH
REGISTER STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
SFRs TIMERS
BUFFER
INCREMENTER PROGRAM COUNTER
PSEN TIMING CONTROL
INSTRUCTION REGISTER
MULTIPLE DPTRs
PORT LATCH
PORT LATCH
OSCILLATOR PORT DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT DRIVERS
P3.0-P3.7
SU00733B
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Table
SYMBOL ACC* AUXR# AUXR1# DPTR: IPH# PCON#1 PSW* RACAP2H# RACAP2L# SADDR# SADEN# SBUF SCON* TCON* T2CON* T2MOD# TH2# TL2#
80C52/80C54/80C58 Special Function Registers
DESCRIPTION Accumulator Auxiliary Auxiliary register Data Pointer bytes) Data Pointer High Data Pointer Interrupt Enable Interrupt Priority Interrupt Priority High Port Port Port Port Power Control Program Status Word Timer Capture High Timer Capture Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control Timer Control Timer Mode Control Timer High Timer High Timer High Timer Timer Timer DIRECT ADDRESS EXF2 RCLK TCLK EXEN2 C/T2 T2OE CP/RL2 DCEN xxxxxx00B
SM0/FE
ADDRESS, SYMBOL, ALTERNATIVE PORT FUNCTION
RESET VALUE xxxxxxx0B xxxxxxx0B
AD14 SMOD0
PT2H AD13
AD12 POF2
PT1H AD11 INT1
PX1H AD10 INT0
PT0H T2EX
PX0H xxxxxxxxB 00xx0000B x0000000B x0000000B
AD15 SMOD1
TMOD Timer Mode GATE SFRs addressable. SFRs modified from added 80C51 SFRs. Reserved bits. Reset value depends reset source. will affected Reset. present 80C52. 1996
GATE
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
PLASTIC LEADED CHIP CARRIER FUNCTIONS
PLASTIC QUAD FLAT PACK FUNCTIONS
PQFP
Function P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
Function P2.7/A15 PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 Function P1.5 P1.6 P1.7 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1
Function P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN P0.7/AD7
Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4
CONNECT
SU00741A
CONNECT
SU00742A
DESCRIPTIONS
NUMBER MNEMONIC P0.0-0.7 39-32 43-36 37-30 TYPE NAME FUNCTION Ground: reference. Power Supply: This power supply voltage normal, idle, power-down operation. Port Port open-drain, bidirectional port. Port pins that have written them float used high-impedance inputs. Port also multiplexed low-order address data during accesses external program data memory. this application, uses strong internal pull-ups when emitting Port also outputs code bytes during program verification. External pull-ups required during program verification. Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally pulled will source current because internal pull-ups. (See Electrical Characteristics: IIL). Port also receives low-order address byte during program memory verification. Alternate functions include: (P1.0): Timer/Counter external count input/Clockout T2EX (P1.1): Timer/Counter Reload/Capture/Direction Control
P1.0-P1.7
40-44,
P2.0-P2.7 21-28
24-31
18-25
Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally being pulled will source current because internal pull-ups. (See Electrical Characteristics: IIL). Port emits high-order address byte during fetches from external program memory during accesses external data memory that 16-bit addresses (MOVX @DPTR). this application, uses strong internal pull-ups when emitting During accesses external data memory that 8-bit addresses (MOV @Ri), port emits contents special function register.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DESCRIPTIONS (Continued)
NUMBER MNEMONIC P3.0-P3.7 10-17 13-19 7-13 TYPE NAME FUNCTION Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally being pulled will source current because pull-ups. (See Electrical Characteristics: IIL). Port also serves special features 80C51 family, listed below: (P3.0): Serial input port (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt (P3.4): Timer external input (P3.5): Timer external input (P3.6): External data memory write strobe (P3.7): External data memory read strobe Reset: high this machine cycles while oscillator running, resets device. internal diffused resistor permits power-on reset using only external capacitor VCC. Address Latch Enable: Output pulse latching byte address during access external memory. normal operation, emitted constant rate oscillator frequency, used external timing clocking. Note that pulse skipped during each access external data memory. disabled setting auxiliary.0. With this set, will active only during MOVX instruction. Program Store Enable: read strobe external program memory. When 80C52/80C54/80C58 executing code from external program memory, PSEN activated twice each machine cycle, except that PSEN activations skipped during each access external data memory. PSEN activated during fetches from internal program memory. External Access Enable: must externally held enable device fetch code from external program memory locations 0000H 7FFFH. held high, device executes from internal program memory unless program counter contains address greater than 7FFFH. security programmed, will internally latched Reset. Crystal Input inverting oscillator amplifier input internal clock generator circuits. Crystal Output from inverting oscillator amplifier.
PSEN
XTAL1 XTAL2
NOTE: avoid "latch-up" effect power-on, voltage time must higher than 0.5V 0.5V, respectively.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
TIMER OPERATION Timer
Timer 16-bit Timer/Counter which operate either event timer event counter, selected C/T2* special function register T2CON (see Figure Timer three operating modes:Capture, Auto-reload down counting) ,and Baud Rate Generator, which selected bits T2CON shown Table
Figure When reset applied DCEN=0 which means Timer will default counting DCEN set, Timer count down depending value T2EX pin. Figure shows Timer which will count automatically since DCEN=0. this mode there options selected EXEN2 T2CON register. EXEN2=0, then Timer counts 0FFFFH sets (Overflow Flag) upon overflow. This causes Timer registers reloaded with 16-bit value RCAP2L RCAP2H. values RCAP2L RCAP2H preset software means. EXEN2=1, then 16-bit reload triggered either overflow 1-to-0 transition input T2EX. This transition also sets EXF2 bit. Timer interrupt, enabled, generated when either EXF2 Figure DCEN=1 which enables Timer count down. This mode allows T2EX control direction count. When logic applied T2EX Timer will count Timer will overflow 0FFFFH flag, which then generate interrupt, interrupt enabled. This timer overflow also causes 16-bit value RCAP2L RCAP2H reloaded into timer registers TH2. When logic applied T2EX this causes Timer count down. timer will underflow when become equal value stored RCAP2L RCAP2H. Timer underflow sets flag causes 0FFFFH reloaded into timer registers TH2. external flag EXF2 toggles when Timer underflows overflows. This EXF2 used 17th resolution needed. EXF2 flag does generate interrupt this mode operation.
Capture Mode
capture mode there options which selected EXEN2 T2CON. EXEN2=0, then timer 16-bit timer counter selected C/T2* T2CON) which, upon overflowing sets TF2, timer overflow bit. This used generate interrupt enabling Timer interrupt register/SFR table). EXEN2= Timer operates described above, with added feature that transition external input T2EX causes current value Timer registers, TH2, captured into registers RCAP2L RCAP2H, respectively. addition, transition T2EX causes EXF2 T2CON set, EXF2 like generate interrupt (which vectors same location Timer overflow interrupt. Timer interrupt service routine interrogate EXF2 determine which event caused interrupt). capture mode illustrated Figure (There reload value this mode. Even when capture event occurs from T2EX, counter keeps counting T2EX transitions osc/12 pulses.).
Auto-Reload Mode Down Counter)
16-bit auto-reload mode, Timer configured either timer counter (C/T2* T2CON)) then programmed count down. counting direction determined DCEN(Down Counter Enable) which located T2MOD register (see
(MSB) Symbol EXF2 Position T2CON.7 T2CON.6 EXF2 RCLK TCLK EXEN2 C/T2
(LSB) CP/RL2
Name Significance Timer overflow flag Timer overflow must cleared software. will when either RCLK TCLK Timer external flag when either capture reload caused negative transition T2EX EXEN2 When Timer interrupt enabled, EXF2 will cause vector Timer interrupt routine. EXF2 must cleared software. EXF2 does cause interrupt up/down counter mode (DCEN Receive clock flag. When set, causes serial port Timer overflow pulses receive clock modes RCLK causes Timer overflow used receive clock. Transmit clock flag. When set, causes serial port Timer overflow pulses transmit clock modes TCLK causes Timer overflows used transmit clock. Timer external enable flag. When set, allows capture reload occur result negative transition T2EX Timer being used clock serial port. EXEN2 causes Timer ignore events T2EX. Start/stop control Timer logic starts timer. Timer counter select. (Timer Internal timer (OSC/12) External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur negative transitions T2EX EXEN2 When cleared, auto-reloads will occur either with Timer overflows negative transitions T2EX when EXEN2 When either RCLK TCLK this ignored timer forced auto-reload Timer overflow.
SU00728
RCLK TCLK EXEN2
T2CON.5 T2CON.4 T2CON.3
C/T2
T2CON.2 T2CON.1
CP/RL2
T2CON.0
Figure Timer/Counter (T2CON) Control Register 1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Table Timer Operating Modes
RCLK TCLK CP/RL2 16-bit Auto-reload 16-bit Capture Baud rate generator (off) MODE
C/T2 (8-bits) C/T2 (8-bits)
Control
Transition Detector
Capture Timer Interrupt RCAP2L RCAP2H
T2EX
EXF2
Control
EXEN2
SU00066
Figure Timer Capture Mode
T2MOD
Address 0C9H Addressable T2OE
Reset Value XXXX XX00B
DCEN
Symbol T2OE DCEN
Function implemented, reserved future use.* Timer Output Enable bit. details Programmable Clock-Out. Down Count Enable bit. When set, this allows Timer configured up/down counter.
User software should write reserved bits. These bits used future 8051 family products invoke features. that case, reset inactive value will active value will value read from reserved indeterminate. Figure Timer Mode (T2MOD) Control Register
SU00746
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
C/T2 (8-BITS) C/T2 (8-BITS)
CONTROL
RELOAD
TRANSITION DETECTOR
RCAP2L
RCAP2H TIMER INTERRUPT
T2EX
EXF2
CONTROL
EXEN2
SU00067
Figure Timer Auto-Reload Mode (DCEN
(DOWN COUNTING RELOAD VALUE)
TOGGLE EXF2
C/T2 OVERFLOW INTERRUPT
C/T2 CONTROL COUNT DIRECTION DOWN RCAP2L RCAP2H T2EX
COUNTING RELOAD VALUE)
SU00730
Figure Timer Auto Reload Mode (DCEN
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Timer Overflow
NOTE: OSC. Freq. divided C/T2 (8-bits) C/T2 Control (8-bits)
SMOD RCLK
Reload
Clock
TCLK
Transition Detector
RCAP2L
RCAP2H
Clock
T2EX
EXF2
Timer Interrupt
Control EXEN2 Note availability additional external interrupt.
SU00068
Figure Timer Baud Rate Generator Mode
Table
Timer Generated Commonly Used Baud Rates
Timer Freq 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 6MHz 6MHz RCAP2H RCAP2L
baud rates modes determined Timer overflow rate given below: Modes Baud Rates Timer Overflow Rate timer configured either "timer" "counter" operation. many applications, configured "timer" operation (C/T2*=0). Timer operation different Timer when being used baud rate generator. Usually, timer would increment every machine cycle (i.e., 1/12 oscillator frequency). baud rate generator, increments every state time (i.e., oscillator frequency). Thus baud rate formula follows: Modes Baud Rates Oscillator Frequency [65536 (RCAP2H, RCAP2L)]] Where: (RCAP2H, RCAP2L)= content RCAP2H RCAP2L taken 16-bit unsigned integer. Timer baud rate generator mode shown Figure valid only RCLK and/or TCLK T2CON register. Note that rollover does TF2, will generate interrupt. Thus, Timer interrupt does have disabled when Timer baud rate generator mode. Also EXEN2 external enable flag) set, 1-to-0 transition T2EX (Timer/counter trigger input) will EXF2 external flag) will cause reload from (RCAP2H, RCAP2L) (TH2,TL2). Therefore when Timer baud rate generator, T2EX used additional external interrupt, needed.
Baud Rate 375K 9.6K 2.8K 2.4K 1.2K
Baud Rate Generator Mode
Bits TCLK and/or RCLK T2CON (Table allow serial port transmit receive baud rates derived from either Timer Timer When TCLK= Timer used serial port transmit baud rate generator. When TCLK= Timer used serial port transmit baud rate generator. RCLK same effect serial port receive baud rate. With these bits, serial port have different receive transmit baud rates generated Timer other Timer Figure shows Timer baud rate generation mode. baud rate generation mode like auto-reload mode,in that rollover causes Timer registers reloaded with 16-bit value registers RCAP2H RCAP2L, which preset software.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
When Timer baud rate generator mode, should read write TL2. baud rate generator, Timer incremented every state time (osc/2) asynchronously from under these conditions, read write accurate. RCAP2 registers read, should written because write might overlap reload cause write and/or reload errors. timer should turned (clear TR2) before accessing Timer RCAP2 registers. Table shows commonly used baud rates they obtained from Timer
obtain reload value RCAP2H RCAP2L, above equation rewritten RCAP2H, RCAP2L 65536 Baud Rate
Timer/Counter Set-up
Except baud rate generator mode, values given T2CON include setting bit. Therefore, must set, separately, turn timer Table set-up Timer timer. Also Table set-up Timer counter.
Summary Baud Rate Equations
Timer baud rate generating mode. Timer being clocked through T2(P1.0) baud rate Baud Rate Timer Overflow Rate Timer being clocked internally, baud rate Baud Rate [65536 (RCAP2H, RCAP2L)]]
POWER FLAG3
Power Flag (POF) on-chip circuitry when level 80C54/80C58 rises from cleared software allowing user determine reset result power-on warm start after powerdown. level must remain above remain unaffected level.
Where fOSC= Oscillator Frequency
Table Timer Timer
T2CON MODE 16-bit Auto-Reload 16-bit Capture Baud rate generator receive transmit same baud rate Receive only Transmit only INTERNAL CONTROL (Note EXTERNAL CONTROL (Note
Table Timer Counter
TMOD MODE 16-bit Auto-Reload INTERNAL CONTROL (Note EXTERNAL CONTROL (Note
NOTES: Capture/reload occurs only timer/counter overflow. Capture/reload occurs timer/counter overflow 1-to-0 transition T2EX (P1.1) except when Timer used baud rate generator mode. present 80C52.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
OSCILLATOR CHARACTERISTICS
XTAL1 XTAL2 input output, respectively, inverting amplifier. pins configured on-chip oscillator. drive device from external clock source, XTAL1 should driven while XTAL2 left unconnected. There requirements duty cycle external clock signal, because input internal clock circuitry through divide-by-two flip-flop. However, minimum maximum high times specified data sheet must observed.
oscillator bringing back high completes exit. Once interrupt serviced, next instruction executed after RETI will following instruction that device into Power Down.
Design Consideration
When idle mode terminated hardware reset, device
normally resumes program execution, from where left off, machine cycles before internal rest algorithm takes control. On-chip hardware inhibits access internal this event, access port pins inhibited. eliminate possibility unexpected write when Idle terminated reset, instruction following that invokes Idle should that writes port external memory.
Reset
reset accomplished holding high least machine cycles oscillator periods), while oscillator running. insure good power-on reset, must high long enough allow oscillator time start (normally milliseconds) plus machine cycles. power-on, voltage must come same time proper start-up. Ports will asynchronously driven their reset condition when voltage above VIH1 (min.) applied RESET.
ONCEMode
ONCE ("On-Circuit Emulation") Mode facilitates testing debugging systems using 80C52/54/58 without removing device from circuit. ONCE Mode invoked Pull while device reset PSEN high; Hold deactivated. While device ONCE Mode, Port pins into float state, other port pins PSEN weakly pulled high. oscillator circuit remains active. While 80C52/54/58 this mode, emulator test used drive circuit. Normal operation restored when normal reset applied.
Idle Mode
idle mode (see Table puts itself sleep while on-chip peripherals stay active. instruction invoke idle mode last instruction executed normal operating mode before idle mode activated. contents, on-chip RAM, special function registers remain intact during this mode. idle mode terminated either enabled interrupt which time process picked interrupt service routine continued), hardware reset which starts processor same manner power-on reset.
Programmable Clock-Out
80C52/54/58 feature. duty cycle clock programmed come P1.0. This pin, besides being regular pin, alternate functions. programmed: input external clock Timer/Counter output duty cycle clock ranging from 61Hz 4MHz 16MHz operating frequency. configure Timer/Counter clock generator, C/T2 T2CON) must cleared T2OE T2MOD must set. (T2CON.2) also must start timer. Clock-Out frequency depends oscillator frequency reload value Timer capture registers (RCAP2H, RCAP2L) shown this equation: Oscillator Frequency (65536 RCAP2H, RCAP2L)
Power-Down Mode
save even more power, Power Down mode (see Table invoked software. this mode, oscillator stopped instruction that invoked Power Down last instruction executed. on-chip Special Function Registers retain their values until Power Down mode terminated. 80C52/54/58 either hardware reset external interrupt used exit from Power Down. Reset redefines SFRs does change on-chip RAM. external interrupt allows both SFRs on-chip retain their values. properly terminate Power Down reset external interrupt should executed before restored normal operating level must held active long enough oscillator restart stabilize (normally less than 10ms). With external interrupt, INT0 INT1 must enabled configured level-sensitive. Holding restarts
Clock-Out mode Timer roll-overs will generate interrupt. This similar when used baud-rate generator. possible Timer baud-rate generator clock generator simultaneously. Note, however, that baud-rate Clock-Out frequency will same.
Table External Status During Idle Power-Down Mode
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External PSEN PORT Data Float Data Float PORT Data Data Data Data PORT Data Address Data Data PORT Data Data Data Data
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Enhanced UART
UART operates usual modes that described first section Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. addition UART perform framing error detect looking missing stop bits, automatic address recognition. 80C52/54/58 UART also fully supports multiprocessor communication does standard 80C51 UART. When used framing error detect UART looks missing stop bits communication. missing will SCON register. shares SCON.7 with function SCON.7 determined PCON.6 (SMOD0) (see Figure SMOD0 then SCON.7 functions SCON.7 functions when SMOD0 cleared. When used SCON.7 only cleared software. Refer Figure Automatic Address Recognition Automatic Address Recognition feature which allows UART recognize certain addresses serial stream using hardware make comparisons. This feature saves great deal software overhead eliminating need software examine every serial address which passes serial port. This feature enabled setting SCON. UART modes, mode mode Receive Interrupt flag (RI) will automatically when received byte contains either "Given" address "Broadcast" address. mode requires that information indicate that received information address data. Automatic address recognition shown Figure mode called Mode this mode flag will enabled information received valid stop following address bits information either Given Broadcast address. Mode Shift Register mode ignored. Using Automatic Address Recognition feature allows master selectively communicate with more slaves invoking Given slave address addresses. slaves contacted using Broadcast address. special Function Registers used define slave's address, SADDR, address mask, SADEN. SADEN used define which bits SADDR used which bits "don't care". SADEN mask logically ANDed with SADDR create "|Given" address which master will addressing each slaves. Given address allows multiple slaves recognized while excluding others. following examples will help show versatility this scheme: Slave SADDR SADEN Given 1100 0000 1111 1101 1100 00X0
Slave
SADDR SADEN Given
1100 0000 1111 1110 1100 000X
above example SADDR same SADEN data used differentiate between slaves. Slave requires ignores Slave requires ignored. unique address Slave would 1100 0010 since slave requires unique address slave would 1100 0001 since will exclude slave Both slaves selected same time address which (for slave (for slave Thus, both could addressed with 1100 0000. more complex system following could used select slaves while excluding slave Slave SADDR SADEN Given SADDR SADEN Given SADDR SADEN Given 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX
Slave
Slave
above example differentiation among slaves lower address bits. Slave requires that uniquely addressed 1110 0110. Slave requires that uniquely addressed 1110 0101. Slave requires that unique address 1110 0011. select Slaves exclude Slave address 1110 0100, since necessary make exclude slave Broadcast Address each slave created taking logical SADDR SADEN. Zeros this result teated don't-cares. most cases, interpreting don't-cares ones, broadcast address will hexadecimal. Upon reset SADDR (SFR address 0A9H) SADEN (SFR address 0B9H) leaded with This produces given address "don't cares" well Broadcast address "don't cares". this effectively disables Automatic Addressing mode allows microcontroller standard 80C51 type UART drivers which make this feature.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
SCON Address Addressable SM0/FE Bit:
Reset Value 0000 0000B
(SMOD0 0/1)*
Symbol
Function Framing Error bit. This receiver when invalid stop detected. cleared valid frames should cleared software. SMOD0 must enable access bit. Serial Port Mode (SMOD0 must access SM0) Serial Port Mode Mode Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate** fOSC/12 variable fOSC/64 fOSC/32 variable
Enables Automatic Address Recognition feature Modes then will unless received data (RB8) indicating address, received byte Given Broadcast Address. Mode then will activated unless valid stop received, received byte Given Broadcast Address. Mode should Enables serial reception. software enable reception. Clear software disable reception. data that will transmitted Modes clear software desired. modes data that received. Mode stop that received. Mode used. Transmit interrupt flag. hardware time Mode beginning stop other modes, serial transmission. Must cleared software. Receive interrupt flag. hardware time Mode halfway through stop time other modes, serial reception (except SM2). Must cleared software.
NOTE: *SMOD0 located PCON6. **fOSC oscillator frequency
SU00043
Figure SCON: Serial Port Control Register
START
DATA BYTE
ONLY MODE
STOP
STOP (FRAMING ERROR) UART MODE CONTROL
SCON (98H)
SMOD1
SMOD0
PCON (87H)
SCON.7 SCON.7
SU00747
Figure UART Framing Error Detection
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
SCON (98H)
RECEIVED ADDRESS PROGRAMMED ADDRESS COMPARATOR
UART MODE MODE INTERRUPT REN=1, RB8=1 "RECEIVED ADDRESS" "PROGRAMMED ADDRESS" WHEN ADDRESS RECEIVED, CLEAR RECEIVE DATA BYTES WHEN DATA BYTES HAVE BEEN RECEIVED: WAIT NEXT ADDRESS.
SU00045
Figure UART Multiprocessor Communication, Automatic Address Recognition
Interrupt Priority Structure
80C52/54/58 6-source four-level interrupt structure. There SFRs associated with interrupts 80C52/54/58. They (See Figures 11.) addition, there (Interrupt Priority High) register that makes four-level interrupt structure possible. located address B7H. structure register description bits shown below: (Interrupt Priority High) (B7H)
PT2H PT1H PX1H PT0H PX0H
PRIORITY BITS IPH.x IP.x INTERRUPT PRIORITY LEVEL Level (lowest priority) Level Level Level (highest priority)
IPH.0 IPH.1 IPH.2 IPH.3 IPH.4 IPH.5 IPH.6 IPH.7
PX0H PT0H PX1H PT1H PT2H
External interrupt priority high Timer interrupt priority high External interrupt priority high Timer interrupt priority high Serial Port interrupt high Timer interrupt priority high implemented implemented
priority scheme servicing interrupts same that 80C51, except there four interrupt levels 80C52/54/58 rather than 80C51. interrupt will serviced long interrupt equal higher priority already being serviced. interrupt equal higher level priority being serviced, interrupt will wait until finished before being serviced. lower priority level interrupt being serviced, will stopped interrupt serviced. When interrupt finished, lower priority level interrupt that stopped will completed.
function simple when combined with determines priority each interrupt. priority each interrupt determined shown following table:
Table
Interrupt Table
POLLING PRIORITY REQUEST BITS TF2, EXF2 CCFn HARDWARE CLEAR? (L)1 (T)2 VECTOR ADDRESS
SOURCE
NOTES: Level activated Transition activated
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
(A8H)
Enable enables interrupt. Enable disables IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 SYMBOL FUNCTION Global disable bit. interrupts disabled. each interrupt individually enabled disabled setting clearing enable bit. Timer interrupt enable bit. Serial Port interrupt enable bit. Timer interrupt enable bit. External interrupt enable bit. Timer interrupt enable bit. External interrupt enable bit.
SU00743
Figure Registers
(B8H)
Priority assigns high priority Priority assigns priority IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 SYMBOL FUNCTION implemented, reserved future use. Timer interrupt priority bit. Serial Port interrupt priority bit. Timer interrupt priority bit. External interrupt priority bit. Timer interrupt priority bit. External interrupt priority bit.
SU00744
Figure Registers
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Reduced Mode
(AUXR.0) AUXR register when disables output.
BIT0 AUXR1
80C52/80C54/80C58 Reduced Mode
AUXR (8EH)
DPTR1 DPTR0 (83H) (82H) EXTERNAL DATA MEMORY
Turns output. Figure DPTR Structure
SU00745A
Dual Data Pointer Register (DPTR)
dual DPTR structure (see Figure which 80C52/54/58 will specify address external data memory location. There 16-bit DPTR registers that address external memory, single called AUXR1/bit0 that allows program code switch between them. DPTR Instructions instructions that refer DPTR refer data pointer that currently selected using AUXR1/bit register. instructions that DPTR follows: DPTR DPTR, #data16 A+DPTR
Register Name: AUXR1# Address: Reset Value: xxxxxxx0B
Increments data pointer Loads DPTR with 16-bit constant Move code byte relative DPTR Move external (16-bit address) Move external (16-bit address) Jump indirect relative DPTR
MOVX DPTR MOVX DPTR DPTR
Where: AUXR1/bit0 Switches between DPTR0 DPTR1. Select DPTR0 DPTR1
data pointer accessed byte-by-byte basis specifying High byte instruction which accesses SFRs. application note AN458 detailed operation
status whould saved software when switching between DPTR0 DPTR1.
ABSOLUTE MAXIMUM RATINGS1,
PARAMETER Operating temperature under bias Storage temperature range Voltage EA/VPP Voltage other Maximum Power dissipation (based package heat transfer limitations, device power consumption) RATING +150 +13.0 -0.5 +6.5 UNIT
NOTES: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these conditions other than those described Electrical Characteristics section this specification implied. This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maxima. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C, 5.0V ±10%; SYMBOL VIH1 VOL1 VOH1 Input voltage Input high voltage (ports Input high voltage, XTAL1, Output voltage, ports Output voltage, port ALE, PSEN8, Output high voltage, ports Output high voltage (port external mode), ALE9, PSEN3 Logical input current, ports Logical 1-to-0 transition current, ports Input leakage current, port Power supply current (see Figure 20): Active mode 16MHz5 Idle mode 16MHz5 Power-down mode Internal reset pull-down resistor capacitance10 (except 4.5V 1.6mA2 4.5V 3.2mA2 4.5V -30µA 4.5V -3.2mA 0.4V 2.0V note 0.45 note Tamb +70°C Tamb +85°C -650 PARAMETER TEST CONDITIONS 4.5V 5.5V LIMITS -0.5 0.2VCC+0.9 0.7VCC TYP1 UNIT 0.2VCC-0.1 VCC+0.5 VCC+0.5
RRST
NOTES: Typical ratings guaranteed. values listed room temperature, Capacitive loading ports cause spurious noise superimposed VOLs ports noise external capacitance discharging into port port pins when these pins make 1-to-0 transitions during operations. worst cases (capacitive loading 100pF), noise pulse exceed 0.8V. such cases, desirable qualify with Schmitt Trigger, address latch with Schmitt Trigger STROBE input. exceed these conditions provided that single output sinks more than more than outputs exceed test conditions. Capacitive loading ports cause PSEN momentarily fall below (VCC-0.7) specification when address bits stabilizing. Pins ports source transition current when they being externally driven from transition current reaches maximum value when approximately Figures through test conditions. Active Mode: FREQ 1.1; Idle Mode: 0.18 FREQ +1.0; Figure This value applies Tamb +70°C. Tamb -40°C +85°C, -750µA. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Under steady state (non-transient) conditions, must externally limited follows: 15mA (*NOTE: This 85°C specification.) Maximum port pin: 26mA Maximum 8-bit port: 71mA Maximum total outputs: exceeds test condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions. tested VOH1, except when then voltage specification. capacitance characterized tested. capacitance less than 25pF. capacitance ceramic package less than 15pF (except 25pF).
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C, ±10%, 0V1, 16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX Serial port clock cycle time Output data setup clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 12tCLCL 10tCLCL-133 2tCLCL-117 pulse width pulse width valid data Data hold after Data float after valid data Address valid data Address valid Data valid transition Data hold after Data valid high address float high high tCLCL-40 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 7tCLCL-150 tCLCL+40 tCLCL-tCLCX tCLCL-tCHCX 2tCLCL-60 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 FIGURE PARAMETER Oscillator frequency Speed versions pulse width Address valid Address hold after valid instruction PSEN PSEN pulse width PSEN valid instruction tCLCL-25 5tCLCL-105 tCLCL-30 3tCLCL-45 3tCLCL-105 VARIABLE CLOCK 2tCLCL-40 tCLCL-40 tCLCL-30 4tCLCL-100 UNIT
Input instruction hold after PSEN Input instruction float after PSEN Address valid instruction PSEN address float
External Clock High time time Rise time Fall time
tXHDV Clock rising edge input data valid 10tCLCL-133 NOTES: Parameters valid over operating temperature range unless otherwise specified. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Interfacing 80C52/54/58 devices with float times 45ns permitted. This limited contention will cause damage Port drivers. application note AN457 external memory interfacing.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C, ±10%, 0V1, 24MHz CLOCK SYMBOL 1/tCLCL FIGURE PARAMETER Oscillator frequency Speed versions (24MHz) (33MHz) pulse width Address valid Address hold after valid instruction PSEN PSEN pulse width PSEN valid instruction Input instruction hold after PSEN Input instruction float after PSEN Address valid instruction PSEN address float pulse width pulse width valid data Data hold after Data float after valid data Address valid data Address valid Data valid transition Data hold after Data valid high address float high high High time time Rise time Fall time Serial port clock cycle time Output data setup clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 12tCLCL 10tCLCL-133 2tCLCL-80 tCLCL-25 3tCLCL-50 4tCLCL-75 tCLCL-30 tCLCL-25 7tCLCL-130 tCLCL+25 tCLCL-tCLCX tCLCL-tCHCX 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-90 tCLCL-25 5tCLCL-80 tCLCL-25 3tCLCL-45 3tCLCL-60 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 VARIABLE CLOCK4 33MHz CLOCK UNIT
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX
External Clock
tXHDV Clock rising edge input data valid 10tCLCL-133 NOTES: Parameters valid over operating temperature range unless otherwise specified. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Interfacing 80C52/54/58 devices with float times 45ns permitted. This limited contention will cause damage Port drivers. Variable clock specified oscillator frequencies greater than 16MHz 33MHz. frequencies equal less than 16MHz, 16MHz Electrial Characteristics", page 1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
EXPLANATION SYMBOLS
Each timing symbol five characters. first character always time). other characters, depending their positions, indicate name signal logical status that signal. designations are: Address Clock Input data Logic level high Instruction (program memory contents) Logic level low, PSEN Output data signal Time Valid signal longer valid logic level Float Examples: tAVLL Time address valid low. tLLPL =Time PSEN low.
tLHLL
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR
tLLAX
tPXIZ
PORT
A0-A7
A0-A7
tAVIV
PORT A0-A15 A8-A15
SU00006
Figure External Program Memory Read Cycle
tWHLH
PSEN
tLLDV tLLWL
tRLRH
tAVLL
PORT
tLLAX tRLAZ
A0-A7 FROM
tRLDV tRHDX
DATA
tRHDZ
A0-A7 FROM
INSTR
tAVWL tAVDV
PORT P2.0-P2.7 A8-A15 FROM A0-A15 FROM
SU00025
Figure External Data Memory Read Cycle
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
tWHLH
PSEN
tLLWL
tWLWH
tAVLL
PORT
tLLAX
tQVWX tQVWH
tWHQX
A0-A7 FROM
DATA
A0-A7 FROM
INSTR
tAVWL
PORT
P2.0-P2.7 A8-A15 FROM
A0-A15 FROM
SU00026
Figure External Data Memory Write Cycle
INSTRUCTION
tXLXL
CLOCK
tQVXH
OUTPUT DATA WRITE SBUF
tXHQX
tXHDV
INPUT DATA VALID CLEAR VALID
tXHDX
VALID VALID VALID VALID VALID VALID
SU00027
Figure Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure External Clock Drive
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
VCC-0.5
0.2VCC+0.9 VLOAD 0.2VCC-0.1
VLOAD+0.1V VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
0.45V
NOTE: inputs during testing driven -0.5 logic 0.45V logic `0'. Timing measurements made logic logic `0'.
NOTE: timing purposes, port longer floating when 100mV change from load voltage occurs, begins float when 100mV change from loaded VOH/VOL level occurs. IOH/IOL ±20mA.
SU00717
SU00718
Figure Testing Input/Output
Figure Float Waveform
ACTIVE MODE ICCMAX FREQ.
ACTIVE MODE
IDLE MODE IDLE MODE 4MHz 8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz FREQ XTAL1
SU00768
Figure FREQ Valid only within frequency specifications device under test
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
(NC) CLOCK SIGNAL XTAL2 XTAL1 (NC) CLOCK SIGNAL XTAL2 XTAL1
SU00719
SU00720
Figure Test Condition, Active Mode other pins disconnected
Figure Test Condition, Idle Mode other pins disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure Clock Signal Waveform Tests Active Idle Modes tCLCH tCHCL
(NC) XTAL2 XTAL1
SU00016
Figure Test Condition, Power Down Mode other pins disconnected. 5.5V
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Security Bits
With none security bits programmed code program memory verified. encryption table programmed, code will encrypted when verified. When only security (see Table programmed, MOVC instructions executed from external program memory disabled from fetching code bytes from
internal memory, latched Reset further programming EPROM disabled. When security bits programmed, addition above, verify mode disabled.
Encryption Array
bytes encryption array initially unprogrammed (all 1s).
Table Program Security Bits
PROGRAM LOCK BITS1, PROTECTION DESCRIPTION Program Security features enabled. (Code verify will still encrypted Encryption Array programmed.) MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory, sampled latched Reset, further programming EPROM disabled.
NOTES: programmed. unprogrammed. other combination security bits defined.
80C52 CODE SUBMISSION
When submitting code 80C52, following must specified: byte user data byte encryption security bits. ADDRESS 0000H 1FFFH 2000H 201FH 2020H CONTENT DATA BIT(S) COMMENT User Data Encryption encryption Security enable security disable security Security enable security disable security
2020H
Security When programmed, this effects masked parts: External MOVC disabled, latched Reset. Security When programmed, this inhibits Verify User ROM.
Code file does include options, following information must included with code. each following, check appropriate box, send Philips along with code: Security Security Encryption:
Enabled Enabled
Disabled Disabled Yes, must send file.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
80C54 CODE SUBMISSION
When submitting code 80C54, following must specified: byte user data byte encryption security bits. ADDRESS 0000H 3FFFH 4000H 401FH 4020H CONTENT DATA BIT(S) COMMENT User Data Encryption encryption Security enable security disable security Security enable security disable security
4020H
Security When programmed, this effects masked parts: External MOVC disabled, latched Reset. Security When programmed, this inhibits Verify User ROM.
Code file does include options, following information must included with code. each following, check appropriate box, send Philips along with code: Security Security Encryption:
Enabled Enabled
Disabled Disabled Yes, must send file.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
80C58 CODE SUBMISSION
When submitting code 80C58, following must specified: byte user data byte encryption security bits. submitting file, format follows: ADDRESS 0000H 7FFFH 8000H 801FH 8020H CONTENT DATA BIT(S) COMMENT User Data Encryption encryption Security enable security disable security Security enable security disable security
8020H
Security When programmed, this effects masked parts: External MOVC disabled, latched Reset. Security When programmed, this inhibits Verify User ROM. code file does include options, following information must included with code. each following check appropriate send Philips along with code: Security Security Encryption:
Enabled Enabled
Disabled Disabled Yes, must send file.
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DIP40: plastic dual in-line package; leads (600 mil)
SOT129-1
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
PLCC44: plastic leaded chip carrier; leads
SOT187-2
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
QFP44: plastic quad flat package; leads (lead length mm); body 1.75
SOT307-2
1996
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative Design
Definition
This data sheet contains design target goal specifications product development. Specifications change manner without notice. This data sheet contains preliminary data, supplementary data will published later date. Philips Semiconductors reserves right make changes time without notice order improve design supply best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves right make changes time without notice, order improve design supply best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors Philips Electronics North America Corporation reserve right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified. Applications that described herein these products illustrative purposes only. Philips Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors Philips Electronics North America Corporation Products designed life support appliances, devices, systems where malfunction Philips Semiconductors Philips Electronics North America Corporation Product reasonably expected result personal injury. Philips Semiconductors Philips Electronics North America Corporation customers using selling Philips Semiconductors Philips Electronics North America Corporation Products such applications their risk agree fully indemnify Philips Semiconductors Philips Electronics North America Corporation damages resulting from such improper sale. Philips Semiconductors East Arques Avenue P.O. 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors Philips Electronics North America Corporation register eligible circuits under Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 rights reserved. Printed U.S.A.
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