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Alpha 21164 Microprocessor Data Sheet
Order Number: EC-QAEPD-TE Revision/Update Information: This document supersedes Alpha 21164 Microprocessor Data Sheet (EC-QAEPC-TE).
Digital Equipment Corporation Maynard, Massachusetts
July 1996 Possession, use, copying software described this publication authorized only pursuant valid written license from Digital authorized sublicensor. While Digital believes information included this publication correct date publication, subject change without notice. Digital Equipment Corporation makes representations that products manner described this publication will infringe existing future patent rights, descriptions contained this publication imply granting licenses make, use, sell equipment software accordance with description. Digital Equipment Corporation 1994, 1995, 1996. rights reserved. Printed U.S.A. AlphaGeneration, DEC, DECchip, Digital, Digital Semiconductor, OpenVMS, VAX, DOCUMENT, AlphaGeneration design mark, DIGITAL logo trademarks Digital Equipment Corporation. Digital Semiconductor Digital Equipment Corporation business. GRAFOIL registered trademark Union Carbide Corporation. IEEE registered trademark Institute Electrical Electronics Engineers, Inc. NetWare registered trademark Novell, Inc. OSF/1 registered trademark Open Software Foundation, Inc. Prentice Hall registered trademark Prentice-Hall, Inc. Englewood Cliffs, Windows trademark Microsoft Corporation. other trademarks registered trademarks property their respective owners.
This document prepared using DOCUMENT Version 2.1.
Contents
3.1.1 3.1.2 3.1.3 3.1.4 3.4.1 3.4.2 3.4.3 3.4.4 3.6.1 3.6.2 3.6.3 3.6.4 5.1.1 5.1.2 5.1.3 About This Data Sheet Alpha 21164 Microprocessor Features Microarchitecture Instruction Fetch/Decode Branch Unit Instruction Prefetch Decode Branch Prediction Instruction Translation Buffer Interrupts Integer Execution Unit Floating-Point Execution Unit Memory Address Translation Unit Data Translation Buffer Miss Address File Store Execution Write Buffer Cache Control Interface Unit Cache Organization Data Cache Instruction Cache Second-Level Cache External Cache Serial Read-Only Memory Interface Pipeline Organization Pinout Signal Descriptions Assignment Alpha 21164 Packaging Alpha 21164 Microprocessor Logic Symbol Alpha 21164 Signal Names Functions Alpha 21164 Microprocessor Functional Overview Clocks Clock System Clock Reference Clock
5.2.1 5.2.2 5.3.1 5.4.1 5.4.2 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.1.11 8.1.12 8.1.13
Board-Level Backup Cache Interface Bcache Victim Buffers Cache Coherence Protocol System Interface Commands Addresses Interrupts Interrupt Signals During Initialization Interrupt Signals During Normal Operation Test Modes Normal Test Interface Mode Serial Interface Port Serial Terminal Port IEEE 1149.1 Test Access Port Test Status Signals Alpha Architecture Basics Architecture Addressing Integer Data Types Floating-Point Data Types Alpha 21164 Microprocessor IEEE Floating-Point Conformance Internal Processor Registers Instruction Fetch/Decode Unit Branch Unit (Ibox) IPRs Istream Translation Buffer Register (ITB_TAG) Instruction Translation Buffer Page Table Entry (ITB_PTE) Register Instruction Translation Buffer Address Space Number (ITB_ASN) Register Instruction Translation Buffer Page Table Entry Temporary (ITB_PTE_TEMP) Register Instruction Translation Buffer Invalidate Process (ITB_IAP) Register Instruction Translation Buffer Invalidate (ITB_IA) Register Instruction Translation Buffer (ITB_IS) Register Formatted Faulting Virtual Address (IFAULT_VA_FORM) Register Virtual Page Table Base Register (IVPTBR) Icache Parity Error Status (ICPERR_STAT) Register Icache Flush Control (IC_FLUSH_CTL) Register Exception Address (EXC_ADDR) Register Exception Summary (EXC_SUM) Register
8.1.14 8.1.15 8.1.16 8.1.17 8.1.18 8.1.19 8.1.20 8.1.21 8.1.22 8.1.23 8.1.24 8.1.25 8.1.26 8.1.27 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 8.2.14 8.2.15 8.2.16 8.2.17
Exception Mask (EXC_MASK) Register Base Address (PAL_BASE) Register Ibox Current Mode (ICM) Register Ibox Control Status Register (ICSR) Interrupt Priority Level Register (IPLR) Interrupt (INTID) Register Asynchronous System Trap Request Register (ASTRR) Asynchronous System Trap Enable Register (ASTER) Software Interrupt Request Register (SIRR) Hardware Interrupt Clear (HWINT_CLR) Register Interrupt Summary Register (ISR) Serial Line Transmit (SL_XMIT) Register Serial Line Receive (SL_RCV) Register Performance Counter (PMCTR) Register Memory Address Translation Unit (Mbox) IPRs Dstream Translation Buffer Address Space Number (DTB_ASN) Register Dstream Translation Buffer Current Mode (DTB_CM) Register Dstream Translation Buffer (DTB_TAG) Register Dstream Translation Buffer Page Table Entry (DTB_PTE) Register Dstream Translation Buffer Page Table Entry Temporary (DTB_PTE_TEMP) Register Dstream Memory Management Fault Status (MM_STAT) Register Faulting Virtual Address (VA) Register Formatted Virtual Address (VA_FORM) Register Mbox Virtual Page Table Base Register (MVPTBR) Dcache Parity Error Status (DC_PERR_STAT) Register Dstream Translation Buffer Invalidate Process (DTB_IAP) Register Dstream Translation Buffer Invalidate (DTB_IA) Register Dstream Translation Buffer Invalidate Single (DTB_IS) Register Mbox Control Register (MCSR) Dcache Mode (DC_MODE) Register Miss Address File Mode (MAF_MODE) Register Dcache Flush (DC_FLUSH) Register
8.2.18 8.2.19 8.2.20 8.2.21 8.2.22 8.2.23 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.5.1 8.5.2 9.1.1 10.1 10.2 10.3 10.4 10.5 10.6 11.1
Alternate Mode (ALT_MODE) Register Cycle Counter (CC) Register Cycle Counter Control (CC_CTL) Register Dcache Test Control (DC_TEST_CTL) Register Dcache Test (DC_TEST_TAG) Register Dcache Test Temporary (DC_TEST_TAG_TEMP) Register External Interface Control (Cbox) IPRs Scache Control (SC_CTL) Register FFF0 00A8) Scache Status (SC_STAT) Register FFF0 00E8) Scache Address (SC_ADDR) Register FFF0 0188) Bcache Control (BC_CONTROL) Register FFF0 0128) Bcache Configuration (BC_CONFIG) Register FFF0 01C8) Bcache Address (BC_TAG_ADDR) Register FFF0 0108) External Interface Status (EI_STAT) Register FFF0 0168) External Interface Address (EI_ADDR) Register FFF0 0148) Fill Syndrome (FILL_SYN) Register FFF0 0068) PALcode Storage Registers Restrictions Cbox PALcode Restrictions PALcode Restrictions-Instruction Definitions PALcode PALcode Entry Points PALcode Trap Entry Points Required PALcode Function Codes Opcodes Reserved PALcode Alpha Instruction Summary Opcodes Reserved Digital Opcodes Reserved PALcode IEEE Floating-Point Instructions Floating-Point Instructions Opcode Summary Required PALcode Function Codes Electrical Data Electrical Characteristics
11.2 Characteristics 11.2.1 Power Supply 11.2.2 Input Signal Pins 11.2.3 Output Signal Pins 11.3 Clocking Scheme 11.3.1 Input Clocks 11.3.2 Clock Termination Impedance Levels 11.3.3 Coupling 11.4 Characteristics 11.4.1 Test Configuration 11.4.2 Timing 11.4.3 Digital Phase-Locked Loop 11.4.4 Timing-Additional Signals 11.4.5 Timing Test Features 11.4.6 Icache BiSt Operation Timing 11.4.7 Automatic SROM Load Timing 11.4.8 Clock Test Modes 11.4.9 Normal Mode 11.4.10 Chip Test Mode 11.4.11 Module Test Mode 11.4.12 Clock Test Reset Mode 11.4.13 IEEE 1149.1 (JTAG) Performance 11.5 Power Supply Considerations 11.5.1 Decoupling 11.5.2 Power Supply Sequencing Thermal Management 12.1 Operating Temperature 12.2 Heat Sink Specifications 12.3 Thermal Design Considerations Mechanical Specifications
Figures
Alpha 21164 Microprocessor Block/Pipe Flow Diagram Instruction Pipeline Stages Alpha 21164 View (Pin Down) Alpha 21164 Bottom View (Pin Alpha 21164 Microprocessor Logic Symbol Alpha 21164 Clock Signals Alpha 21164 Uniprocessor Clock Alpha 21164 Reference Clock Multiprocessor Systems
Alpha 21164 Bcache Interface Signals Alpha 21164 System Interface Signals Alpha 21164 Interrupt Signals Alpha 21164 Test Signals Istream Translation Buffer Register (ITB_TAG) Instruction Translation Buffer Page Table Entry (ITB_PTE) Register Write Format Instruction Translation Buffer Page Table Entry (ITB_PTE) Register Read Format Instruction Translation Buffer Address Space Number (ITB_ASN) Register Instruction Translation Buffer (ITB_IS) Register Formatted Faulting Virtual Address (IFAULT_VA_FORM) Register (NT_Mode=0) Formatted Faulting Virtual Address (IFAULT_VA_FORM) Register (NT_Mode=1) Virtual Page Table Base Register (IVPTBR) (NT_Mode=0) Virtual Page Table Base Register (IVPTBR) (NT_Mode=1) Icache Parity Error Status (ICPERR_STAT) Register Exception Address (EXC_ADDR) Register Exception Summary (EXC_SUM) Register Exception Mask (EXC_MASK) Register Base Address (PAL_BASE) Register Ibox Current Mode (ICM) Register Ibox Control Status Register (ICSR) Interrupt Priority Level Register (IPLR) Interrupt (INTID) Register Asynchronous System Trap Request Register (ASTRR) Asynchronous System Trap Enable Register (ASTER) Software Interrupt Request Register (SIRR) Hardware Interrupt Clear (HWINT_CLR) Register Interrupt Summary Register (ISR) Serial Line Transmit (SL_XMIT) Register Serial Line Receive (SL_RCV) Register Performance Counter (PMCTR) Register Dstream Translation Buffer Address Space Number (DTB_ASN) Register
viii
Dstream Translation Buffer Current Mode (DTB_CM) Register Dstream Translation Buffer (DTB_TAG) Register Dstream Translation Buffer Page Table Entry (DTB_PTE) Register-Write Format Dstream Translation Buffer Page Table Entry Temporary (DTB_PTE_TEMP) Register Dstream Memory Management Fault Status (MM_STAT) Register Faulting Virtual Address (VA) Register Formatted Virtual Address (VA_FORM) Register (NT_Mode=1) Formatted Virtual Address (VA_FORM) Register (NT_Mode=0) Mbox Virtual Page Table Base Register (MVPTBR) Dcache Parity Error Status (DC_PERR_STAT) Register Dstream Translation Buffer Invalidate Single (DTB_IS) Register Mbox Control Register (MCSR) Dcache Mode (DC_MODE) Register Miss Address File Mode (MAF_MODE) Register Alternate Mode (ALT_MODE) Register Cycle Counter (CC) Register Cycle Counter Control (CC_CTL) Register Dcache Test Control (DC_TEST_CTL) Register Dcache Test (DC_TEST_TAG) Register Dcache Test Temporary (DC_TEST_TAG_TEMP) Register Scache Control (SC_CTL) Register Scache Status (SC_STAT) Register Scache Address (SC_ADDR) Register Bcache Control (BC_CONTROL) Register Bcache Configuration (BC_CONFIG) Register Bcache Address (BC_TAG_ADDR) Register External Interface Status (EI_STAT) Register External Interface Address (EI_ADDR) Register Fill Syndrome (FILL_SYN) Register osc_clk_in_h,l Input Network Terminations
Clock Input Differential Impedance Input/Output Timing Bcache Timing sys_clk System Timing ref_clk System Timing BiSt Timing Event-Time Line SROM Load Timing Event-Time Line Serial Load Timing Type Heat Sink Type Heat Sink Package Dimensions
Tables
Alphabetic Signal List Alpha 21164 Signal Descriptions Alpha 21164 Signal Descriptions Function Bcache States Cache Coherency Protocols Alpha 21164 Commands System System Commands 21164 System Clock Divisor System Clock Delay Alpha 21164 Test Port Pins Ibox, Mbox, Dcache, PALtemp Encodings Granularity Hint Bits ITB_PTE_TEMP Read Format Icache Parity Error Status Register Fields Exception Summary Register Fields Ibox Control Status Register Fields Software Interrupt Request Register Fields Hardware Interrupt Clear Register Fields Interrupt Summary Register Fields Serial Line Transmit Register Fields Serial Line Receive Register Fields Performance Counter Register Fields PMCTR Counter Select Options Measurement Mode Control
Dstream Memory Management Fault Status Register Fields Formatted Virtual Address Register Fields Dcache Parity Error Status Register Fields Mbox Control Register Fields Dcache Mode Register Fields Miss Address File Mode Register Fields Alternate Mode Register Settings Cycle Counter Control Register Fields Dcache Test Control Register Fields Dcache Test Register Fields Dcache Test Temporary Register Fields Cbox Internal Processor Register Descriptions Scache Control Register Fields Scache Status Register Fields SC_CMD Field Descriptions Scache Address Register Fields Bcache Control Register Fields PM_MUX_SEL Register Fields Bcache Configuration Register Fields Bcache Address Register Fields Loading Locking Rules External Interface Registers EI_STAT Register Fields Syndromes Single-Bit Errors Cbox PALcode Restrictions PALcode Restrictions Table PALcode Trap Entry Points Required PALcode Function Codes Opcodes Reserved PALcode Instruction Format Opcode Notation Architecture Instructions Opcodes Reserved Digital Opcodes Reserved PALcode IEEE Floating-Point Instruction Function Codes Floating-Point Instruction Function Codes Opcode Summary
Required PALcode Function Codes Alpha 21164 Absolute Maximum Ratings CMOS Input/Output Characteristics Input Clock Specification Bcache Loop Timing Output Driver Characteristics Alpha 21164 System Clock Output Timing Alpha 21164 Reference Clock Input Timing ref_clk System Timing Stages Input Timing sys_clk_out- ref_clk_in-Based Systems Output Timing sys_clk_out- ref_clk_in-Based Systems Bcache Control Signal Timing BiSt Timing Some System Clock Ratios, Port Mode=Normal (System Cycles) BiSt Timing Some System Clock Ratios, Port Mode=Normal (CPU Cycles) SROM Load Timing Some System Clock Ratios (System Cycles) SROM Load Timing Some System Clock Ratios (CPU Cycles) Test Modes IEEE 1149.1 Circuit Performance Specifications Various Airflows Maximum Various Airflows
About This Data Sheet
This data sheet provides technical overview Alpha 21164 microprocessor, including: Functional units Signal descriptions External interface Internal processor registers (IPRs) Privileged architecture library code (PALcode) instructions Electrical characteristics Thermal characteristics Mechanical packaging
This data sheet intended provide reader with everything needed begin chip implementation. more comprehensive description 21164 Alpha architecture, refer documents listed Technical Support Ordering Information section located this document. Document Conventions Throughout this data sheet, following conventions used: INTn refers NATURALLY ALIGNED groups 8-bit bytes. example: INT16-The four least significant address bits INT8-The three least significant address bits INT4-The least significant address bits Values used some tables. signifies don't care convention, which determined system designer.
Preliminary-Subject Change-July 1996
Alpha 21164 Microprocessor Features
Fully pipelined 64-bit advanced RISC architecture supports multiple operating systems, including: Microsoft Windows OSF/1 OpenVMS 266-MHz through 300-MHz operation Superscalar 4-way instruction issue High-bandwidth (128-bit) interface Peak execution rate 1200 MIPS 0.50-m CMOS technology Three onchip caches: 8K-byte, direct-mapped, instruction cache 8K-byte, dual-ported, direct-mapped, write-through data cache 96K-byte, 3-way, set-associative, write-back data instruction cache Supports optional board-level cache ranging from byte bytes
21164 microprocessor implements IEEE S_floating T_floating, F_floating G_floating data types supports longword (32-bit) quadword (64-bit) integers. Provides byte (8-bit) word (16-bit) support byte-manipulation instructions. Limited hardware support provided D_floating data type.
Preliminary-Subject Change-July 1996
Microarchitecture
Alpha 21164 Microprocessor high-performance implementation Digital's Alpha architecture. following sections provide overview chip's architecture major functional units. Figure block diagram 21164. larger version this figure printed foldout page Alpha 21164 Microprocessor Hardware Reference Manual. 21164 consists following sections (Figure Instruction fetch/decode branch unit (Ibox) Integer execution unit (Ebox) Memory address translation unit (Mbox) Cache control interface unit (Cbox) Floating-point execution unit (Fbox) Data cache (Dcache) Instruction cache (Icache) Secondary cache (Scache) Serial read-only memory (SROM) interface
Preliminary-Subject Change-July 1996
Pipe Stages
Floating-Point Execution Unit
Load Data Floating-Point Divider
Figure
Floating-Point Pipe Divider Floating- Point Register File Floating-Point Multiply Pipe Floating-Point Store Data Instruction Slot Logic Integer Unit Store Data Integer Multiplier
Istream Fill
Refill Buffer
Instruction Buffer
Next Index Logic
Instruction Cache
Bytes 32-Byte Block Direct-Mapped
Preliminary-Subject Change-July 1996
Integer Pipe Integer Register File ADD, LOG, SHIFT, IMUL, CMP, CMOV, BYTE, WORD
Program Counter Logic
Instruction Translation Buffer
48-Entry Associative Integer Pipe Issue Scoreboard Logic Data Cache (Dcache) Bytes 32-Byte Block Direct-Mapped Dual Read-Ported Floating-Point Unit Data from Pins Miss Address File Second-Level Cache (Scache) Bytes 64-Byte Block 3-Way Set-Associative Address Pins Write Buffer Store Data 32-Byte Entries Instruction Data Fills Backup Cache (Bcache) Byte Bytes Direct-Mapped (Offchip) Address File Entries ADD, LOG, CMP, CMOV
Integer Execution Unit
Instruction Fetch/Decode Unit
Store Fill Data
Dual-Read Translation Buffer 64-Entry Associative Dual-Ported Instruction Stream Miss (Physical Address) Data Misses Istream Misses
Memory Address Translation Unit
Cache Control Interface Unit
MK-1455-13
Alpha 21164 Microprocessor Block/Pipe Flow Diagram
Instruction Fetch/Decode Branch Unit
primary function instruction fetch/decode branch unit (Ibox) manage issue instructions Ebox, Mbox, Fbox. also manages instruction cache. Ibox contains: Prefetcher instruction buffer Instruction slot issue logic Program counter (PC) branch prediction logic 48-entry instruction translation buffers (ITBs) Abort logic Register conflict logic Interrupt exception logic
3.1.1 Instruction Prefetch Decode Ibox handles only NATURALLY ALIGNED groups four instructions (INT16). Ibox does advance group four instructions until instructions group issued. branch middle INT16 group occurs, then Ibox attempts issue instructions from branch target current INT16, then proceeds next INT16 instructions after instructions target INT16 issued. Thus, proper code scheduling required achieve optimal performance. 3.1.2 Branch Prediction branch unit, prediction logic, also part Ibox. Branch prediction necessary predict begin fetching target instruction stream before branch jump instruction issued. Each instruction location instruction cache (Icache) contains 2-bit history state record outcome branch instructions. 3.1.3 Instruction Translation Buffer Ibox includes 48-entry, fully associative instruction translation buffer (ITB). buffer stores recently used instruction stream (Istream) address translations protection information pages ranging from kilobytes uses not-last-used replacement algorithm. 21164 provides optional translation extensions called superpages. Access superpages allowed only while executing privileged mode. superpage maps virtual address bits <39:13> physical address bits <39:13>, one-to-one basis, when virtual address bits <42:41> equal
Preliminary-Subject Change-July 1996
other superpage maps virtual address bits <29:13> physical address bits <29:13>, one-to-one basis, forces physical address bits <39:30> when virtual address bits <42:30> equal 1FFE(hex).
3.1.4 Interrupts Ibox exception logic supports three sources interrupts: Hardware interrupts There seven level-sensitive hardware interrupt sources supplied following signals: irq_h<3:0> sys_mch_chk_irq_h pwr_fail_irq_h mch_halt_irq_h Software interrupts There prioritized software interrupts sourced onchip internal processor register (IPR). Asynchronous system traps There four asynchronous system traps (ASTs) controlled onchip IPRs. Most interrupts independently masked onchip enable registers. addition, interrupts qualified current processor mode. interrupts disabled when processor executing PALcode.
Integer Execution Unit
integer execution unit (Ebox) contains 64-bit integer execution pipelines-E0 which include following: adders logic boxes barrel shifter Byte-manipulation logic integer multiplier
Ebox also includes 40-entry, 64-bit integer register file (IRF) that contains integer registers defined Alpha architecture PALshadow registers. register file four read ports write ports, which provide operands both integer execution pipelines accept results from both pipes. register file also accepts load instruction results (memory data) same write ports.
Preliminary-Subject Change-July 1996
Floating-Point Execution Unit
onchip, pipelined floating-point unit (FPU) execute both IEEE floating-point instructions. 21164 supports IEEE S_floating T_floating data types, rounding modes. also supports F_floating G_floating data types, provides limited support D_floating format. contains: 32-entry, 64-bit floating-point register file (FRF). user-accessible control register. floating-point multiply pipeline. floating-point pipeline-The floating-point divide unit associated with floating-point pipeline pipelined.
accept instructions every cycle, with exception floatingpoint divide instructions. result latency nondivide, floating-point instructions four cycles.
Memory Address Translation Unit
memory address translation unit (Mbox) contains three major sections: Data translation buffer (dual ported) Miss address file (MAF) Write buffer address file
Mbox receives virtual addresses every cycle from Ebox. translation buffer generates corresponding physical addresses access control information each virtual address. 21164 implements 43-bit virtual address 40-bit physical address. 3.4.1 Data Translation Buffer 64-entry, fully associative, dual-read-ported data translation buffer (DTB) stores recently used data stream (Dstream) page table entries (PTEs). Each entry supports four granularity hint-bit combinations, that single entry provide translation contiguously mapped, 8K-byte pages. also supports register-enabled superpage extension. superpage maps provide virtual-to-physical address translation regions virtual address space.
Preliminary-Subject Change-July 1996
3.4.2 Miss Address File Mbox begins execution each load instruction translating virtual address accessing data cache (Dcache). Translation Dcache read operations occur parallel. addressed location found Dcache hit), then data from Dcache formatted written either integer register file (IRF) floating-point register file (FRF). formatting required depends particular load instruction executed. data found Dcache miss), then address, target register number, formatting information entered miss address file (MAF). performs load-merging function. When load miss occurs, each entry checked contains load miss that addresses same Dcache (32-byte) block. does, certain merging rules satisfied, then load miss merged with existing entry. This allows Mbox service more load misses with data fill from Cbox. There entries load misses four more Ibox instruction fetches prefetches. Load misses usually highest Mbox priority. 3.4.3 Store Execution Dcache follows write-through protocol. During execution store instruction, Mbox probes Dcache determine whether location overwritten currently cached. Dcache hit), Dcache updated. Regardless Dcache state, Mbox forwards data Cbox. load instruction that issued cycle after store instruction pipeline creates conflict both load store operations access same memory location. (The store instruction updated location when load instruction reads it.) This conflict handled forcing load instruction take replay trap; that Ibox flushes pipeline restarts execution from load instruction. time load instruction arrives Dcache second time, conflicting store instruction written Dcache load instruction executed normally. Replay traps avoided scheduling load instruction issue three cycles after store instruction. load instruction scheduled issue cycles after store instruction, then will issue-stalled cycle. 3.4.4 Write Buffer Mbox also contains write buffer that 32-byte entries. write buffer provides finite, high-bandwidth resource receiving store data minimize number stall cycles.
Preliminary-Subject Change-July 1996
Cache Control Interface Unit
cache control interface unit (Cbox) processes accesses sent Mbox implements memory-related external interface functions, particularly coherence protocol functions write-back caching. controls second-level cache (Scache) optional board-level backup cache (Bcache). Cbox handles instruction primary Dcache read misses, performs function writing data from write buffer into shared coherent memory subsystem, major role executing Alpha memory barrier (MB) instruction. Cbox also controls 128-bit bidirectional data bus, address bus, control.
Cache Organization
21164 three onchip caches-a primary data cache, primary instruction cache, second-level combined data instruction cache. memory cells onchip caches fully static, 6-transistor, CMOS structures. 21164 also provides control optional board-level, external cache. 3.6.1 Data Cache data cache (Dcache) dual-read-ported, single-write-ported, 8K-byte cache. write-through, read-allocate, direct-mapped, physical cache with 32-byte blocks. 3.6.2 Instruction Cache instruction cache (Icache) 8K-byte, virtual, direct-mapped cache with 32-byte blocks. Each block contains: 7-bit address space number (ASN) field defined Alpha architecture 1-bit address space match (ASM) field defined Alpha architecture 1-bit PALcode (physically addressed) indicator
Software, rather than Icache hardware, maintains Icache coherence with memory.
Preliminary-Subject Change-July 1996
3.6.3 Second-Level Cache second-level cache (Scache) 96K-byte, 3-way, set-associative, physical, write-back, write-allocate cache with 64-byte blocks. mixed data instruction cache. Scache fully pipelined; processes read write operations rate INT16 cycle alternate between read write accesses without bubble cycles. When operating 32-byte block mode, Scache 64-byte blocks with 32-byte subblocks, block. configured bytes, Scache organized three sets blocks, with each block divided into 32-byte subblocks. configured bytes, Scache three sets 64-byte blocks. 3.6.4 External Cache Cbox implements control optional, external, direct-mapped, physical, write-back, write-allocate cache with 64-byte blocks. 21164 supports board-level cache sizes megabytes.
Serial Read-Only Memory Interface
serial read-only memory (SROM) interface provides initialization data load path from system SROM instruction cache. Following initialization, this interface function diagnostic port using privileged architecture library code (PALcode).
Pipeline Organization
21164 7-stage 7-cycle) pipeline integer operate memory reference instructions, 9-stage pipeline floating-point operate instructions. Ibox maintains state pipeline stages track outstanding register write operations. Figure shows integer operate, memory reference, floating-point operate pipelines Ibox, FPU, Ebox, Mbox. first four stages executed Ibox. Remaining stages executed Ebox, Fbox, Mbox, Cbox.
Preliminary-Subject Change-July 1996
Figure Instruction Pipeline Stages
Instruction Cache Read Instruction Buffer, Branch Decode, Determine Next Slot Function Unit Register File Access Checks, Integer Register File Access Integer Operate Pipeline
First Integer Operate Stage Needed, Second Integer Operate Stage Write Integer Register File FloatingPoint Pipeline
Arithmetic, logical, shift compare instructions complete pipeline stage (1-cycle latency). CMOV completes stage (2-cycle latency). IMULL 9-cycle latency. CMOV issue parallel (0-cycle latency) with dependent instruction.
Floating-Point Register File Access First Floating-Point Operate Stage Write Floating-Point Register File, Last Floating-Point Operate Stage Memory Reference Pipeline
Dcache Read Begins Dcache Read Ends Dcache Data, Store Writes Dcache, Scache, Access Scache Data Access Begins Scache Data Access Ends Fill Dcache Scache Data
LJ-03560-TI0A
Preliminary-Subject Change-July 1996
Pinout Signal Descriptions
Sections list describe 21164 microprocessor external signals, their associated pins.
Assignment
21164 package pins aligned interstitial grid array (IPGA) design. Table lists 21164 signal pins their corresponding grid array (PGA) locations alphabetic order. There functional signal pins, spare (unused) signal pins, power (Vdd) pins, ground (Vss) pins. Table Alphabetic Signal List
Signal addr_bus_req_h addr_h<5> addr_h<8> addr_h<11> addr_h<14> addr_h<17> addr_h<20> addr_h<23> addr_h<26> addr_h<29> addr_h<32> addr_h<35> addr_h<38> addr_res_h<1> cfail_h cmd_h<0> cmd_h<3> data_bus_req_h data_check_h<2> Location BC13 AW13 AV12 BA09 BC07 AW07 AW37 BC37 BA35 AV32 AW31 BC31 Signal addr_cmd_par_h addr_h<6> addr_h<9> addr_h<12> addr_h<15> addr_h<18> addr_h<21> addr_h<24> addr_h<27> addr_h<30> addr_h<33> addr_h<36> addr_h<39> addr_res_h<2> clk_mode_h<0> cmd_h<1> cpu_clk_out_h data_check_h<0> data_check_h<3> Location BA13 BC11 AW11 AV10 BA07 BC05 AV36 AW35 BC35 BA33 AV30 BB30 AU21 BA25 Signal addr_h<4> addr_h<7> addr_h<10> addr_h<13> addr_h<16> addr_h<19> addr_h<22> addr_h<25> addr_h<28> addr_h<31> addr_h<34> addr_h<37> addr_res_h<0> cack_h clk_mode_h<1> cmd_h<2> dack_h data_check_h<1> data_check_h<4> Location BB14 AV14 BA11 BC09 AW09 AV08 BC39 BA37 AV34 AW33 BC33 BA31 BA23
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Preliminary-Subject Change-July 1996
Table (Cont.) Alphabetic Signal List
Signal data_check_h<5> data_check_h<8> data_check_h<11> data_check_h<14> data_h<1> data_h<4> data_h<7> data_h<10> data_h<13> data_h<16> data_h<19> data_h<22> data_h<25> data_h<28> data_h<31> data_h<34> data_h<37> data_h<40> data_h<43> data_h<46> data_h<49> data_h<52> data_h<55> data_h<58> data_h<61> data_h<64> data_h<67> data_h<70> Location AA43 AC41 AD38 AE39 AF38 AJ41 AK42 AK38 AN41 AR43 AR39 AT38 AW41 Signal data_check_h<6> data_check_h<9> data_check_h<12> data_check_h<15> data_h<2> data_h<5> data_h<8> data_h<11> data_h<14> data_h<17> data_h<20> data_h<23> data_h<26> data_h<29> data_h<32> data_h<35> data_h<38> data_h<41> data_h<44> data_h<47> data_h<50> data_h<53> data_h<56> data_h<59> data_h<62> data_h<65> data_h<68> data_h<71> Location AA39 AB38 AC39 AE43 AG43 AG39 AH38 AL43 AL39 AM38 AR41 AU43 AU39 AV38 Signal data_check_h<7> data_check_h<10> data_check_h<13> data_h<0> data_h<3> data_h<6> data_h<9> data_h<12> data_h<15> data_h<18> data_h<21> data_h<24> data_h<27> data_h<30> data_h<33> data_h<36> data_h<39> data_h<42> data_h<45> data_h<48> data_h<51> data_h<54> data_h<57> data_h<60> data_h<63> data_h<66> data_h<69> data_h<72> Location AA41 AC43 AD42 AE41 AG41 AJ43 AJ39 AL41 AN43 AN39 AP38 AU41 AW43 AW39
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Preliminary-Subject Change-July 1996
Table (Cont.) Alphabetic Signal List
Signal data_h<73> data_h<76> data_h<79> data_h<82> data_h<85> data_h<88> data_h<91> data_h<94> data_h<97> data_h<100> data_h<103> data_h<106> data_h<109> data_h<112> data_h<115> data_h<118> data_h<121> data_h<124> data_h<127> dc_ok_h fill_id_h index_h<4> index_h<7> index_h<10> index_h<13> index_h<16> index_h<19> index_h<22> Location AA03 AC01 AD02 AE03 AG03 AJ01 AJ05 AL03 AN01 AN05 AP06 AU03 AW01 AW05 AU23 Signal data_h<74> data_h<77> data_h<80> data_h<83> data_h<86> data_h<89> data_h<92> data_h<95> data_h<98> data_h<101> data_h<104> data_h<107> data_h<110> data_h<113> data_h<116> data_h<119> data_h<122> data_h<125> data_ram_oe_h fill_error_h fill_nocheck_h index_h<5> index_h<8> index_h<11> index_h<14> index_h<17> index_h<20> index_h<23> Location AA01 AC03 AD06 AE05 AF06 AJ03 AK02 AK06 AN03 AR01 AR05 AT06 AW03 Signal data_h<75> data_h<78> data_h<81> data_h<84> data_h<87> data_h<90> data_h<93> data_h<96> data_h<99> data_h<102> data_h<105> data_h<108> data_h<111> data_h<114> data_h<117> data_h<120> data_h<123> data_h<126> data_ram_we_h fill_h idle_bc_h index_h<6> index_h<9> index_h<12> index_h<15> index_h<18> index_h<21> index_h<24> Location AA05 AB06 AC05 AE01 AG01 AG05 AH06 AL01 AL05 AM06 AR03 AU01 AU05 AV06
(continued next page)
Preliminary-Subject Change-July 1996
Table (Cont.) Alphabetic Signal List
Signal index_h<25> int4_valid_h<2> irq_h<1> mch_hlt_irq_h perf_mon_h pwr_fail_irq_h scache_set_h<1> srom_data_h st_clk_h sys_clk_out1_l sys_mch_chk_irq_h tag_data_h<20> tag_data_h<23> tag_data_h<26> tag_data_h<29> tag_data_h<32> tag_data_h<35> tag_data_h<38> tag_ram_oe_h tag_valid_h tdo_h test_status_h<1> victim_pending_h Location AU27 AU25 AW29 AV26 BC19 BB24 BA27 BA17 AV16 Signal int4_valid_h<0> int4_valid_h<3> irq_h<2> osc_clk_in_h port_mode_h<0> ref_clk_in_h shared_h srom_oe_l system_lock_flag_h sys_clk_out2_h sys_reset_l tag_data_h<21> tag_data_h<24> tag_data_h<27> tag_data_h<30> tag_data_h<33> tag_data_h<36> tag_data_par_h tag_ram_we_h tck_h temp_sense tms_h spare_in<438> Location BC29 BC21 AY20 AW25 AW19 AV24 BC27 AW17 AW15 AV18 Signal int4_valid_h<1> irq_h<0> irq_h<3> osc_clk_in_l port_mode_h<1> scache_set_h<0> srom_clk_h srom_present_l sys_clk_out1_h sys_clk_out2_l tag_ctl_par_h tag_data_h<22> tag_data_h<25> tag_data_h<28> tag_data_h<31> tag_data_h<34> tag_data_h<37> tag_dirty_h tag_shared_h tdi_h test_status_h<0> trst_l spare_io<250> Location BA29 AW27 BB22 BB20 BA19 AV20 AW23 BC25 BC17 BA15 BC15 AV28
(continued next page)
Preliminary-Subject Change-July 1996
Table (Cont.) Alphabetic Signal List
Signal Vss-Metal planes Location A03, A41, AA07, AA37, AC07, AC37, AD04, AD40, AF02, AF42, AG07, AG37, AH04, AH40, AL07, AL37, AM04, AM40, AP02, AP42, AR07, AR37, AT04, AT40, AU09, AU13, AU17, AU31, AU35, AV02, AV22, AV42, AW21, AY04, AY08, AY12, AY16, AY22, AY24, AY28, AY32, AY36, AY40, B02, B06, B10, B18, B26, B34, B38, B42, BA01, BA21, BA43, BB02, BB06, BB10, BB18, BB26, BB34, BB38, BB42, BC03, BC41, C01, C43, D04, D08, D12, D16, D20, D24, D28, D32, D36, D40, F02, F42, G09, G13, G17, G31, G35, H04, H40, J07, J37, K02, K42, M04, M40, N07, N37, T04, T40, U07, U37, V02, V42, Y04, AB02, AB04, AB40, AB42, AE07, AE37, AF04, AF40, AH02, AH42, AJ07, AJ37, AK04, AK40, AM02, AM42, AN07, AN37, AP04, AP40, AT02, AT42, AU07, AU11, AU15, AU19, AU29, AU33, AU37, AV04, AV40, AY02, AY06, AY10, AY14, AY18, AY26, AY30, AY34, AY38, AY42, B04, B08, B12, B16, B22, B28, B32, B36, B40, BA03, BA05, BA39, BA41, BB04, BB08, BB12, BB16, BB28, BB32, BB36, BB40, BC23, C03, C05, C39, C41, D02, D06, D10, D14, D18, D22, D26, D30, D34, D38, D42, F04, F40, G11, G15, G19, G29, G33, G37, H02, H42, K04, K40, L07, L37, M02, M42, P04, P40, R07, R37, T02, T42, V04, V40, W07,
Metal planes
Metal Metal
plane 2-Seal ring connection tied plane 5-Heat slug braze connections tied
Preliminary-Subject Change-July 1996
Alpha 21164 Packaging
Figure shows 21164 pinout from view with pins facing down. Figure
Alpha 21164 View (Pin Down)
21164 View (Pin Down)
LJ-03453-TI0A
Preliminary-Subject Change-July 1996
Figure shows 21164 pinout from bottom view with pins facing Figure
Alpha 21164 Bottom View (Pin
21164 Bottom View (Pin
LJ-03413-TI0B
Alpha 21164 Microprocessor Logic Symbol
Figure shows logic symbol 21164 chip.
Preliminary-Subject Change-July 1996
Figure
Alpha 21164 Microprocessor Logic Symbol
21164
addr_bus_req_h cack_h cfail_h dack_h data_bus_req_h fill_h fill_error_h fill_id_h fill_nocheck_h idle_bc_h shared_h system_lock_flag_h addr_h<39:4>
System/Bcache Interface
addr_cmd_par_h addr_res_h<2:0> cmd_h<3:0> data_h<127:0> data_check_h<15:0> data_ram_oe_h data_ram_we_h index_h<25:4> int4_valid_h<3:0> scache_set_h<1:0> st_clk_h tag_ctl_par_h tag_data_h<38:20> tag_data_par_h tag_dirty_h tag_ram_oe_h tag_ram_we_h tag_shared_h tag_valid_h victim_pending_h
irq_h<3:0> mch_hlt_irq_h pwr_fail_irq_h sys_mch_chk_irq_h clk_mode_h<1:0> osc_clk_in_h osc_clk_in_l ref_clk_in_h sys_reset_l dc_ok_h perf_mon_h port_mode_h<1:0> srom_data_h tdi_h temp_sense tms_h
Interrupts
cpu_clk_out_h
Clocks
sys_clk_out1_h sys_clk_out1_l sys_clk_out2_h sys_clk_out2_l srom_clk_h
Test Modes Miscellaneous
srom_oe_l srom_present_l tck_h tdo_h test_status_h<1:0> trst_l
MK145506
Preliminary-Subject Change-July 1996
Alpha 21164 Signal Names Functions
following table defines 21164 signal types referred this section:
Signal Type Definition Bidirectional Input only Output only
remaining tables describe function each 21164 external signal. Table lists signals alphanumeric order. This table provides full signal descriptions. Table lists signals function provides abbreviated description. Table
Signal addr_h<39:4>
Alpha 21164 Signal Descriptions
Type Count Description Address bus. These bidirectional signals provide address requested data operation between 21164 system. asserted, then reference noncached, memory space. Address request. system interface uses this signal gain control addr_h<39:4>, addr_cmd_par_h, cmd_h<3:0> pins. Address command parity. This parity current command address buses. 21164 takes machine check parity error detected. system should same detects error. Address response bits <0>. system commands, 21164 uses these pins indicate state block Scache: Bits Command NOACK ACK/Scache ACK/Bcache Meaning Nothing. Data found clean. Data from Scache. Data from Bcache. (continued next page)
addr_bus_req_h
addr_cmd_par_h
addr_res_h<1:0>
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal addr_res_h<2>
Alpha 21164 Signal Descriptions
Type Count Description Address response <2>. system commands, 21164 uses this indicate command hits Scache onchip load lock register. Command acknowledge. system interface uses this signal acknowledge commands driven 21164. Command fail. This signal uses. asserted during cack cycle WRITE BLOCK LOCK command indicate that write operation successful. this case, both cack_h cfail_h asserted together. also asserted instead cack_h force instruction fetch/decode unit (Ibox) timeout event. This causes 21164 partial reset trap machine check (MCHK) PALcode entry point, which indicates serious hardware error. Clock test mode. These signals specify relationship between osc_clk_in_h,l cycle time. These signals should deasserted normal operation mode. Command bus. These signals drive receive commands from command bus. following tables define commands that driven cmd_h<3:0> 21164 system. (continued next page)
cack_h
cfail_h
clk_mode_h<1:0>
cmd_h<3:0>
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal
Alpha 21164 Signal Descriptions
Type Count Description 21164 Commands System: cmd_h <3:0> 0000 0001 0010
Command LOCK FETCH
Meaning Nothing. Lock register address. 21164 passes FETCH instruction system. 21164 passes FETCH_M instruction system. instruction. Dirty shared clear. Request write block. Request write block with lock. Request data. Request data. Request data; modify intent. Request data; modify intent. Bcache victim should removed. Reserved. Request data, STx_C data. Request data, STx_C data. (continued next page)
0011
FETCH_M
0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
MEMORY BARRIER DIRTY WRITE BLOCK WRITE BLOCK LOCK READ MISS0 READ MISS1 READ MISS MOD0 READ MISS MOD1 BCACHE VICTIM READ MISS STC0 READ MISS STC1
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal
Alpha 21164 Signal Descriptions
Type Count Description System Commands 21164: cmd_h <3:0> 0000 0001
Command FLUSH
Meaning Nothing. Remove block from caches; return dirty data. Invalidate block from caches. Block goes shared state. Read block. Read block; shared. Read block; invalidate.
0010 0011 0100 0101 0111
INVALIDATE SHARED READ READ DIRTY READ DIRTY/INV
cpu_clk_out_h dack_h
clock output. This signal used test purposes. Data acknowledge. system interface uses this signal control data transfer between 21164 system. Data bus. These signals used move data between 21164, system, Bcache. Data request. 21164 samples this signal asserted rising edge sysclk then 21164 does drive data rising edge sysclk n+1. Before asserting this signal, system should assert idle_bc_h correct number cycles. 21164 samples this signal deasserted rising edge sysclk then 21164 drives data rising edge sysclk n+1. Data check. These signals even byte parity INT8 current data cycle. (continued next page)
data_h<127:0> data_bus_req_h
data_check_h<15:0>
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal data_ram_oe_h data_ram_we_h dc_ok_h
Alpha 21164 Signal Descriptions
Type Count Description Data output enable. This signal asserted Bcache read operations. Data write-enable. This signal asserted Bcache write operation. voltage Must deasserted until voltage reaches proper operating level. After that, dc_ok_h asserted. Fill warning. 21164 samples this signal asserted rising edge sysclk then 21164 provides address indicated fill_id_h Bcache rising edge sysclk n+1. Bcache begins write that sysclk. sysclk n+1, 21164 waits next sysclk then begins write operation again dack_h asserted. Fill error. this signal asserted during fill from memory, indicates 21164 that system detected invalid address hard error. system still provides apparently normal read sequence with correct ECC/parity though data valid. 21164 traps machine check (MCHK) PALcode entry point indicates serious hardware error. fill_error_h should asserted when data returned. Each assertion produces MCHK trap. Fill identification. Asserted with fill_h indicate which register used. 21164 supports outstanding load instructions. this signal asserted when 21164 samples fill_h asserted, then 21164 provides address from miss register deasserted, then address miss register used read operation. Fill checking off. this signal asserted, then 21164 does check parity current data cycle fill. Idle Bcache. When asserted, 21164 finishes current Bcache read write operation does start read write operation until signal deasserted. system interface must assert this signal time idle Bcache before fill data arrives. Index. These signals index Bcache. (continued next page)
fill_h
fill_error_h
fill_id_h
fill_nocheck_h
idle_bc_h
index_h<25:4>
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal
Alpha 21164 Signal Descriptions
Type Count Description INT4 data valid. During write operations noncached space, these signals used indicate which INT4 bytes data valid. This useful noncached write operations that have been merged write buffer. int4_valid_h<3:0> xxx1 xx1x x1xx 1xxx Write Meaning data_h<31:0> valid data_h<63:32> valid data_h<95:64> valid data_h<127:96> valid
int4_valid_h<3:0>
During read operations noncached space, these signals indicate which INT8 bytes 32-byte block need read returned processor. This useful read operations noncached memory. int4_valid_h<3:0> xxx1 xx1x x1xx 1xxx Read Meaning data_h<63:0> valid data_h<127:64> valid data_h<191:128> valid data_h<255:192> valid
Note: both read write operations, multiple int4_valid_h<3:0> bits simultaneously. (continued next page)
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal irq_h<3:0>
Alpha 21164 Signal Descriptions
Type Count Description System interrupt requests. These signals have multiple modes operation. During normal operation, these level-sensitive signals used signal interrupt requests. During initialization, these signals used cycle time divisor sys_clk_out1_h,l follows: irq_h High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High Ratio
mch_hlt_irq_h
Machine halt interrupt request. This signal multiple modes operation. During initialization, this signal used sys_clk_out2_h,l delay. During normal operation, used signal halt request. Oscillator clock inputs. These signals provide differential clock input that fundamental timing 21164. These signals driven twice desired internal clock frequency. (Under normal operating conditions cycle time one-half frequency osc_clk_in.) (continued next page)
osc_clk_in_h osc_clk_in_l
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal perf_mon_h
Alpha 21164 Signal Descriptions
Type Count Description Performance monitor. This signal used input 21164 internal performance monitoring hardware from offchip events (such activity). Select test port interface modes (normal, manufacturing, debug). normal operation, both signals must deasserted. Power failure interrupt request. This signal multiple modes operation. During initialization, this signal used sys_clk_out2_h,l delay. During normal operation, this signal used signal power failure. Reference clock input. Optional. Used synchronize timing multiple microprocessors single reference clock. this signal used, must tied proper operation. Secondary cache set. During read miss request, these signals indicate Scache number that will filled when data returned. This information used system maintain duplicate copy Scache store. Keep block status shared. systems without Bcache, when WRITE BLOCK/NO VICTIM PENDING WRITE BLOCK LOCK command acknowledged, this used keep block status shared private Scache. Serial clock. Supplies clock that causes SROM advance next bit. cycle time this clock times cycle time clock. Serial data. Input SROM. Serial output enable. Supplies output enable SROM. Serial present. Indicates that SROM present ready load Icache.
port_mode_h<1:0>
pwr_fail_irq_h
ref_clk_in_h
scache_set_h<1:0>
shared_h
srom_clk_h
srom_data_h srom_oe_l srom_present_l1
This
signal shown bidirectional. However, normal operation input only. output function used during manufacturing test verification only.
(continued next page)
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal st_clk_h
Alpha 21164 Signal Descriptions
Type Count Description STRAM clock. Clock Bcache synchronously timed RAMs (STRAMs). This signal synchronous with index_h<25:4> during private read write operations, with sys_clk_out1_h,l during read fill operations. System clock outputs. Programmable system clock (cpu_clk_out_h divided value used board-level cache system logic. System clock outputs. version sys_clk_out1_h,l delayed programmable amount from cycles. System machine check interrupt request. This signal multiple modes operation. During initialization, used sys_clk_out2_h,l delay. During normal operation, used signal machine interrupt check request. System reset. This signal protects 21164 from damage during initial power-up. must asserted until dc_ok_h asserted. After that, deasserted 21164 begins reset sequence. System lock flag. During fills, 21164 logically ANDs value system copy with copy produce true value lock flag. control parity. This signal indicates parity tag_valid_h, tag_shared_h, tag_dirty_h. During fills, system should drive correct parity based state valid, shared, dirty bits. Bcache data bits. This range supports 1M-byte 64M-byte Bcaches. data parity bit. This signal indicates parity tag_data_h<38:20>. dirty state bit. During fills, system should assert this signal 21164 request READ MISS MOD, shared asserted. output enable. This signal asserted during Bcache read operation. (continued next page)
sys_clk_out1_h sys_clk_out1_l sys_clk_out2_h sys_clk_out2_l sys_mch_chk_irq_h
sys_reset_l
system_lock_flag_h
tag_ctl_par_h
tag_data_h<38:20> tag_data_par_h tag_dirty_h
tag_ram_oe_h
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal tag_ram_we_h
Alpha 21164 Signal Descriptions
Type Count Description write-enable. This signal asserted during write operation. During first cycle write operation, write pulse deasserted. second following cycles write operation, write pulse asserted corresponding write pulse register asserted. Bits BC_WE_CTL<8:0> control shape pulse. shared bit. During fills, system should drive this signal with correct value mark cache block shared. valid bit. During fills, this signal asserted indicate that block valid data. JTAG boundary scan clock. JTAG serial boundary scan data-in signal. JTAG serial boundary scan data-out signal. Temperature sense. This signal used measure temperature manufacturing only. normal operation, this signal must left disconnected. Icache test status. These signals used manufacturing test purposes only extract Icache test status information from chip. test_status_h<0> asserted ICSR<39> true, Ibox timeout, remains asserted Icache built-in self-test (BiSt) fails. Also, test_status_h<0> outputs value written PALcode test_status_h<1> through access. JTAG test mode select signal. JTAG test access port (TAP) reset signal. Victim pending. When asserted, this signal indicates that current read miss generated victim.
tag_shared_h
tag_valid_h tck_h tdi_h tdo_h temp_sense
test_status_h<1:0>
tms_h trst_l
victim_pending_h
This
signal shown bidirectional. However, normal operation input only. output function used during manufacturing test verification only.
Preliminary-Subject Change-July 1996
Table lists signals function provides abbreviated description. Table
Signal Clocks clk_mode_h<1:0> cpu_clk_out_h osc_clk_in_h,l ref_clk_in_h st_clk_h sys_clk_out1_h,l sys_clk_out2_h,l sys_reset_l Bcache data_h<127:0> data_check_h<15:0> data_ram_oe_h data_ram_we_h index_h<25:4> tag_ctl_par_h tag_data_h<38:20> tag_data_par_h tag_dirty_h tag_ram_oe_h tag_ram_we_h tag_shared_h tag_valid_h Data bus. Data check. Data output enable. Data write-enable. Index. control parity. Bcache data bits. data parity bit. dirty state bit. output enable. write-enable. shared bit. valid bit. (continued next page) Clock test mode. clock output. Oscillator clock inputs. Reference clock input. Bcache STRAM clock output. System clock outputs. System clock outputs. System reset.
Alpha 21164 Signal Descriptions Function
Type Count Description
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal System Interface addr_h<39:4> addr_bus_req_h addr_cmd_par_h addr_res_h<2:0> cack_h cfail_h cmd_h<3:0> dack_h data_bus_req_h fill_h fill_error_h fill_id_h fill_nocheck_h idle_bc_h
Alpha 21164 Signal Descriptions Function
Type Count Description
Address bus. Address request. Address command parity. Address response. Command acknowledge. Command fail. Command bus. Data acknowledge. Data request. Fill warning. Fill error. Fill identification. Fill checking off. Idle Bcache. INT4 data valid. Secondary cache set. Keep block status shared. System lock flag. Victim pending.
int4_valid_h<3:0> scache_set_h<1:0> shared_h system_lock_flag_h victim_pending_h Interrupts irq_h<3:0> mch_hlt_irq_h pwr_fail_irq_h sys_mch_chk_irq_h
System interrupt requests. Machine halt interrupt request. Power failure interrupt request. System machine check interrupt request. (continued next page)
Preliminary-Subject Change-July 1996
Table (Cont.)
Signal
Alpha 21164 Signal Descriptions Function
Type Count Description
Test Modes Miscellaneous dc_ok_h perf_mon_h port_mode_h<1:0> srom_clk_h srom_data_h srom_oe_l srom_present_l tck_h tdi_h tdo_h temp_sense test_status_h<1:0> tms_h trst_l
This
voltage Performance monitor. Select test port interface modes (normal, manufacturing, debug). Serial clock. Serial data. Serial output enable. Serial present. JTAG boundary scan clock. JTAG serial boundary scan data JTAG serial boundary scan data out. Temperature sense. Icache test status. JTAG test mode select. JTAG test access port (TAP) reset.
signal shown bidirectional. However, normal operation input only. output function used during manufacturing test verification only.
Preliminary-Subject Change-July 1996
Alpha 21164 Microprocessor Functional Overview
This section provides overview 21164 external signals that support following: Clocks Bcache interface System interface Interrupts Test modes
Figure block diagram 21164.
Preliminary-Subject Change-July 1996
Clocks
21164 accepts clock signal inputs develops three clock signal outputs:
Signal Input Clock Signals osc_clk_in_h,l ref_clk_in_h Differential inputs normally driven times desired internal frequency. system-supplied clock which 21164 synchronizes timing multiprocessor systems. Description
Output Clock Signals cpu_clk_out_h sys_clk_out1_h,l sys_clk_out2_h,l 21164 internal clock that drive system clock. clock programmable speed supplied external interface. delayed copy sys_clk_out1_h,l. delay programmable integer number cpu_clk_out_h periods.
Figure shows 21164 clock signals. Figure Alpha 21164 Clock Signals
21164 clock_mode_h<1:0> dc_ok_h osc_clk_in_h osc_clk_in_l ref_clk_in_h sys_reset_l cpu_clk_out_h sys_clk_out1_h sys_clk_out1_l sys_clk_out2_h sys_clk_out2_l
MK-1455-16
Preliminary-Subject Change-July 1996
5.1.1 Clock 21164 uses differential input clock lines osc_clk_in_h,l source generate clock. input signals clk_mode_h<1:0> control generation clock. 5.1.2 System Clock clock divided programmable value between generate system clock. programmable feature allows system designer maximum flexibility when choosing external logic interface with 21164. sys_clk_out1_h,l signals delayed programmable number cycles between produce sys_clk_out2_h,l. output programmable divider symmetric divisor even. output asymmetric divisor odd. Figure shows 21164 driving system clock uniprocessor system. Figure Alpha 21164 Uniprocessor Clock
Memory ASIC sys_clk_out 21164 ASIC
LJ-03676-TI0
Preliminary-Subject Change-July 1996
5.1.3 Reference Clock 21164 provides reference clock input that other CPUs system devices synchronized multiprocessor systems. clock asserted signal ref_clk_in_h, then sys_clk_out1_h,l signals synchronized that reference clock means digital phase-locked loop (DPLL). Figure shows 21164 synchronized system reference clock. Figure Alpha 21164 Reference Clock Multiprocessor Systems
Memory ASIC ref_clk_in 21164 ASIC Reference Clock Memory ASIC ref_clk_in 21164 ASIC sys_clk_out sys_clk_out
LJ-03675-TI0
Preliminary-Subject Change-July 1996
Board-Level Backup Cache Interface
21164 includes interface control optional board-level backup cache (Bcache). This section describes Bcache interface. Bcache interface made following: data (which shares with system interface) control bits determining coherence SRAM output SRAM write control signals
Figure shows 21164 system interface signals. Figure Alpha 21164 Bcache Interface Signals
21164
data_check_h<15:0> data_h<127:0> data_ram_oe_h data_ram_we_h index_h<25:4> tag_ctl_par_h tag_data_h<38:20> tag_data_par_h tag_dirty_h tag_ram_oe_h tag_ram_we_h tag_shared_h tag_valid_h
MK-1455-18
Preliminary-Subject Change-July 1996
Bcache interface managed cache control interface unit (Cbox). Bcache interface 128-bit bidirectional data bus. read write speed Bcache programmed independently each other independently system clock ratio. Optionally, Bcache operate psuedo-pipeline manner. Internal processor registers used program Bcache timing enable wave pipelining. Alpha 21164 Microprocessor Hardware Reference Manual more information. Bcache system supports block sizes bytes must like secondary cache (Scache). block size selected mode bit. Scache 3-way, set-associative subset larger externally implemented, direct-mapped Bcache. systems with Bcache, Scache block size must bytes. 5.2.1 Bcache Victim Buffers 21164 designed support systems with more offchip Bcache victim buffers. External victim buffers improve overall performance Bcache. Bcache victim generated when 21164 deallocates dirty block from Bcache. Each time Bcache victim produced, 21164 stops reading Bcache until system takes current victim, then Bcache operations resume.
Preliminary-Subject Change-July 1996
5.2.2 Cache Coherence Protocol Cache coherency concern single multiprocessor 21164-based systems there several caches processor module several more multiprocessor systems. system hardware designer need concerned about Icache Dcache coherency. Coherency Icache software concern-it flushed with (PALcode) instruction. 21164 maintains coherency between Dcache Scache. system does have Bcache, system designer must create mechanisms system interface logic support cache coherency between Scache, main memory, other caches system. system Bcache, 21164 maintains cache coherency between Scache Bcache. Scache subset Bcache. this case, designer must create mechanisms system interface logic support cache coherency between Bcache, main memory, other caches system. following tasks must performed maintain cache coherency: Cbox 21164 maintains coherency Dcache keeps subset Scache. optional Bcache present, then 21164 maintains Scache subset Bcache. Scache set-associative kept subset larger externally implemented direct-mapped Bcache. System logic must help 21164 keep Bcache coherent with main memory other caches system. Icache subset cache also kept coherent with memory system.
Table describes Bcache states that determine cache coherence protocol 21164 systems.
Preliminary-Subject Change-July 1996
Table Bcache States Cache Coherency Protocols
Valid1 Shared1 Dirty1 State Cache Line valid. Valid read write operations. This cache line contains only cached copy block copy memory identical this line. Valid read write operations. This cache line contains only cached copy block. contents block have been modified more recently than copy memory. Valid read write operations. This block another CPU's cache. Valid read write operations. This block another CPU's cache. contents block have been modified more recently than copy memory.
tag_valid_h, tag_shared_h, tag_dirty_h signals described Table
Preliminary-Subject Change-July 1996
System Interface
system interface made bidirectional address command buses, data that shares with Bcache interface, several control signals. Figure shows 21164 system interface signals. Figure Alpha 21164 System Interface Signals
addr_bus_req_h cack_h cfail_h dack_h data_bus_req_h fill_h fill_error_h fill_id_h fill_nocheck_h idle_bc_h shared_h system_lock_flag_h
21164
addr_h<39:4> addr_cmd_par_h addr_res_h<2:0> cmd_h<3:0> data_h<127:0> data_check_h<15:0> int4_valid_h<3:0> scache_set_h<1:0> st_clk_h victim_pending_h
MK-1455-14
system interface under control cache control interface unit (Cbox). system interface 128-bit bidirectional data bus. cycle time system interface programmable speeds one-third one-fifteenth cycle time. system interface signals driven sampled 21164 rising edge sys_clk_out1_h. 5.3.1 Commands Addresses 21164 take commands from system time. interface buffer hold misses Scache victim addresses time. miss occurs when 21164 searches caches does find addressed block. 21164 queue misses system. Scache victim occurs when 21164 deallocates dirty block from Scache. system requests misses, victims arbitrate Bcache. highest priority Bcache data movement system, which includes fill, read dirty data, invalidate, shared activities.
Preliminary-Subject Change-July 1996
there system requests Bcache, then 21164 command selected.
Tables provide brief description commands that 21164 system drive command bus. Table
cmd<3:0> 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Alpha 21164 Commands System
Command LOCK FETCH FETCH_M MEMORY BARRIER DIRTY WRITE BLOCK WRITE BLOCK LOCK READ MISS0 READ MISS1 READ MISS MOD0 READ MISS MOD1 BCACHE VICTIM READ MISS STC0 READ MISS STC1 Meaning Nothing. lock register address. 21164 passes FETCH system. 21164 passes FETCH_M system. instruction. Dirty shared clear. Request write block. Request write block with lock. Request data. Request data. Request data; modify intent. Request data; modify intent. Bcache victim should removed. Spare. Request data, STx_C data. Request data, STx_C data.
Preliminary-Subject Change-July 1996
Table System Commands 21164
cmd<3:0> 0000 0001 0010 0011 0100 0101 0111 Command FLUSH INVALIDATE SHARED READ READ DIRTY READ DIRTY/INV Meaning Nothing. Remove block from caches; return dirty data (flush protocol). Remove block (write invalidate protocol). Block goes shared state (write invalidate protocol). Read block (flush protocol). Read block; shared (write invalidate protocol). Read block; invalidate (write invalidate protocol).
Preliminary-Subject Change-July 1996
Interrupts
21164 seven interrupt signals that have different uses during initialization normal operation. Figure shows 21164 interrupt signals. Figure Alpha 21164 Interrupt Signals
21164 irq_h<3:0> mch_hlt_irq_h pwr_fail_irq_h sys_mch_chk_irq_h
MK-1455-17
5.4.1 Interrupt Signals During Initialization 21164 interrupt signals work tandem with sys_reset_l signal values many user-selectable clocking ratios interface timing parameters. During initialization, 21164 reads system clock configuration parameters from interrupt pins.
Preliminary-Subject Change-July 1996
Table shows system clock divisor settings. system clock frequency determined dividing ratio into clock frequency. Table System Clock Divisor
irq_h<3> High High High High irq_h<2> High High High High High irq_h<1> High High High High High irq_h<0> High High High High High Ratio
Table shows three remaining interrupt signals used determine length sys_clk_out2 delay. These signals provide flexible timing system use. Table System Clock Delay
sys_mch_chk_irq_h High High High High pwr_fail_irq_h High High High High mch_halt_irq_h High High High High Delay Cycles
Preliminary-Subject Change-July 1996
5.4.2 Interrupt Signals During Normal Operation During normal operation, interrupt signals request various interrupts described Table
Test Modes
Figure shows 21164 test signals. Figure Alpha 21164 Test Signals
21164 port_mode_h<1:0> srom_data_h tdi_h trst_l temp_sense
srom_clk_l srom_oe_l srom_present_l tck_h tdo_h test_status_h<1:0> tms_h
MK-1455-15
Preliminary-Subject Change-July 1996
21164 test interface port consists dedicated signals. Table summarizes 21164 test port signals their function. Table
Name port_mode_h<1> port_mode_h<0> srom_present_l srom_data_h/Rx srom_clk_h/Tx srom_oe_l tdi_h tdo_h tms_h tck_h trst_l test_status_h<0> test_status_h<1>
Alpha 21164 Test Port Pins
Type Function Must false. Must false. Tied serial ROMs (SROMs) present system. Receives SROM serial terminal data. Supplies clock SROMs transmits serial terminal data. SROM enable. IEEE 1149.1 port. IEEE 1149.1 port. IEEE 1149.1 port. IEEE 1149.1 port. IEEE 1149.1 optional TRST port. Indicates Icache BiSt status. Outputs IPR-written value timeout reset.
5.5.1 Normal Test Interface Mode test port default normal test interface mode when port_mode_h<1:0> signals tied this mode, test port supports following: Serial interface port Serial diagnostic terminal interface port IEEE 1149.1 test access port
5.5.2 Serial Interface Port following signals make serial (SROM) interface: srom_present_l srom_data_h srom_oe_l srom_clk_h
Preliminary-Subject Change-July 1996
During system reset, 21164 samples srom_present_l signal presence SROM. SROMs detected reset, then srom_present_l deasserted SROM load disabled. reset sequence clears Icache valid bits, which causes first instruction fetch miss Icache seek instructions from offchip memory. SROMs present during setup, then system performs SROM load follows: srom_oe_l signal supplies output enable SROM. srom_clk_h signal supplies clock that causes advance next bit. cycle time this clock 1266 times system clock ratio. srom_data_h signal reads SROM data. 5.5.3 Serial Terminal Port After serial data loaded into Icache, three SROM load signals become parallel pins that drive diagnostic terminal such RS422. 5.5.4 IEEE 1149.1 Test Access Port test access port complies with requirements IEEE 1149.1 (JTAG) standard. following signals make test access port: tms_h-Test access port select. trst_l-Test access port reset. tck_h-Test access port clock. tdi_h tdo_h-Input output serial boundary scan, die-ID, bypass, instruction registers.
5.5.5 Test Status Signals test_status_h signals extract test status information from chip. test_status_h<0> signal indicates when Icache built-in self-test (BiSt) fails. test_status_h<1> signal detects unrepairable Icache indicating more than failing Icache rows.
Preliminary-Subject Change-July 1996
Alpha Architecture Basics
This section provides some basic information about Alpha architecture. more detailed information about Alpha architecture, Alpha Architecture Reference Manual.
Architecture
Alpha architecture 64-bit load store RISC architecture designed with particular emphasis speed, multiple instruction issue, multiple processors, software migration from many operating systems. registers bits length operations performed between 64-bit registers. instructions bits length. Memory operations either load store operations. data manipulation done between registers. Alpha architecture supports following data types: 16-, 32-, 64-bit integers IEEE 32-bit 64-bit floating-point formats architecture 32-bit 64-bit floating-point formats
Alpha architecture, instructions interact with each other only instruction writing register memory location another instruction reading from that register memory location. This resources makes easy build implementations that issue multiple instructions every cycle. 21164 uses subroutines, called privileged architecture library code (PALcode), that specific particular Alpha operating system implementation hardware platform. These subroutines provide operating system primitives context switching, interrupts, exceptions, memory management. These subroutines invoked hardware CALL_PAL instructions. CALL_PAL instructions function field instruction vector specified subroutine. PALcode written standard machine code with some implementation-specific extensions provide direct access low-level hardware functions. PALcode supports optimizations multiple operating systems, flexible memory-management implementations, multi-instruction atomic sequences. Alpha architecture performs byte shifting masking with normal 64-bit, register-to-register instructions; does include single-byte load store instructions.
Preliminary-Subject Change-July 1996
Addressing
basic addressable unit Alpha architecture 8-bit byte. 21164 supports 43-bit virtual address. Virtual addresses seen program translated into physical memory addresses memory-management mechanism. 21164 supports 40-bit physical address.
Integer Data Types
Alpha architecture supports four integer data types:
Data Type Byte Description byte contiguous bits that start addressable byte boundary. byte 8-bit value. byte supported Alpha architecture EXTRACT, MASK, INSERT, instructions. word contiguous bytes that start arbitrary byte boundary. word 16-bit value. word supported Alpha architecture EXTRACT, MASK, INSERT instructions. longword contiguous bytes that start arbitrary byte boundary. longword 32-bit value. longword supported Alpha architecture sign-extended load store instructions longword arithmetic instructions. quadword contiguous bytes that start arbitrary byte boundary. quadword supported Alpha architecture load store instructions quadword integer operate instructions.
Word
Longword
Quadword
Note Alpha implementations impose significant performance penalty when accessing operands that NATURALLY ALIGNED. Refer Alpha Architecture Reference Manual details.
Preliminary-Subject Change-July 1996
Floating-Point Data Types
21164 supports following floating-point data types: Longword integer format floating-point unit Quadword integer format floating-point unit IEEE floating-point formats S_floating T_floating
floating-point formats F_floating G_floating D_floating (limited support)
Preliminary-Subject Change-July 1996
Alpha 21164 Microprocessor IEEE Floating-Point Conformance
21164 supports IEEE floating-point operations defined Alpha architecture. Support complete implementation IEEE Standard Binary Floating-Point Arithmetic (ANSI/IEEE Standard 1985) provided combination hardware software described Alpha Architecture Reference Manual. Additional information about writing code support precise exception handling (necessary complete conformance standard) Alpha Architecture Reference Manual. following information specific 21164: Invalid operation (INV) invalid operation trap always enabled. trap occurs, then destination register UNPREDICTABLE. This exception signaled architecture operand nonfinite (reserved operand dirty zero) operation take exception (that certain instructions, such CPYS, never take exception). This exception signaled IEEE operand nonfinite (NAN, INF, denorm) operation take exception. This trap also signaled IEEE format divide divided exception occurs, then FPCR<INV> trap signaled Ibox. Divide-by-zero (DZE) divide-by-zero trap always enabled. trap occurs, then destination register UNPREDICTABLE. architecture format, this exception signaled whenever numerator valid denominator zero. IEEE format, this exception signaled whenever numerator valid non-zero, with denominator exception occurs, then FPCR<DZE> trap signaled Ibox. IEEE format divides, signals INV, DZE. Floating overflow (OVF) floating overflow trap always enabled. trap occurs, then destination register UNPREDICTABLE. exception signaled rounded result exceeds magnitude largest finite number, which represented destination format. This applies only operations whose destination floating-point data type. exception occurs, then FPCR<OVF> trap signaled Ibox.
Preliminary-Subject Change-July 1996
Underflow (UNF) underflow trap disabled. underflow occurs, then destination register forced true zero, consisting full bits zero. This done even proper IEEE result would have been exception signaled rounded result smaller magnitude than smallest finite number that represented destination format. exception occurs, then FPCR<UNF> set. trap enabled, then trap signaled Ibox. 21164 never produces denormal number; underflow occurs instead.
Inexact (INE) inexact trap disabled. destination register always contains properly rounded result, whether trap enabled. exception signaled rounded result different from what would have been produced infinite precision (infinitely wide data) were available. floating-point results, this requires both infinite precision exponent fraction. integer results, this requires infinite precision integer integral result. exception occurs, then FPCR<INE> set. trap enabled, then trap signaled Ibox. IEEE-754 specification allows occur concurrently with either UNF. Whenever signaled inexact trap enabled), also signaled. Whenever signaled inexact trap enabled), also signaled. inexact trap also occurs concurrently with integer overflow. valid opcodes that enable also enable both overflow underflow. CVTQL results integer overflow (IOV), then FPCR<INE> automatically set. (The trap never signaled Ibox because there CVTQL opcode that enables inexact trap.)
Integer overflow (IOV) integer overflow trap disabled. destination register always contains low-order bits (<64> <32>) true result (not truncated bits). Integer overflow occur with CVTTQ, CVTGQ, CVTQL. conversions from floating quadword integer longword integer, integer overflow occurs rounded result outside range 0263 .26301 conversions from quadword integer longword integer, integer overflow occurs result outside range 0231 .23101 exception occurs, then appropriate floating-point control register (FPCR) set. trap enabled, then trap signaled Ibox.
Preliminary-Subject Change-July 1996
Software completion (SWC) software completion signal recorded FPCR. state this signal always sent Ibox. Ibox detects assertion listed exceptions concurrent with assertion signal, then sets EXC_SUM<SWC>.
Input exceptions always take priority over output exceptions. both exception types occur, then only input exception recorded FPCR only input exception signaled Ibox.
Preliminary-Subject Change-July 1996
Internal Processor Registers
This section describes 21164 microprocessor internal processor registers (IPRs). organized follows: Instruction fetch/decode unit branch unit (Ibox) IPRs Memory address translation unit (Mbox) IPRs Cache control interface unit (Cbox) IPRs storage registers Restrictions
Ibox, Mbox, data cache (Dcache), PALtemp IPRs accessible PALcode means HW_MTPR HW_MFPR instructions. Table lists numbers these instructions. Cbox, second-level cache (Scache), backup cache (Bcache) IPRs accessible physical address region FFF0 0000 FFFF FFFF. Table summarizes Cbox, Scache, Bcache IPRs. Table lists restrictions IPRs. Note Windows 21164-P1 21164-P2 users, following bits must set: IBOX control status register (ICSR<28>) SPE<0> must always (Section 8.1.17). Clearing this will cause 21164-Pn operation UNPREDICTABLE. MBOX control register (MCSR<01>) SP<0> must always (Section 8.2.14). Clearing this will cause 21164-Pn operation UNPREDICTABLE.
Note Unless explicitly stated, IPRs cleared hardware chip timeout reset.
Preliminary-Subject Change-July 1996
Table Ibox, Mbox, Dcache, PALtemp Encodings
Mnemonic Ibox IPRs ITB_TAG ITB_PTE ITB_ASN ITB_PTE_TEMP ITB_IA ITB_IAP ITB_IS SIRR ASTRR ASTER EXC_ADDR EXC_SUM EXC_MASK PAL_BASE IPLR INTID IFAULT_VA_FORM IVPTBR HWINT_CLR SL_XMIT SL_RCV ICSR IC_FLUSH_CTL ICPERR_STAT PMCTR R/W0C R/W1C Access Index16 Ibox Slots Pipe
(continued next page)
Preliminary-Subject Change-July 1996
Table (Cont.) Ibox, Mbox, Dcache, PALtemp Encodings
Mnemonic PALtemp IPRs PALtemp0 PALtemp1 PALtemp2 PALtemp3 PALtemp4 PALtemp5 PALtemp6 PALtemp7 PALtemp8 PALtemp9 PALtemp10 PALtemp11 PALtemp12 PALtemp13 PALtemp14 PALtemp15 PALtemp16 PALtemp17 PALtemp18 PALtemp19 PALtemp20 PALtemp21 PALtemp22 PALtemp23 Mbox IPRs DTB_ASN DTB_CM (continued next page) Access Index16 Ibox Slots Pipe
Preliminary-Subject Change-July 1996
Table (Cont.) Ibox, Mbox, Dcache, PALtemp Encodings
Mnemonic DTB_TAG DTB_PTE DTB_PTE_TEMP MM_STAT VA_FORM MVPTBR DTB_IAP DTB_IA DTB_IS ALT_MODE CC_CTL MCSR DC_FLUSH DC_PERR_STAT DC_TEST_CTL DC_TEST_TAG DC_TEST_TAG_TEMP DC_MODE MAF_MODE Access R/W1C Index16 Ibox Slots Pipe
Preliminary-Subject Change-July 1996
Instruction Fetch/Decode Unit Branch Unit (Ibox) IPRs
Ibox internal processor registers (IPRs) described Section 8.1.1 through Section 8.1.27. 8.1.1 Istream Translation Buffer Register (ITB_TAG) ITB_TAG write-only register written hardware ITBMISS/IACCVIO, with field faulting virtual address. ensure integrity instruction translation buffer (ITB), page table entry (PTE) fields entry updated simultaneously write operation ITB_PTE register. This write operation causes contents ITB_TAG register written into field location, which determined not-last-used replacement algorithm. field obtained from HW_MTPR ITB_PTE instruction. Figure shows ITB_TAG register format. Figure Istream Translation Buffer Register (ITB_TAG)
VA<42:13>
VA<42:13>
LJ-03473-TI0
Preliminary-Subject Change-July 1996
8.1.2 Instruction Translation Buffer Page Table Entry (ITB_PTE) Register ITB_PTE read/write register. Write Format write operation this register writes both fields location determined not-last-used replacement algorithm. fields updated simultaneously ensure integrity ITB. write operation ITB_PTE register increments not-last-used (NLU) pointer, which allows writing entire entries. HW_MTPR ITB_PTE instruction falls shadow trapping instruction, pointer incremented multiple times. field location determined contents ITB_TAG register. field provided HW_MTPR ITB_PTE instruction. Write operations this register memory format bits, described Alpha Architecture Reference Manual. Figure shows ITB_PTE register write format. Figure Instruction Translation Buffer Page Table Entry (ITB_PTE) Register Write Format
PFN<39:13>
LJ-03474-TI0
Read Format read ITB_PTE requires instructions. read ITB_PTE register returns pointed pointer ITB_PTE_ TEMP register increments pointer. HW_MFPR ITB_PTE instruction falls shadow trapping instruction, pointer incremented multiple times. zero value returned integer register file. second read ITB_PTE_TEMP register returns general purpose integer register file (IRF). Figure shows ITB_PTE register read format.
Preliminary-Subject Change-July 1996
Figure Instruction Translation Buffer Page Table Entry (ITB_PTE) Register Read Format
GHD<2:0>
PFN<39:13>
LJ-03475-TI0
Preliminary-Subject Change-July 1996
8.1.3 Instruction Translation Buffer Address Space Number (ITB_ASN) Register ITB_ASN read/write register that contains address space number (ASN) current process. Figure shows ITB_ASN register format. Figure Instruction Translation Buffer Address Space Number (ITB_ASN) Register
RAZ/IGN ASN<6:0> RAZ/IGN
RAZ/IGN
LJ-03476-TI0
Preliminary-Subject Change-July 1996
8.1.4 Instruction Translation Buffer Page Table Entry Temporary (ITB_PTE_TEMP) Register ITB_PTE_TEMP read-only holding register ITB_PTE read data. read ITB_PTE register returns data this register. second read ITB_PTE_TEMP register returns data general purpose integer register file (IRF). Figure shows ITB_PTE register format. Table shows settings ITB_PTE_TEMP register. Table Granularity Hint Bits ITB_PTE_TEMP Read Format
Name Extent <29> <30> <31> Type Description granularity hint equals granularity hint equals granularity hint equals
8.1.5 Instruction Translation Buffer Invalidate Process (ITB_IAP) Register ITB_IAP write-only register. write operation this register invalidates entries that have address space match (ASM) that equals zero. 8.1.6 Instruction Translation Buffer Invalidate (ITB_IA) Register ITB_IA write-only register. write operation this register invalidates entries, resets not-last-used (NLU) pointer initial state. RESET PALcode must execute HW_MTPR ITB_IA instruction order initialize pointer.
Preliminary-Subject Change-July 1996
8.1.7 Instruction Translation Buffer (ITB_IS) Register ITB_IS write-only register. Writing virtual address this register invalidates entry that meets either following criteria: entry whose virtual address (VA) field matches ITB_IS<42:13> whose field matches ITB_ASN<10:04>. entry whose field matches ITB_IS<42:13> whose set.
Figure shows ITB_IS register format. Figure Instruction Translation Buffer (ITB_IS) Register
VA<42:13>
VA<42:13>
LJ-03478-TI0
Preliminary-Subject Change-July 1996
8.1.8 Formatted Faulting Virtual Address (IFAULT_VA_FORM) Register IFAULT_VA_FORM read-only register containing formatted faulting virtual address ITBMISS/IACCVIO (except IACCVIOs generated sign-check errors). formatted faulting address generated depends whether superpage mapping enabled through ICSR SPE<0>. Figure shows IFAULT_VA_FORM register format non-NT mode. Figure Formatted Faulting Virtual Address (IFAULT_VA_FORM) Register (NT_Mode=0)
VA<42:13>
VPTB<63:33> VA<42:13>
LJ-03479-TI0
Figure shows IFAULT_VA_FORM register format mode. Figure Formatted Faulting Virtual Address (IFAULT_VA_FORM) Register (NT_Mode=1)
VA<31:13> VPTB<63:30> VPTB<63:30>
LJ-03480-TI0
Preliminary-Subject Change-July 1996
8.1.9 Virtual Page Table Base Register (IVPTBR) IVPTBR read/write register. Bits <32:30> UNDEFINED read this register non-NT mode. Figure shows IVPTBR format non-NT mode. Figure Virtual Page Table Base Register (IVPTBR) (NT_Mode=0)
RAZ/IGN
VPTB<63:33>
MA0602
Figure shows IVPTBR format mode. Figure Virtual Page Table Base Register (IVPTBR) (NT_Mode=1)
RAZ/IGN VPTB<63:30> VPTB<63:30>
LJ-03481-TI0
Preliminary-Subject Change-July 1996
8.1.10 Icache Parity Error Status (ICPERR_STAT) Register ICPERR_STAT read/write register. Icache parity error status bits cleared writing appropriate bits. Figure Table describe ICPERR_STAT register format. Figure Icache Parity Error Status (ICPERR_STAT) Register
RAZ/IGN RAZ/IGN RAZ/IGN
LJ-03482-TI0
Table Icache Parity Error Status Register Fields
Name Extent <11> <12> <13> Type Description Data parity error parity error Timeout reset error cfail_h/no cack_h error
8.1.11 Icache Flush Control (IC_FLUSH_CTL) Register IC_FLUSH_CTL write-only register. Writing value this register flushes entire Icache.
Preliminary-Subject Change-July 1996
8.1.12 Exception Address (EXC_ADDR) Register EXC_ADDR read/write register used restart system after exceptions interrupts. HW_REI instruction causes return instruction pointed EXC_ADDR register. This register written both hardware software. Hardware write operations occur result exceptions/interrupts CALL_PAL instructions. Hardware write operations that occur result exceptions/interrupts take precedence over other write operations. case exception/interrupt, hardware writes program counter (PC) this register. case precise exceptions, this value instruction that caused exception. case imprecise exceptions/interrupts, this value next instruction that would have issued exception/interrupt reported. case CALL_PAL instruction, value next instruction after CALL_PAL written EXC_ADDR. <00> this register used indicate PALmode. HW_REI instruction, mode system determined <00> EXC_ADDR. Figure shows EXC_ADDR register format. Figure Exception Address (EXC_ADDR) Register
PC<63:2> RAZ/IGN
PC<63:2>
LJ-03483-TI0
Preliminary-Subject Change-July 1996
8.1.13 Exception Summary (EXC_SUM) Register EXC_SUM read/write register that records different arithmetic traps that occur between EXC_SUM write operations. write operation this register clears bits <16:10>. Figure Table describe EXC_SUM register format. Figure Exception Summary (EXC_SUM) Register
RAZ/IGN RAZ/IGN
RAZ/IGN
LJ-03484-TI0
Table Exception Summary Register Fields
Name Extent <10> Type Description Indicates software completion possible. This after floating-point instruction containing modifier completes with arithmetic trap previous floating-point instructions that trapped since last HW_MTPR EXC_SUM instruction also contained modifier. cleared whenever floating-point instruction without modifier completes with arithmetic trap. remains cleared regardless additional arithmetic traps until register written HW_MTPR instruction. always cleared upon HW_MTPR write operation EXC_SUM register. (continued next page)
Preliminary-Subject Change-July 1996
Table (Cont.) Exception Summary Register Fields
Name Extent <11> <12> <13> <14> <15> <16> Type Description Indicates invalid operation. Indicates divide zero. Indicates floating-point overflow. Indicates floating-point underflow. Indicates floating inexact error. Indicates floating-point execution unit (Fbox) convert integer overflow integer arithmetic overflow.
Preliminary-Subject Change-July 1996
8.1.14 Exception Mask (EXC_MASK) Register EXC_MASK read/write register that records destinations instructions that have caused arithmetic trap between EXC_MASK write operations. destination recorded single mask 64-bit representing F0-F31 I0-I31. write operation EXC_SUM clears EXC_MASK register. Figure shows EXC_MASK register format. Figure Exception Mask (EXC_MASK) Register
131130129
F31F30
LJ-03485-TI0
Preliminary-Subject Change-July 1996
8.1.15 Base Address (PAL_BASE) Register PAL_BASE read/write register containing base address PALcode. register cleared hardware reset. Figure shows PAL_BASE register format. Figure Base Address (PAL_BASE) Register
PAL_BASE<39:14> RAZ/IGN
RAZ/IGN PAL_BASE<39:14>
LJ-03486-TI0
Preliminary-Subject Change-July 1996
8.1.16 Ibox Current Mode (ICM) Register read/write register containing current mode bits architecturally defined processor status, described Alpha Architecture Reference Manual. Figure shows register format. Figure Ibox Current Mode (ICM) Register
RAZ/IGN RAZ/IGN
RAZ/IGN
LJ-03487-TI0
Preliminary-Subject Change-July 1996
8.1.17 Ibox Control Status Register (ICSR) ICSR read/write register containing Ibox-related control status information. Figure Table describe ICSR format. Figure Ibox Control Status Register (ICSR)
RAZ/IGN RAZ/IGN
PME<1:0> IMSK<3:0> SPE<1:0> RAZ/IGN RAZ/IGN CRDE ISTA
LJ-03488-TI0
Preliminary-Subject Change-July 1996
Table Ibox Control Status Register Fields
Name PME<1:0> Extent <09:08> Type RW,0 Description Performance counter master enable bits. both PME<1> PME<0> clear, performance counters PMCTR disabled. either PME<1> PME<0> set, counter enabled according settings PMCTR fields. set, each IMSK<3:0> signal disables corresponding IRQ_H<3:0> interrupt. set, timeout counter counts thousand cycles before asserting timeout reset. clear, timeout counter counts billion cycles before asserting timeout reset. set, disables Ibox timeout counter. Does affect cfail_h/no cack_h error. set, floating-point instructions issued. clear, floating-point instructions cause exceptions. set, allows PALRES instructions issued kernel mode. 21164-266, 21164-300, 21164-333 SPE<1> set, enables superpage mapping Istream virtual address VA<39:13> directly physical address PA<39:13> assuming VA<42:41> Virtual address VA<40> ignored this translation. Access allowed only kernel mode. SPE<0> mode), enables superpage mapping Istream virtual addresses VA<42:30> 1FFE16 directly physical address PA<39:30> VA<30:13> mapped directly PA<30:13>. Access allowed only kernel mode. 21164-P1 21164-P2 SPE<0> must always set. Clearing this will cause 21164-Pn operation UNPREDICTABLE. (continued next page)
IMSK<3:0> <23:20> <24>
RW,0 RW,0
<25> <26>
RW,0 RW,0
SPE<1:0>
<27> <29:28>
RW,0 RW,0
Preliminary-Subject Change-July 1996
Table (Cont.) Ibox Control Status Register Fields
Name CRDE Reserved ISTA Extent <30> <32> <33> <34> <35> <36> <37> <38> <39> Type RW,0 RW,0 RW,0 RW,0 RW,0 RW,0 RW,1 RW,0 Description set, enables shadow registers. set, enables correctable error interrupts. set, enables serial line interrupts. set, forces miss Icache references. normal operation. set, forces Icache parity. normal operation. set, forces Icache data parity. normal operation. Reserved Digital. Must one. Reading this indicates ICACHE BIST status. set, ICACHE BIST successful. Writing this asserts test_status_h<1> signal.
Preliminary-Subject Change-July 1996
8.1.18 Interrupt Priority Level Register (IPLR) IPLR read/write register that accessed PALcode value interrupt priority level (IPL). Whenever hardware detects interrupt whose target greater than value IPLR<04:00>, interrupt taken. Figure shows IPLR register format. Figure Interrupt Priority Level Register (IPLR)
RAZ/IGN IPL<4:0>
RAZ/IGN
LJ-03489-TI0
Preliminary-Subject Change-July 1996
8.1.19 Interrupt (INTID) Register INTID read-only register that written hardware with target highest priority pending interrupt. hardware recognizes interrupt being read greater than given IPLR<04:00>. Interrupt service routines value this register determine cause interrupt. PALcode, interrupt service, must ensure that INTID greater than specified IPLR. This restriction required because level-sensitive hardware interrupt disappear before interrupt service routine entered (passive release). contents INTID correct HALT interrupt because this particular interrupt does have target which masked. When HALT interrupt occurs, INTID indicates next highest priority pending interrupt. PALcode interrupt service must check interrupt summary register (ISR) determine HALT interrupt occurred. Figure shows INTID register format. Figure Interrupt (INTID) Register
RAZ/IGN INTID<4:0>
RAZ/IGN
LJ-03490-TI0
Preliminary-Subject Change-July 1996
8.1.20 Asynchronous System Trap Request Register (ASTRR) ASTRR read/write register containing bits request asynchronous system trap (AST) interrupts each four processor modes (U,S,E,K). order generate interrupt, corresponding enable ASTER must current processor mode given ICM<04:03> should equal higher than mode associated with request. Figure shows ASTRR format. Figure Asynchronous System Trap Request Register (ASTRR)
RAZ/IGN
RAZ/IGN
LJ-03491-TI0
Preliminary-Subject Change-July 1996
8.1.21 Asynchronous System Trap Enable Register (ASTER) ASTER read/write register containing bits enable corresponding asynchronous system trap (AST) interrupt requests. Figure shows ASTER format. Figure Asynchronous System Trap Enable Register (ASTER)
RAZ/IGN
RAZ/IGN
LJ-03492-TI0
Preliminary-Subject Change-July 1996
8.1.22 Software Interrupt Request Register (SIRR) SIRR read/write register used control software interrupt requests. software request particular requested setting appropriate SIRR<15:01>. Figure Table describe SIRR format. Figure Software Interrupt Request Register (SIRR)
RAZ/IGN SIRR<15:1> RAZ/IGN
RAZ/IGN
LJ-03493-TI0
Table Software Interrupt Request Register Fields
Name SIRR<15:1> Extent <18:04> Type Description Request software interrupts.
Preliminary-Subject Change-July 1996
8.1.23 Hardware Interrupt Clear (HWINT_CLR) Register HWINT_CLR write-only register used clear edge-sensitive hardware interrupt requests. Figure Table describe HWINT_CLR register format. Figure Hardware Interrupt Clear (HWINT_CLR) Register
PC0C PC1C PC2C
CRDC
LJ-03495-TI0
Table Hardware Interrupt Clear Register Fields
Name PC0C PC1C PC2C CRDC Extent <27> <28> <29> <32> <33> Type Description Clears performance counter interrupt requests. Clears performance counter interrupt requests. Clears performance counter interrupt requests. Clears correctable read data interrupt requests. Clears serial line interrupt requests.
Preliminary-Subject Change-July 1996
8.1.24 Interrupt Summary Register (ISR) read-only register containing information about pending hardware, software, asynchronous system trap (AST) interrupt requests. Figure Table describe format. Figure Interrupt Summary Register (ISR)
SISR<15:1> ASTRR<3:0> ASTER<3:0>
LJ-03496-TI0A
Preliminary-Subject Change-July 1996
Table Interrupt Summary Register Fields
Name Extent Type Description Boolean ASTRR<USEK> with ASTER<USEK> used indicate enabled requests. Software interrupt requests through corresponding through request corresponding enable processor mode equal higher than request mode. External hardware interrupt-irq_h<0>. External hardware interrupt-irq_h<1>. External hardware interrupt-irq_h<2>. External hardware interrupt-irq_h<3>. External hardware interrupt-performance counter (IPL 29). External hardware interrupt-performance counter (IPL 29). External hardware interrupt-performance counter (IPL 29). External hardware interrupt-power failure (IPL 30). External hardware interrupt-system machine check (IPL 31). Correctable errors (IPL 31). Serial line interrupt. External hardware interrupt-halt.
ASTRR<3:0> <03:00> ASTER<3:0> SISR<15:1> <18:04> <19>
RO,0
<20> <21> <22> <23> <27> <28> <29> <30> <31> <32> <33> <34>
Preliminary-Subject Change-July 1996
8.1.25 Serial Line Transmit (SL_XMIT) Register SL_XMIT write-only register used transmit bit-serial data microprocessor chip under control software timing loop. value transmitted offchip srom_clk_h signal. normal operation mode (not debugging mode), srom_clk_h signal serves both serial line transmission Icache serial interface. Figure Table describe SL_XMIT register format. Figure Serial Line Transmit (SL_XMIT) Register
LJ-03497-TI0
Table Serial Line Transmit Register Fields
Name Extent <07> Type WO,1 Description Serial line transmit data
Preliminary-Subject Change-July 1996
8.1.26 Serial Line Receive (SL_RCV) Register SL_RCV read-only register used receive bit-serial data under control software timing loop. SL_RCV register functionally connected srom_data_h signal. serial line interrupt requested whenever transition detected srom_data_h signal ICSR set. During normal operations (not test mode), srom_data_h signal serves both serial line reception Icache serial (SROM) interface. Figure Table describe SL_RCV register format. Figure Serial Line Receive (SL_RCV) Register
LJ-03498-TI0
Table Serial Line Receive Register Fields
Name Extent <06> Type Description Serial line receive data
Preliminary-Subject Change-July 1996
8.1.27 Performance Counter (PMCTR) Register PMCTR read/write register that controls three onchip performance counters. Figure Table describe PMCTR format. Performance counter interrupt requests summarized Section 8.1.24. Cbox inputs counter select options described Table Note arrangement select option tables meant imply restrictions permitted combinations selections. only cases which selection counter influences another's count SEL1=8 (SEL 2=2, other).
Figure Performance Counter (PMCTR) Register
CTR2<13:0> CTL0 CTL1 CTL2
SEL1<3:0> SEL2<3:0>
SEL0
CTR0<15:0>
CTR1<15:0>
MA-0601A
Preliminary-Subject Change-July 1996
Table Performance Counter Register Fields
Name CTR0<15:0> CTR1<15:0> SEL0 CTR2<13:0> CTL0<1:0> Extent <63:48> <47:32> <31> <30> <29:16> <15:14> Type RW,0 Description 16-bit counter events selected SEL0 enabled CTL0<1:0>. 16-bit counter. Counter0 Select-refer Table Kill user mode-disables counters user mode (refer Table 22). 14-bit counter CTR0 counter control: counter disable, interrupt disable counter enable, interrupt disable counter enable, interrupt count 65536 (Refer Section 8.1.23 Section 8.1.24.) counter enable, interrupt count CTR1 counter control: counter disable,interrupt disable counter enable, interrupt disable counter enable, interrupt count 65536 counter enable, interrupt count CTR2 counter control: counter disable,interrupt disable counter enable, interrupt disable counter enable, interrupt count 16384 counter enable, interrupt count Kill PALmode-disables counters PALmode (refer Table 22). Kill kernel, executive, supervisor mode- disables counters kernel, executive, supervisor modes (refer Table 22). Ku=1, Kp=1, Kk=1 enables counters executive supervisor modes only. Counter1 Select-refer Table Counter2 Select-refer Table
CTL1<1:0>
<13:12>
RW,0
CTL2<1:0>
<11:10>
RW,0
<09> <08>
SEL1<3:0> SEL2<3:0>
<07:04> <03:00>
Preliminary-Subject Change-July 1996
Table shows PMCTR counter select options. Table PMCTR Counter Select Options
Counter0 SEL0<0> 0:Cycles Counter1 SEL1<3:0> 0x0: nonissue cycles Valid instruction none issued. 0x1: split-issue cycles Some, all, instructions issued. 0x2: pipe-dry cycles valid instruction 0x3: replay trap replay trap occurred. 0x4: single-issue cycles Exactly instruction issued. 0x5: dual-issue cycles Exactly instructions issued. 0x6: triple-issue cycles Exactly three instructions issued. 0x7: quad-issue cycles Exactly four instructions issued. 1:Instructions 0x8: jsr-ret sel2=PC-M Instruction issued sel2 PC-M. 0x8: cond-branch sel2=BR-M Instruction issued sel2 BR-M 0x8: flow-change instructions sel2=! (PC-M BR-M) 0x9: IntOps issued 0xA: FPOps issued 0xB: loads issued 0xC: stores issued 0xD: Icache issued 0x4: Icache/RFB misses 0x5: misses 0x6: Dcache misses 0x7: misses 0x8: merged (continued next page) 0x2: PC-mispredicts Counter2 SEL2<3:0> 0x0: long(>15 cycle) stalls
0x1: reserved
0x3: BR-mispredicts
Preliminary-Subject Change-July 1996
Table (Cont.) PMCTR Counter Select Options
Counter0 SEL0<0> Counter1 SEL1<3:0> 0xE: Dcache accesses Counter2 SEL2<3:0> 0x9: replay traps 0xA:WB/MAF full replay traps 0xB: external perf_mon_h input. This counts cycles, input sampled sysclk cycles. external status perf_mon_h sampled once system clock held through system clock period. This means that ``sysclock ratio'' counts occur each system clock cycle which status true. 0xC: cycles 0xD: stall cycles 0xE: LDxL instructions issued 0xF: pick CBOX input 0xF: pick CBOX input
Preliminary-Subject Change-July 1996
Table Measurement Mode Control
Kill Settings Measurement Mode Desired Program only only (kernel, executive, supervisor) User only except (not user) User (not kernel, executive, supervisor) Executive supervisor only1
this instance, means kill kernel only. combination Ku=1, Kp=1, Kk=1 used gather events executive supervisor modes only.
Note Both user operating system make subroutine calls that machine PALmode. ``OS only,'' ``user only,'' ``executive supervisor only'' modes measure events during subroutine calls made user. ``OS PAL'' ``user PAL'' modes should used carefully. ``OS PAL'' mode measures events during calls made user, whereas ``user PAL'' mode measures events during calls made
Preliminary-Subject Change-July 1996
Memory Address Translation Unit (Mbox) IPRs
Mbox internal processor registers (IPRs) described Section 8.2.1 through Section 8.2.23. 8.2.1 Dstream Translation Buffer Address Space Number (DTB_ASN) Register DTB_ASN write-only register that must written with exact duplicate ITB_ASN register field. Figure shows DTB_ASN register format. Figure Dstream Translation Buffer Address Space Number (DTB_ASN) Register
ASN<6:0>
LJ-03499-TI0
Preliminary-Subject Change-July 1996
8.2.2 Dstream Translation Buffer Current Mode (DTB_CM) Register DTB_CM write-only register that must written with exact duplicate Ibox current mode (ICM) register field. These bits indicate current mode machine, described Alpha Architecture Reference Manual. Figure shows DTB_CM register format. Figure Dstream Translation Buffer Current Mode (DTB_CM) Register
LJ-03500-TI0
Preliminary-Subject Change-July 1996
8.2.3 Dstream Translation Buffer (DTB_TAG) Register DTB_TAG write-only register that writes contents DTB_PTE register DTB. ensure integrity DTBs, DTB's array updated simultaneously from internal DTB_PTE register when DTB_TAG register written. entry written chosen time DTB_TAG write operation not-last-used replacement algorithm implemented hardware. write operation DTB_TAG register increments translation buffer (TB) entry pointer DTB, which allows writing entire entries. entry pointer initialized entry zero valid bits cleared chip reset timeout reset. Figure shows DTB_TAG register format. Figure Dstream Translation Buffer (DTB_TAG) Register
VA<42:13>
VA<42:13>
LJ-03501-TI0
Preliminary-Subject Change-July 1996
8.2.4 Dstream Translation Buffer Page Table Entry (DTB_PTE) Register DTB_PTE read/write register representing 64-entry page table entries (PTEs). entry written chosen not-last-used replacement algorithm implemented hardware. Write operations DTB_PTE memory format positions, described Alpha Architecture Reference Manual, with exception that some fields ignored. particular, page frame number (PFN) valid stored DTB. ensure integrity DTB, actually written temporary register transferred until DTB_TAG register written. result, writing DTB_PTE then reading without intervening DTB_TAG write operation does return data previously written DTB_PTE register. Read operations DTB_PTE require instructions. First, read from DTB_PTE sends data DTB_PTE_TEMP register. zero value returned integer register file (IRF) DTB_PTE read operation. second instruction reading from DTB_PTE_TEMP register returns entry register file. Reading DTB_PTE register increments entry pointer DTB, which allows reading entire entries. Figure shows DTB_PTE register format. Note Alpha Architecture Reference Manual provides descriptions fields PTE.
Preliminary-Subject Change-July 1996
Figure Dstream Translation Buffer Page Table Entry (DTB_PTE) Register-Write Format
GH<1:0>
PFN<39:13>
LJ-03502-TI0
Preliminary-Subject Change-July 1996
8.2.5 Dstream Translation Buffer Page Table Entry Temporary (DTB_PTE_TEMP) Register DTB_PTE_TEMP read-only holding register used DTB_PTE data. Read operations DTB_PTE require instructions return data register file. first reads DTB_PTE register DTB_PTE_TEMP register returns zero register file. second returns DTB_ PTE_TEMP register integer register file (IRF). Figure shows DTB_PTE_TEMP register format. Figure Dstream Translation Buffer Page Table Entry Temporary (DTB_PTE_TEMP) Register
PFN<39:13> PFN<39:13>
PFN<39:13>
LJ-03503-TI0
Preliminary-Subject Change-July 1996
8.2.6 Dstream Memory Management Fault Status (MM_STAT) Register MM_STAT read-only register that stores information Dstream faults Dcache parity errors. VA_FORM, MM_STAT registers locked against further updates until software reads register. STAT bits only modified hardware when register locked memory management error, miss, Dcache parity error occurs. MM_STAT register unlocked cleared reset. Figure Table describe MM_STAT register format. Figure Dstream Memory Management Fault Status (MM_STAT) Register
OPCODE DTB_MISS BAD_VA
LJ-03504-TI0
Table Dstream Memory Management Fault Status Register Fields
Name DTB_MISS BAD_VA Extent <00> <01> <02> <03> <04> <05> Type Description reference that caused error write operation. reference caused access violation. Includes virtual address. reference read operation set. reference write operation set. reference resulted miss. reference virtual address. (continued next page)
Preliminary-Subject Change-July 1996
Table (Cont.) Dstream Memory Management Fault Status Register Fields
Name OPCODE Extent <10:06> <16:11> Type Description field faulting instruction. Opcode field faulting instruction.
Preliminary-Subject Change-July 1996
8.2.7 Faulting Virtual Address (VA) Register read-only register. When Dstream faults, misses, Dcache parity errors occur, effective virtual address associated with fault, miss, error latched register. VA_FORM, MM_STAT registers locked against further updates until software reads register. register unlocked reset. Figure shows register format. Figure Faulting Virtual Address (VA) Register
Virtual Address
Virtual Address
LJ-03505-TI0
Preliminary-Subject Change-July 1996
8.2.8 Formatted Virtual Address (VA_FORM) Register VA_FORM read-only register containing virtual page table entry (PTE) address calculated function faulting virtual address virtual page table base MVPTBR registers). This done performance enhancement Dstream TBmiss flow. virtual address formatted 32-bit when NT_Mode (MCSR<01>) (see Figure 46). VA_FORM locked Dstream fault, miss, Dcache parity error. VA_FORM, MM_STAT registers locked against further updates until software reads register. VA_FORM register unlocked reset. Figure shows VA_FORM register format when MCSR<01> clear. Figure Formatted Virtual Address (VA_FORM) Register (NT_Mode=1)
VA<31:13> VPTB<63:30>
VPTB<63:30>
LJ-03507-TI0
Figure Formatted Virtual Address (VA_FORM) Register (NT_Mode=0)
VA<42:13>
VPTB<63:33> VA<42:13>
LJ-03506-TI0
Preliminary-Subject Change-July 1996
Table describes VA_FORM register fields. Table Formatted Virtual Address Register Fields
Name NT_Mode=0 VPTB VA<42:13> NT_Mode=1 VPTB VA<31:13> <63:30> <21:03> Virtual page table base address stored MVPTBR Subset original faulting virtual address <63:33> <32:03> Virtual page table base address stored MVPTBR Subset original faulting virtual address Extent Type Description
Preliminary-Subject Change-July 1996
8.2.9 Mbox Virtual Page Table Base Register (MVPTBR) MVPTBR write-only register containing virtual address base page table structure. stored Mbox used calculating VA_FORM value Dstream TBmiss flow. Unlike register, MVPTBR locked against further updates when Dstream fault, Miss, Dcache parity error occurs. Figure shows MVPTBR format. Figure Mbox Virtual Page Table Base Register (MVPTBR)
VPTB<63:30>
VPTB<63:30>
LJ-03508-TI0
Preliminary-Subject Change-July 1996
8.2.10 Dcache Parity Error Status (DC_PERR_STAT) Register DC_PERR_STAT read/write register that locks stores Dcache parity error status. VA_FORM, MM_STAT registers locked against further updates until software reads register. Dcache parity error detected while Dcache parity error status register unlocked, error status loaded into DC_PERR_STAT<05:02>. LOCK register locked against further updates (except bit) until software writes clear LOCK bit. when Dcache parity error occurs while Dcache parity error status register locked. Once set, locked against further updates until software writes DC_PERR_STAT<00> unlock clear bit. when Dcache parity errors detected both pipes within same cycle. this particular situation, pipe0/pipe1 Dcache parity error status bits indicate existence second parity error. DC_PERR_STAT register unlocked cleared reset. Figure Table describe DC_PERR_STAT register format. Figure Dcache Parity Error Status (DC_PERR_STAT) Register
LOCK
LJ-03509-TI0
Preliminary-Subject Change-July 1996
Table Dcache Parity Error Status Register Fields
Name Extent <00> Type Description second Dcache parity error occurred cycle after register locked. result second parity error that occurs within same cycle first. parity error detected Dcache. Bits <05:02> locked against further updates when this set. Bits <05:02> cleared when LOCK cleared. data parity error Dcache bank data parity error Dcache bank parity error Dcache bank parity error Dcache bank
LOCK
<01>
<02> <03> <04> <05>
Preliminary-Subject Change-July 1996
8.2.11 Dstream Translation Buffer Invalidate Process (DTB_IAP) Register DTB_IAP write-only register. write operation this register invalidates data translation buffer (DTB) entries which address space match (ASM) equal zero. 8.2.12 Dstream Translation Buffer Invalidate (DTB_IA) Register DTB_IA write-only register. write operation this register invalidates entries, resets not-last-used (NLU) pointer initial state.
Preliminary-Subject Change-July 1996
8.2.13 Dstream Translation Buffer Invalidate Single (DTB_IS) Register DTB_IS write-only register. Writing virtual address this register invalidates entry that meets either following criteria: entry whose field matches DTB_IS<42:13> whose field matches DTB_ASN<63:57>. entry whose field matches DTB_IS<42:13> whose set.
Figure shows DTB_IS register format. Figure Dstream Translation Buffer Invalidate Single (DTB_IS) Register
VA<42:13>
VA<42:13>
LJ-03510-TI0
Note DTB_IS register written before normal Ibox trap point. invalidate single operation aborted Ibox only following trap conditions: miss mispredict When HW_MTPR DTB_IS executed user mode
Preliminary-Subject Change-July 1996
8.2.14 Mbox Control Register (MCSR) MCSR read/write register that controls features records status Mbox. This register cleared chip reset timeout reset. Figure Table describe MCSR format. Figure Mbox Control Register (MCSR)
RAZ/IGN M_BIG_ENDIAN SP<1:0> E_BIG_ENDIAN
RAZ/IGN
LJ-03511-TI0
Preliminary-Subject Change-July 1996
Table Mbox Control Register Fields
Name M_BIG_ ENDIAN SP<1:0> Extent <00> Type RW,0 Description Mbox Endian mode enable. When set, physical address inverted longword Dstream references. 21164-266, 21164-300, 21164-333 Superpage mode enables. Note: Superpage access only allowed kernel mode. SP<1> enables superpage mapping when VA<42:41> this mode, virtual addresses VA<39:13> mapped directly physical addresses PA<39:13>. Virtual address VA<40> ignored this translation. SP<0> enables one-to-one superpage mapping Dstream virtual addresses with VA<42:30> 1FFE16 this mode, virtual addresses VA<29:13> mapped directly physical addresses PA<29:13>, with bits <39:30> physical address SP<0> NT_Mode that used control virtual address formatting read operation from VA_FORM register. 21164-P1 21164-P2 SP<0> must always set. Clearing this will cause 21164-Pn operation UNPREDICTABLE. Reserved E_BIG_ ENDIAN <03> <04> RW,0 RW,0 Reserved Digital. Must zero (MBZ). Ebox Endian mode enable. This sent Ebox enable Endian support EXTxx, MSKxx INSxx byte instructions. This causes shift amount inverted (one's-complemented) prior shifter operation. Reserved Digital. Must zero (MBZ).
<02:01>
RW,0
Reserved
<05>
RW,0
Preliminary-Subject Change-July 1996
8.2.15 Dcache Mode (DC_MODE) Register DC_MODE read/write register that controls diagnostic test modes Dcache. This register cleared chip reset timeout reset. Figure Table describe DC_MODE register format. Note following settings required normal operation: DC_ENA DC_FHIT DC_BAD_PARITY DC_PERR_DISABLE
Figure

Order Number: EC-QAEPD-TE Revision/Update Information: This document s

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