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SDRAM Serial Presence Detect (SPD) Specification REVISION 1.2B No


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SDRAM Serial Presence Detect (SPD) Specification
SDRAM Serial Presence Detect (SPD) Specification
REVISION 1.2B November, 1999
Nov, 1999
Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
THIS SPECIFICATION PROVIDED WITH WARRANTIES WHATSOEVER, INCLUDING WARRANTY MERCHANTABILITY, NONINFRINGEMENT, FITNESS PARTICULAR PURPOSE, WARRANTY OTHERWISE ARISING PROPOSAL, SPECIFICATION SAMPLE. Intel disclaims liability, including liability infringement proprietary rights, relating information this specification. license, express implied, estoppel otherwise, intellectual property rights granted herein.
*Third-party brands names property their respective owners.
Copyright Intel Corporation, 1997, 1999
Nov, 1999
Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
Changes:
Revision 1.2B:
Updated Table Serial Present Detect Data format, consistency: Definitions bytes 32-35 were added this summary table since they were already defined specs Added Section 5.0, data format example.
Revision 1.2A:
Modified specification name Corrects typos Rev1.2 revision history Byte definition reserved thermal information, values
Revision adds:
Bytes 126, 127: Additional Information "backward compatibility" Bytes 93-94: Manufacturing Date Code Bytes 32-35: Additional Timing Information Byte Changed nomenclature from Bank DIMM remove confusion Rows Banks DIMM
Revision adds comments clarify several Bytes:
Bytes 3-4: Note added clarify address row/column 1/16 rollup usage. Bytes 5,17: Note added clarify Module, SDRAM Device bank usage. Bytes 23-26: Note added clarify timing1/16ns rollup usage.
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Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
TABLE CONTENTS
CHANGE HISTORY LIST TABLES LIST FIGURES INTRODUCTION SDRAM MODULE PERFORMANCE GRADES EEPROM COMPONENT SPECIFICATIONS SERIAL PRESENCE DETECT EEPROM DATA DATA FORMAT EXAMPLE
LIST TABLES
TABLE EEPROM COMPONENT ABSOLUTE MAXIMUM RATINGS TABLE EEPROM COMPONENT OPERATING CONDITIONS TABLE EEPROM COMPONENT A.C. D.C. CHARACTERISTICS TABLE EEPROM COMPONENT A.C. TIMING PARAMETERS TABLE SERIAL PRESENCE DETECT DATA FORMAT TABLE DATA FORMAT EXAMPLE
LIST FIGURES
FIGURE EEPROM COMPONENT A.C. TIMING PARAMETERS FIGURE EEPROM DATA VALIDITY FIGURE EEPROM START STOP CONDITIONS FIGURE EEPROM ACKNOWLEDGE FIGURE EEPROM BYTE WRITE OPERATION FIGURE EEPROM PAGE WRITE OPERATION FIGURE EEPROM CURRENT ADDRESS READ OPERATION FIGURE EEPROM RANDOM READ OPERATION FIGURE EEPROM SEQUENTIAL READ OPERATION
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Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
Introduction
This specification defines Serial Presence Detect (SPD) electrical Data Structure requirements Synchronous DRAM Dual In-Line Memory Modules (SDRAM DIMMs) Smalloutline Memory Modules (SO-DIMM). These SDRAM DIMMs intended main memory installed personal computer, work-station, and/or server motherboards.
168-DIMM reference
This specification largely follows JEDEC defined 168-pin SO-144 SDRAM DIMM specs July 1996. Changes process currently shown italics.
SDRAM Module Performance Grades
Three performance grades defined matrix: Latency Latency Latency highest latency, lowest performance highest latency highest latency, highest performance (may restrict freq)
This relative series three latencies, being most commonly available this speed grade. performance grade module determined read data access time (Tac), cycle time (Trc) supported SDRAM components. Latency numbers sequence will depend speeds which supported module.
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SDRAM Serial Presence Detect (SPD) Specification
EEPROM Component Specifications
Serial Presence Detect function implemented using 2048 EEPROM component. This nonvolatile storage device contains data programmed DIMM manufacturer that identifies module type various SDRAM organization timing parameters. System read/write operations EEPROM device occur using DIMM's (clock) (data) signals, together with SA(2:0) which provide EEPROM Device Address. EEPROM device Write Protect input pin, must tied non-write protect state DIMM PCB. EEPROM device selected DIMM manufacturer must SA(2:0) device address signals. EEPROM must operate with Vdc.
Table EEPROM Component Absolute Maximum Ratings
Parameter Input Output Voltages with Respect Ground Ambient Storage Temperature Range +4.6V -0.3V +100
Table EEPROM Component Operating Conditions
Parameter Ambient Operating Temperature Positive Power Supply Range 3.0V 3.6V
Table EEPROM Component A.C. D.C. Characteristics
Symbol ICCA Parameter Active Power Supply Current Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Test Conditions fSCL VOUT Units
-0.3
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SDRAM Serial Presence Detect (SPD) Specification
Table EEPROM Component A.C. Timing Parameters
Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSU:STO Parameter Clock Frequency Noise Suppression Time Constant SCL, inputs Data Valid Time Must Free before Transmission Start Start Condition Hold Time Clock Time Clock High Time Start Condition Setup Time (for Repeated Start Condition) Data Hold Time Data Setup Time Rise Time Fall Time Stop Condition Setup Time Data Hold Time Write Cycle Time Units
Note: write cycle time (tWR) time from valid stop condition write sequence EEPROM internal erase/program cycle. During write cycle, EEPROM interface circuits disabled, remains high pull-up resistor, EEPROM does respond slave address.
HIGH
SU:STA
HD:STA
SU:DAT
SU:STO
Figure EEPROM Component A.C. Timing Parameters
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Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
Data stable
Data change
Figure EEPROM Data Validity
START START High transition while high STOP high transition while high
STOP
Figure EEPROM Start Stop conditions
Output from transmitter
Output from receiver START ACKNOWLEDGE
ACKNOWLEDGE: Transmitter releases after transmitting eight bits. During ninth clock cycle receiver pulls acknowledge receit eight bits.
Figure EEPROM Acknowledge
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Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
SYSTEM MASTER:
slave address (write)
word address
data
EEPROM:
Figure EEPROM Byte Write Operation
SYSTEM MASTER:
slave address (write)
word address
data
data
data n+15
EEPROM:
Figure EEPROM Page Write Operation
SYSTEM MASTER:
slave address (Read)
EEPROM:
data
Figure EEPROM Current Address Read Operation
SYSTEM MASTER:
slave address (write)
word address
slave address (read)
EEPROM:
data
Figure EEPROM Random Read Operation
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Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
SYSTEM MASTER:
slave address (read)
EEPROM:
data
data
data
Figure EEPROM Sequential Read Operation
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SDRAM Serial Presence Detect (SPD) Specification
Serial Presence Detect EEPROM Data
Table Serial Presence Detect Data Format
Byte Number 36-61 64-71 73-90 91-92 93-94 95-98 99-125 128+ Function Defines bytes written into serial memory module manufacturer Total bytes memory device Fundamental memory type (FPM, EDO, SDRAM.) from Appendix addresses this assembly (includes Mixed-size addr) Column Addresses this assembly (includes Mixed-size addr) Module Rows this assembly Data Width this assembly Data Width continuation Voltage interface standard this assembly SDRAM Cycle time, CL=X (highest latency) SDRAM Access from Clock (highest latency) DIMM Configuration type (non-parity, ECC) Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM width Minimum Clock Delay Back Back Random Column Address Burst Lengths Supported Banks Each SDRAM Device CAS# Latencies Supported Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle time (2nd highest latency) SDRAM Access from Clock (2nd highest latency) SDRAM Cycle time (3rd highest latency) SDRAM Access from Clock (3nd highest latency) Precharge Time (Trp) Active Active (Trrd) Delay (Trcd) Minimum Pulse Width (Tras) Density each module (mixed, non-mixed sizes) Command Address signal input setup time Command Address signal input hold time Data signal input setup time Data signal input hold time Superset Information (may used future) Data Revision Code Checksum bytes 0-62 Manufacturer's JEDEC code JEP-108E Manufacturing Location Manufacturer's Part Number Revision Code Manufacturing Date Assembly Serial Number Manufacturer Specific Data Intel specification frequency Intel Specification CAS# Latency support Unused storage locations Required/ Optional Required Required Required Required Required Required Required Required Required Required Required Required Required Required Required Required* Required* Required* Required* Required* Required* Required* Required* Required* Required* Optional* Optional* Required* Required* Required* Required* Required Required Required Required Required Required Required Optional Optional Optional Optional Optional Optional Optional Required Required
Notes: Required/Optional* (bold*) SDRAM only bytes
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SDRAM Serial Presence Detect (SPD) Specification
Byte Number Bytes used Module Manufacturer (General)
This field describes total number bytes used module manufacturer data (optional) specific supplier information. byte count includes fields required optional data.
Number bytes Undefined Value
Byte Total Memory Size (General)
This field describes total size serial memory used hold Serial Presence Detect data.
Serial Memory Size Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes 1024 Bytes 2048 Bytes 4096 Bytes 8192 Bytes Value
Byte Memory Type (General)
This field describes fundamental memory type implemented module.
Memory Type SDRAM Value
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SDRAM Serial Presence Detect (SPD) Specification
Note Bytes 3-4: Bytes show roll-up value (i.e., 1row/16rows).
SDRAM devices over duration Byte (SPD Jedec level), values 1-3rows/cols expected, equivalent 16-18rows/columns. Jedec Byte would change level values row/col become available.
Byte Number Address Bits (SDRAM specific)
This field describes number address bits SDRAM array. Note: number address bits does include bank selects (BA0, BA1). module only bank module banks same size organization, then bits describe number address bits, bits module banks with different size/organization, then bits describe addressing bank bits describe addressing bank
Number Addr bits Undefined 1/16 2/17 Number Addr bits Undefined 1/16 2/17 Bits Value Bits Value
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SDRAM Serial Presence Detect (SPD) Specification
BYTE Number Column Address Bits (SDRAM specific)
This field describes number column address bits SDRAM array. Note: number column address bits does include bank selects (BA0, BA1), AutoPrecharge bit. module only bank module banks same size organization, then bits describe number column address bits, bits module banks with different size/organization, then bits describe column addressing bank bits describe column addressing bank
Number Addr bits Undefined 1/16 2/17 Number Addr bits Undefined 1/16 2/17 Bits Value Bits Value
BYTE Number Module Rows
This field describes number rows SDRAM components module. Byte applies SDRAM device banks module with rows could have devices with 2-16 internal banks).
Number Banks Undefined Value
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BYTES Module Data Width
This field describes data width SDRAM module. byte byte MSB.
Module Data Width Undefined Byte (Hex) Byte (Hex)
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Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
BYTE Module Interface Signal Levels
This field describes SDRAM module signal voltage interface.
Voltage Interface Volt/TTL LVTTL HSTL SSTL SSTL Table Value
BYTE SDRAM Cycle time (highest latency)
This field defines total minimum cycle time (clock period) SDRAM. example SDRAMs support latency indicated byte 18), this byte defines Tclk latency byte broken into nibbles: high order nibble (bits through designate cycle time granularity value presented order nibble granularity 1/10 added value higher nibble.
BYTE SDRAM Access time from Clock (highest latency)
This field defines maximum clock data SDRAM (Tac). example SDRAMs support latency indicated byte 18), this byte defines latency byte broken into nibbles: high order nibble (bits through designate cycle time granularity value presented order nibble granularity 1/10 added value higher nibble.
BYTE Module Configuration Type
This field defines module's error detection correction scheme.
Error Detect/Correct None Parity Value
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SDRAM Serial Presence Detect (SPD) Specification
BYTE Refresh Rate/Type
This field defines module's refresh rate type.
Refresh Period Normal (15.625 Reduced (.25x).3.9 Reduced (.5x) Extended (2x) 31.3 Extended (4x) 62.5 Extended (8x) Normal (15.625 Reduced (.25x).3.9 Reduced (.5x) Extended (2x) 31.3 Extended (4x) 62.5 Extended (8x) Self Refresh Flag Self Refresh Bits (hex)
BYTE SDRAM Width (Primary SDRAM)
Bits this byte define data width primary SDRAM components used module. primary SDRAM that which used data. Examples primary (data) SDRAM widths x16, x32. this byte flag which indicates that bank module primary SDRAM width that first bank. module banks with same Primary SDRAM width, then remains "0".
Primary SDRAM Component Data Width Undefined Bank Configuration Bank -ORBank uses same width Primary SDRAM Bank Bank Primary SDRAM width Bank Bits Value Bits Value
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SDRAM Serial Presence Detect (SPD) Specification
BYTE Error Checking SDRAM Width
module incorporates error checking primary data SDRAM does include these bits; i.e. there separate error checking SDRAMs, then error checking SDRAM's width expressed this byte. Examples error checking SDRAM widths include x16. Bits this byte define data width Error Checking SDRAM components used module. flag which indicates that bank module Error Checking SDRAM width that first bank. module banks with same Error Checking SDRAM width, then remains "0".
Error Checking SDRAM Component Data Width Undefined Bank Configuration Bank -ORBank uses same width SDRAM Bank Bank SDRAM width Bank Bits Value Bits Value
BYTE SDRAM Device Attributes, Clock Delay Back Back Random Column Addresses
Number Clocks Undefined Value
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SDRAM Serial Presence Detect (SPD) Specification
BYTE SDRAM Device Attributes, Burst Lengths Supported
This byte defines various burst lengths supported. burst length supported, then corresponding
Burst Length Page Burst Length Burst Length Burst Length Burst Length
BYTE SDRAM Device Attributes, Number Banks SDRAM Device
This byte defines number banks internal SDRAM devices each DIMMs.
Number Device Banks Resvd. Value
BYTE SDRAM Device Attributes, Latency
This byte defines which latencies supported. then that Latency supported.
Latency Latency Latency Latency Latency Latency Latency
BYTE SDRAM Device Attributes, Latency
This byte defines which latencies acceptable Module. then that Latency supported.
Latency Latency Latency Latency Latency Latency Latency
BYTE SDRAM Device Attributes, Latency
This byte defines which latencies acceptable Module. then that Latency supported.
Latency Latency Latency Latency Latency Latency Latency
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SDRAM Serial Presence Detect (SPD) Specification
BYTE SDRAM Module Attributes
This byte defines various aspects module. aspect TRUE, then corresponding "1".
Redundant Addr Differential Clock Input Registered DQMB Inputs Buffered DQMB Inputs On-Card (Clock) Registered Address/ Control Inputs Buffered Address/ Control Inputs
Address, RAS, CAS, CKE, Redundant addressing implies SDRAMs having same address depth (e.g. 4Mx4 mixed with 4Mx16) same 8-byte quad word, having different RAS/CAS addressing and/or different numbers device banks. Actual implementation determined.
BYTE SDRAM Device Attributes, General
This byte defines various aspects SDRAMs module. aspect TRUE, then corresponding "1".
Upper tolerance: Lower tolerance: Supports Write1/Rea Burst Supports Precharge Supports AutoPrecharge Supports Early RAS# Precharge
Tolerance refers voltage range under which SDRAMs operate timings specified bytes 23-30.
Note Bytes 23-24: Bytes 23-24 show roll-up value (i.e., 1ns/16ns).
SDRAM devices over duration Byte (SPD Jedec level), values 1-3ns expected, equivalent 16-18ns. Jedec Byte will change level when values become available.
BYTE SDRAM Cycle time (2nd highest latency)
This field defines minimum cycle time (clock period) SDRAM when operating highest latency. example SDRAMs support latency indicated byte 18), this byte defines Tclk latency byte broken into nibbles: high order nibble (bits through designate cycle time granularity value presented order nibble granularity 1/10 added value higher nibble.
Nanoseconds Undefined 16ns 17ns Bits Value 1/10 nanoseconds Bits Value
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SDRAM Serial Presence Detect (SPD) Specification
BYTE SDRAM Access from Clock (2nd highest latency)
This field defines maximum clock data SDRAM (Tac) when operating highest latency. example SDRAMs support latency indicated byte 18), this byte defines latency byte broken into nibbles: high order nibble (bits through designate cycle time granularity value presented order nibble granularity 1/10 added value higher nibble.
Nanoseconds Undefined 16ns 17ns Bits Value 1/10 nanoseconds Bits Value
BYTE SDRAM Cycle time (3rd highest latency)
This field defines minimum cycle time (clock period) SDRAM when operating highest latency. example SDRAMs support latency indicated byte 18), this byte defines Tclk latency byte broken into sections: high order bits (bits 7:2) designate cycle time granularity value presented bits granularity added value higher nibble.
Nanoseconds Undefined Bits Binary Value 000000 000001 000010 000011 000100 111111 nanoseconds Bits binary value
BYTE SDRAM Access from Clock (3rd highest latency)
This field defines maximum clock data SDRAMs (Tac) when operated highest latency. example SDRAMs support latency indicated byte 18), this byte defines latency byte broken into sections: high order bits (bits 7:2) designate access time granularity value presented bits granularity added value higher nibble.
Nanoseconds Undefined Bits Binary Value 000000 000001 000010 000011 000100 111111 nanoseconds Bits Binary Value
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SDRAM Serial Presence Detect (SPD) Specification
BYTE Minimum Precharge Time
This byte defines precharge activate minimum (Trp) using granularity.
Precharge Minimum undefined Bits Value
BYTE Active Active
This byte defines minimum activate activate delay (Trrd) using granularity.
Minimum undefined Bits Value
BYTE Delay
This byte defines minimum delay (Trcd) using granularity.
Delay Minimum undefined Bits Value
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Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
BYTE Minimum Pulse Width
This byte defines minimum activate precharge time (Tras) using granularity.
Activate Precharge Minimum undefined Bits Value
BYTE Density Each Module
This byte describes memory capacity each physical DIMM module. This byte will have least represent least row's size. there more than module represented Byte they have same size, then only this field set. module more than different sizes then more than will set. example: Banks
512MByte
Size 32MByte 32MByte 32MByte
256MByt 128MByte
Size 32MByte 16MByte
64MByte
Byte contents 0000 1000 0000 1000 0000 1100
32MByte 16MByte 8MByte 4MByte
Size
BYTE 32-35 Input setup Hold time (Under JEDEC Committee Ballot JC42.5-97119)
Definition these bytes JEDEC Ballot process. proposed data structure defined:
Positive/ Negative Setup Time Setup Time tenth
defines positive setup time w.r.t. clock defines negative setup time w.r.t clock Defines setup time 3-0= Defines setup time tenth
Nov, 1999
Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification Some encoded values table:
Comment -0.1 -0.2 -0.9 -1.0 -1.1 -1.9 -2.0 -7.0 -7.9
BYTE Command Address signal input setup time:
This byte describes input setup time w.r.t rising edge clock input. Both positive negative setup times supported.
Positve/ Negative Setup Time Setup Time tenth
defines positive setup time w.r.t. clock defines negative setup time w.r.t clock Defines setup time 3-0= Defines setup time tenth Example: address input setup time +2.5ns byte value will 0101) Similarly: address input setup time -0.5ns byte value will 0101)
Nov, 1999
Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
BYTE Command Address signal input hold time:
This byte describes input hold time w.r.t rising edge clock input. Both positive negative hold times supported.
Positive/ Negative Hold Time Hold Time tenth
defines positive hold time w.r.t. clock defines negative hold time w.r.t clock Defines hold time 3-0= Defines hold time tenth Example: command input hold time +2.5ns byte value will 0101) Similarly: command input hold time -0.5ns byte value will 0101)
BYTE Data signal input setup time:
This byte describes input setup time w.r.t rising edge clock input. Both positive negative setup times supported.
Positive/ Negative Setup Time Setup Time tenth
defines positive setup time w.r.t. clock defines negative setup time w.r.t clock Defines setup time 3-0= Defines setup time tenth Example: data input setup time +2.5ns byte value will 0101) Similarly, data input setup time -0.5ns byte value will 0101)
Nov, 1999
Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
BYTE Data signal input hold time:
This byte describes input hold time w.r.t rising edge clock input. Both positive negative hold times supported.
Positive/ Negative Hold Time Hold Time tenth
defines positive hold time w.r.t. clock defines negative hold time w.r.t clock Defines hold time Defines hold time tenth Example: data input hold time +2.5ns byte value will 0101) Similarly, data input hold time -0.5ns byte value will 0101)
BYTE Data Revision Code This byte specifies SDRAM DIMM Data revision which module conforms.
Revision Current Release Nov. Bits Value
This byte indicates revision number. revision higher should encoded BCD. example, 1.2, data should
BYTE Checksum Bytes 0-62
This byte checksum bytes through This byte contains value 8-bits arithmetic bytes through
BYTES 64-71 Manufacturer's JEDEC Code BYTE Manufacturing Location BYTE 73-90 Manufacturer's Part Number BYTE 91-92 Revision Code BYTE 93-94 Manufacturing Date
Definition these bytes JEDEC Ballot process. proposed data structure
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SDRAM Serial Presence Detect (SPD) Specification
BYTE 95-98 Assembly Serial Number BYTE 99-125 Manufacturer Specific Data BYTE Intel specification frequency
This byte defines clock frequency Intel SDRAM DIMM specification.
Intel Specification Frequency Value
100Mhz support this byte should programmed (64)h. 66Mhz support this byte should programmed (66)h, which required backward compatibility with existing BIOS code.
BYTE Intel Specification details 100MHz Support
This byte defines SDRAM component Clock interconnection details DIMMs defined:
CLK0 CLK1 CLK2 CLK3 Junction Temp Latency Latency Intel "Concurrent
bit7= CLK0 connected DIMM bit7= CLK0 connected DIMM bit6= CLK1 connected DIMM bit6= CLK1 connected DIMM bit5= CLK2 connected DIMM bit5= CLK2 connected DIMM bit4= CLK3 connected DIMM bit4= CLK3 connected DIMM bit3= component tested case temperature (value TBD) bit3= component tested case temperature (value TBD) support shown:
Performance Grade Latency Latency Value Bits 2-1)
bit0= supports Intel defined Concurrent Auto-precharge bit0= does supports Intel defined Concurrent Auto-precharge
66hex value 66Mhz preserved backward compatibility Bits "preserved" backward compatibility with existing BIOSes complete definition "Intel Concurrent functionality consult Intel's PC-SDRAM specification.
Nov, 1999
Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification Example Byte with following encoding will imply:
CLK0 CLK1 CLK2 CLK3 Junction Temp Latency Latency Intel
Single sided DIMM CLK0 CLK2 connected DIMM junction temp SDRAMs with CL=2 support SDRAMs supporting Intel defined Concurrent Auto-precharge Example Byte with following encoding will imply:
CLK0 CLK1 CLK2 CLK3 Junction Temp Latency Latency Intel
Double sided DIMM CLK0, CLK1, CLK2 CLK3 connected DIMM junction temp SDRAMs with CL=2 support supporting Intel defined Concurrent Auto-precharge
full CL=2 support 100mhz BIOS needs check bytes full CL=2 support 100mhz BIOS needs check bytes
Nov, 1999
Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
Data Format Example
table below serves example data implemented. example shows data particular PC100-222 PC133-333 unbuffered SDRAM DIMM with following characteristics: 128MB, x64, 8Mx8. Note that SDRAM with different characteristics than above, some values will changed accordingly; also, some data vendor dependent.
Table data format example
Byte Description Number bytes used module manufacturer Total memory size Memory type Number address bits Number column address bits Number module rows Module data width, Module data width, Module interface signal levels SDRAM cycle time highest (Tclk) SDRAM access time from clock highest (Tac) Module configuration type Refresh rate/type Primary SDRAM width Error Checking SDRAM width SDRAM device attributes, clock delay back back random column addresses (Tccd) SDRAM device attributes, burst lengths supported SDRAM device attributes, number banks SDRAM device SDRAM device attributes, latency SDRAM device attributes, latency SDRAM device attributes, latency SDRAM module attributes SDRAM device attributes, general SDRAM cycle time highest (Tclk) SDRAM access time from clock highest (Tac) Value PC100-222 Value PC133-333 Comment bytes used bytes SDRAM address bits column address bits rows LVTTL Tclk 10ns 100MHz Tclk 7.5ns 133MHz 100MHz 5.4ns 133MHz Non-parity, non-ECC 15.6us/Self refresh None clock
Burst length page banks latency latency Unbuffered Supports auto-precharge, precharge all, write1/read burst Tclk 10ns
Nov, 1999
Revision 1.2B
SDRAM Serial Presence Detect (SPD) Specification
SDRAM cycle time highest (Tclk) SDRAM access time from clock highest (Tac) Minimum precharge time (Trp) Minimum active active delay (Trrd) Minimum delay (Trcd) Minimum pulse width (Tras)
20ns (value vendor dependent) 15ns (value vendor dependent) 20ns (value vendor dependent) 45ns 133MHz 50ns 100MHz (value vendor dependent) 64MB 2.0ns 100MHz 1.5ns 133MHz 1.0ns 100MHz 0.8ns 133MHz 2.0ns 100MHz 1.5ns 133MHz 1.0ns 100MHz 0.8ns 133MHz Rev. Value SDRAM dependent Value vendor dependent 100MHz (for PC-100 compatibility) Contains correct value PC100 support
36-61 64125
Module bank density Command Address signal input setup time Command Address signal input hold time Data signal input setup time Data signal input hold time Reserved revision Checksum byte 0-62 Manufacturer's Data Intel specification frequency Details PC100
Nov, 1999
Revision 1.2B

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