Single-Chip Parallel Multiple Instruction Multiple Data (MIMD) Digital
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
Single-Chip Parallel Multiple Instruction Multiple Data (MIMD) Digital Signal Processor (DSP) More Than Billion RISC-Equivalent Operations Second Master Processor (MP) 32-Bit Reduced Instruction Computing (RISC) Processor IEEE-754 Floating-Point Capability 4K-Byte Instruction Cache 4K-Byte Data Cache Four Parallel Processors (PP) 32-Bit Advanced DSPs 64-Bit Opcode Provides Many Parallel Operations Cycle 2K-Byte Instruction Cache 8K-Byte Data Transfer Controller 64-Bit Data Transfers Megabytes Second (MBps) Transfer Rate 32-Bit Addressing Direct DRAM VRAM Interface With Dynamic Sizing Intelligent Queuing Cycle Prioritization Video Controller Provides Video Timing Video Random-Access Memory (VRAM) Control Dual-Frame Timers Simultaneous Image-Capture Display Systems Big- Little-Endian Operation 50K-Byte On-Chip 4G-Byte Address Space 20-ns Cycle Time 3.3-V Operation IEEE Standard 1149.1 Test Access Port (JTAG) Military Operating Temperature Range 55°C 125°C
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Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. IEEE Standard 1149.1-1990, IEEE Standard Test Access Port Boundary-Scan Architecture
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1998, Texas Instruments Incorporated
products compliant MIL-PRF-38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
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Table Contents description Assignments Numerical Listing Assignments Alphabetical Listing Assignments Numerical Listing Assignments Alphabetical Listing Terminal Functions architecture master processor (MP) architecture control registers parameter interrupt vectors opcode formats opcode summary architecture registers data-unit registers address-unit registers program flow control (PFC) unit registers cache architecture parameter PP-interrupt vectors data unit architecture multiplier program-flow-control unit architecture address-unit architecture instruction opcode formats EALU operations architecture local memory interface external memory timing examples SDRAM-type cycles special register cycles device reset absolute maximum ratings over specified temperature ranges recommended operating conditions electrical characteristics over recommended ranges supply voltage operating case temperature signal transition levels timing parameter symbology general notes timing parameters CLKIN timing requirements local-bus switching characteristics over full operating range: CLKOUT device reset timing requirements local timing requirements: cycle configuration inputs local timing: cycle completion inputs general output signal characteristics over operating conditions data input timing local timing: 2-cycle/column timing external interrupt timing input timing host-interface timing video interface timing: SCLK timing video interface timing: FCLK input video outputs video interface timing: external sync inputs emulator interface connection MECHANICAL DATA MECHANICAL DATA
description
SMJ320C80 single-chip, MIMD parallel processor capable performing over billion operations second. consists 32-bit RISC master processor with 100-MFLOPS (million floating-point operations second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), transfer controller with 400-MBps off-chip transfer rate, video controller. processors coupled tightly through on-chip crossbar that provides shared access on-chip RAM. This performance programmability make 'C80 ideally suited video, imaging, high-speed telecommunications applications.
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Assignments Numerical Listing
NUMBER NAME HACK DQM7 DQM5 SCLK1 EINT1 REQ1 DQM6 DQM3 DQM1 DDIN FCLK0 CSYNC0 HBLNK0 STATUS3 CLKIN DQM2 NUMBER NAME DBEN CAREA0 CBLNK0 VBLNK0 RETRY UTIME RESET REQ0 DQM0 FCLK1 CAREA1 SCLK0 VSYNC0 FAULT STATUS2 READY HREQ DQM4 STATUS5 CLKOUT LINT4 EINT3 NUMBER NAME HSYNC0 EINT2 CBLNK1 VBLNK1 STATUS0 CSYNC1 HBLNK1 STATUS1 EMU1 STATUS4 VSYNC1 HSYNC1 NUMBER NAME TRST XPT1 XPT0 EMU0
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Assignments Numerical Listing (Continued)
NUMBER AA31 AA33 AA35 AB32 AB34 AC31 AC33 AC35 AD32 AD34 AE31 AE33 AE35 AF32 AF34 NAME XPT2 NUMBER AG31 AG33 AG35 AH32 AH34 AJ31 AJ33 AJ35 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK32 AK34 AL11 AL13 AL15 NAME NUMBER AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM32 AM34 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 NAME NUMBER AN29 AN31 AN33 AP10 AP12 AP14 AP16 AP18 AP20 AP22 AP24 AP26 AP28 AP30 AP32 AR11 AR13 AR15 AR17 AR19 AR21 AR23 AR25 AR27 AR29 AR31 NAME
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Assignments Alphabetical Listing
NAME CAREA0 CAREA1 CAS/DQM0 NUMBER NAME CAS/DQM1 CAS/DQM2 CAS/DQM3 CAS/DQM4 CAS/DQM5 CAS/DQM6 CAS/DQM7 CBLNK0/VBLNK0 CBLNK1/VBLNK1 CLKIN CLKOUT CSYNC0/HBLNK0 CSYNC1/HBLNK1 NUMBER AM10 AP10 AN11 AL11 AR13 AN13 AP14 AM14 AR15 AL15 AP16 AN17 AM16 AL17 AL19 AN19 AM20 NAME NUMBER AL21 AM22 AP20 AK22 AN23 AL25 AR21 AM26 AL27 AM28 AP22 AN29 AR23 AN25 AL29 AP26 AR27 AP28 AJ33 AR31 AH32 AN31 AF32 AP32 AL33 AF34 AM34 AE33 AC33 AL35 AH34 AB32 AG35 AE35 AB34 NAME DBEN DDIN EINT1 EINT2 EINT3 EMU0 EMU1 FAULT FCLK0 FCLK1 HACK HREQ HSYNC0 HSYNC1 LINT4 READY REQ0 REQ1 RESET RETRY SCLK0 SCLK1 STATUS0 STATUS1 STATUS2 STATUS3 STATUS4 NUMBER AK18
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Assignments Alphabetical Listing (Continued)
NAME STATUS5 TRG/CAS TRST UTIME NUMBER NAME NUMBER AA31 AA33 AC35 AD34 AG31 AJ35 AK12 AK16 AK24 AK28 AK34 AM32 AN15 AN21 AN33 AP12 AP18 AP24 AP30 AR19 NAME NUMBER AR29 NAME VSYNC0 VSYNC1 XPT0 XPT1 XPT2 NUMBER AA35 AC31 AD32 AE31 AG33 AJ31 AK10 AK14 AK20 AK26 AK32 AL13 AL23 AL31 AM12 AM18 AM24 AM30 AN27 AR11 AR17 AR25
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Assignments Numerical Listing
NUMBER NAME STATUS3 STATUS2 STATUS1 STATUS0 FAULT READY RETRY UTIME RESET HREQ HACK REQ1 REQ0 CLKIN CAS/DQM7 NUMBER NAME CAS/DQM6 CAS/DQM5 CAS/DQM4 CAS/DQM3 CAS/DQM2 CAS/DQM1 CAS/DQM0 TRG/CAS FCLK1 STATUS5 DBEN DDIN CLKOUT CAREA1 SCLK1 FCLK0 SCLK0 CAREA0 NUMBER NAME LINT4 EINT3 EINT2 EINT1 CBLNK1 VBLNK1 CBLNK0 VBLNK0 CSYNC1 HBLNK1 CSYNC0 HBLNK0 VSYNC1 VSYNC0 HSYNC1 HSYNC0 TRST EMU1 XPT0 XPT1 EMU0 NUMBER NAME XPT2
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Assignments Numerical Listing (Continued)
NUMBER NAME NUMBER NAME NUMBER NAME NUMBER NAME STATUS4
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Assignments Alphabetical Listing
NAME CAREA0 CAREA1 CAS/DQM0 NUMBER NAME CAS/DQM1 CAS/DQM2 CAS/DQM3 CAS/DQM4 CAS/DQM5 CAS/DQM6 CAS/DQM7 CBLNK0/VBLNK0 CBLNK1/VBLNK1 CLKIN CLKOUT CSYNC0/HBLNK0 CSYNC1/HBLNK1 NUMBER NAME NUMBER NAME DBEN DDIN EINT1 EINT2 EINT3 EMU0 EMU1 FAULT FCLK0 FCLK1 HACK HREQ HSYNC0 HSYNC1 LINT4 READY REQ0 REQ1 RESET RETRY SCLK0 SCLK1 STATUS0 STATUS1 STATUS2 STATUS3 STATUS4 STATUS5 NUMBER
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Assignments Alphabetical Listing (Continued)
NAME TRG/CAS TRST UTIME NUMBER NAME NUMBER NAME NUMBER NAME VSYNC0 VSYNC1 XPT0 XPT1 XPT2 NUMBER
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Terminal Functions
TERMINAL NAME TYPE DESCRIPTION LOCAL MEMORY INTERFACE DBEN DDIN FAULT READY RETRY STATUS5 STATUS0 Address bus. output 32-bit byte address external memory cycle. address multiplexed DRAM accesses. Address-shift selection. determine column address appears address bus. Eight shift values supported, including zero. size selection. indicate size memory other devices being accessed, allowing dynamic sizing data buses less than bits wide. Cycle timing selection. signals determine timing current memory access. Data bus. transfer bits data memory cycle into 'C80. Data-buffer enable. DBEN drives active-low output enables bidirectional transceivers that used buffer input output data Data direction indicator. DDIN indicates direction data that passes through transceivers. When DDIN low, transfer from external memory into 'C80. Fault. FAULT driven external circuitry inform 'C80 that fault occurred current memory access. Page size indication. indicate page size memory device(s) being accessed current cycle. 'C80 uses this information determine when begin access. Ready. READY indicates that external device ready complete memory cycle. READY driven external circuitry insert wait states into memory cycle. latch. high-to-low transition used latch valid 32-bit byte address that present Retry. RETRY driven external circuitry indicate that addressed memory busy. 'C80 memory cycle rescheduled. Status code. time, STATUS5 STATUS0 indicate type cycle being performed. column time, they identify processor type request that initiated cycle. User-timing selection. UTIME causes timing DQM7 DQM0 modified that custom memory timings generated. During reset, UTIME selects endian mode which 'C80 operates. DRAM, VRAM, SDRAM CONTROL DQM7 DQM0 Column-address strobes. DQM7 DQM0 drive inputs DRAMs VRAMs, input synchronous dynamic random-access memories (SDRAMs). eight strobes provide byte-write access memory. Special function. selects special VRAM functions such block-write, load color register, split-register transfer, synchronous graphics random-access memory (SGRAM) block write. Row-address strobe. drives inputs DRAMs, VRAMs, SDRAMs. Transfer output enable column-address strobe. used output enable DRAMs VRAMs, also transfer enable VRAMs. also drives inputs SDRAMs. Write enable. driven before during write cycles. controls direction transfer during VRAM transfer cycles.
UTIME
input, output, high-impedance This internal pullup left unconnected during normal operation. This internal pulldown left unconnected during normal operation. proper operation, pins must connected externally.
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Terminal Functions (Continued)
TERMINAL NAME TYPE HOST INTERFACE HACK Host acknowledge. 'C80 drives HACK output following active HREQ indicate that driven local memory signals high-impedance state relinquishing bus. HACK driven high asynchronously following HREQ being detected inactive, then 'C80 resumes driving bus. Host request. external device drives HREQ request ownership local memory bus. When HREQ high, 'C80 owns drives bus. HREQ synchronized internally 'C80's internal clock. Also, HREQ used reset determine power-up state HREQ rising edge RESET, comes running. HREQ high, remains halted until first interrupt occurrence EINT3. Internal cycle request. REQ1 REQ0 provide two-bit code indicating highest-priority memory cycle request that being received External logic monitor REQ1 REQ0 determine necessary relinquish local memory 'C80. SYSTEM CONTROL CLKIN CLKOUT Input clock. CLKIN generates internal 'C80 clocks which processor functions (except frame timers) synchronous. Local output clock. CLKOUT provides synchronize external circuitry internal timings. 'C80 output signals (except signals) synchronous this clock. Edge-triggered interrupts. EINT1, EINT2 EINT3 allow external devices interrupt master processor (MP) three interrupt levels (EINT1 highest priority). interrupts rising-edge triggered. EINT3 also serves unhalt signal. powered-up halted, first rising edge EINT3 causes unhalt fetch reset vector (the EINT3 interrupt-pending this case). Level-triggered interrupt. LINT4 provides active-low level-triggered interrupt priority falls below that edge-triggered interrupts. interrupt request should remain until recognized 'C80. Reset. RESET driven reset 'C80 (all processors). During reset, internal registers their initial state outputs driven their inactive high-impedance levels. During rising edge RESET, reset mode 'C80's operating endian mode determined levels HREQ UTIME pins, respectively. External packet transfer. XPT2 XPT0 used external devices request high-priority EMULATION CONTROL EMU0, EMU1 Emulation pins. EMU0 EMU1 used support emulation host interrupts, special functions targeted single processor, multiprocessor halt-event communications. Test clock. provides clock 'C80 IEEE-1149.1 logic, allowing compatible with other IEEE-1149.1 devices, controllers, test equipment designed different clock rates. Test data input. provides input data IEEE-1149.1 instructions data scans 'C80. Test data output. provides output data IEEE-1149.1 instructions data scans 'C80. Test-mode select. controls IEEE-1149.1 state machine. Test reset. TRST resets 'C80 IEEE-1149.1 module. When low, boundary-scan logic disabled, allowing normal 'C80 operation. DESCRIPTION
HREQ
REQ1, REQ0
EINT1, EINT2, EINT3
LINT4
RESET
XPT2 XPT0
input, output, high-impedance This internal pullup left unconnected during normal operation. This internal pulldown left unconnected during normal operation. proper operation, pins must connected externally.
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Terminal Functions (Continued)
TERMINAL NAME TYPE VIDEO INTERFACE CAREA0, CAREA1 Composite area. CAREA0 CAREA1 define special area such overscan boundary. This area represents logical internal horizontal vertical area signals. Composite blanking vertical blanking. Each CBLNK0 VBLNK0 CBLNK1 VBLNK1 provides blanking functions, depending configuration CSYNC HBLNK pin: CBLNK0 VBLNK0, CBLNK1 VBLNK1 Composite blanking disables pixel display /capture during both horizontal vertical retrace periods enabled when CSYNC selected composite-sync video systems. Vertical blanking disables pixel display /capture during vertical retrace periods enabled when HBLNK selected separate-sync video systems. Following reset, CBLNK0 VBLNK0 CBLNK1 VBLNK1 configured CBLNK0 CBLNK1, respectively. Composite sync horizontal blanking. CSYNC0 HBLNK0 CSYNC1 HBLNK1 programmed functions: Composite sync composite-sync video systems programmed input, output, high-impedance signal. input, 'C80 extracts horizontal vertical sync information from externally generated active-low sync pulses. output, active-low composite-sync pulses generated from either external HSYNC VSYNC signals 'C80's internal video timers. high-impedance state, neither driven allowed drive circuitry. Horizontal blank disables pixel display capture during horizontal retrace periods separate-sync video systems used output only. Immediately following reset, CSYNC0 HBLNK0 CSYNC1 HBLNK1 configured high-impedance CSYNC0 CSYNC1, respectively. FCLK0, FCLK1 Frame clock. FCLK0 FCLK1 derived from external video system's dotclock used drive 'C80 video logic frame timer frame timer Horizontal sync. HSYNC0 HSYNC1 control video system. They programmed input, output, high impedance signals. input, HSYNC synchronizes video timer externally generated horizontal sync pulses. output, HSYNC active-low horizontal sync pulse generated 'C80 on-chip frame timer. high-impedance state, driven, internal synchronization allowed occur. Immediately following reset, HSYNC0 HSYNC1 high-impedance state. Serial data clock. SCLK0 SCLK1 used 'C80 shift register transfer (SRT) controller track VRAM point when using midline reload. SCLK0 SCLK1 should same signals that clock serial register VRAMs controlled frame timer frame timer respectively. Vertical sync. VSYNC0 VSYNC1 control video system. They programmed inputs, outputs, high-impedance signals. inputs, VSYNCx synchronize frame timer externally generated vertical-sync pulses. outputs, VSYNCx active-low vertical-sync pulses generated 'C80 on-chip frame timer. high-impedance state, driven internal synchronization allowed occur. Immediately following reset, VSYNCx high-impedance state. POWER Ground. Electrical ground inputs Power. Nominal 3.3-V power supply inputs input, output, high-impedance This internal pullup left unconnected during normal operation. This internal pulldown left unconnected during normal operation. proper operation, pins must connected externally. DESCRIPTION
CSYNC0 HBLNK0, CSYNC1 HBLNK1
I/O/Z
HSYNC0, HSYNC1
I/O/Z
SCLK0, SCLK1
VSYNC0, VSYNC1
I/O/Z
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Terminal Functions (Continued)
TERMINAL NAME TYPE MISCELLANEOUS connect serves alignment factory must left unconnected. input, output, high-impedance This internal pullup left unconnected during normal operation. This internal pulldown left unconnected during normal operation. proper operation, pins must connected externally. DESCRIPTION
architecture
Figure shows major components 'C80: master processor (MP), parallel digital signal processors (PPs), transfer controller TC), IEEE-1149.1 emulation interface. Shared access on-chip achieved through crossbar. Crossbar connections represented Each perform three accesses cycle through local global instruction ports. access RAMs cycle through crossbar/data instruction ports, access through crossbar interface. nine simultaneous accesses supported each cycle. Addresses changed every cycle, allowing crossbar matrix changed cycle-by-cycle basis. Contention between processors same same cycle resolved round-robin priority scheme. addition crossbar, 32-bit data path exists between This allows access control registers that memory-mapped into memory space. 'C80 4G-byte address space shown Figure lower bytes used address internal memory-mapped registers.
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architecture (continued)
ADSP3 IEEE1149.1 (JTAG) ADSP2 ADSP1 ADSP0
Instruction Cache Instruction Cache Instruction Cache Instruction Cache Instruction Cache Instruction Cache Parameter Parameter Parameter Parameter Parameter Data Cache Data Cache Data RAM2 Data RAM1 Data RAM0 Data RAM2 Data RAM1 Data RAM0 Data RAM2 Data RAM1 Data RAM0 Data RAM2 Data RAM1 Data RAM0
Local port Global port Instruction port Crossbar/data port
Figure Block Diagram Showing Data Paths
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architecture (continued)
0xFFFFFFFF ADSP3 Parameter bytes) Reserved bytes) ADSP2 Parameter bytes) Reserved bytes) ADSP1 Parameter bytes) 0x02000000 0x01FFFFFF 0x01820400 0x018203FF 0x01820200 0x018201FF 0x01820000 0x0181FFFF 0x01819000 0x01818FFF 0x01818000 0x01817FFF 0x01811000 0x01810FFF 0x01810000 0x0180FFFF 0x01808000 0x01807FFF 0x01807800 0x018077FF 0x01806000 0x01805FFF 0x01805800 0x018057FF 0x01804000 0x01803FFF 0x01803800 0x018037FF 0x01802000 0x01801FFF 0x01801800 0x018017FF 0x01010800 0x010107FF 0x01010000 0x0100FFFF 0x01003800 Reserved bytes) ADSP0 Parameter bytes) Reserved 338K bytes) ADSP3 Data RAM2 bytes) Reserved bytes) ADSP2 Data RAM2 bytes) Reserved bytes) ADSP1 Data RAM2 bytes) Reserved bytes) ADSP0 Data RAM2 bytes) Reserved (16K bytes) ADSP3 Data RAM1 bytes) ADSP3 Data RAM0 bytes) ADSP2 Data RAM1 bytes) ADSP2 Data RAM0 bytes) ADSP1 Data RAM1 bytes) ADSP1 Data RAM0 bytes) ADSP0 Data RAM1 bytes) ADSP0 Data RAM0 bytes) 0x00004000 0x00003FFF 0x00003800 0x000037FF 0x00003000 0x00002FFF 0x00002800 0x000027FF 0x00002000 0x00001FFF 0x00001800 0x000017FF 0x00001000 0x00000FFF 0x00000800 0x000007FF 0x00000000 0x0000B800 0x0000B7FF 0x0000B000 0x0000AFFF 0x0000A800 0x0000A7FF 0x0000A000 0x00009FFF 0x00009800 0x000097FF 0x00009000 0x00008FFF 0x00008800 0x000087FF 0x00008000 0x00007FFF 0x010037FF 0x01003000 0x01002FFF 0x01002800 0x010027FF 0x01002000 0x01001FFF 0x01001800 0x010017FF 0x01001000 0x01000FFF 0x01000800 0x010007FF 0x01000000 0x00FFFFFF
External Memory (4064M bytes)
Reserved 063K bytes) Memory-Mapped Registers (512 bytes) Memory-Mapped Registers (512 bytes) Reserved (28K bytes) Instruction Cache bytes) Reserved (28K bytes) Data Cache bytes) Reserved (32K bytes) ADSP3 Instruction Cache bytes) Reserved bytes) ADSP2 Instruction Cache bytes) Reserved bytes) ADSP1 Instruction Cache bytes) Reserved bytes) ADSP0 Instruction Cache bytes) Registers 132K bytes) Parameter bytes) Registers (50K bytes)
Figure Memory
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master processor (MP) architecture
master processor (MP) 32-bit RISC processor with integral IEEE-754 floating-point unit. designed effective execution code capable performing well over dhrystones/s. Major tasks which typically performs are:
Task control user interface Information processing analysis IEEE-754 floating point (including graphics transforms)
functional block diagram Figure shows block diagram master processor. features include: 32-bit RISC processor Load/store architecture Three operand arithmetic logical instructions
4K-byte instruction cache 4K-byte data cache Four-way associative Least-recently-used (LRU) information replacement Data writeback
4K-byte noncached parameter Thirty-one 32-bit general-purpose registers Register accumulator scoreboard 15-bit 32-bit immediate constants 32-bit byte addressing Scalable timer Leftmost-one rightmost-one logic IEEE-754 floating-point hardware Four double-precision floating-point vector accumulators Vector floating-point instructions Floating-point operation parallel load store Multiply accumulate
High performance million instructions second (MIPS) million floating-point operations second (MFLOPS) Over dhrystones/s
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functional block diagram (continued)
Register File (Thirty-One 32-Bit Registers) Scoreboard
Barrel Rotator Mask Generator Zero Comparator Integer Arithmetic Logic Unit (ALU) Double-Precision Floating-Point Multiplier (Single-Precision Core)
Leftmost Rightmost Timer Double-Precision Floating-Point Accumulators
Control Registers Double-Precision Floating-Point Adder
Instruction Register Program Counters (PCs) Incrementer Emulation Logic Instruction Cache Controller
Endian Multiplexers Data-Cache Controller Crossbar Interface
Figure Block Diagram general-purpose registers contains 32-bit general-purpose registers, R31. Register always reads zero writes discarded. Double-precision values always stored even-odd register pair with higher-numbered register always holding sign exponent. R0/R1 pair available this use. scoreboard keeps track which registers awaiting loads result previous instruction stalls instruction pipeline until register contains valid data. recommended software convention, typically used stack pointer return-address link register. Figure shows general-purpose registers.
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general-purpose registers (continued)
Zero/Discard Available R30, 32-Bit Registers 64-Bit Register Pairs
Figure General-Purpose Registers 32-bit registers contain signed-integer, unsigned-integer, single-precision floating-point values. Signed unsigned bytes halfwords sign-extended zero-filled. Doublewords stored 64-bit even/odd register pair. Double-precision floating-point values referenced using even register number register pair. Figure through Figure show register data formats.
Single-Precision Floating Point Signed 32-bit Integer Unsigned 32-Bit Integer Sign Exponent Value Signed integer value Unsigned integer value Most significant Least signficant
Figure Register 32-Bit Data Formats
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general-purpose registers (continued)
Signed Byte Unsigned Byte Signed Halfword Unsigned Halfword Sign bit(s) Signed byte/halfword value Unsigned byte/halfword value Most significant Least signficant
Figure Register 8-Bit 16-Bit Data Formats
Register Even Register Least Significant 32-Bit Word Register Even Register Sign bit(s) Exponent Signed byte/halfword value Unsigned byte/halfword value Most significant Least signficant Most Significant 32-Bit Word
Figure Register 64-Bit Data Formats
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double-precision floating-point accumulators There four double-precision floating-point registers (see Figure accumulate intermediate floating-point results.
Sign Exponent Value Most significant Least signficant Accumulator Accumulator Accumulator Accumulator
Figure Double-Precision Floating-Point Accumulators
control registers
addition general-purpose registers, there number control registers that used represent state processor. Table shows control register numbers accessible registers. Table Control Register Numbers
NUMBER 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 NAME CONFIG INTPEN FPST PPERROR PKTREQ TCOUNT TSCALE FLTOP FLTADR FLTTAG FLTDTL FLTDTH DESCRIPTION Exception Program Counter Exception Instruction Pointer Configuration Reserved Interrupt Pending Register Reserved Interrupt Enable Register Reserved Floating-Point Status Reserved Error Register Reserved Reserved Packet-Transfer Request Register Current Counter Value Counter Reload Value Faulting Operation Faulting Address Faulting Faulting Data (low) Faulting Data (high) NUMBER 0x0015-0x001F 0x0020 0x0021 0x0022-0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035-0x0038 0x0039 0x003A 0x003B-0x01FF 0x0200 0x020F 0x0300 0x0400-0x040F 0x0500 0x4000 0x4001 0x4002 NAME SYSSTK SYSTMP ECOMCNTL ANASTAT BRK1 BRK2 iCACHET iCACHEL dCACHET dCACHEL IN0P IN1P OUTP Reserved System Stack Pointer System Temporary Register Reserved Emulator Exception Program Counter Emulator Exception Instruction Pointer Reserved Emulator Communication Control Emulation Analysis Status Register Reserved Emulation Breakpoint Register Emulation Breakpoint Register Reserved Instruction Cache Tags Instruction Cache Register Data Cache Tags Data Cache Register Vector Load Pointer Vector Load Pointer Vector Store Pointer DESCRIPTION
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pipeline registers uses three-stage fetch, execute, access (FEA) pipeline. primary pipeline registers manipulated implicitly branch trap instructions accessible user. exception emulation pipeline registers user-accessible control registers. pipeline registers bits.
Program Execution Mode Normal Program Counter Instruction Pointer Instruction Register Exception/emulator instruction pointer (EIP/MIP) points instruction that would have been executed exception emulation trap occurred. Exception/emulator program counter (EPC/MPC) points instruction fetched returning from exception/emulation trap. Exception Emulation
Instruction register (IR) contains instruction being executed. Instruction pointer (IP) points instruction being executed. Program counter (PC) points instruction being fetched.
Figure Pipeline Registers configuration (CONFIG) register (0x0002) CONFIG register controls reflects state certain options shown Figure
Reserved
Type
Reserved
Release
Reserved
Type Release
Endian mode; big-endian, little-endian, read only PPData round robin; fixed, variable, read write packet transfer (PT) round robin; variable, fixed, read write High priority events; disabled, enabled, read write Externally initiated packet transfers; disabled, enabled, read write Number device, read only SMJ320C80 version number
Figure CONFIG Register
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interrupt-enable (IE) register (0x0006) register contains enable bits each interrupts/traps shown Figure global-interrupt-enable (ie) appropriate individual interrupt-enable must order interrupt occur.
error External interrupt (LINT4) External interrupt (EINT3) packet transfer Packet transfer busy Packet transfer complete message interrupt message interrupt
message interrupt message interrupt message interrupt Integer overflow Memory fault External interrupt (EINT2) External interrupt (EINT1) timer interrupt
Frame-timer interrupt Frame-timer interrupt Floating-point inexact Floating-point underflow Floating-point overflow Floating-point divide-by-zero Floating-point invalid Global-interrupt enable
Figure Register interrupt-pending (INTPEN) register (0x0004) bits INTPEN register show current state each interrupt/trap. Pending interrupts occur unless corresponding interrupt-enable set. Software must write appropriate INTPEN clear interrupt. Figure shows INTPEN register locations.
error External interrupt (LINT4) External interrupt (EINT3) packet transfer Packet transfer busy Packet transfer complete message interrupt message interrupt
message interrupt message interrupt message interrupt Integer overflow Memory fault External interrupt (EINT2) External interrupt (EINT1) timer interrupt
Frame-timer interrupt Frame-timer interrupt Floating-point inexact Floating-point underflow Floating-point overflow Floating-point divide-by-zero Floating-point invalid Global-interrupt enable
Figure INTPEN Register
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floating-point status (FPST) register (0x0008) FPST contains status control information floating-point unit (FPU) shown Figure Bits 17-21 read/write control bits. Bits read/write accumulated status bits. other bits show status last instruction complete read only.
dest
opcode
dest
opcode
Destination register value Accumulated value invalid Accumulated divide-by-zero Accumulated overflow Accumulated underflow Accumulated inexact Sequential mode select Floating-point stall Vector fast mode Rounding mode nearest positive zero negative Last opcode tenth exponent
ninth exponent Destination precision single float double float Rounding mode nearest zero multiply overflow Invalid Divide-by-zero Overflow Underflow Inexact
signed unsigned positive negative
Figure FPST Register error (PPERROR) register (0x000A) bits PPERROR register reflect parallel processor errors (see Figure 14). these when error interrupt occurs determine cause error.
PPhalted illegal instruction fault type icache Direct external access (DEA)
Reserved
Reserved
Reserved
Figure PPERROR Register packet-transfer request (PKTREQ) register (0x000D) PKTREQ controls submission priority packet-transfer requests shown Figure also indicates that packet transfer currently active.
Reserved Immediate (urgent) priority selected High (foreground) priority selected Suspend packet transfer Packet transfer queued; read only Submit packet-transfer request
Figure PKTREQ Register
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memory-fault registers five read-only memory-fault registers contain information about memory address exceptions, shown Figure
FLTOP (0x0010) Dest
Reserved
Reserved
Block
FLTTAG (0x0011)
22-Bit Cache Address
Sub-Block FLTADR (0x0012) FLTDTH (0x0013) FLTDTL (0x0014) Dest Faulting Address Accessed Instruction Faulting Write Most-Significant-Data Word Faulting Write Least-Significant-Data Word
Destination Register Number Kind Operation: load unsigned load store cache flush/clean Size Data: 8-bit 16-bit 32-bit 64-bit
Block
icache fault dcache fault Fault Modified return sequence Faulting block number Sub-block present. Dirty
Figure Memory-Fault Registers
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cache registers ILRU DLRU registers track least-recently-used (LRU) information sixteen instruction-cache sixteen data-cache blocks. ITAGxx registers contain block addresses present flags each sub-block. DTAGxx registers identical ITAGxx registers include dirty bits each sub-block. Figure shows cache registers.
ILRU (0x0300) DLRU (0x0500)
NMRU
NLRU
NMRU
NLRU
NMRU
NLRU
NMRU
NLRU
ITAG0 -ITAG15 (0x0200 0x020F) Sub-Block DTAG0 DTAG15 (0x0400 0x040F)
22-Bit Cache Address
22-Bit Cache Address
Sub-Block NMRU NLRU Most-recently-used Next most-recently-used Next least-recently-used Least-recently-used Sub-block present Sub-block dirty
mru, nmru, nlru, have value representing block number mutually exclusive each set.
Figure Cache Registers
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cache architecture contains four-way set-associative, caches instructions data. Each cache divided into four sets with four blocks each set. Each block represents bytes contiguous instructions data aligned 256-byte address boundary. Each block partitioned into four sub-blocks that each contain sixteen 32-bit words aligned 64-byte boundaries within block. Cache misses cause sub-block loaded into cache. Figure shows cache architecture four sets each cache. Figure shows addresses into cache using cache tags address bits.
Block Sub-Blocks Block Block Block (Block (Block (Block (Block NLRU NMRU Stack
NLRU NMRU
Least-recently-used Next least-recently-used Next most-recently-used Most-recently-used
Figure Cache Architecture Sets)
32-Bit Logical Address
On-Chip Cache RAMS Bank Bank Address On-Chip Cache Bank Address Bits Select Bits Sub-Block (within block) Select Word (within sub-block) Select Byte (within word) Select Block Select (which matched)
Figure Cache Addressing
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parameter
parameter noncachable, 2K-byte, on-chip that contains interrupt vectors, MP-requested task buffers, general-purpose area. Figure shows parameter address map.
0x001010000- 0x0101007F 0x001010800- 0x010100DF 0x0010100E0- 0x010100FB 0x0010100FC- 0x010100FF 0x001010100- 0x0101017F 0x001010180- 0x0101021F 0x001010220- 0x0101029F 0x0010102A0- 0x010107FF Suspended Parameters (128 Bytes) Reserved Bytes) Linked List Start Addresses Bytes) Linked List Start Address Off-Chip Off-Chip Buffer (128 Bytes) Interrupt Trap Vectors (160 Bytes) Off-Chip Off-Chip Buffer (128 Bytes) General-Purpose (3472 Bytes) XPTf Linked List Start Add. XPTe Linked List Start Add. XPTd Linked List Start Add. XPTc Linked List Start Add. XPTb Linked List Start Add. XPTa Linked List Start Add. XPT9 Linked List Start Add. XPT8 Linked List Start Add. XPT7 Linked List Start Add. XPT6 Linked List Start Add. XPT5 Linked List Start Add. XPT4 Linked List Start Add. XPT3 Linked List Start Add. XPT2 Linked List Start Add. XPT1 Linked List Start Add. 0x010100E0 0x010100E4 0x010100E8 0x010100EC 0x010100F0 0x010100F4 0x010100F8
Figure Parameter
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interrupt vectors
Table Table show interrupts traps their vector addresses. Table Maskable Interrupts
(TRAP#) NAME VECTOR ADDRESS 0x01010180 0x01010188 0x0101018C 0x01010194 0x01010198 0x0101019C 0x010101A0 0x010101A4 0x010101A8 0x010101AC 0x010101B0 0x010101B8 0x010101BC 0x010101C0 0x010101C4 0x010101C8 0x010101CC 0x010101E4 0x010101E8 0x010101EC 0x010101F0 0x010101F4 0x010101F8 0x010101FC Floating-point invalid Floating-point divide-by-zero Floating-point overflow Floating-point underflow Floating-point inexact Reserved Reserved timer interrupt External interrupt (EINT1) External interrupt (EINT2) Memory fault Integer overflow message interrupt message interrupt Reserved Reserved message interrupt Packet-transfer complete Packet-transfer busy packet transfer External interrupt (EINT3) External interrupt (LINT4) error MASKABLE INTERRUPT
Table Nonmaskable Traps
TRAP NUMBER NAME VECTOR ADDRESS 0x01010200 0x01010204 0x01010208 0x0101020C 0x01010210 0x01010214 0x01010218 0x0101021C 0x010102A0 0x010107FC NONMASKABLE TRAP Emulator trap1 (reserved) Emulator trap2 (reserved) Emulator trap3 (reserved) Emulator trap4 (reserved) Floating-point error Reserved Illegal instruction Reserved System- user-defined
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opcode formats three basic classes instruction opcodes are: short immediate, three register, long immediate. Figure shows opcode structure each class instruction.
Short Immediate Dest Source Opcode 15-Bit Immediate
Three Register Dest
Source
Opcode
Options
Source
Long Immediate Dest
Source
Opcode
Options
Source
32-Bit Long Immediate
Figure Opcode Formats opcode summary Table through Table show opcode formats Table summarizes master processor instruction set.
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opcode summary (continued) Table Short-Immediate Opcodes
illop0 trap cmnd rdcr swcr brcr shift.dz shift.dm shift.ds shift.ez shift.em shift.es shift.iz shift.im and.tt and.tf and.ft or.tt and.ff xnor or.tf or.ft or.ff ld.u dcache bcnd
Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Source Link Link BITNUM BITNUM Cond Dest Dest Dest
Source
Unsigned Immediate Unsigned Trap Number Unsigned Immediate Unsigned Control Register Number Unsigned Control Register Number Unsigned Control Register Number Endmask Endmask Endmask Endmask Endmask Endmask Endmask Endmask Unsigned Immediate Unsigned Immediate Unsigned Immediate Unsigned Immediate Unsigned Immediate Unsigned Immediate Unsigned Immediate Unsigned Immediate Unsigned Immediate Unsigned Immediate Signed Offset Signed Offset Signed Offset Signed Offset Signed Offset Signed Offset Signed Offset Signed Offset Signed Offset Signed Immediate Signed Immediate Signed Immediate Modify, write modified address back register Rotate sense shifting Size byte, halfword, word, doubleword) Unsigned form Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate
Source Source Source Source Source Source Source Source Source Source2 Source2 Source2 Source2 Source2 Source2 Source2 Source2 Source2 Source2 Base Base Base Source2 Base Source Source Source Source2 Source2 Source2
Reserved (code Annul delay slot instruction branch taken Emulation trap Clear present flags Invert endmask
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opcode summary (continued) Table Long-Immediate Three-Register Opcodes
trap cmnd rdcr swcr brcr shift.dz shift.dm shift.ds shift.ez shift.em shift.es shift.iz shift.im and.tt and.tf and.ft or.tt and.ff xnor or.tf or.ft or.ff ld.u dcache bcnd
Dest Dest
Source1 Rotate Rotate Rotate Rotate Rotate Rotate Rotate Rotate
Source Source Source Source Source Source Source Source Source Source2 Source2 Source2 Source2 Source2 Source2 Source2 Source2 Source2 Source2 Base Base Base Source2 Base Source Source Source Source2 Source2 Source2
Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest Dest
Endmask Endmask Endmask Endmask Endmask Endmask Endmask Endmask
Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1 Offset Offset Offset Source Offset Offset Target Target Target Source1 Source1 Source1
Source Link Link BITNUM BITNUM Cond Dest Dest Dest
Reserved (code Direct external access Emulation trap Clear present flags Invert endmask
Long immediate Modify, write modified address back register Rotate sense shifting Scale offset data size Size byte, halfword, word, doubleword
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opcode summary (continued) Table Miscellaneous Instruction Opcodes
vadd vsub vmpy vmsub vrnd(FP) vrnd(Int) vmac vmac fadd fsub fmpy fdiv frndx fcmp fsqrt estop illopF
Dest Dest Dest Dest Dest Dest Dest Dest Dest
Source2 Dest Source2 Dest Source2 Dest Dest Dest Dest Source2 Source2 Source2 Source2 Source2 Source2 Source2 Source Source
Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1 Source1
Dest
Reserved (code Floating-point accumulator select Constant operands rather than register Destination precision vector Long immediate 32-bit data Parallel memory operation specifier Vector store load source register Destination register
Destination precision parallel load store single, double) Precision source1 operand Precision source2 operand Precision destination result Rounding Mode Scale offset data size rather than accumulator
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opcode summary (continued) Table Summary Opcodes
INSTRUCTION and.tt and.ff and.ft and.tf bcnd brcr cmnd dcache estop fadd fcmp fdiv fmpy frndx fsqrt fsub illop ld.u or.tt Bitwise Bitwise with complement Bitwise with complement Bitwise with complement Branch Branch zero Branch conditional Branch always Branch control register Branch save return Send command Integer compare Flush data cache sub-block Emulation stop Floating-point Floating-point compare Floating-point divide Floating-point multiply Floating-point convert/round Floating-point square root Floating-point subtract Illegal operation Jump save return Load signed into register Load unsigned into register Leftmost Bitwise DESCRIPTION Signed integer INSTRUCTION or.ff or.ft or.tf rdcr shift.dz shift.dm shift.ds shift.ez shift.em shift.es shift.iz shift.im swcr trap vadd vmac vmpy vmsc vmsub vrnd(FP) vrnd(Int) vsub xnor DESCRIPTION Bitwise with complement Bitwise with complement Bitwise with complement Read control register Rightmost Shift, disable mask, zero extend Shift, disable mask, merge Shift, disable mask, sign extend Shift, enable mask, zero extend Shift, enable mask, merge Shift, enable mask, sign extend Shift, invert mask, zero extend Shift, invert mask, merge Store register into memory Signed integer subtract Swap control register Trap Vector floating-point Vector floating-point multiply accumulator Vector floating-point multiply Vector floating-point multiply subtract from accumulator Vector floating-point subtract accumulator from source Vector round with floating-point input Vector round with integer input Vector floating-point subtract Bitwise exclusive Bitwise exclusive
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architecture
parallel processor (PP) 32-bit integer optimized imaging graphics applications. Each execute parallel: multiply, operation, memory accesses within single instruction. This internal parallelism allows single achieve over million operations second certain algorithms. three-input that supports three input Boolean combinations many combinations arithmetic Boolean functions. Data-merging bit-to-byte, bit-to-word, bit-to-halfword translations supported hardware input data path ALU. Typical tasks performed include:
Pixel-intensive processing Motion estimation Convolution PixBLTs Warp Histogram Mean square error
Domain transforms Discrete Cosine Transform (DCT) Fast Fourier Transform (FFT) Hough
Core graphics functions Line Circle Shaded fills Fonts
Image analysis Segmentation Feature extraction
Bit-stream encoding/decoding Data merging Table look-ups
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functional block diagram Figure shows block diagram parallel processor. features include:
64-bit instruction word (supports multiple parallel operations) Three-stage pipeline fast instruction cycle Numerous registers data, address, index registers other user-visible registers
Data Unit integer multiplier (optional dual Splittable 3-input 32-bit barrel rotator Mask generator Multiple status flag expander translations to/from bit-per-pixel space. Conditional assignment data unit results Conditional source selection Special processing hardware Leftmost rightmost Leftmost change rightmost change
Memory addressing address units (global local) provide 32-bit accesses parallel with data unit operation. addressing modes (immediate indexed) Byte, halfword, word addressability Scaled indexed addressing Conditional assignment loads Conditional source selection stores
Program flow Three hardware loop controllers Zero overhead looping branching Nested loops Multiple loop endpoints Instruction cache management mapped register file Interrupts messages context switching
Algebraic assembly language
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functional block diagram (continued)
Data Unit
Multiplier Data Path
Data Path
Expander Mask Generator Barrel Rotator Three-Input Registers
Local Address Unit
Global Address Unit
Local Destination Source
Global Destination Global Source
a12,
Local Data Path
Global Data Path
Program Flow Control Unit Three Zero-Overhead Loop Branch Controllers
Instruction Cache Control
Repl
Repl
Local Data Port
Global Data Port Repl Replicate hardware Align/sign-extend hardware
Instruction Port Instruction address port Local address port Global address port
Figure Block Diagram
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registers
contains many general-purpose registers, status registers, configuration registers. registers 32-bit registers. Figure shows accessible registers blocks.
Data-Unit Registers Data Registers EALU Operation Address-Unit Registers Global-Address Unit Address Registers Index Flags Stack Pointer Same Physical Register Multiple Flags Status
Local-Address Unit Address Registers Index Flags
Prgram Flow Control (PFC) Unit Registers PC-Related Registers Loop Addresses (br, call) iprs (read only) (read only) Cache Tags tag0 (read only) tag1 (read only) tag2 (read only) tag3 (read only) Loop Control lctl
Loop Counts
Communications comm Interrupts lntflg inten
Figure Registers
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data-unit registers
data unit contains eight 32-bit general-purpose data registers (d0-d7) referred registers. register also acts control register extended (EALU) operations. register Figure shows format when used EALU control register.
FMOD FMOD
EALU Function Code
Function modifiers Arithmetic enable EALU carry-In Invert-carry-In Sign extend Nonmultiple mask
Explicit multiple carry-in Expanded multiple flags Default multiply shift amount Split multiply Rounded multiply Default barrel rotate amount
Figure Format EALU Operations multiple flags (mf) register register records status information from each split segment multiple arithmetic operations. register expanded generate mask ALU. Figure shows register format.
Figure Register Format status register (sr) contains status control bits ALU. Figure
Msize
Asize
Negative status Carry status Overflow status Zero status Rotation
Msize Asize
status selection zero extended result sign reserved Expander data size Split data size
Figure Format
address-unit registers
address registers address unit contains 32-bit address registers which contain base address address computations which used general-purpose data. registers used local-address computations registers a8-a12 used global-address computations.
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index registers 32-bit index registers contain index values with address registers address computations they used general-purpose data. Registers used local-address unit registers used global-address unit. stack pointer (sp) contains address PP's system stack. stack pointer addressed local-address unit global-address unit. Figure shows register format.
Word-Aligned Address
Figure Register Format zero registers zero registers read-as-zero address registers local address unit (a7) global-address unit (a15). Writes registers ignored specified when operational results discarded.
Figure Zero Registers
program flow control (PFC) unit registers
loop registers loop registers control three levels zero-overhead loops. 32-bit loop-start registers (ls0 ls2) loop-end registers (le0 le2) contain starting ending addresses loops. loop-counter registers (lc0 lc2) contain number repetitions remaining their associated loops. registers loop reload registers used support nested loops. format loop-control (lctl) register shown Figure There also special write-only mappings loop-reload registers. lrs0 lrs2 codes used fast initialization lsn, lrn, registers multi-instruction loops while lrse0 lrse2 codes used single instruction-loop fast initialization.
LCD2
LCD1
LCD0
LCDn
Loop-end enable Loop-counter designator None reserved
Figure lctl Register pipeline registers unit contains pointer each stage pipeline. contains program counter which points instruction being fetched. points instruction address stage pipeline points instruction execute stage pipeline. instruction pointer return-from-subroutine (iprs) register contains return address subroutine call.
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pipeline registers (continued)
(29-Bit Doubleword Address) Global Interrupt Enable
Loop Inhibit
32-Bit Copy Previous Register Value
32-Bit Copy Previous Register Value
iprs
29-Bit Doubleword Return Address
Figure Pipeline Registers interrupt registers interrupt-enable (inten) register allows individual interrupts enabled configures interrupt flag (intflg) register operation. intflg register contains interrupt flag bits. Interrupt priority increases moving from left right intflg.
inten
intflg
PPnMSG
Reserved (write Enable interrupt Write mode writing clears intflg writing sets intflg message interrupt
MPMSG PTEND PTERR TASK
message interrupt Packet transfer complete Packet-transfer error Packet transfer queued task interrupt
Figure PP-Interrupt Registers
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communication (comm) register comm register contains packet-transfer handshake bits indicator bits.
High-priority packet transfer Packet-transfer suspend Packet transfer queued Submit packet transfer request
Number (read only) implemented
Figure comm Register cache-tag registers tag0 tag3 registers contain address sub-block present bits each cache block.
23-Bit Address Present Least-recently-used code Most-recently-used (MRU) next next (NMRU) Sub-Block
Figure Cache-Tag Registers
cache architecture
Each 2K-byte instruction cache. Each cache divided into four blocks each block divided into four sub-blocks containing 64-bit instructions each. Cache misses cause sub-block loaded into cache. Figure shows cache architecture four sets each cache. Figure shows addresses into cache using cache tags address bits.
Block Sub-Blocks Block Block Block (Block (Block (Block (Block NLRU NMRU Stack
Figure Cache Architecture
23-Bit Value
instruction
ignored
sub-block
Figure Register Cache-Address Mapping
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parameter
parameter 2K-byte, on-chip which contains PP-interrupt vectors, PP-requested task buffers, general-purpose area. parameter does cache memory. Figure shows parameter address map.
Suspended Parameters (128 Bytes) 0x0100#000- 0x0100#07F
Reserved (120 Bytes)
0x0100#080- 0x0100#0F7
Cache Fault Address Linked-List Start Address Off-Chip Off-Chip Buffer (128 Bytes) Interrupt Vectors (128 Bytes) General-Purpose (3572 Bytes Less Stack Size)
0x0100#0F8- 0x0100#0FB 0x0100#0FC 0x0100#0FF 0x0100#100- 0x0100#17F
0x0100#180- 0x0100#1FF 0x0100#200 Application-Dependent Boundary
Stack Stack State Information After Reset Bytes)
0x0100#FF7
Stack Pointer After Reset
0x0100#FF4- 0x0100#FFF Number
Figure Parameter Address
PP-interrupt vectors
interrupts their vector addresses shown Table Table PP-Interrupt Vectors
NAME TASK PTERR PTEND MPMSG PP0MSG PP1MSG VECTOR ADDRESS 0x0100#1B8 0x0100#1C4 0x0100#1C8 0x0100#1CC 0x0100#1D0 0x0100#1E0 0x0101#1E4 INTERRUPT Task Interrupt Packet Transfer Queued Packet-Transfer Error Packet Transfer Message Message Message
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data-unit architecture
data unit independent data paths multiplier, each with hardware functions. multiplier data path includes multiplier, halfword swapper, rounding hardware. data path includes 32-bit three-input ALU, barrel rotator, mask generator, multiple flag (mf) expander, left/rightmost left/rightmost bit-change logic, several multiplexers. Figure shows data-unit block diagram.
src1 src2 dstc dst2 src3 src4 src4 src2 src1 dst1
Rotate Amount Multiplexer
Mask Generator Multiplexer
LMO, RMO, LMBC, RMBC Barrel Rotator Mask Generator
Expander
Multiplier (Splittable) Scale Round Swap Merge
Port Multiplexer
Barrel Rotator Input Sign
Three-Input (Splittable)
Function Code Logic
src1 scr2 scr3 scr4 dst/dst1 register, only left/right most (LMO/RMO), left/right most change (LMBC/RMBC) hardware sometimes 5/32-bit immediate dst2 only only dstc only (destination companion source) only Constant register Constant LSBs
Figure Data-Unit Block Diagram
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data-unit architecture (continued)
PP's split into 32-bit ALU, 16-bit ALUs, four 8-bit ALUs. Figure shows multiple arithmetic data flow case four 8-bit split (called multiple-byte arithmetic). operates independent parallel ALUs where each receives same function code.
Register Expander (Replicate) C-Out C-IN C-Out C-IN C-Out C-IN
Rotate Clear
C-Out C-IN
sr(C)
C-IN Logic
C-IN Logic
C-IN Logic
C-IN Logic
Figure Multiple-Byte Arithmetic Data Flow
multiplier
PP's hardware multiplier perform 16x16 multiply with 32-bit result multiplies with 16-bit results single cycle. 16x16 multiply signed unsigned operands shown Figure
Signed Input
Signed Signed Result
Unsigned Input
Unsigned Unsigned Result
Figure Multiplier Data Formats
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multiplier (continued)
When performing simultaneous split multiplies, first input word contains unsigned byte operands second input word contains signed unsigned byte operands. These formats shown Figure Figure
Unsigned Input
Unsigned Input
Signed Input
Signed Input
Signed Result
Signed Result
Figure Signed Split Multiply Data Formats
Unsigned Input
Unsigned Input
Unsigned Input
Unsigned Input
Unsigned Result
Unsigned Result
Figure Unsigned Split Multiply Data Formats
program-flow-control unit architecture
program-flow-control (pfc) unit performs instruction fetching decoding, loop control, handshaking with transfer controller. unit architecture shown Figure three-stage fetch, address, execute (FAE) pipeline shown Figure ipa, registers point address instruction each stage pipeline. each cycle which pipeline advances, copied into ipe, copied into ipa, incremented instruction bytes).
Instruction Three Fetch Address Fetch Execute Address Fetch Execute Address Execute
Figure FAE-Instruction Pipeline
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program-flow-control unit architecture (continued)
incrementer lprs Cache Controller
Comparators
Registers Loop Controller Present Bits Stack
Comparator
lctl
Instruction Decode
Pipeline Control
decr. zero Loop Control
Control Signal Generation
Loop Controller Instruction Loop Controller Control Signal Instruction Address
Figure Program-Flow-Control Unit Block Diagram
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address-unit architecture
both local- global-address unit which operate independently each other. address units support twelve different addressing modes. place performing memory access, either both address units perform address computation that written directly register instead being used memory access. This address unit arithmetic provides additional arithmetic operation supplement data unit during compute-intensive algorithms.
From Global Destination Offset Global Source From Global Destination (local) (global) Offset Global Source
(a15
Index Multiplexer
pba,
Index Multiplexer
PP-Relative Multiplexer
Index Scaler
Scale Data Size
PP-Relative Multiplexer
Index Scaler
Scale Data Size
32-Bit Adder Subtracter Unit
32-Bit Adder Subtracter Unit
Preindex Postindex Multiplexer
Preindex Postindex
Preindex Postindex Multiplexer
Preindex Postindex
Local-Address Port
Global-Address Port
Figure Address-Unit Architecture
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instruction
instructions represented algebraic expressions operations performed parallel multiplier, ALU, global-address unit, local-address unit. expressions symbol indicate operations that performed parallel. operator syntax shown Table data unit operations (multiplier ALU) summarized Table parallel transfers (global local) summarized Table Table Operators Precedence
OPERATOR src1 src1-1 =[cond] =[cond.pro] FUNCTION Select (n=true) even (n=false) register register pair based negative condition code Subexpression delimiters Expander operator Mask generator Nonmultiple mask generator (EALU only) Modified mask generator (0xFFFFFFFF output input) Nonmultiple shift right mask generator (EALU only) Rotate left Shift left (pseudo-op rotate mask) Unsigned shift right Signed shift right Bitwise Bitwise Bitwise Addition Subtraction Conditional assignment Conditional assignment with status protection Equate
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instruction (continued)
Table Summary Data-Unit Operations
Operation Description Syntax Examples Operation Description Syntax Examples Operation Description Syntax Example Operation Description Syntax Examples Operation Description Syntax Base ALUs Perform operation specifying function, dest operand, operand routing. function three-input Boolean operations arithmetic operations combined with function modifiers. [fmod] [[cond [.pro] ALU_EXPRESSION [nn.nv] EALU ROTATE Perform extended (EALU) operation (specified with data routings optionally write barrel rotator output second dest register. function Boolean arithmetic. dst1 [[cond [.pro] ealu (src2, [dst2 [[cond]] src1 [[[n]] src1-1] src3, src4) dst1 [fmod] [[cond [.pro] ealu (label:EALU_EXPRESSION dst2 [[cond]] src1 [[n]] src1-1] src3]) [nn] ealu(d2, [nn] d3\\d1, %d4) ealu(mylabel: (d5\\d6 %d7) d5\\d6) Perform 16x16 multiply with optional parallel subtract. Condition code applies both multiply add. dst2 [sign] [[cond]] src3 src4 [[cond[.pro] src2 src1 [[n]] src1 dst2 [sign] [[cond]] src3 src4 [[cond[.pro] src2 src1 [[n]] src1 SADD Perform 16x16 multiply with parallel right-shift subtract. Condition code applies multiply, shift, add. dst2 [sign] [[cond]] src3 src4 cond [.pro] src2 src1 [[n]] src1 dst2 [sign] [[cond]] src3 src4 cond [.pro] src2 src1 [[n]] src1 EALU Perform multiply optional parallel EALU. Multiply rounding, scaling, splitting features. Generic Form: dst2 [sign] [[cond]] src3 src4 [[cond [.pro] ealu[f] (src2, src1 [[n]] src1 %d0) dst2 [sign] [[cond]] src3 src4 ealu() Explicit Form: dst2 [sign] [opt] [[cond]] src3 src4 [<<dms] dst1 [fmod] [[cond [.pro] ealu (label: EALU_EXPRESSION) dst2 [sign] [opt] [[cond]] src3 src4 [<<dms] ealu (label) ealu(d1, d6\\d0, %d0) ealu (mylabel: divi Perform iteration unsigned divide algorithm. Generates quotient execution using iterative subtraction. dst1 [[cond [.pro] divi (src2, dst2 [[cond]] src1 [[n]] src1 -1]) divi (d1, divi (d1, d3[n]d2) dint; eint; Globally disable interrupts; globally enable interrupts; nothing data unit dint eint Optional parameter extension Square brackets must used Protect status bits complement cond fmod sign Condition code Function modifier Default multiply shift amount unsigned, signed generic form explicit form
Examples Operation Description Syntax Examples Misc. Operations Description Syntax
Legend:
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instruction (continued)
Table Summary Parallel Transfers
Operation Description Syntax Examples Operation Description Syntax Examples Operation Description Syntax Examples Operation Description Syntax Examples Operation Description Syntax Example Operation Description Syntax Example Legend: item Load Transfer from memory into register [sign] [size] [[cond]] addrexp [sign] [size] [[cond]] an.element uh[n]* (a9++=[2]) a2.sMY_ELEMENT Store Transfer from register into memory addrexp [size] [[n]] src-1] an.element [size] [[n]] src-1] *--a2 *a9.sMY_ELEMENT Address unit arithmetic Compute address store register [size] [[cond]] addrexp [size] [[cond]] an.element &*(a3 &*a9.sMY_ELEMENT Move Transfer from register register [[cond]] Field extract move Transfer from register register extracting right-aligning byte halfword [sign] [size item] Field replicate move Transfer from register register replicating least significant byte least significant halfword bits [size] [[cond]] Optional parameter extension Square brackets must used global unit byte0/halfword0, byte1/halfword1, byte2, byte3 cond sign size Condition code unsigned, signed byte, halfword, word (default)
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opcode formats
instruction uses 64-bit opcode. opcode divided essentially into data unit portion parallel transfer portion. There five data unit opcode formats comprising bits 38-63 opcode. Bits 0-38 opcode specify parallel transfer formats. alphabetical list mnemonics used Figure data unit parallel transfer portions opcode shown Table Table respectively.
Data Unit Formats
class class class oper src3 dst2 dst1 src1 src1 src1 src1 src4 src2 Parallel Transfers Parallel Transfers Parallel Transfers s1bnk cond 32-Bit Immediate Six-Operand (MPYIIADD, etc.) Base (5-Bit Immediate) Base (Register src2) Base (32-Bit Immediate) Miscellaneous
Operation Operation Operation
imm. src2 src2
dstbank Operation
Parallel Transfers
Reserved Reserved
Transfer Formats
Lmode Lmode Lmode Lmode Lmode cond cond cond cond size size size size Gim/X 0bank dstbank dstbank bank bank Adstbank dstbank dstbank bank Adstbank Gmode size srcbank size Lim/X Lim/X Lim/X Double Parallel Move Local Field Move Local Local (Long Offset) Lim/X Global (Long Offset) Non-D Local Conditional Conditional Mode Conditional Conditional Field Move Conditional Conditional Global
Gmode
Local Long Offset size As1bank srcbank size size As1bank
Global Long Offset size
Gmode
Gim/X
Conditional Non-D
Figure Opcode Formats
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opcode formats (continued)
Table Data Unit Mnemonics
MNEMONIC Operation class cond dst1 dst2 dstbank imm.src2 32-Bit Immediate oper Operation src1 src2 src3 src4 s1bnk FUNCTION selects arithmetic operations, selects Boolean operations Boolean operation select eight function signals. arithmetic operation bits specify function even bits define function modifiers. Operation class: determines routing operands condition code register destination lower bits non-D register code dest. MPY||ADD, MPY||EALU, EALU||ROTATE operation. register lower bits non-D register code Multiply dest. MPY||ADD MPY||EALU operation, rotate dest. EALU||ROTATE operation. register register bank 5-bit immediate src2 operation 32-bit immediate src2 operation Six-operand data unit operation (MPY||ADD, MPY||SADD, MPY||EALU, EALU||ROTATE, divi) Miscellaneous operation source register code register unless srcbank s1bnk used) register used source register multiplier source (MPY||ADD MPY||EALU) rotate amount (EALU||ROTATE) reg. port operand EALU||ROTATE mask generator input multiplier source MPY||ADD, MPY||EALU Bits src1 register code (bit assumed
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opcode formats (continued)
Table Parallel Transfer Mnemonics
MNEMONIC 0bank Adstbank As1bank bank cond dstbank Gmode Lmode size srcbank Bits destination register code Bits source register code Bits global local) store source load destination Conditional choice register src1 operand Protect status register's carry Condition code register lower bits register code local transfer source/destination Duplicate least significant data during moves three lowest bits register code move field-move destination Bits move destination register code Sign-extend local (bit 31), sign-extend global (bit Conditional global transfer Global address register load, store, address unit arithmetic Global address unit immediate offset index register Global unit addressing mode Global PP-relative addressing mode Number items selected field-extract move selects load operation, selects store address unit arithmetic operation Local address register load, store, address unit arithmetic Local address unit immediate offset index register Local unit addressing mode Local PP-relative addressing mode Protect status register's negative Conditional write result Register number used with bank 0bank global load, store, address unit arithmetic Enable index scaling. Additional index byte accesses arithmetic operations (bit local; global) Size data transfer (bits local; bits global) Three lowest bits register code register-register move source non-field moves. register source field move Bits register code register-register move source Protect status register's overflow Protect status register's zero Unused (fill with FUNCTION Bits global transfer source/destination register code (bit assumed
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opcode formats (continued)
Table summarizes supported parallel-transfer formats indicates whether transfers local global. also lists allowed operations states whether conditions status protection supported. Table Parallel-Transfer Format Summary
FORMAT Double parallel Move Local Field move Local Global (long offset) Local (long offset) Non-D Local Conditional move Conditional field move Conditional global Conditional non-D 32-bit imm. base Legend: OPERANDS dst1 src1 Lower GLOBAL TRANSFER Cond Status Protection Move Load Store Lower Index X/short X/long X/short LOCAL TRANSFER Load Store Index X/short X/short X/short X/long X/short Port Local Local Local Global Global
Data unit Address unit arithmetic Source/destination register Relative addressing support
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opcode formats (continued)
Table shows encoding used opcodes specify particular registers. 3-bit register field contains three least significant bits (LSBs). register codes used src, src1, src2, src3, src4, dst, dst1, dst2, reg, Gim/X, Lim/X opcode fields. four most significant bits (MSBs) specify register bank which concatenated register field full 7-bit code. register bank codes used dstbank, s1bnk, srcbank, 0bank, bank, Adstbank, As1bank opcode fields. When associated bank specified register field opcode, register bank assumed. When bank code specified opcode 0bank s1bnk), assumed indicating lower register. Table Register Codes
LOWER REGISTERS (MSB BANK CODING BANK 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0001 0001 0001 0001 0010 0010 0010 0010 0010 0010 0010 0010 0011 0011 0011 0011 0011 0011 0011 0011 Read only REGISTER reserved (sp) (zero) reserved (sp) (zero) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved CODING BANK 0100 0100 0100 0100 0100 0100 0100 0100 0101 0101 0101 0101 0101 0101 0101 0101 0110 0110 0110 0110 0110 0110 0110 0110 0111 0111 0111 0111 0111 0111 0111 0111 REGISTER reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pc/call ipa/br iprs inten intflg comm lctl BANK 1000 1000 1000 1000 1000 1000 1000 1000 1001 1001 1001 1001 1001 1001 1001 1001 1010 1010 1010 1010 1010 1010 1010 1010 1011 1011 1011 1011 1011 1011 1011 1011 UPPER REGISTERS (MSB BANK CODING REGISTER reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved CODING BANK 1100 1100 1100 1100 1100 1100 1100 1100 1101 1101 1101 1101 1101 1101 1101 1101 1110 1110 1110 1110 1110 1110 1110 1110 1111 1111 1111 1111 1111 1111 1111 1111 REGISTER reserved reserved lrse0 lrse1 lrse2 reserved lrs0 lrs1 lrs2 reserved reserved reserved reserved reserved reserved reserved tag0 tag1 tag2 tag3
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data unit operation code data unit opcode format 4-bit operation code specifies six-operand operations associated data path. Figure Table Six-Operand Format Operation Codes
oper FIELD OPERATION TYPE MPYU EALU EALU ROTATE divi
Legend: Unsigned complement EALU function code Subtract mask expander
operation class code base opcodes (formats operation-class code specify eight different routings ports ALU. Figure Table Base Class Summary
CLASS Legend: dstc src2 srd1 DESTINATION PORT src2 dstc dstc dstc src2 src2 dstc src1 src1 src1 src1 src1 src1 src1 src1 src2 src2 PORT PORT src2 %src2 %src2 src2 src2
Rotate left Expand function Mask generation Companion register Destination register register dstbank Adstbank used with destination. Source register immediate Source register register As1bank used lower register s1bnk used
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operation code base Boolean opcodes (A=0), function formed Boolean products selected operation opcode bits shown Table base arithmetic opcodes (A=1), four operation bits specify arithmetic operation described Table while four even bits specify function modifiers shown Table Table list operators Figure opcode formats. Table Base-Set Boolean Function Codes
OPCODE PRODUCT TERM A&B&C
Table Base Arithmetics
OPCODE BITS CARRY C(n) ~C(n) ~@mf) ~@mf) A+B/A-B A+B/A-B B>0> B>0> A-B/A+B A-B/A+B field sign=0 class class 6-7, sign=1 class class 6-7, sign=1 sign=0 ALGEBRAIC DESCRIPTION NATURAL FUNCTION MODIFIED FUNCTION DIFFERENT FROM NATURAL FUNCTION)
Legend: C(n)
each part port register Zero-extend shift right Zero-extend shift left One-extend shift right One-extend shift left
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ALU-operation code (continued) Table Function Modifier Codes
FUNCTION MODIFIER BITS Normal operation maskgen instruction, maskgen maskgen instruction, maskgen port port port maskgen, lmbc maskgen port maskgen, rmbc maskgen bit(s) carry out(s). (mc) bit(s) based status register field. (me) Rotate Asize, bit(s) carry out(s). (mrc) Rotate Asize, bit(s) based status register field. (mre) Clear bit(s) carry out(s). (mzc) Clear bit(s) based status register field. (mze) setting bits register. (mx) Reserved rmbc Modified mask generator Rightmost-bit change Rightmost MODIFICATION PERFORME
Legend: lmbc
Carry from sr(C) Leftmost-bit change Leftmost
miscellaneous operation code data-unit opcode format operation field selects miscellaneous operations. Table Miscellaneous Operation Codes
OPCODE BITS MNEMONIC reserved eint dint reserved reserved reserved Global-interrupt enable Global-interrupt disable OPERATION data-unit operation. Status modified
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addressing mode codes Lmode (bits 35-38) Gmode (bits 13-16) opcode specify local global transfer various parallel transfer opcode formats (Lmode formats Gmode formats Figure opcode formats. Table shows coding addressing mode fields. Table Addressing Mode Codes
CODING 00xx 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Legend: *(an *(an *(an imm) *(an imm) *(an *(an *(an imm) *(an imm) *(an *(an *(an imm) *(an imm) EXPRESSION DESCRIPTION (nonaddressing mode operation) Postaddition index register, with modify Postsubtraction index register, with modify Postaddition immediate, with modify Postsubtraction immediate, with modify Preaddition index register Presubtraction index register Preaddition immediate Presubtraction immediate Preaddition index register, with modify Presubtraction index register, with modify Preaddition immediate, with modify Presubtraction immediate, with modify
Address register local/global (l/g) address unit Immediate offset Index register same unit register
codes bits combine specify type parallel transfer performed. local transfer, bits respectively. global transfer, bits respectively. Figure opcode formats. Table Parallel Transfer Type
PARALLEL TRANSFER Store Address unit arithmetic Zero-extend load Sign-extend load
size codes size code specifies data transfer size. field moves (parallel transfer format only byte halfword data sizes valid.
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CODING DATA SIZE Byte bits) Halfword bits) Word bits) Reserved
Table Transfer Data Size
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relative-addressing mode codes opcode fields allow local-address global-address units, respectively, select PP-relative addressing shown Table Table Relative-Addressing Mode Codes
CODING RELATIVE-ADDRESSING MODE Normal (absolute addressing) Reserved PP-relative PP-relative
Legend: Data base base address Paramater base base address
condition codes four conditional parallel transfer opcodes (formats 7-10), condition code field specifies condition codes applied data unit operation source, data unit result, global transfer based settings bits, respectively. Table shows condition codes. 32-bit immediate data unit opcode (format condition applies data unit result only. Figure opcode formats. Table Condition Codes
CONDITION BITS Unconditional (default) Positive Lower than same Higher than Less than Less than equal Greater than equal Greater than Higher than same, carry Lower than, carry Equal, zero equal, zero Overflow overflow Negative Nonnegative None MNEMONIC DESCRIPTION STATUS COMBINATION
EALU operations
Extended (EALU) operations allow execution more advanced functions than those specified base opcodes. opcode EALU instructions contains operands operation while register extends opcode specifying EALU operation performed. format EALU operations shown Figure
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EALU Boolean functions EALU operations support Boolean functions plus flexibility carry-in Boolean sum. Boolean function performed ~C)) ~C)) ~C)) ~C))
+cin]
Table EALU Boolean Function Codes
FUNCTION SIGNAL PRODUCT TERM A&B&C
EALU arithmetic functions EALU operations support arithmetic functions provided three-input plus flexibility carry-in result. arithmetic function performed
f(A,B,C) f1(B,C) f2(B,C) cin]
f1(B,C) f2(B,C) independent Boolean combinations inputs. function specified selecting desired subfunction then XORing code from Table create function code bits 19-26 Additional operations such absolute values signed shifts performed using bits which control function based sign inputs. Table f1(B,C) f2(B,C) Subfunctions
CODE CODE ((-B ((-B SUBFUNCTION Zero term (All Negate Negate Force bits where bits Force bits where bits negate Force bits where bits Force bits where bits negate Force bits where bits Force bits where bits negate Force bits where bits Force bits where bits negate Choose Choose COMMON USAGE
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architecture
transfer controller (TC) combined memory controller (direct memory access) machine. handles movement data within 'C80 system requested master processor, parallel processors, external devices. transfer controller performs following data movement memory control functions:
instruction cache fills data-cache fills dirty block write-back direct external accesses (DEAs) packet transfers Externally initiated packet transfers (XPTs) Shift register transfer (SRT) packet transfers updating VRAM-based frame buffers DRAM refresh Host request
functional block diagram Figure shows functional block diagram transfer controller. features include: Crossbar interface 64-bit data path Single-cycle access
External memory interface 4G-Byte address range Programmable: size: 16-, 32-, 64-bits page size bank size address multiplexing cycle timing block-write mode bank priority Big- little-endian operation
Cache, VRAM, refresh controller Programmable refresh rate VRAM block-write support
Independent addressing Autonomous addressing based packet-transfer parameters Data read write different rates Numerous data merging alignment functions performed during transfer
Intelligent request prioritization
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functional block diagram (continued)
Alignment
Packet Transfer FIFO Cache Buffer
Alignment
Crossbar Interface
External Memory Interface
Controller Cache, VRAM, Refresh Controller
Controller Memory Configuration Cache
Control Registers
Control Registers
Request Queuing Prioritization
Requests
Requests
Requests
Requests
Host Requests
Figure Block Diagram registers contains four on-chip memory-mapped registers accessible
refresh control (REFCNTL) register (0x01820000)
REFCNTL register controls refresh cycles.
RPARLD RPARLD Refresh Pseudo-Address Reload Value REFRATE
REFRATE Refresh Interval clock cycles)
Figure REFCNTL Register
packet-transfer minimum (PTMIN) register (0x01820004)
PTMIN register determines minimum number cycles that packet transfer executes before being suspended higher priority packet transfer.
PTMIN
Figure PTMIN Register
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maximum (PTMAX) register (0x01820008)
PTMAX register determines maximum number cycles after PTMIN elapsed that packet transfer executes before timing out.
PTMAX
Figure PTMAX Register
fault status (FLTSTS) register (0x0182000C)
FLTSTS register indicates cause memory access fault. Fault status bits cleared writing appropriate bit.
Faulting Packet-Transfer Fault
Cache Fault Packet-Transfer Fault
Figure FLTSTS Register packet-transfer parameters most efficient method data movement SMJ320C80 system through packet transfers (PTs). Packet transfers allow move blocks data autonomously between specified memory region. Requests execute packet transfer made PPs, external devices. packet-transfer parameter table describing data packet transferred must programmed on-chip memory before transfer requested. SMJ320C80 supports shortand long-form packet transfers. parameter table format shown Figure
Next Entry Address Options Start Base Address Start Base Address Count Count Count Count Pitch Pitch Pitch Guide Table Pointer Pitch Guide Table Pointer Transparency Color Word Transparency Color Word Reserved Reserved Words swapped big-endian mode
Count Entries Count Entries 64-byte aligned on-chip starting address parameter table
Figure Packet-Transfer Parameter Table
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PT-options field PT-options field parameter table controls type transfer that performs. format options field shown Figure
S
D
Stop status Active Fault Suspended Fault Interrupt when complete Reverse addressing Reverse addressing Reverse addressing Reverse addressing Reverse addressing Exchange parameters
D
Access Mode Normal Block Write Transfer Mode Dimensioned Fill Reserved update mode None Pitch
Transfer Transfer Transfer Transfer Delta-Guided Offset-Guided Fixed Delta-Guided Fixed Offset-Guided Pitch Pitch Reverse
Valid only.
Figure PT-Options Field
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local memory interface status codes Status codes output STATUS[5:0] describe cycle being performed. During time, STATUS[5:0] pins indicate type cycle being performed. cycle type latched using used external logic perform memory bank decoding enable special hardware features. During column time, STATUS[5:0] pins indicate requesting processor special column information. Table Row-Time Status Codes
STATUS[5:0] CYCLE TYPE Normal Read Normal Write Refresh SDRAM DCAB Peripheral Device Read Peripheral Device Write Reserved Reserved Reserved Block-Write Reserved Reserved SDRAM Load Color Register Reserved Reserved Frame Read Transfer Frame Write Transfer Frame Split-Read Transfer Frame Split-Write Transfer Frame Read Transfer Frame Write Transfer Frame Split-Read Transfer Frame Split-Write Transfer Reserved Reserved Reserved Reserved Read Transfer Write Transfer Reserved Idle STATUS[5:0] CYCLE TYPE Reserved Reserved Reserved Reserved XPT1 Read XPT1 Write XPT1 PDPT Read XPT1 PDPT Write XPT2 Read XPT2 Write XPT2 PDPT Read XPT2 PDPT Write XPT3 Read XPT3 Write XPT3 PDPT Read XPT3 PDPT Write XPT4 SAM1 Read XPT4 SAM1 Write XPT4 SAM1 PDPT Read XPT4 SAM1 PDPT Write XPT5 SOF1 Read XPT5 SOF1 Write XPT5 SOF1 PDPT Read XPT5 SOF1 PDPT Write XPT6 SAM0 Read XPT6 SAM0 Write XPT6 SAM0 PDPT Read XPT6 SAM0 PDPT Write XPT7 SOF0 Read XPT7 SOF0 Write XPT7 SOF0 PDPT Read XPT7 SOF0 PDPT Write
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local memory interface (continued) Table Column-Time Status Codes
STATUS[5:0] CYCLE TYPE Low-Priority Packet Transfer High-Priority Packet Transfer Instruction Cache Low-Priority Packet Transfer High-Priority Packet Transfer Instruction Cache Low-Priority Packet Transfer High-Priority Packet Transfer Instruction Cache Low-Priority Packet Transfer High-Priority Packet Transfer Instruction Cache Low-Priority Packet Transfer High-Priority Packet Transfer Urgent Packet Transfer (Low) Urgent Packet Transfer (High) VCPT Progress VCPT Complete Instruction Cache (Low) Instruction Cache (High) (Low) (High) Data Cache (Low) Data Cache (High) Frame Frame Refresh Idle STATUS[5:0] CYCLE TYPE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Write Drain SDRAM DCAB
operating low-(normal) priority mode High operating high-priority mode
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address multiplexing support various devices, SMJ320C80 provide multiplexed column addresses address bus. full 32-bit address always output time. alignment column addresses configured value input AS[2:0] pins time.
Pins
Time Pins
[2:0]
Column Time
Figure Address Multiplexing dynamic sizing 'C80 supports data sizes bits. value input BS[1:0] pins time indicates size addressed memory. This determines maximum number bytes which 'C80 transfer during each column access. number bytes transferred exceeds size, multiple accesses performed automatically complete transfer. Table Size Selection
BS[1:0] SIZE bits bits bits bits
selected size also determines which portion data used transfer. 64-bit memory, entire data used. 32-bit memory, D[31:0] used little-endian mode D[63:32] used big-endian mode. 16-bit buses D[15:0] D[63:48] 8-bit buses D[7:0] D[63:56] littleand big-endian modes, respectively. 'C80 always aligns data proper portion activates appropriate strobes ensure that only valid bytes transferred.
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cycle time selection 'C80 supports eight basic sets memory timings support various memory types directly. cycle timing selected value input CT[2:0] pins time. selected timing remains effect until next access. Table Cycle-Timing Selection
CT[2:0] MEMORY TIMING Pipelined (Burst Length SDRAM, Latency Pipelined (Burst Length SDRAM, Latency Interleaved (Burst Length SDRAM, Latency Interleaved (Burst Length SDRAM, Latency Pipelined Cycle Column Nonpipelined Cycle Column Cycle Column Cycle Column
page sizing Whenever external memory access occurs, records most significant bits address internal LASTPAGE register. address each subsequent (column) access compared this value. page size value input PS[3:0] pins determines which bits LASTPAGE used this comparison. difference exists between enabled LASTPAGE bits corresponding bits next access, then page changed next memory access begins with row-address cycle. Table Page-Size Selection
PS[3:0] ADDRESS BITS COMPARED A[31:6] A[31:7] A[31:8] A[31:9] A[31:10] A[31:18] A[31:19] A[31:20] A[31:0] A[31:11] A[31:12] A[31:13] A[31:14] A[31:15] A[31:16] A[31:17] PAGE SIZE (BYTES) 256K 512K 128K
PS[3:0] 1000 disables page-mode cycles that effective page size same size
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block-write support SMJ320C80 supports three modes VRAM block-write. block-write mode dynamically selectable that software specify block-writes regardless type block-write addressed memory supports. Block-writes supported only 64-bit buses. During block-write load-color-register cycles, BS[1:0] inputs determine which block mode will used. Table Block-Write Selection
BS[1:0] BLOCK-WRITE MODE Simulated Reserved
SDRAM support SMJ320C80 provides direct support synchronous DRAM (SDRAM), synchronous VRAM (SVRAM), synchronous graphics (SGRAM). During 'C80 power-up refresh cycles, external system must signal presence these memories inputting value This causes 'C80 perform special deactivate (DCAB) mode register (MRS) commands initialize synchronous RAMs. Figure shows value generated 'C80.
SDRAM Mode Register
CT0, input start cycle
Figure Value Because register programmed through SDRAM address inputs, alignment data 'C80 logical-address bits adjusted size (see Figure 55). appearance bits 'C80 physical-address dependent address multiplexing selected AS[2:0] inputs.
'C80 LOGICAL ADDRESS BITS BS[1:0]
Figure Value Alignment memory cycles SMJ320C80 external memory cycles generated TC's external memory controller. controller's state machine generates sequence states which define transition memory interface signals. state sequence dependent cycle timing selected memory access being performed shown Figure Memory cycles consist states column pipeline.
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memory cycles (continued)
rhiz release idle abort request always cycle
always
fault, retry, abort
cycle
always
wait
!SRS
refresh
refresh
refresh
always
DCAB
!MRS !DCAB spin rspin spin
access
wait
access
Column Pipeline
Figure Memory Cycle State Diagram
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page
page write)
always
SMJ320C80 DIGITAL SIGNAL PROCESSOR
states states make time each memory access. They occur when each page access begins. transition indicators determine conditions that cause transitions another state. Table States
STATE DESCRIPTION Beginning state memory accesses. Outputs address (A[31:0]) cycle type (STATUS[5:0]) drives control signals their inactive state Common memory accesses. Asserts drives DDIN according data transfer direction. AS[2:0], BS[1:0], CT[2:0], PS[3:0], UTIME inputs sampled Common memory accesses. DBEN driven active level. non-SDRAM, CAS, driven their active levels, non-SDRAM refreshes, strobes activated. FAULT, READY, RETRY inputs sampled. Inserted cycle column accesses (CT=111) only. signal transitions occur. RETRY input sampled. Common SDRAM cycle column accesses (CT=0xx 11x). driven low. driven DCAB cycles driven SDRAM refresh cycles. Common memory accesses. SDRAM cycles, RAS, CAS, driven high. non-SDRAM, driven already) CAS, driven their appropriate levels. DBEN driven READY RETRY sampled. Additional state allow column time pipeline load. signal transitions occur. RETRY sampled. rspin state can, occasion, repeat multiple times. Common cycle column refreshes (CT=11x). Processor activity code output STATUS[5:0]. RETRY input sampled. cycle column refreshes only (CT=111). signal transitions occur. RETRY input sampled. Common refresh cycles. Processor activity code output STATUS[5:0] RETRY input sampled. Occurs SDRAM cycles 0xx) pipelined cycle column writes only. SDRAM cycles, RAS, activated perform DCAB command. pipelined writes, strobes activated. High-impedance state. Occurs during host requests repeats until released host
rspin rhiz
Table State Transition Indicators
INDICATOR cycle CT=xxx abort fault retry wait spin page Continuation current cycle State change occurs indicated CT[2:0] value latched state) Current cycle aborted favor higher-priority cycle FAULT input sampled state), memory access faulted RETRY input sampled state), row-time retry READY input sampled last column state) repeat current state Internally generated wait state allow pipeline load next access requires page change (new access) DESCRIPTION
external memory timing examples
following sections contain descriptions 'C80 memory cycles illustrate signal transitions those cycles. Memory cycles separated into basic categories: DRAM-type cycles with DRAM-like devices, SRAM, peripherals, SDRAM-type cycles with SDRAM-like devices.
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DRAM-type cycles DRAM-type cycles page-mode accesses consisting access followed more column accesses. Column accesses one, two, three clock cycles length with three cycle accesses allowing insertion wait states accommodate slow devices. Idle cycles occur after necessary column accesses have completed between column accesses "bubbles" data-flow pipeline. pipeline diagrams Figure show pipeline stages each access type when CAS/ signal corresponding column access activated.
Idle Idle
Pipelined cycle column 0000)
Pipelined cycle column 0000) reads, read transfers, split read transfers Idle
writes, load color register (LCR), block writes
Idle
Nonpipelined cycle column 0001) writes, LCRs, block writes
Nonpipelined cycle column 0001) reads, read transfers, split read transfers
Idle
Idle cycle column 0010)
cycle column 0010) writes, LCRs, block writes
reads, read transfers, split read transfers
Idle cycle column 0011) reads, read transfers, split read transfers
cycle column 0011) writes, LCRs, block writes
Figure DRAM Cycle Column Pipelines
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read cycles
Read cycles transfer data instructions from external memory 'C80. cycles occur result packet transfer, cache request, request. During cycle, held high, driven after enable memory output drivers DBEN DDIN that data transceivers drive into 'C80. During column time, places D[63:0] into high-impedance state, allowing driven memory latches input data during appropriate column state. always reads bits extracts aligns appropriate bytes. Invalid bytes sizes less than bits discarded. During peripheral device packet transfers, DBEN DDIN remain high.
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read cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN Cycle Type Idle
Normal Reads, PDPT Reads
user-modified timing: UTIME DQM[7:0]
Figure Pipelined 1-Cycle Column Read-Cycle Timing
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read cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] Cycle Type Idle
D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0]
Normal Reads, PDPT Reads
Figure Nonpipelined 1-Cycle Column Read-Cycle Timing
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read cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Cycle Type Idle
Normal Reads, PDPT Reads
Wait state inserted external logic (example) Internally generated pipeline bubble (example)
Figure 2-Cycle Column Read-Cycle Timing
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read cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Wait state inserted external logic (example) Internally generated pipeline bubble (example)
Normal Reads, PDPT Reads Column Column Column Cycle Type Idle
Figure 3-Cycle Column Read-Cycle Timing
write cycles
Write cycles transfer data from 'C80 external memory. These cycles occur result packet transfer, request, data cache write-back. During cycle TRG/ held high, driven after fall enable early-write cycles, DDIN high that data transceivers drive toward memory. drives data D[63:0] indicates valid bytes activating appropriate CAS/ strobes. During peripheral device packet transfers, DBEN remains high D[63:0] placed high impedance that peripheral device drive data into memory.
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
write cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Internally generated pipeline bubble (example)
Cycle Type
rspin
rspin
Idle
Drain
Normal Write, PDPT Write
Figure Pipelined 1-Cycle Column Write-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
write cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type rspin rspin
Idle
A[31:0] DQM[7:0] D[63:0] DBEN DDIN
Normal Write, PDPT Write
user-modified timing: UTIME DQM[7:0]
Internally generated pipeline bubble (example)
Figure Nonpipelined 1-Cycle Column Write-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
write cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Wait state inserted external logic (example) Internally generated pipeline bubble (example)
Cycle Type Idle
rspin
Normal Write, PDPT Write
Figure 2-Cycle Column Write-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
write cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Wait state inserted external logic (example) Internally generated pipeline bubble (example)
Cycle Type Idle
Normal Write, PDPT Write
Figure 3-Cycle Column Write-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
load-color-register cycles
Load-color-register (LCR) cycles used load VRAM's color register prior performing block-write. cycles supported only 64-bit data buses. cycle closely resembles normal write cycle because writes into VRAM. difference that output high both fall fall CAS/ DQM. Also, because VRAM color register single location, only column access occurs. address that output used bank-decode only. Normally, VRAM banks should selected during cycle because another cycle cannot occur when block-write memory-page change occurs. column address that output during likewise irrelevant because VRAM color register only location written. strobes active during cycle. exception support given bank enabled, EXCEPT [1:0] inputs sampled during column states must valid levels. retry code (EXCEPT [1:0] column time effect, however, because only column access performed. field configuration cache entry given bank indicates that addressed memory supports only simulated block-writes, cycle will changed into normal write cycle start simulated block-write.
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
load-color-register cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN Color Cycle Type Drain rspin rspin
user-modified timing: UTIME DQM[7:0]
Figure Pipelined 1-Cycle Column Load-Color-Register-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
load-color-register cycles (continued)
State rspin rspin
CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Color Cycle Type
Figure Nonpipelined 1-Cycle Column Load-Color-Register-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
load-color-register cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN Color Value Cycle Type rspin
user-modified timing: UTIME DQM[7:0]
Figure 2-Cycle Column Load-Color-Register-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
load-color-register cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Color Value Cycle Type
Figure 3-Cycle Column Load-Color-Register-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
block-write cycles
Block-write cycles cause data stored VRAM color registers written memory locations enabled appropriate data bits output D[63:0] bus. This allows total bytes (depending type block-write being used) written single-column access. This cycle identical standard write cycle with following exceptions:
active (high) fall CAS, enabling block-write function within VRAMs. Only 64-bit sizes supported during block-write; therefore, BS[1:0] inputs used indicate type block-write that supported addressed VRAMs, rather than size. three LSBs (depending type block-write) column address ignored VRAMs because these column locations specified data inputs. values output D[63:0] represent column locations written using color register value. Depending type block-write supported VRAM, data bits necessarily used VRAMs. Block-writes always begin with access. Upon completion block-write, memory interface returns state await next access.
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
block-write cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Internally generated pipeline bubble (example) Cycle Type Idle Drain rspin rspin
Figure Pipelined 1-Cycle Column Block-Write-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
block-write cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Internally generated pipeline bubble (example) Cycle Type Idle rspin rspin
Figure Nonpipelined 1-Cycle Column Block-Write-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
block-write cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Wait state inserted external logic (example) Internally generated pipeline bubble (example)
Cycle Type Idle
rspin
Figure 2-Cycle Column Block-Write-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
block-write cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0]
Cycle Type Idle
Wait state inserted external logic (example) Internally generated pipeline bubble (example)
Figure 3-Cycle Column Block-Write-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
transfer cycles
Read-transfer (memory-to-register) cycles transfer from VRAM memory array into VRAM shift register (sequential-access memory, SAM). This causes entire (both halves split SAM) loaded with array data. Split-register read-transfer (memory-to-split-register) cycles also transfer data from memory array SAM. However, these transfers cause only half written. Split-register read transfers allow inactive half loaded with data while other active half continues shift data out. Write-transfer (register-to-memory) cycles transfer data from into VRAM array. This transfer causes entire (both halves split SAM) written into array. Split-register write-transfer (split-register-to-memory) cycles also transfer data from memory array. However, these transfers write only half into array. Split-register write transfers allow inactive half transferred into memory while other (active) half continues shift serial data out. Read split-read transfers resemble standard read cycle. Write split-write transfers resemble standard write cycle. output driven prior fall indicate transfer cycle. Only single column access performed RETRY, while required valid level, effect asserted column time. value output A[31:0] column time represents point.
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
transfer cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN Full Transfer, Split Transfer Point Cycle Type Idle
user-modified timing: UTIME DQM[7:0]
Figure Pipelined 1-Cycle/Column Read-Transfer Split-Register Read-Transfer-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
transfer cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] Full Transfer, Split Transfer D[63:0] DBEN DDIN Point Cycle Type Idle
user-modified timing: UTIME DQM[7:0]
Figure Nonpipelined 1-Cycle/Column Read-Transfer Split-Register Read-Transfer-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
transfer cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN Full Transfer, Split Transfer Point Cycle Type
user-modified timing: UTIME DQM[7:0]
Figure 2-Cycle/Column Read-Transfer Split-Register Read-Transfer-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
transfer cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0] Full Transfer, Split Transfer Point Cycle Type
Figure 3-Cycle/Column Read-Transfer Split-Register Read-Transfer-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
transfer cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN
Full Transfer, Split Transfer Point Cycle Type Drain
rspin
rspin
user-modified timing:
UTIME DQM[7:0]
Figure Pipelined 1-Cycle/Column Write-Transfer Split-Register Write-Transfer-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
transfer cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0]
Full Transfer, Split Transfer Point Cycle Type
rspin
rspin
Figure Nonpipelined 1-Cycle/Column Write-Transfer Split-Register Write-Transfer-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
transfer cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN user-modified timing: UTIME DQM[7:0]
Full Transfer, Split Transfer
rspin
Cycle Type
Point
Figure 2-Cycle/Column Write-Transfer Split-Register Write-Transfer-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
transfer cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:0] DQM[7:0] D[63:0] DBEN DDIN
Full Transfer, Split Transfer
Cycle Type
Column
user-modified timing: UTIME DQM[7:0]
Figure 3-Cycle/Column Write-Transfer Split-Register Write-Transfer-Cycle Timing
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
refresh cycles
Refresh cycles generated programmed refresh interval. They characterized following signal activity:
falls prior RAS. pins CAS[7:0]) active. TRG, DBEN remain inactive (high) because data transfer occurs. active (high) fall driven inactive prior fall RAS. data driven high-impedance state. upper half address (A[31:16]) contains refresh pseudo-address lower half (A[15:0]) driven zeros. RETRY asserted sample point during cycle, cycle timing modified. Instead, pseudo-address backlog counters simply decremented. Selecting user-modified timing effect cycles. Upon completion refresh cycle, memory interface returns state await next access.
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SMJ320C80 DIGITAL SIGNAL PROCESSOR
refresh cycles (continued)
State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] A[31:16] A[15:0] DQM[7:0] D[63:0] DBEN DDIN Refresh Pseudo Address Cycle Type
Figure 1-Cycle/Column Refresh-Cycle Timing
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