PACKAGE (TOP VIEW) description SMJ320C50A digital signal pro

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SMJ320C50A DIGITAL SIGNAL PROCESSOR
PACKAGE (TOP VIEW)
description
SMJ320C50A digital signal processor (DSP) high-performance, 16-bit, fixed-point processor manufactured 0.8-µm double-level metal CMOS technology. SMJ320C50A first from designed fully static device. Full-static CMOS design contributes power consumption while maintaining high performance, making ideal applications such battery-operated communications systems, satellite systems, advanced control algorithms.
EPIC trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1994, Texas Instruments Incorporated
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Military Operating Temperature Range: 55°C 125°C Processed MIL-STD-883, Class Fast Instruction Cycle Times Source-Code Compatible With 'C1x 'C2x Devices RAM-Based Operation 16-Bit Single-Cycle On-Chip Program/Data 1056 16-Bit Dual-Access On-Chip Data 16-Bit On-Chip Boot 224K 16-Bit Maximum Addressable External Memory Space (64K Program, Data, I/O, Global) 32-Bit Arithmetic Logic Unit (ALU) 32-bit Accumulator (ACC) 32-Bit Accumulator Buffer (ACCB) 16-Bit Parallel Logic Unit (PLU) 16-Bit Multiplier, 32-Bit Product Context-Switch Registers Buffers Circular Addressing Full-Duplex Synchronous Serial Port Time-Division Multiplexed Serial Port (TDM) Timer With Control Counter Registers Software Programmable Wait-State Generators Divide-by-One Clock Option JTAG Boundary Scan Logic (IEEE 1149.1) Operations Fully Static Texas Instruments EPIC0.8-µm CMOS Technology Packaging 141-Pin Ceramic Grid Array (GFA Suffix) 132-Lead Ceramic Quad Flat Package (HFG Suffix)
PACKAGE (TOP VIEW)
SMJ320C50A DIGITAL SIGNAL PROCESSOR
description (continued)
number enhancements basic SMJ320C2x architecture give 'C50A minimum performance over previous generation. four-deep instruction pipeline, incorporating delayed branching, delayed call subroutine, delayed return from subroutine, allows 'C50A perform instructions fewer cycles. addition parallel logic unit (PLU) gives 'C50A method manipulating bits data memory without using accumulator ALU. 'C50A additional shifting scaling capability proper alignment multiplicands storage values data memory. 'C50A achieves power consumption through IDLE2 instruction. IDLE2 removes functional clock from internal hardware 'C50A, which puts into total-sleep mode that uses only logic level external interrupt with duration least five clock cycles ends IDLE2 mode. 'C50A available with clock speeds. clock frequencies MHz, giving 50-ns cycle time, MHz, giving 40-ns cycle time.
AVAILABLE OPTIONS PART NUMBER SMJ320C50AGFAM40 SMJ320C50AGFAM50 SMJ320C50AHFGM40 SMJ320C50AHFGM50 SPEED 50-ns cycle time 40-ns cycle time 50-ns cycle time 40-ns cycle time SUPPLY VOLTAGE TOLERANCE ±10% ±10% ±10% ±10% PACKAGE grid array grid array Quad flat package Quad flat package
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
functional block diagram
Program (Address) Program (Data)
IPTR BMAR
INT#
IN
PC(16) PASR BRAF MP/MC PAER
Compare Stack
Program Memory
BRCR
Data (Data)
TREG2 TREG1 TREG0
Multiplier COUNT PREG(32) Prescaler P-Scaler
ALU(32) ACCB(32) ACC(32)
Post-Scaler
DBMR
PLU(16) Data (Data)
CBER
INDX
ARCR
AUXREGS
CBSR DP(9) dma(7)
CBCR
ARAU(16) Data (Address) Data Memory OVLY GREG
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
ASSIGNMENTS PKG. PKG. NAME (LSB) INT1 INT2 INT3 INT4 CLKR PKG. PKG. NAME (LSB) CLKMD1 PKG. PKG. NAME STRB CLKIN2 X2/CLKIN CLKMD2 TFSX/TFRM HOLDA CLKOUT1 IACK EMU0 EMU1/OFF PKG. PKG. NAME TOUT TCLKX CLKX TFSR/TADD TCLKR READY HOLD TRST MP/MC (MSB)
connect. Package additional connections: VDD: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, VSS: T14, C17, C19, D14, D16, D18, F16, H16, K16, M16,
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
Terminal Functions
SIGNAL (MSB) (LSB) (MSB) (LSB) TYPE DESCRIPTION ADDRESS DATA BUSES
I/O/Z
Parallel address bus. Multiplexed address external data, program memory, I/O. high-impedance state hold mode when active (low). These signals used inputs external access on-chip single-access RAM. They become inputs while HOLDA active (low) externally driven low.
I/O/Z
Parallel data bus. Multiplexed transfer data between core external data, program memory, devices. high-impedance state when outputting data, when HOLD asserted, when active (low). These signals also used external access on-chip single-access RAM.
MEMORY CONTROL SIGNALS READY Data, program, space select signals. Always high unless asserted communicating particular external space. high-impedance state hold mode when active (low). Data ready input. Indicates that external device prepared transaction completed. device ready (READY low), processor waits cycle checks READY again. READY also indicates grant external device after (bus request) signal. Read write. Indicates transfer direction during communication external device. Normally read mode (high) unless asserted performing write operation. high-impedance state hold mode when active (low). Used external access cell. While HOLDA active (low), this signal used indicate direction data reads (high) writes (low).
I/O/Z
NOTE: input pins that unused should connected external pullup resistor. internal pullup performing on-chip RAM. emulation, TRST internal pulldown, TMS, TCK, have internal pullups. EMU0 EMU1 require external pullups support emulation.
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
Terminal Functions (continued)
SIGNAL TYPE DESCRIPTION MEMORY CONTROL SIGNALS (CONTINUED) Strobe. Always high unless asserted indicate external cycle. STRB high-impedance state hold mode when active (low). Used external access on-chip single-access RAM. While HOLDA active (low), this signal used select memory access. Read select. Indicates active external read cycle connect directly output enable (OE) external devices. This signal active external program, data, reads. high-impedance state hold mode when active (low). Write enable. falling edge indicates that device driving external data (D15 D0). Data latched external device rising edge This signal active external program, data, writes. high-impedance state hold mode when active (low). MULTIPROCESSING SIGNALS HOLD Hold. Asserted request control address, data, control lines. When acknowledged 'C50A, these lines high-impedance state. Hold acknowledge. Indicates external circuitry that processor hold state that address, data, memory control lines high-impedance state that they available external circuitry access local memory. This signal also goes high-impedance state when active (low). request. Asserted during access external global data memory space. READY asserted when global data memory available transaction. used extend data memory address space words. goes high-impedance state when active low. used external access on-chip single-access RAM. While HOLDA active (low), externally driven (low) request access on-chip single-access RAM. Instruction acquisition. Asserted (active) when there instruction address address bus; goes into high-impedance state when active (low). also used external access on-chip single-access RAM. While HOLDA active (low), acknowledges request access on-chip single-access stops indicating instruction acquisition. Branch control. Samples condition. low, device executes conditional instruction. must active during fetch conditional instruction. External flag (latched software-programmable signal). high specific instruction loading status register (ST1). Used signaling other processors multiprocessor configurations general-purpose output. goes high-impedance state when active (low) high reset. Interrupt acknowledge. Indicates receipt interrupt that program counter fetching interrupt vector location designated IACK goes high-impedance state when active (low). INITIALIZATION, INTERRUPT, RESET OPERATIONS INT4 INT3 INT2 INT1 External interrupts. Prioritized maskable interrupt mask register (IMR) interrupt mode (INTM, status register These signals polled reset interrupt flag register. Nonmaskable interrupt. External interrupt that cannot masked INor IMR. When activated, processor traps appropriate vector location. Reset. Causes device terminate execution forces program counter zero. When brought high level, execution begins location zero program memory. Microprocessor microcomputer select. active (low) reset (microcomputer mode), signal causes internal program mapped into program memory space. microprocessor mode, program memory mapped externally. This signal sampled only during reset, mode that reset overridden software control PMST register.
STRB
I/O/Z
HOLDA
I/O/Z
IACK
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
Terminal Functions (continued)
SIGNAL TYPE DESCRIPTION OSCILLATOR TIMER SIGNALS CLKOUT1 Master clock CLKIN2 frequency). CLKOUT1 cycles machine-cycle rate CPU. internal machine cycle bounded rising edges this signal. This signal goes high-impedance state when active (low). CLKMD1 CLKMD1 CLKMD2 CLKMD2 Clock mode External clock with divide-by-two option. Input clock provided X2/CLKIN1. Internal oscillator disabled. Reserved test purposes External divide-by-one option. Input clock provided CLKIN2. Internal oscillator disabled internal enabled. Internal external divide-by-two option. Input clock provided X2/CLKIN1. Internal oscillator enabled internal disabled.
CLKIN CLKIN2 TOUT
Input internal oscillator from crystal. internal oscillator being used, clock input device CLKIN. internal machine cycle half this clock rate. Output from internal oscillator crystal. internal oscillator used, should left unconnected. This signal does high-impedance state when active (low). Divide-by-one input clock driving internal machine rate. Timer output. TOUT signals pulse when on-chip timer counts down past zero. pulse CLKOUT1 cycle wide. SUPPLY PINS
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10
Power supply data
Power supply address Power supply inputs internal logic Power supply address Power supply memory control signals Power supply inputs internal logic Power supply memory control signals Ground memory control signals
Ground data
Ground address
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
Terminal Functions (continued)
SIGNAL VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 TYPE DESCRIPTION SUPPLY PINS (CONTINUED) Ground memory control signals
Ground inputs internal logic
SERIAL PORT SIGNALS CLKR TCLKR Receive clock. External clock signal clocking data from (data receive) (TDM data receive) into (serial port receive shift register). Must present during serial port transfers. serial port being used, these signals sampled input serial port control (SPC) serial port control (TSPC) registers. Transmit clock. Clock signal clocking data from (data transmit) (TDM data transmit pins). CLKX input serial port control register also driven device CLKOUT1 frequency when serial port being used, this sampled input TSPC register. This signal goes into high-impedance state when active (low). Serial data receive. Serial data received (serial port receive shift register) TDR. Serial port transmit. Serial data transmitted from (serial port transmit shift register) TDX. This signal high-impedance state when transmitting when active (low). Frame synchronization pulse receive. falling edge TFSR initiates data receive process, which begins clocking RSR. TFSR becomes input output (TADD) when serial port operating mode (TDM mode, this used input /output address port. This signal goes into high-impedance state when active (low). Frame synchronization pulse transmit. falling edge FSX/TFSX initiates data transmit process, which begins clocking XSR. Following reset, default operating condition FSX/TFSX input. This selected software output when serial control register This signal goes high-impedance state when active (low). When operating mode (TDM TFSX becomes TFRM, frame synchronization pulse. TEST SIGNALS JTAG test clock. This normally free-running clock with duty cycle. changes (test access port) input signals (TMS TDI) clocked into controller, instruction register, selected test data register rising edge TCK. Changes output signal (TDO) occur falling edge TCK. JTAG test data input. clocked into selected register (instruction data) rising edge TCK. JTAG test data output. contents selected register (instruction data) shifted falling edge TCK. high-impedance state except when scanning data progress. This signal also goes high-impedance state when active (low). JTAG test mode select. This serial control input clocked into test access port (TAP) controller rising edge TCK. JTAG test reset. Asserting this signal gives JTAG scan system control operations device. this signal connected driven low, device operates functional mode JTAG signals ignored.
CLKX TCLKX
I/O/Z
TFSR TADD
I/O/Z
TFSX TFRM
I/O/Z
TRST
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
Terminal Functions (continued)
SIGNAL TYPE DESCRIPTION TEST SIGNALS (CONTINUED) EMU0 I/O/Z Emulator When TRST driven low, EMU0 must high activation condition (see EMU1/OFF). When TRST driven high, EMU0 used interrupt from emulator system defined input/output JTAG scan. Emulator 1/OFF. When TRST driven high, EMU1 used interrupt from emulator system defined input/output JTAG scan. When TRST driven low, EMU1 configured OFF. When signal active (low), output drivers high-impedance state. used exclusively testing emulation purposes (not multiprocessing applications). condition, following conditions apply: RESERVED Quad flat pack only TRST EMU0 High EMU1/OFF
EMU1
I/O/Z
Reserved. This should left unconnected.
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Input voltage range Output voltage range Maximum operating case temperature 125°C Minimum operating free-air temperature, 55°C Storage temperature range 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect VSS.
recommended operating conditions
Supply voltage Supply voltage CLKIN, CLKIN2 High-level input voltage Low-level input voltage High-level output current Low-level output current Operating case temperature Operating free-air temperature CLKX, CLKR, TCLKX, TCLKR others UNIT
electrical characteristics over recommended ranges supply voltage operating free-air temperature (unless otherwise noted)
PARAMETER High-level output Low-level output High-impedance output current (VDD MAX) others TRST (with internal pulldown) Input current VDD) Supply current, core Supply current, pins Supply current, standby current Input capacitance TMS, TCK, (with internal pullups) X2/CLKIN other inputs IDDC IDDP Operating, Operating, 25°C, 25°C, 55°C, 5.25 40.96 TEST CONDITIONS UNIT
IDLE instruction,
5.25 40.96 IDLE2 instruction, Clocks shut off, 55°C,
Output capacitance conditions shown MAX, appropriate value specified under "recommended operating conditions". typical nominal values 25°C. input output voltage levels TTL-compatible. Figure shows tested load circuit; Figure Figure show voltage reference levels. These values specified pending detailed characterization.
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
Tester Electronics VLOAD Output Under Test
Where: VLOAD (all outputs) (all outputs) typical load circuit capacitance
Figure Test Load Circuit
signal transition levels
TTL-output levels driven minimum logic-high level maximum logic-low level Figure shows TTL-level outputs.
Figure TTL-Level Outputs TTL-output transition times specified follows:
high-to-low transition, level which output said longer high level which output said low-to-high transition, level which output said longer level which output said high
Figure shows TTL-level inputs.
Figure TTL-Level Inputs TTL-compatible input transition times specified follows:
high-to-low transition input signal, level which input said longer high level which input said high transisiton input signal, level which input said longer level which input said high
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
CLOCK CHARACTERISTICS TIMING
'C50A either internal oscillator external frequency source clock. clock mode determined CLKMD1 CLKMD2 pins. following table outlines selection clock mode these pins.
CLKMD1 CLKMD2 CLOCK SOURCE External divide-by-one clock option Reserved test purposes External divide-by-two option internal divide-by-two clock option with external crystal External divide-by-two option with internal oscillator disabled
internal divide-by-two clock option with external crystal
internal oscillator enabled connecting crystal across /CLKIN. frequency CLKOUT1 one-half crystal's oscillating frequency. crystal should either fundamental overtone operation parallel resonant, with effective series resistance power dissipation should specified load capacitance Overtone crystals require additional tuned circuit. Figure shows external crystal (fundamental frequency) connected on-chip oscillator.
recommended operating conditions internal divide-by-two clock option
PARAMETER Input clock frequency SMJ320C50A-40 SMJ320C50A-50 UNIT
Load capacitance This device utilizes fully static design therefore operate with tc(CI) approaching device characterized frequencies approaching tested minimum meet device test time requirements. Other timings 'C50A-50 device same those 'C50A-40 device except where otherwise indicated.
Crystal
/CLKIN
Figure Internal Clock Option
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
external divide-by-two clock option
external frequency source used injecting frequency directly into /CLKIN with left unconnected, CLKMD1 high, CLKMD2 high. external frequency divided generate internal machine cycle. external frequency injected must conform specifications listed timing requirements table.
switching characteristics over recommended operating conditions tc(CO)]
PARAMETER tc(CO) (CO) td(CIH-CO) tf(CO) tr(CO) tw(COL) tw(COH) Cycle time, CLKOUT1 time Delay time, CLKIN high CLKOUT1 high/low Fall time, CLKOUT1 Rise time, CLKOUT1 Pulse duration, CLKOUT1 Pulse duration, CLKOUT1 high '320C50-40 '320C50-50 2tc(CI) 2tc(CI) UNIT
timing requirements over recommended ranges supply voltage operating free-air temperature
tc(CI) (CI) tf(CI) tr(CI) tw(CIL) (CIL) tw(CIH) (CIH) Cycle time, CLKIN time Fall time, Rise time, Pulse duration CLKIN duration, Pulse duration, CLKIN high duration '320C50A-40 '320C50A-50 '320C50A-40 '320C50A-50 '320C50A-40 '320C50A-50 UNIT
This device utilizes fully static design therefore operate with tc(CI) approaching device characterized frequencies approaching tested minimum meet device test time requirements. Other timings 'C50A-50 device same those 'C50A-40 device except where otherwise indicated. Values derived from characterization data tested. tw(CIH) tr(CI) tw(CIL) tf(CI)
tc(CI) CLKIN tc(CO) td(CIH-CO) CLKOUT1 tw(COH)
tf(CO) tr(CO) tw(COL)
Figure External Divide-by-Two Clock Timing
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
external divide-by-one clock option
external frequency source used injecting frequency directly into CLKIN2 with left unconnected connected VDD. This external frequency divided generate internal machine cycle. divide-by-one option used when CLKMD1 strapped high CLKMD2 strapped low. external frequency injected must conform specifications listed timing requirements table.
switching characteristics over recommended operating conditions tc(CO)]
PARAMETER tc(CO) (CO) td(CIH-CO) tf(CO) tr(CO) tw(COL) tw(COH) Cycle time, CLKOUT1 time Delay time, CLKIN2 high CLKOUT1 high Fall time, CLKOUT1 Rise time, CLKOUT1 Pulse duration, CLKOUT1 Pulse duration, CLKOUT1 high Transitory phase synchronized after CLKIN2 supplied '320C50A-40 '320C50A-50 tc(CI) tc(CI) UNIT cycles
timing requirements over recommended ranges supply voltage operating free-air temperature
tc(CI) (CI) tf(CI) tr(CI) tw(CIL) (CIL) tw(CIH) (CIH) Cycle time, CLKIN2 time Fall time, Rise time, Pulse duration, CLKIN2 duration Pulse duration, CLKIN2 high duration '320C50A-40 '320C50A-50 '320C50A-40 '320C50A-50 '320C50A-40 '320C50A-50 UNIT
Clocks stopped only while device executes IDLE2 when using external divide-by-one clock option. Note that (the transitory phase) will occur when restarting clock from IDLE2 this mode. Other timings 'C50A-50 device same those 'C50A-40 device except where indicated otherwise. Values specified design tested. Values derived from characterization data tested. tw(CIH) tc(CI) CLKIN2 td(CIH-CO) tc(CO) CLKOUT1 Unstable tw(COH) tf(CO) tw(COL) tr(CO) tw(CIL) tr(CI) tf(CI)
Figure External Divide-by-One Clock Timing
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
MEMORY PARALLEL INTERFACE READ switching characteristics over recommended operating conditions 0.5tc(CO)]
tsu(A)R th(A)R tw(RL) tw(RH) PARAMETER Setup time, address valid before Hold time, address valid after high Pulse duration, Pulse duration, UNIT
td(RW) Delay time, high R/W, timings included timings referenced address. Figure address timing variation with load capacitance. STRB timing from CLKOUT1 timing read cycles, following first cycle after reset, which always wait-state cycle. Values derived from characterization data tested.
timing requirements over recommended ranges supply voltage operating free-air temperature 0.5tc(CO)]
ta(A) ta(R) tsu(D)R Access time, read data valid from address valid time Access time, read data valid after Setup time, read data valid before high '320C50A-40 '320C50A-50# UNIT
th(D)R Hold time, read data valid after high Figure address timing variation with load capacitance. Other timings 'C50A-50 device same 'C50A-40 device except where indicated otherwise.
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
MEMORY PARALLEL INTERFACE WRITE switching characteristics over recommended operating conditions 0.5tc(CO)]
tsu(A)W th(A)W tw(WL) tw(WH) td(WR) tsu(D)W PARAMETER Setup time, address valid before Hold time, address valid after high Pulse duration, Pulse duration, Delay time, high Setup time, write data valid before UNIT
th(D)W Hold time, write data valid after ten(D)W Enable time, data driven A0,PS, R/W, timings included timings referenced address. Figure address timing variation with load capacitance. STRB edges from CLKOUT1 edges writes. Rising falling edges these signals track each other; tolerance resulting pulse durations Values derived from characterization data tested. This value holds true zero wait state only. ADDRESS tsu(A)W ta(A) ta(R) tsu(D)R DATA tsu(A)R tw(RH) tw(RL) tw(WH) STRB NOTE timings wait states. However, external writes always require cycles prevent external conflicts. above diagram illustrates one-cycle read two-cycle write drawn scale. external writes immediately preceded external read immediately followed external read require three machine cycles. td(RW) td(WR) th(A)R tsu(D)W th(D)R ten(D)W th(D)W th(A)W
tw(WL)
Figure Memory Parallel Interface Read Write Timing
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
Change Address Timing
1.75 1.50 1.25 0.75 0.50 0.25
Change Load Capacitance
Figure Address Timing Variation With Load Capacitance
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
READY TIMING EXTERNALLY GENERATED WAIT STATES timing requirements over recommended ranges supply voltage operating free-air temperature
tsu(R-CO) th(CO-R) tsu(R)R th(R)R tv(R)W th(R)W Setup time, READY before CLKOUT1 rises Hold time, READY after CLKOUT1 rises Setup time, READY before falls Hold time, READY after falls Valid time, READY after falls Hold time, READY after falls UNIT
CLKOUT1 tsu(R-CO) ADDRESS th(CO-R) READY tsu(R)R Wait State Generated th(R)R Internally Wait State Generated READY
Figure Ready Timing Externally Generated Wait States During External Read Cycle
CLKOUT1 th(R-CO) ADDRESS tsu(R-CO) READY tv(R)W th(R)W
Wait State Generated READY
Figure Ready Timing Externally Generated Wait States During External Write Cycle
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
RESET, INTERRUPT, timing requirements over recommended ranges supply voltage operating free-air temperature 0.5tc(CO)]
PARAMETER tsu(IN) th(IN) tw(INL)s tw(INH)s Setup time, INT1 INT4, NMI, before CLKOUT1 Hold time, INT1 INT4, NMI, after CLKOUT1 Pulse duration, INT1 INT4, low, synchronous 4H+15 6H+15 4H+15 H+15 UNIT
Pulse duration, INT1 INT4, high, synchronous tw(INL)a Pulse duration, INT1 INT4, low, asynchronous tw(INH)a Pulse duration, INT1 INT4, high, asynchronous tsu(R) tw(RSL) td(EX) tw(BI)s tw(BI)a tsu(BI) Setup time, before X2/CLKIN Pulse duration, Delay time, high reset vector fetch Pulse duration, low, synchronous Pulse duration, low, asynchronous Setup time, before CLKOUT1
th(BI) Hold time, after CLKOUT1 These parameters must synchronous timings. Both reset interrupts operate asynchronously. pulse durations require extra half-cycle assure internal synchronization. IDLE2, these timings. Values derived from characterization data tested. Values specified design tested. X2/CLKIN tsu(R) CLKOUT1 tw(BI)s INT4 INT1 tsu(IN) tw(INH)s th(BI) tW(RSL) tsu(BI) tsu(IN) td(EX)
tsu(IN) tw(INL)s
th(IN)
Figure Reset, Interrupt, Timings
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK), EXTERNAL FLAG (XF), TOUT switching characteristics over recommended operating conditions 0.5tc(CO)]
PARAMETER tsu(A)IAQ th(A)IAQ tw(IAQL) td(TOUT) tsu(A)IACK th(A)IACK tw(IACKL) tw(TOUT) Setup time, address valid before Hold time, address valid after Pulse duration, Delay time, CLKOUT1 falling TOUT Setup time, address valid before IACK Hold time, address valid after IACK high Pulse duration, IACK Pulse duration, TOUT UNIT
td(XF) Delay time, valid after CLKOUT1 goes during instruction acquisition. goes only first cycle read when wait states used. falling edge should used latch valid address. AVIS PMST register must zero address valid when instruction being addressed resides on-chip memory. Valid only external address reflects current instruction activity (that code executing chip with external cycles AVIS code executing off-chip). IACK goes during fetch first word interrupt vector. goes only first cycle read when wait states used. Address pins decoded falling edge identify interrupt being acknowledged. AVIS PMST register must zero address valid when vectors reside on-chip memory. th(A)IAQ ADDRESS tsu(A)IAQ tw(IAQL) tsu(A)IACK IACK tw(IACKL) STRB CLKOUT1 td(TOUT) td(XF) th(A)IACK
td(TOUT)
TOUT tw(TOUT) NOTE: IACK affected wait states.
Figure IAQ, IACK, Timings Example With External Wait States
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
EXTERNAL switching characteristics over recommended operating conditions 0.5tc(CO)] (see Note
PARAMETER td(H-HA) td(HH-HA) tdis(M-HA) ten(HA-M) td(B-I) td(BH-I) td(D)XR th(D)XR ten(I-D) tdis(W) Delay time, HOLD HOLDA Delay time, HOLD high before HOLDA high Disable time, address high-impedance state before HOLDA Enable time, HOLDA high address driven Delay time, Delay time, high high Delay time, read data valid after XSTRB Hold time, read data after XSTRB high Enable time, read data Disable time, XR/W data high-impedance state UNIT
tdis(I-D) Disable time, high data high-impedance state ten(D)RW Enable time, data from XR/W going high Values derived from characterization data tested. HOLD acknowledged until current external access request complete. This parameter includes memory control lines. This parameter refers delay between time condition (IAQ XR/W satisfied time that SMJ320C50A data lines become valid. NOTE preceding name refers external drive signal.
timing requirements over recommended ranges supply voltage operating free-air temperature
td(HA-B) td(I-XS) tsu(XA) tsu(XD)W th(WD)W th(XA)W tw(XSL) tw(XSH) Delay time, HOLDA low# Delay time, XSTRB low# Setup time, Xaddress valid before XSTRB Setup time, Xdata valid before XSTRB Hold time, Xdata hold after XSTRB Hold time, write Xaddress hold after XSTRB Pulse duration, XSTRB Pulse duration, XSTRB high UNIT
tsu(XS)RW Setup time, valid before XSTRB th(XA)R Hold time, read Xaddress after XSTRB high XBR, XR/W, XSTRB lines should pulled with 10-k resistor assure that they inactive (high) state during transition period between SMJ320C50A driving them external circuit driving them. NOTE preceding name refers external drive signal.
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
EXTERNAL
HOLD td(H- HOLDA Address Bus/ Control Signals td(B- td(I- XSTRB tw(XSH) tw(XSL) tsu(XA) th(D)XR th(XA)R ten(I- XADDRESS td(D)XR tsu(XA) th(XA)W tdis(I- DATA(RD) ten(I-D) th(WD)W tsu(XD)W XDATA(WR) R/W, timings included timings referenced address bus/control signals. ten(D)RW tsu(XS)RW td(BH- tdis(M- ten(HA- td(HH-
td(HA-
ten(I-B)
tdis(W)
Figure External Timing
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
SERIAL-PORT RECEIVE timing requirements over recommended ranges supply voltage operating free-air temperature 0.5tc(CO)]
PARAMETER tc(SCK) tf(SCK) tr(SCK) tw(SCK) tsu(FS) th(FS) Cycle time, serial-port clock Fall time, serial-port clock Rise time, serial-port clock Pulse duration, serial-port clock low/high Setup time, before CLKR falling edge Hold time, after CLKR falling edge 2.1H 5.2H UNIT
tsu(DR) Setup time, before CLKR falling edge th(DR) Hold time, after CLKR falling edge serial-port design fully static therefore operate with tc(SCK) approaching characterized approaching input frequency tested much higher frequency minimize test time. Values derived from characterization data tested. tc(SCK) tw(SCK) CLKR th(FS) tw(SCK) tsu(FS) tsu(DR) th(DR) (see Note (see Note tr(SCK) tf(SCK)
NOTE Depending whether information sent 8-bit 16-bit packet.
Figure Serial-Port Receive Timing
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
SERIAL-PORT TRANSMIT, EXTERNAL CLOCKS EXTERNAL FRAMES switching characteristics over recommended operating conditions (see Note
PARAMETER td(DX) tdis(DX) th(DX) Delay time, valid after CLKX rising Disable time, valid after CLKX rising Hold time, valid after CLKX rising UNIT
timing requirements over recommended ranges supply voltage operating free-air temperature 0.5tc(CO)] (see Note
tc(SCK) tf(SCK) tr(SCK) tw(SCK) td(FS) th(FS) Cycle time, serial-port clock Fall time, serial-port clock Rise time, serial-port clock Pulse duration, serial-port clock low/high Delay time, after CLKX rising edge 2.1H 5.2H UNIT
Hold time, after CLKX falling edge th(FS)H Hold time, after CLKX rising edge Values derived from characterization data tested. serial-port design fully static therefore operate with tc(SCK) approaching characterized approaching input frequency tested much higher frequency minimize test time. pulse does meet this specification, first serial data will driven until falling edge FSX. After falling edge FSX, data will shifted pin. transmit-buffer-empty interrupt will generated when th(FS) th(FS)H specification met. NOTE Internal clock with external vice versa also allowable. However, timings CLKX always defined depending source FSX, CLKX timings always dependent upon source CLKX. Specifically, relationship CLKX independent source CLKX. tc(SCK) CLKX td(FS) th(FS) td(DX) th(DX) (see Note (see Note th(FS)H tw(SCK) tdis(DX) tr(SCK) tw(SCK) tf(SCK)
NOTE Depending whether information sent 8-bit 16-bit packet.
Figure Serial-Port Transmit Timing External Clocks External Frames
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
SERIAL-PORT TRANSMIT, INTERNAL CLOCKS INTERNAL FRAMES switching characteristics over recommended operating conditions 0.5tc(CO)] (see Note
PARAMETER td(FS) td(DX) tdis(DX) tc(SCK) tf(SCK) tr(SCK) Delay time, CLKX rising Delay time, CLKX rising Disable time, CLKX rising Cycle time, serial-port clock Fall time, serial-port clock Rise time, serial-port clock UNIT
tw(SCK) Pulse duration, serial-port clock low/high th(DX) Hold time, valid after CLKX rising Values derived from characterization tested. NOTE Internal clock with external vice versa also allowable. However, timings CLKX always defined depending source FSX, CLKX timings always dependent upon source CLKX. Specifically, relationship CLKX independent source CLKX. tc(SCK) tw(SCK) CLKX td(FS) td(FS) td(DX) tdis(DX) th(DX) (see Note (see Note tw(SCK) tr(SCK) tf(SCK)
NOTE Depending whether information sent 8-bit 16-bit packet.
Figure Serial-Port Transmit Timing Internal Clocks Internal Frames
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SERIAL-PORT RECEIVE MODE timing requirements over recommended ranges supply voltage operating free-air temperature 0.5tc(CO)]
tc(SCK) tf(SCK) tr(SCK) tw(SCK) tsu(LB) th(LB) tsu(SB) th(SB) Cycle time, serial-port clock Fall time, serial-port clock Rise time, serial-port clock Pulse duration, serial-port clock low/high Setup time, TDAT/TADD before TCLK rising Hold time, TDAT/TADD after TCLK rising Setup time, TDAT/TADD before TCLK Hold time, TDAT/TADD after TCLK Setup time, TRFM before TCLK rising Hold time, TRFM after TCLK rising 2.1H 5.2H UNIT
tsu(FS) th(FS) serial-port design fully static therefore operate with tc(SCK) approaching characterized approaching input frequency tested much higher frequency minimize test time. Values derived from characterization data tested. These parameters apply only first bits serial string. TFRM timing waveforms shown Figure external TFRM. TFRM also configured internal. TFRM internal case illustrated transmit timing diagram Figure tf(SCK) TCLK tc(SCK) TDAT th(SB) tsu(FS) TADD th(FS) TFRM th(SB) tsu(SB) tsu(LB) th(LB) tr(SCK) tw(SCK) tw(SCK)
Figure Serial-Port Receive Timing Mode
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
SERIAL-PORT TRANSMIT MODE switching characteristics over recommended operating conditions 0.5tc(CO)]
PARAMETER th(AD) td(FS) Hold time, TDAT/TADD valid after TCLK rising Delay time, TFRM valid after TCLK rising 3H+10 UNIT
td(AD) Delay time, TCLK valid TDAT/TADD TFRM timing waveforms shown Figure internal TFRM. TFRM also configured external, TFRM external case illustrated receive timing diagram Figure
timing requirements over recommended ranges supply voltage operating free-air temperature 0.5tc(CO)]
tc(SCK) tf(SCK) Cycle time, serial-port clock Fall time, serial-port clock 5.2H UNIT
tr(SCK) Rise time, serial-port clock tw(SCK) Pulse duration, serial-port clock low/high 2.1H When generated internally. serial-port design fully static therefore operate with tc(SCK) approaching characterized approaching input frequency tested much higher frequency minimize test time. Values derived from characterization data tested. tf(SCK) tr(SCK) TCLK tc(SCK) TDAT th(SB) TADD td(FS) td(FS) TFRM th(AD) td(AD) td(AD) tw(SCK)
tw(SCK)
Figure Serial-Port Transmit Timing Mode
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SMJ320C50A DIGITAL SIGNAL PROCESSOR
MECHANICAL DATA SMJ320C50 132-lead non-conductive ceramic (HFG suffix)
51,44 (2.025) (0.960) (0.945) (0.806) (0.795) 0,13 (.005)
Indicator
(2.015) (1.990)
30,73 (1.210)
Detail
0,64 (0.025)
0,635 (0.025)
(0.070) (0.050)
(0.016) (0.009) (0.013) (0.006) Detail
(0.010) (0.005) (0.091) (0.077)
(0.014) (0.002) Braze Pads)
LINEAR DIMENSIONS MILLIMETERS PARENTHETICALLY INCHES
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Detail 1,02 (0.040) 0,76 (0.030) Thermal Resistance Characteristics PARAMETER °C/W 38.4 Detail
SMJ320C50A DIGITAL SIGNAL PROCESSOR
MECHANICAL DATA
GFA/S-CPGA1-P141.080 (27,43) 1.040 (26,42)
SMJ320C31 CERAMIC GRID ARRAY, CAVITY
0.900 (22,86)
0.025 (0,64) 0.006 (0,15) 0.034 (0,86)
0.145 (3,68) 0.110 (2,79)
0.048 (1,22) Places 0.0215 (0,55) 0.0160 (0,41)
0.140 (3,56) 0.120 (3,05) 0.050 (1,27) 4040133/A-10/93
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Thermal Resistance Characteristics PARAMETER °C/W 39.0
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