2485.7 Numerically Controlled Oscillator/Modulator Intersil

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2485.7 Numerically Controlled Oscillator/Modulator Intersil

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HSP45116
2485.7
Numerically Controlled Oscillator/Modulator
Intersil HSP45116 combines high performance quadrature Numerically Controlled Oscillator (NCO) high speed 16-bit Complex Multiplier/Accumulator (CMAC) single This combination functions allows complex vector multiplied internally generated (cos, sin) vector quadrature modulation demodulation. shown Block Diagram, HSP45116 divided into three main sections. Phase/Frequency Control Section (PFCS) Sine/Cosine Section together form complex NCO. CMAC multiplies output Sine/ Cosine Section with external complex vector. inputs Phase/Frequency Control Section consist microprocessor interface individual control lines. phase resolution PFCS bits, which results frequency resolution better than 0.008Hz 33MHz. output PFCS argument sine cosine. spurious free dynamic range complex sinusoid greater than 90dBc. output vector from Sine/Cosine Section inputs Complex Multiplier/Accumulator. CMAC multiplies this (cos, sin) vector external complex vector accumulate result. resulting complex vectors available through 20-bit output ports which maintain 90dB spectral purity. This result accumulated internally implement accumulate dump filter. quadrature down converter implemented loading center frequency into Phase/Frequency Control Section. signal down converted Vector Input CMAC, which multiplies data rotating vector from Sine/Cosine Section. resulting complex output down converted signal.
Features
CMAC Chip 15MHz, 25.6MHz, 33MHz Versions 32-Bit Frequency Control 16-Bit Phase Modulation 16-Bit CMAC 0.008Hz Tuning Resolution 33MHz Spurious Frequency Components -90dBc Fully Static CMOS
Applications
Frequency Synthesis Modulation PSK, FSK, Demodulation, Phase Shifter Polar Cartesian Conversions
Ordering Information
PART NUMBER HSP45116VC-15 HSP45116VC-25 HSP45116GC-15 HSP45116GC-25 HSP45116GC-33 HSP45116GI-15 HSP45116GI-25 HSP45116GI-33 HSP45116GM-15/883 HSP45116GM-25/883 HSP45116AVC-52 TEMP. RANGE (oC) PACKAGE PKG.
MQFP Q160.28x28 MQFP Q160.28x28 CPGA G145.A CPGA G145.A CPGA G145.A CPGA G145.A CPGA G145.A CPGA G145.A CPGA G145.A CPGA G145.A MQFP Q160.28x28
This part data sheet under HSP45116A, AnswerFAX document 4156.
Block Diagram
VECTOR INPUT SINE/ COSINE ARGUMENT
MICROPROCESSOR INTERFACE INDIVIDUAL CONTROL SIGNALS
PHASE/ FREQUENCY CONTROL SECTION
SINE/ COSINE SECTION CMAC
VECTOR OUTPUT
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
HSP45116 Pinouts
VIEW
IMIN IMIN IMIN IMIN IMIN IMIN RBYTILD IMIN IMIN IMIN INDEX IMIN IMIN IMIN IMIN IMIN IMIN IMIN IMIN IMIN PACO
IMIN
ENPH ENOF TICO
PEAK
LOAD ENCF MODPI /2PI OUTMUX
OEREXT
BINFMT
OUTMUX
OEIEXT
PACI
PMSEL CLROFR ENTIREG
ENPHAC
HSP45116 Pinouts
(Continued) BOTTOM VIEW
PACO IMIN IMIN IMIN IMIN IMIN IMIN IMIN IMIN IMIN IMIN IMIN IMIN INDEX IMIN IMIN IMIN IMIN RBYTILD IMIN IMIN
IMIN
ENPH ENOF TICO
OEREXT
OUTMUX ENPHAC MODPI /2PI ENCF LOAD
PEAK
OEIEXT
OUTMUX
BINFMT
ENTIREG CLROFR PMSEL
PACI
HSP45116 Pinouts
(Continued) 160LEAD MQFP VIEW
IMIN1 IMIN2 IMIN3 IMIN4 IMIN5 IMIN6 IMIN7 IMIN8 IMIN9 IMIN10 IMIN11 IMIN12 IMIN13 IMIN14 IMIN15 IMIN16 IMIN17 IMIN18 IO19 IO18 IO17 IO16 IO15 IO14 IO13 IO12 IO11 IO10
IMIN0 RIN18 RIN17 RIN16 RIN15 RIN14 RIN13 RIN12 RIN11 RIN10 RIN9 RIN8 RIN7 RIN6 RIN5 RIN4 RIN3 RIN2 RIN1 RIN0 ENPHREG ENOFREG PEAK RBYTILD BINFMT TICO MOD1 MOD0 PACI LOAD PMSEL
RO19 RO18 RO17 RO16 RO15 RO14 RO13 RO12 RO11 RO10 DET1 DET0
CLROFR ENCFREG ENPHAC ENTIREG MODPI/2PI OUTMUX1 OUTMUX0 OEREXT OEIEXT PACO
HSP45116 Description
NAME C0-15 AD0-1 ENPHREG ENOFREG ENCFREG ENPHAC ENTIREG NUMBER A15, J15, A14, H15, P15, N8-11, P8-13, Q9-14 TYPE Power supply input. Power supply ground input. Control input loading phase frequency data into PFCS. MSB. Address pins selecting destination C0-15 data. Chip Select (active low). Write Enable. Data clocked into register selected AD0-1 rising edge when line low. Clock. registers, except control registers clocked with clocked (when enabled) rising edge CLK. Phase Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENPHREG enables clocking data into phase register. Frequency Offset Register Enable (active Low). Registered chip CLK. When active, after being clocked onto chip, ENOFREG enables clocking data into frequency offset register. Center Frequency Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENCFREG enables clocking data into center frequency register. Phase Accumulator Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENPHAC enables clocking phase accumulator register. Time Interval Control Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENTIREG enables clocking data into time accumulator register. Real Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered chip CLK. When active, after being clocked onto chip, enables clocking data into real imaginary input data register. Modulo Select. When low, Sine Cosine ROMs addressed modulo (360 degrees). When high, most significant address held that ROMs addressed modulo (180 degrees). This input registered chip clock. Frequency Offset Register Output Zero (active low). Registered chip CLK. When active, after being clocked onto chip, CLROFR zeros data path from frequency offset register frequency adder. data still clocked into frequency offset register; CLROFR does affect contents register. Phase Accumulator Load Control (active low). Registered chip CLK. Zeroes feedback path phase accumulator without clearing phase accumulator register. External Modulation Control Bits. When selected with PMSEL line, these bits 180, degree offset current phase phase accumulator. lower bits phase control path zero. These bits loaded into phase register when ENPHREG low. PMSEL Phase Modulation Select Line. This line determines source data clocked into phase register. When high, phase control register selected. When low, external modulation pins (MOD0-1) selected most significant bits least significant bits least significant bits zero. This control registered CLK. Bypass, Timer Load. Active low, registered CLK. This input bypasses sine/ cosine that 16-bit phase adder output lower bits phase accumulator directly CMAC's sine cosine inputs, respectively. also enables loading timer accumulator register zeroing feedback accumulator. Phase Accumulator Carry Input (active low). this causes phase accumulator increment one, addition values phase accumulator register frequency adder. DESCRIPTION
MODPI/2PI
CLROFR
LOAD MOD0-1
RBYTILD
PACI
HSP45116 Description
NAME PACO (Continued) TYPE DESCRIPTION Phase Accumulator Carry Output. Active registered CLK. this output indicates that phase accumulator overflowed, i.e., sine/cosine cycle been reached. Time Interval Accumulator Carry Output. Active low, registered CLK. This output goes when carry generated time interval accumulator. This function provided time control events such synchronizing register clocking data timing. Real Input Data Bus. This external real component into complex multiplier. clocked into real input data register when asserted; two's complement.
NUMBER
TICO
RIN0-18
E13, F1-3, J1-3, A2-7, B2-7, C3-8,
IMIN0-18
Imaginary Input Data Bus. This external imaginary component into complex multiplier. clocked into real input data register when asserted; two's complement. Shift Control Inputs. These lines control input shifters inputs complex multiplier. shift controls common shifters both busses. Accumulate/Dump Control. This input controls complex accumulators their holding registers. When high, accumulators accumulate holding registers disabled. When low, feedback accumulators zeroed cause accumulators load. holding registers enabled clock results accumulation. This input registered CLK.
SH0-1
BINFMT
This input used convert two's complement output offset binary (unsigned) applications using converters. When low, bits RO19 IO19 inverted from internal two's complement representation. This input registered CLK. This input enables peak detect feature block floating point detector. When high, maximum growth output holding registers encoded output DET0-1 pins. When PEAK input asserted, block floating point detector output will track maximum growth holding registers, including data holding registers time that PEAK activated. These inputs select data output RO0-19 IO0-19. Real Output Data Bus. These Three-state outputs controlled OEREXT. OUTMUX0-1 select data output bus.
PEAK
OUTMUX0-1 RO0-19
N12, C15, D14, D15, E14, E15, F13-15, G13-15, H13, H14, J13, J14, K13-15, L15, A10-13, B8-15, C914, D13, N15,
IO0-19 DET0-1
Imaginary Output Data Bus. These Three-state outputs controlled OEIEXT. OUTMUX0-1 select data output bus. These output pins indicate number bits growth accumulators. While PEAK low, these pins indicate peak growth. detector examines bits 15-18, real imaginary accumulator holding registers bits 30-33 real imaginary CMAC holding registers. bits indicate largest growth four registers. Three-state control bits RO0-15. Outputs enabled when line low. Three-state control bits RO16-19. Outputs enabled when line low. Three-state control bits IO0-15. Outputs enabled when line low. Three-state control bits IO16-19. Outputs enabled when line low.
OEREXT OEIEXT
HSP45116
IMIN(18:0) RIN(18:0) MOD(1:0) ENCODE PHASE INPUT REGISTER R.PMSEL R.ENPHREG PHASE REGISTER
IMIN(18:0) RIN(18:0)
C(15:0) PHEN
INPUT REGISTER
MSEN
INPUT REGISTER
CENTER FREQUENCY REGISTER OFFSET FREQUENCY R.ENCFREG REGISTER
FREQUENCY ADDER SIN/COS ARGUMENT
PHASE
LSEN AD(1:0) DECODER R.ENOFREG
SINE/COSINE GENERATOR
R.CLROFR R.PMSEL R.ENPHREG R.ENCFREG R.ENOFREG R.CLROFR R.LOAD R.ENPHAC R.MODPI/2PI R.RBYTILD R.ENTIREG PHASE ACCUMULATOR PACO
PMSEL ENPHREG ENCFREG ENOFREG CLROFR LOAD ENPHAC MODPI/2PI RBYTILD ENTIREG
PHASE ADDER
PHASE ACCUMULATOR ADDER PHASE ACCUMULATOR REGISTER MSBs
R.ENPHAC R.LOAD PACI R.MODPI/2PI SH(1:0) PEAK BINFMT R.SH(1:0) R.ENI R.ACC R.PEAK R.BINFMT CARRY R.RBYTILD R.SH(1:0) R.ENI R.ACC R.PEAK R.BINFMT PACI LSBs
Functional Block Diagram
TIME ACCUMULATOR REGISTER TICO
OEIEXT OEREXT OUTMUX(1:0)
ADDER
R.ENTIREG TIME ACCUMULATOR
TIME INCREMENT
TICO PACO
HSP45116
IMIN(18:0) RIN(18:0)
R.ENI
RIN0-18 SHIFTER
IMIN0-18 SHIFTER
R.SH(1:0)
PHASE
COMPLEX MULTIPLIER
ADDER R1.ACC
ADDER
R.RBYTILD
COMPLEX ACCUMULATOR
R2.ACC
ROUND
ADDER
ADDER
ROUND CMAC ACCUMULATOR
R1.ACC
R.PEAK
R.ACC
(Continued)
R.SH(1:0) R.ENI R.PEAK R.BINFMT OEIEXT OEREXT
OUTMUX(1:0) R.BINFMT
Functional Block Diagram
R.ENI
OUTMUX(1:0)
RO(19-16) RO(15:0)
DET(1:0)
IO(19-16) IO(15:0)
R.SH(1:0)
OUTMUX(1:0) Table
GROWTH DETECT
OUTMUX(1:0) Table
HSP45116 Functional Description
Numerically Controlled Oscillator/Modulator (NCOM) produces digital complex sinusoid waveform whose amplitude, phase frequency controlled input command words. When used Numerically Controlled Oscillator (NCO), generates 16-bit sine cosine vectors maximum sample rate 33MHz. NCOM preprogrammed produce constant (CW) sine cosine output Direct Digital Synthesis (DDS) applications. Alternatively, phase frequency inputs updated real time produce PSK, FSK, modulated waveform. Complex Multiplier/ Accumulator (CMAC) used multiply this waveform input signal signals. stepping phase input, output becomes twiddle factor; when data input Vector Inputs (see Block Diagram), NCOM calculates butterfly. shown Block Diagram, NCOM consists three parts: Phase Frequency Control Section (PFCS), Sine/Cosine Generator, CMAC. PFCS stores phase frequency inputs uses them calculate phase angle rotating complex vector. Sine/Cosine Generator performs lookup this phase outputs appropriate values sine cosine. sine cosine form inputs CMAC, which multiplies them input vector form modulated output. register. overflow used output indicate timing accumulation overflows. Time Accumulator, overflow generates TICO, Time Accumulator carry (which only output Time Accumulator). Phase Accumulator, overflow inverted generate Phase Accumulator Carry Out, PACO. output Phase Accumulator goes Phase Adder, which adds offset bits phase. This 32-bit number forms argument sine cosine, which passed Sine/Cosine Generator. Both accumulators loaded bits time over C0-15 bus. Data C0-15 loaded into three input registers when low. data Most Significant Input Register Least Significant Input Register forms 32-bit word that input Center Frequency Register, Offset Frequency Register Time Accumulator. These registers loaded enabling proper register enable signal; example, load Center Frequency Register, data loaded into Input Registers, ENCFREG zero; next rising edge will pass registered version ENCFREG, R.ENCFREG, clock enable Center Frequency Register; this register then gets loaded following rising edge CLK. contents Input Registers will continuously loaded into Center Frequency Register long R.ENCFREG low. Phase Register loaded similar manner. Assuming PMSEL high, contents Phase Input Register loaded into Phase Register every rising clock edge that R.ENPHREG low. PMSEL low, MOD0-1 supply most significant bits into Phase Register (MOD1 MSB) least significant bits loaded with MOD0-1 used generate Quad Phase Shift Keying (QPSK) signal (Table
TABLE AD0-1 DECODING FUNCTION Load least significant bits frequency input. Load most significant bits frequency input. Load phase register. Reserved. Operation.
Phase Frequency Control Section
phase frequency internally generated sine cosine controlled PFCS (Block Diagram). PFCS generates 32-bit word that represents current phase sine cosine waves being generated; Sine/ Cosine Argument. Stepping this phase angle from through full scale (232 corresponds phase angle sinusoid starting advancing around unit circle counterclockwise. PFCS automatically increments phase preprogrammed amount every rising edge external clock. value phase step (which Center Offset Frequency Registers)
Signal Frequency Phase Step Clock Frequency
PFCS divided into sections: Phase Accumulator uses data C0-15 compute phase angle that input Sine/Cosine Section (Sine/Cosine Argument); Time Accumulator supplies pulse mark passage preprogrammed period time. Phase Accumulator Time Accumulator work same principle: 32-bit word added contents 32-bit accumulator register every clock cycle; when causes adder overflow, accumulation continues with bits adder going into accumulator
Phase Accumulator consists registers adders that compute value current phase every clock. three inputs: Center Frequency, which corresponds carrier frequency signal; Offset Frequency, which deviation from Center Frequency; Phase, which 16-bit number that added current phase
HSP45116
modulation schemes. These three values used Phase Accumulator Phase Adder form phase internally generated sine cosine. values Center Offset Frequency Registers corresponds desired phase increment (modulo 232) from clock next. example, loading both registers with zero will cause Phase Accumulator zero current output; output PFCS will remain current value; i.e., output NCOM will signal. hexadecimal 00000001 loaded into Center Frequency Control Register, output PFCS will increment after every clock. This will step through every location Sine/Cosine Generator, that output will lowest frequency above that generated NCOM, i.e., clock frequency divided 232. input Center Frequency Control Register 80000000, PFCS will step through Generator with half maximum step size, that frequency output waveform will half sample rate. operation Offset Frequency Control Register identical that Center Frequency Control Register; having separate registers allows user generate signal loading carrier frequency Center Frequency Control Register updating Offset Frequency Control Register with value frequency offset difference between carrier frequency frequency output signal. logic CLROFR disables output Offset Frequency Register without clearing contents register.
TABLE MOD0-1 DECODE MOD1 MOD0 PHASE SHIFT (DEGREES)
increments loaded into Input Registers latched into Time Accumulator Register rising edges while ENTIREG low. output Time Accumulator accumulator carry out, TICO. TICO used timer enable periodic sampling output NCOM. number programmed into this register equals period/desired time interval. TICO disabled phase initialized zeroing feedback path accumulator with RBYTILD.
Sine/Cosine Section
Sine/Cosine Section (Figure converts output PFCS into appropriate values sine cosine. takes most significant bits PFCS output passes them through look table form 16-bit sine cosine inputs CMAC.
SIN/COS ARGUMENT SINE/COSINE GENERATOR
R.RBYTILD
FIGURE SINE/COSINE SECTION
Initializing Phase Accumulator Register done putting LOAD line. This zeroes feedback path accumulator, that register loaded with current value phase increment summer next clock. final phase value going Generator adjusted using MODPI/2PI force range phase 180o (modulo 360o (modulo Modulo mode used modulation, demodulation, direct digital synthesis, etc. Modulo used calculate FFTs. This explained greater detail Applications Section. Phase Register adds offset output Phase Accumulator. Since Phase Register only bits, added bits Phase Accumulator. Time Accumulator consists register which incremented every clock. amount which
20-bit word maps into radians that angular resolution 2/220. address zero corresponds radians address FFFFF corresponds (2/220) radians. outputs Generator Section complement sine cosine values. sine cosine outputs range from hexadecimal 8001, which represents negative full scale, 7FFF, which represents positive full scale. Note that normal range two's complement numbers 8000 7FFF; output range SIN/COS generator scaled that symmetric about sine cosine values computed reduce amount needed. magnitude error computed value complex vector less than -90.2dB. error sine cosine alone approximately better. RBYTILD low, output PFCS goes directly inputs CMAC. real imaginary inputs CMAC programmed 7FFF respectively, then output PFCS will appear output bits through NCOM with output multiplexers bring most significant bits CMAC output (OUTMUX 00). most significant bits PFCS appears IOUT0-15 least significant bits come ROUT0-15.
HSP45116
Complex Multiplier/Accumulator
CMAC (Figure performs types functions: complex multiplication/accumulation modulation demodulation digital signals, operations necessary implement butterfly. Modulation demodulation implemented using complex multiplier associated accumulator; rest circuitry this section, i.e., complex accumulator, input shifters growth detect logic used along with complex multiplier/accumulator FFTs. complex multiplier performs complex vector multiplication output Sine/Cosine Section vector represented real imaginary inputs IIN. vectors combined following manner: ROUT IOUT latched into input registers passed through shift stages. Clocking input registers enabled with ENI. amount shift latched data programmed with SH0-1 (Table output shifters sent CMAC auxiliary accumulators.
TABLE INPUT SHIFT SELECTION SELECTED BITS RIN0-15, IMIN0-15 RIN1-16, IMIN1-16 RIN2-17, IMIN2-17 RIN3-18, IMIN3-18
33-bit real imaginary outputs Complex Multiplier latched Multiplier Registers then through Accumulator Section CMAC. line high, feedback accumulators enabled; zeroes feedback path, that next real imaginary data complex multiplier stored CMAC Output Registers. data CMAC Output Registers goes Multiplexer, output which determined OUTMUX0-1 lines (Table BINFMT controls whether output Multiplexer presented two's complement unsigned format; BINFMT inverts ROUT19 IOUT19 unsigned output, while BINFMT selects two's complement.
TABLE OUTPUT MULTIPLEXER SELECTION
RO16-19
RO0-15
IO16-19
IO0-15
Real CMAC Real CMAC Imag CMAC Imag CMAC 31-34 15-30 31-34 15-30 Real CMAC Real Imag CMAC Imag 31-34 CMAC 0-14 31-34 CMAC 0-14 Real 16-19 Reserved Real 0-15 Reserved Imag 16-19 Reserved Imag 0-15 Reserved
Complex Accumulator duplicates accumulator CMAC. input comes from data shifters, 20-bit complex output goes Multiplexer. controls whether accumulator enabled not. OUTMUX0-1 determines whether accumulator output appears ROUT IOUT.
HSP45116
RIN0-18 R.ENI R.SH0-1 SHIFTER SHIFTER IMIN0-18
R1.ACC COMPLEX MULTIPLIER COMPLEX ACCUMULATOR ADDER ADDER
R2.ACC
ADDER
ADDER
CMAC ACCUMULATOR
R1.ACC
R.PEAK
OUTMUX0-1
GROWTH DETECT
OUTMUX0-1
R.BINFMT OEREXT
R.BINFMT OEIEXT
IO16-19 IO0-15
DET0-1
RO16-19 RO0-15
SH0-1 PEAK BINFMT
R.ENI R.SH0-1 R.PEAK R.BINFMT
R1.ACC R2.ACC
FIGURE COMPLEX MULTIPLIER/ACCUMULATOR; REGISTERS CLOCKED
HSP45116
Growth Detect circuitry outputs value that signifies amount growth data CMAC Complex Accumulator. output, DET0-1, encoded shown Table PEAK low, highest value DET0-1 latched Growth Detect Output Register. relative weighting bits inputs outputs CMAC shown Figure Note that binary point sine, cosine, right most significant bit, while binary point right fifth most significant bit. These CMAC external input output busses aligned with each other facilitate cascading NCOMs applications.
SIN/COS INPUT 2-10 2-11 2-12 2-13 2-14 2-15 TABLE GROWTH ENCODING NUMBER BITS GROWTH ABOVE
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR INPUT (RIN, IIN) 2-10 2-11 2-12 2-13 2-14 2-15
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, OUTMUX 2-10 2-11 2-12 2-13 2-14 2-15
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, OUTMUX 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30
COMPLEX ACCUMULATOR OUTPUT (RO, OUTMUX 2-10 2-11 2-12 2-13 2-14 2-15
Radix Point FIGURE WEIGHTING
HSP45116 Applications
NCOM used Amplitude, Phase Frequency modulation, well variations combinations these techniques, such QAM. most effective applications requiring multiplication rotating complex sinusoid external vector. These include modulators digital receivers. NCOM implements modulation single chip, element demodulation, where performs complex down conversion. combined with Intersil HSP43220 Decimating Digital Filter form front digital receiver.
IMIN CENTER FREQUENCY NCOM SINE/COSINE GENERATOR PFCS CMAC
XMTR
Modulation/Demodulation
Figure shows block diagram modulator. this example, phase increment carrier frequency loaded into center frequency register, modulating input clocked into real input CMAC, with imaginary input modulated output obtained real output CMAC. With sixteen bit, two's complement signal input, output will 16-bit real number, ROUT0-15 (with OUTMUX 00).
SIGNAL INPUT CENTER FREQUENCY
FIGURE QUADRATURE AMPLITUDE MODULATION (QAM)
SINE/COSINE GENERATOR
PFCS
CMAC
NCOM also works with HSP43220 Decimating Digital Filter implement down conversion pass filtering digital receiver (Figure NCOM performs complex down conversion wideband input signal multiplying input vector internally generated complex sinusoid. resulting signal components twice center frequency HSP43220s, each real imaginary outputs HSP45116, perform pass filtering decimation down converted data, resulting complex baseband signal.
HSP45116 NCOM
NCOM MODULATED OUTPUT XMTR
(wt)
HSP43220
FIGURE AMPLITUDE MODULATION
SAMPLED INPUT DATA
replacing real input with complex vector, similar setup generate signals (Figure this case, carrier frequency loaded into center frequency register before, modulating vector carries both amplitude phase information. Since input vector internally generated sine cosine waves both bits, number states only limited characteristics transmission medium analog electronics transmitter receiver. phase amplitude resolution Sine/Cosine section (16-bit output), delivers spectral purity greater than 90dBc. This means that unwanted spectral components phase uncertainty (phase noise) will greater than 90dB below desired output (dBc, decibels below carrier). With 32-bit phase accumulator Phase/Frequency Control Section, frequency tuning resolution equals clock frequency divided 232. example, 25MHz clock gives tuning resolution 0.006Hz.
(wt)
INPUT
NCOM OUTPUT
OUTPUT
10MHz
20MHz
FIGURE CHANNELIZED RECEIVER CHIP
HSP45116
Absolute Maximum Ratings
Supply Voltage +8.0V Input, Output Voltage Applied .GND -0.5V +0.5V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) MQFP Package 22.0 Package. 23.1 Maximum Junction Temperature MQFP Package .150oC Package. .175oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) .300oC (MQFP Lead Tips Only)
Operating Conditions
Operating Voltage Range. +4.75V +5.25V Operating Temperature Range 70oC
Characteristics
Component Count 103,000 Transistors
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Logical Input Voltage Logical Zero Input Voltage High Level Clock Input Level Clock Input Output HIGH Voltage Output Voltage Input Leakage Current Leakage Current Standby Power Supply Current Operating Power Supply Current SYMBOL VIHC VILC ICCSB ICCOP 5.25V 4.75V 5.25V 4.75V -400mA, 4.75V 2.0mA, 4.75V GND, 5.25V VOUT GND, 5.25V 5.25V, Note 15MHz, GND, 5.25V, Notes TEST CONDITIONS UNITS
Capacitance
25oC, Note SYMBOL TEST CONDITIONS FREQ 1MHz, Open, measurements referenced device ground UNITS
PARAMETER Input Capacitance Output Capacitance NOTES:
Power supply current proportional operating frequency. Typical rating ICCOP 10mA/MHz. tested, characterized initial design major process/design changes. Output load test load circuit with switch open 40pF.
HSP45116
Electrical Specifications
PARAMETER Period High High Setup Time; AD0-1, Going High Hold Time; AD0, AD1, from Going High Setup Time C0-15 from Going High Hold Time C0-15 from Going High Setup time High High Setup Time MOD0-1 Going High Hold Time MOD0-1 from Going High Setup Time PACI Going High Hold Time PACI from Going High Setup ENPHREG, ENCFREG, ENOFREG, ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD from Going High Hold Time ENPHREG, ENCFREG, ENOFREG, ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD from Going High Setup Time RIN0-18, IMIN0-18 Going High Hold Time RIN0-18, IMIN0-18 from Going High Output Delay RO0-19, IO0-19 Output Delay DET0-1 Output Delay PACO Output Delay TICO Output Enable Time OER, OEI, OEREXT, OEIEXT OUTMUX0-1 Output Delay Output Disable Time Output Rise, Fall Time NOTES: testing performed follows: Input levels (CLK Input) 4.0V input levels (all other inputs) 3.0V; timing reference levels (CLK) 2.0V; others 1.5V. Output load test load circuit with switch closed 40pF. Output transition measured 1.5V 1.5V. Controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. Applicable only when outputs being monitored ENCFREG, ENPHREG, ENTIREG active. 5.0V ±5%, 70oC (Note (15MHz) SYMBOL tAWS tAWH tCWS tCWH tMCS tMCH tPCS tPCH tECS NOTES (25.6MHz) (33MHz) UNITS
tECH
tDEO
HSP45116 Test Load Circuit
(NOTE)
SWITCH OPEN ICCSB ICCOP
1.5V
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
Waveforms
tMCS MOD0-1 tPCS PACI tECS CONTROL INPUTS RIN0-19 IIN0-19 ROUT0-19 IOUT0-19 tDEO DET0-1 PACO TICO tECH tPCH tMCH
FIGURE INPUT OUTPUT TIMING
HSP45116 Waveforms
(Continued)
tAWS tAWS AD0-1 tCWS C0-15
tAWH
tAWH
tCWH
FIGURE CONTROL TIMING
OEREXT OEIEXT
OUTMUX0-1 1.5V RO0-19 HIGH IMPEDANCE IO0-19 1.5V
RO0-19 IO0-19
HIGH IMPEDANCE
1.7V 1.3V
FIGURE OUTPUT ENABLE, DISABLE TIMING
FIGURE MULTIPLEXER TIMING
2.0V 0.8V
FIGURE OUTPUT RISE FALL TIMES
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2485.7 Numerically Controlled Oscillator/Modulator Intersil

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