2.5V 10/100-TX 5-Port Repeater/4+1 Uplink Port with Bridge Controller

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2.5V 10/100-TX 5-Port Repeater/4+1 Uplink Port with Bridge Controller

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AC206
2.5V 10/100-TX 5-Port Repeater/4+1 Uplink Port with Bridge Controller
GENERAL DESCRIPTION AC206 5-port 10/100Mbps integrated repeater with bridge controller. AC206 provides cost, integrated solution unmanaged repeater applications. AC206 Class Repeater that fully compliant with IEEE 802.3 standards. device provides five 10/100 Mbps copper media ports. addition, port supports 10/100 interface uplink functionality. AC206 also provides selectable MII/7-wire interface. MII/ 7-wire interface connected Switch managed repeater stack hybrid Switch/Repeater Applications. AC206 provides 10/100 Mbps auto-negotiation parallel detection ports. option configure technology each port EEPROM interface available. AC206 provides internal repeater state machines, operates 10Mbps other 100Mbps. Once technology set, device automatically connects each port appropriate repeater segment. AC206 provides backplanes expansion. operates 10Mbps, other 100Mbps. ports connected into repeater using backplane buses. AC206 integrates repeater controller switch engine technologies with "store forward" forwarding mechanisms. FEATURES power (<1A total current consumption when used with 1.25;1 transformer) five port 10/100 Mbps integrated repeater controller with built-in bridge function. MDC/MDIO control/status. Five integrated 10/100 Mbps IEEE 802.3u compliant transceivers. Fully integrated adaptive equalizer provides phase/ amplitude compensation various cable lengths 30dB 100MHz. Patent-pending restoration technique reduces offset/baseline wander. IEEE 802.3u-compliant auto-negotiation. Unique scrambler seed port better EMI. Supports Media Independent Interface (MII) 7-wire interface connect MAC. Cascadable backplanes compatible with AC108RM, AC108RU AC208. Non-blocking 10/100M bridge with controller switching engine. segment bridge fixed 100Mbps while other configured 100Mbps. Bridge functions include: Embedded bytes memory address table packet buffer. Local address filtering. hashing scheme. Short routing decision time. Forwarding schemes: store-and-forward. Address table entries. Programmable display activity, link, speed, partition, utilization, collision rate. Advanced power management includes: Each port turned independently. Standby mode, which reduces power when port connected. power 2.5V 0.25µm CMOS implementation with 128-pin package. Input tolerance 3.3V
100M
_100
100M
Figure
Functional Block Diagram
AC206-DS03-R
16215 Alton Parkway P.O. 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
06/19/01
REVISION HISTORY
REVISION
AC206-DS00-R AC206-DS01-R
DATE
10/9/00 02/08/01
CHANGE DESCRIPTION
Initial release Updated text "Scrambler" subsection "Functional Description" read that "When Control register 23.11 data scrambling function disabled, 5-bit data stream clocked directly device's sublayer." Added #114 "DGND" Table Power Ground. Added pins 103, 104, 106, Table Connects. Updated Section Electrical Characteristics, Section Digital Timing Characteristics. Added Section "Mechanical Information", outlining packaging specifications. Updated Digital Input Voltage from "-0.5V Vcc" "-0.5V 3.3V" Section Electrical Characteristics. Updated Timing. Various text changes.
AC206-DS02-R
04/10/01
Updated Table Connections. Updated Table Control Set-up. Updated Table Register Set. Updated Table Port Status. Updated Table Initial Repeater Configuration Register. Changed section titled "Test Effect Register" "LED Effect Register". Updated Figure Display Matrix.
AC206-DS03-R
06/19/01
Updated Table Connections. Updated Table Power Ground. Updated Table Register Set. Updated Table Initial Repeater Configuration Register. Updated Table Bridge Control Register. Updated Table Control Register. Updated Table Effect with Partition/Isolation Event. Updated Table EEPROM.
Altima Communications, Inc. Wholly Owned Subsidiary Broadcom Corporation P.O. 57013 16215 Alton Parkway Irvine, 92619-7013 2001 Altima Communicaitons, Inc. rights reserved Printed U.S.A.
Broadcom®, pulse logo®, QAMLink registered trademarks Broadcom Corporation and/or subsidiaries United States certain other countries. other trademarks property their respective owners.
Advance Data Sheet
06/19/01
AC206
TABLE CONTENTS
Revision History
Section Functional Description.
Functional Description Clocks, Reset Power Management Functions Transceiver Transmit Function Scrambler. Parallel Serial NRZI MLT-3 Conversion. Multimode Transmit Driver Clock Synthesizer. Receive Function Adaptive Equalizer Link Monitor Baseline Wander Compensation Clock/Data Recovery Decoder/Descrambler Auto-Negotiation Miscellaneous Functions Parallel Detection. Carrier Sense/RXDV Port Only. Cable Length Monitor Bridge Function. Interface Address Recognition. Reset Restart Media Access Control Initialization Setup Hardware Configuration Software Configuration LEDs Addressing Algorithm, Routing, Learning Aging Address Table. Address Recognition. Routing Decision.
Document AC206-DS03-R Table Contents Page
AC206
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Learning Process. Aging Time Forwarding Scheme Buffer Management Queues
Section Pins.
Descriptions Display/Configuration/PROM Interface.16
Section Register Descriptions
Register Description.19 Port Status Register Initial Repeater Configuration Register.21 Bridge Control Register Registers Control Register.23 Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register.26 Auto-Negotiation Next Page Transmit Register.26 Control Register Interrupt Control/Status Register Diagnostic Register Test Register Cable Length Register.29 Receive Error Count Power Management Register Operation Mode Register Recent Received Packet Effect Register Effect with Partition/Isolation Event Effect with Link Event Effect with Activity (CRS) Event Effect with Auto-Negotiating Event
Page Table Contents Document AC206-DS03-R
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AC206
Effect with Speed100 Event. Register Control Mode EEPROM Table 4B/5B Code-Group Table Display Matrix. System Considerations
Section Electrical Characteristics.
Absolute Maximum Ratings Operating Range REFCLK Pins. Characteristics Pins BASE-TX Transceiver Characteristics BASE-T Transceiver Characteristics.
Section Digital Timing Characteristics
Power Reset Management Data Interface 7-Wire Input Timing. 7-Wire Output Timing. 100BASE-TX Input Timing 100BASE-TX Output Timing 10BASE-TX Input Timing 10BASE-TX Output Timing 100Mbps Repeater BackPlane Receive/Transmit Timing. 10Mbps Repeater BackPlane Receive/Transmit Timing. EEPROM Interface Timing 10/100BASE-TX Reverse Output Timing 10/100BASE-TX Reverse Input Timing Timing Application Termination
Section Mechanical Information. Section Ordering Information.56
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AC206
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06/19/01
Page Table Contents Document AC206-DS03-R
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06/19/01
AC206
LIST FIGURES
Figure Functional Block Diagram Figure Exclusive Hashing Algortithm. Figure Address Learning Recognition Figure Basic Memory Management Concept Figure Display Matrix. Figure Power Reset. Figure Management Data Interface Timing Figure 7-Wire Input Timing Figure 7-Wire Output Timing Figure 100BASE-TX Input Timing Figure 100BASE-TX Output Timing Figure 10BASE-TX Input Timing Figure 10BASE-TX Output Timing Figure 100Mbps Receive/Transmit Timing Figure 10Mbps Receive/Transmit Timing Figure EEPROM Interface Timing Figure 10/100BASE-TX RvMII Output Timing Figure 10/100BASE-TX RvMII Input Timing. Figure Timing. Figure Application Termination. Figure 128-pin PQFP.
Document AC206-DS03-R List Figures Page
AC206
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Page viii List Figures Document AC206-DS03-R
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AC206
LIST TABLES
Table Connections. Table Content Address Lookup Table Table Embedded Memory Structure. Table (Media Dependent Interface) Pins (TX) Table (Media Independent Interface) Pins Table Reverse (Media Independent Interface) Pins Table 7-wire (Serial Network Interface) Pins Table Serial Configuration Prom Table Serial Management Interface Table 100Mbps Internal Repeater Bus. Table 10Mbps Internal Repeater Bus. Table Pins. Table Control Set-up Table Clock Reset Table Power Ground Table Connects. Table Register Set. Table Port Status Register Table Port Status. Table Initial Repeater Configuration Register. Table Bridge Control Register Table Control Register Table Status Register Table Identifier Register Table Identifier Register Table Auto-Negotiation Advertisement Register Table Auto-Negotiation Link Partner Ability Register Table Register Auto-Negotiation Expansion Register Table Auto-Negotiation Next Page Transmit Register. Table Control Register Table Interrupt Control/Status Register Table Diagnostic Register
Document AC206-DS03-R List Tables Page
AC206
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06/19/01
Table Test Register.29 Table Cable Length Register Table Receive Error Count Table Power Management Register Table Operation Mode Register Table Recent Received Packet.31 Table Effect with Partition/Isolation Event.31 Table Effect with Link Event.31 Table Effect with Activity (CRS) Event Table Effect with Auto-Negotiating Event Table Effect with Speed100 Event Table Register Control Mode Table EEPROM Table 4B/5B Code-Group Table Table Total Power Consumption.37 Table Characteristics Table REFCLK Pins Table Characteristics Pins Table BASE-TX Transceiver Characteristics Table BASE-T Transceiver Characteristics.40 Table Power Reset Table Management Data Interface Table 7-Wire Input Timing.43 Table 7-Wire Output Timing Table 100BASE-TX Input Timing Table 100BASE-TX Output Timing Table 10BASE-TX Input Timing Table 10BASE-TX Output Timing Table 100Mbps Repeater BackPlane Receive/Transmit Timing.49 Table 10Mbps Repeater BackPlane Receive/Transmit Timing.50 Table EEPROM Interface Timing.51 Table 10/100BASE-TX Reverse Output Timing. Table 10/100BASE-TX Reverse Input Timing Table Timing Table Package Dimensions AC206
Page List Tables Document AC206-DS03-R
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06/19/01
AC206
FUNCTIONAL DESCRIPTION
AC206 integrated 10/100 Mbps repeater with bridge function. device provides eight 10/100BASE-TX twisted pair interface ports. AC206 includes built-in 2-segment switch 10/100Mbps connection. AC206 provides highest integration chip solution dual speed system. result ultra power consumption that consumes less than maximum when ports running 100BASE-TX full-speed. built-in power management function powers down individual port when used cable detected) which further drives down power consumption improves long-term reliability.
CLOCKS, RESET POWER MANAGEMENT FUNCTIONS
AC206 requires single clock signal input pin. internal generates clock frequencies needed device from single clock input. AC206 reset ways: During initial power Hardware reset: logic signal pulse width applies pin.
During reset, mode pins latch internal address table initialized, internal state machine reset known states. completion reset sequence, ports enabled frame reception transmission. AC206 offers following power management: Power down mode: Refer Power-down register. example, port base address During power down, device able respond through serial management interface. Energy detects mode: device powers down unused circuitry when cable installed. Energy Detect (ED) circuit stays monitor incoming signals from media. portion turned response management transaction. transmit circuit sends link pulse with minimum power consumption. valid signal received from media, device powered resumes normal transmit/receive operation.
TRANSCEIVER TRANSMIT FUNCTION
100BASE-TX mode, Transceiver transmits MLT-3 signal cable isolation transformer. MLT-3 data three level signal data. This data scrambled when transmitted media. MLT-3 data synchronous clock. 10BASE-T mode, Manchester code generated 10BASE-T core logic, which synthesizes through output waveshaping driver. This helps reduce emission, which eliminates need external filter.
transmit data interface 4-bit nibbles 25/2.5 rate. This data transferred from controller into repeater controller lines. controller asserts TX_EN during transmission, forces error encoded data using TX_ER.
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AC206
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06/19/01
SCRAMBLER
100BASE-TX mode, internal 5-bit transmit data stream scrambled defined TP-PMD Stream Cipher function order reduce radiated emissions twisted pair cable. scrambler encodes plain text stream using stream periodic sequence 2047 bits generated recursive linear function: [n-11] [n-9] (modulo scrambler reduces peak emissions randomly spreading signal energy over transmit frequency range, thus eliminating peaks single frequency. emission further reduced assigning unique scrambled seed each port. When Control register 23.11 data scrambling function disabled, 5-bit data stream clocked directly device's sublayer.
PARALLEL SERIAL NRZI MLT-3 CONVERSION
internal 5-bit data clocked into Transceiver's shift register with clock, clocked with clock convert into serial stream. Both clocks generated on-chip clock synthesizer, they sync each other. serialized data further converted from NRZI format, which produces transition every Logic transition Logic further reduce emission, NRZI data converted MLT-3 signal. effect offers reduction emissions over un-converted NRZI signals, thus increases output signals' margin operating within Class limit. When there transition occurring NRZI data, there corresponding transition MLT-3 data. NRZI data, changes count up/down direction after every single transition. MLT-3 data, changes count up/down direction after every transitions. NRZI MLT-3 data conversion implemented without reference timing clock information. conversion requires detecting transition incoming NRZI data count up/down direction MLT-3 data. Asserting FX_SEL high bypasses this encoding.
MULTIMODE TRANSMIT DRIVER
multimode driver transmits MLT-3 coded signal 100BASE-TX mode Manchester coded signal 10BASE-T mode. slew rate transmitted MLT-3 signal controlled eliminate high frequency component. MLT-3 signal after magnetic typical rise/fall time approximately which within target range specified ANSI standard. 10BASE-T mode, high frequency pre-emphasis performed which extends cable-driving distance without need external filter. FLP/NLP also drive through 10BASe-T driver. 10BASE-T 100BASE-TX transmit signals multiplexed transmit output driver. This arrangement results using same external transformer both 10BASE-T 100BASE-TX. driver output level built-in bandgap reference external resistor connected RIBB output pin. resistor sets output current modes operation. Each TXOP/N outputs open drain device which source resistance maximum current rating Vp-p MLT3 signal, 5Vp-p Manchester signal when used transformer.
CLOCK SYNTHESIZER
Transceiver also includes on-chip clock synthesizer that generates 125MHz 25MHz clock 100BASETX 100MHz 20MHz clock 10BASE-T Auto-Negotiation operations. clock generator uses fully differential cell that induces very jitter. Zero Dead Zone Phase Detection method implemented this design provides excellent phase tracking. charge pump with charge sharing compensation also included further reduce jitter different loop filter voltages. On-chip loop filter eliminates need external components avoids external noise pickup. Only external 25MHz crystal signal source required reference clock.
Page Section Functional Description Document AC206-DS03-R
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AC206
RECEIVE FUNCTION
100BASE-TX mode, receive function implements reverse order function transmit path. includes receiver with adaptive equalization restoration, MLT-3 NRZI conversion, data clock recovery 125MHz, NRZI conversion, Serial-to-Parallel conversion, de-scrambling, decoding. receiver circuit starts with bias differential RX+/- inputs, follows with low-pass filter filter high frequency noise from transmission channel media. energy detect circuit also added determine whether there signal energy media. This useful power-saving mode. amplification ratio slicer threshold on-chip bandgap reference. 10BASE-T mode, signal first passes through order lowpass filter, which filters noise from cable, board, transformer. This eliminates need 10BASE-T external filter. Manchester decoder Serial-to Parallel follows generate 4-bit data mode.
ADAPTIVE EQUALIZER
Each eight transceivers designed accommodate maximum cable length meters CAT5 cable. meters CAT-5 cable, such AT&T 1061, attenuation MHz. typical attenuation 100-meter cable worst case attenuation around 24-26 defined TP-PMD. amplitude phase distortion from cable causes inter-symbol interference (ISI) which makes clock data recovery impossible. Adaptive equalizer done matching inverse transfer function twist-pair cable. This variable equalizer that changes equalizer frequency response accordance cable length. cable length estimated based comparisons incoming signal strength against some known cable characteristics. equalizer monotonically frequency response, tunes itself automatically cable length compensate amplitude phase distortion incurred from cable.
LINK MONITOR
Signal levels detected through squelch detection circuitry. signal detect (SD) circuit follows equalizer asserted high when peak detector detects post-equalized signal with peak ground voltage level larger than This approximately normal signal voltage level. addition, energy level must sustained longer than order signal detects asserted. gets de-asserted approximately after energy level consistently less than from peak ground. 100BASE-TX mode, when signal invalid signal detected receive pair, link monitor enters link fail state where only scrambled idle code transmitted. When valid signal detected minimum period time, link monitor enters link pass state transmit receive functions entered. 10BASe-T mode, link-pulse detection circuit constantly monitors RXIP/RXIN pins presence valid link pulses.
BASELINE WANDER COMPENSATION
100BASE-TX data stream always balanced. transformer blocks component incoming signal, thus offset differential receives inputs wander. shift signal levels, coupled with non-zero rise fall times serial stream cause pulse-width distortion, creating jitter possible increases error rates. Therefore, restoration circuit needed compensate attenuation component. Transceiver implemented patent-pending restoration circuit, unlike traditional implementation; does need feedback information from slicer clock recovery. This only simplifies system/circuit design also eliminates random/systematic offset receive path. 10BASE-T mode, baseline wander correction circuit required bypassed.
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AC206
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06/19/01
CLOCK/DATA RECOVERY
equalized MLT-3 signal passes through slicer circuit that converts NRZI format. Transceiver uses mixedsignal phase locked loop (PLL) extract clock information incoming NRZI data. extracted clock used re-time data stream data boundaries. transmit clock locked 25MHz clock input while receive clock locked incoming data streams. When initial lock achieved, switches lock data stream, extracts 125MHz clock uses that framing recover data. recovered 125MHz clock also used generate internal 25MHz RX_CLK. requires external components operation high noise immunity jitter. provides fast phase align (lock) data transition data/clock acquisition time after power-on less than transitions. maintain lock run-lengths data bits absence signal transitions. When valid data present, i.e. when de-asserted, switches back lock with TX_CLK, provides continuously running RX_CLK.
DECODER/DESCRAMBLER
descrambler detects state transmit Linear Feedback Shift Register (LFSR) looking sequence representing consecutive idle codes. descrambler acquires lock with data stream recognizing IDLE bursts more bits locking de-ciphering Linear Feedback Shift Register (LFSR). Once lock acquired, device operates with inter-packet-gap (IPG) Before lock occurs, de-scrambler requires minimum idle between packet order acquire lock. deciphering logic also tracks number consecutive receive errors detected while RX_DV asserted. Once error counter exceeds limit (currently consecutive errors), logic assumes that lock been lost, decipher circuit resets itself. process regaining lock begins again. Stream cipher de-scrambler used 10BASE-T mode.
AUTO-NEGOTIATION MISCELLANEOUS FUNCTIONS
Each Transceiver contains ability negotiate mode operation over twisted pair using auto-negotiation mechanism defined clause IEEE 802.3u specification. Auto-negotiation disabled software EEPROM. Transceiver automatically chooses mode operation detecting incoming signal. During auto-negotiation, auto-negotiation advertisement register sent link partner through series fast link pulse (FLP). When auto-negotiation enabled, Transceiver sends during following conditions: power link loss, restart command. same time, device monitors incoming data determine mode operation. Parallel detection circuit enabled soon 10BASE-T idle 100BASE-TX idle detected. mode operation configured based technology incoming signal. When device receives burst from link partner with identical link code words (ignoring acknowledge bit), stores these code words auto-negotiation link partner ability register waits next identical code word. Once device detects second code word, configures itself highest technology that common both ends. technology priorities 100BASE-TX, half-duplex, 10BASET half-duplex. Once auto-negotiation complete, status register reflects actual speed that chosen.
PARALLEL DETECTION
Transceiver also checks 10BASE-T 100BASE-TX idle symbols. either detected, device automatically configures match detected operating speed half-duplex mode. This ability allows device communicate with legacy 10BASE-T 100BASE-TX systems.
Page Section Functional Description Document AC206-DS03-R
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AC206
CARRIER SENSE/RXDV PORT ONLY
Carrier sense asserted asynchronously pins soon activity detected receive data stream. RX_DV asserted soon valid (Start-of-Stream Delimiter) detected. Carrier sense RX_DV de-asserted synchronously upon detection valid stream delimiter consecutive idle code groups receive data stream. carrier sense asserted valid detected immediately, RX_ER asserted instead RX_DV. 10BASE-T mode, carrier sense asserted asynchronously when valid preamble activity detected RXIP/RXIN pins. half duplex mode, activated during transmit receive data.
CABLE LENGTH MONITOR
AC206 also detect length cable display result interrupt control/status register, i.e., 0000 stands cable used, 0001 stands meter cable, 1111 stands meter cable. This especially useful management functions. detects proper connectivity cable helps manage cable distribution.
BRIDGE FUNCTION
INTERFACE
Switch engine supports 10/100Mbps. Port switch engine support either 100, while port supports only Mbps. Refer mode table configure port
FORWARDING SCHEME
switch supports store-and-forward scheme only. does support cut-through-forward. With store-and-forward, incoming packet should completely received buffer without error before sent out.
ADDRESS RECOGNITION
self-learning bridge function based source address field packets. switch uses hashing algorithm address look-up table. Programmable aging time fast aging control supported.
RESET RESTART
When switch engine power initially goes SRAM self-test mode. generates patterns evaluate SRAM status.
MEDIA ACCESS CONTROL
switch engine implements functions IEEE 802.3 protocol such frame formatting, collision handling. generates 56-bit preamble start frame delimiter while packet sending. half duplex mode, device listens before transmitting, prevent traffic jam. During collision, packet retransmitted random time.
Document AC206-DS03-R Section Functional Description Page
AC206
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06/19/01
INITIALIZATION SETUP
HARDWARE CONFIGURATION
Several different states operation chosen through hardware configuration. External pins pulled high reset time. combination high values determines power state device. Many these pins multi-function pins which change their meaning when reset ends.
SOFTWARE CONFIGURATION
Several different states operation chosen through MDC/MDIO interface. Refer Section "Register Descriptions".
LEDS
Using display matrix with refresh technique, only pins required drive LEDs with unique information. Off, Flash states used indicate different information. With reduced number signals, display easier route board, less costly. active-low data driven LED_D[0:7] pins each port corresponding functions LED_LN[5:0] pin. Refer to"LED Display/Configuration/PROM Interface" "LED Display Matrix" details. AC206 supports LEDs port. following table describes each connected. Signals LED_D[2:6] indicators port through Signals LED_LN[0:5] events driven port through
Table Connections Signals
LED_LN[0] LED_LN[1] LED_LN[2]
Events
Link Status/Activity Speed/Partition Display utilization Mbps domain
Descriptions
Active indicates 100M link good. Blinking indicates 100M activity. Active indicates link good. Blinking indicates activity. LED_LN[2] active low, indicating 100M utilization. Utilization indicator port basis, rather segment basis. LED_D[0:7] indicates percentage utilization. LED_D[0:7] Percent Util.
LED_LN[3]
Display utilization Mbps domain
LED_LN[3] active low, indicating utilization. Utilization indicator port basis, rather segment basis. LED_D[0:7] indicates percentage utilization. LED_D[0:7] Percent Util.
LED_LN[4]
Display collision Mbps domain
LED_LN[4] active low, indicating collision. Collision indicator port basis, rather segment basis. LED_D[1:7] indicates percentage collision. However, LED_D0 only indicates collision occurrence. LED_D[0:7] Percent Col. Col.
Page Section Functional Description Document AC206-DS03-R
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AC206
Table Connections (Cont.) Signals
LED_LN[5]
Events
Display collision Mbps domain
Descriptions
LED_LN[5] active low, indicating collision. Collision indicator port basis, rather segment basis. LED_D[1:7] indicates percentage collision. However, LED_D0 only indicates collision occurrence. LED_D[0:7] Percent Col. Col.
ADDRESSING ALGORITHM, ROUTING, LEARNING AGING
ADDRESS TABLE
address table store entries each entry consists 48-bit address, 8-bit port identifier, 1-bit indication flag 6-bit aging timer.
Table Content Address Lookup Table 3130
MAC#3 Timer Port# MAC#4 MAC#1 MAC#5 MAC#2 MAC#6
Entry valid empty indication, valid entry, empty entry. 29-24: Aging timer. 23-16: Port number
ADDRESS RECOGNITION
exclusive addressing algorithm used address lookup table addressing. Refer Figure
MAC#6
MAC#4
MAC#2
Hashed address[15:0]
MAC#5
MAC#3
MAC#1
Figure
Exclusive Hashing Algortithm
final address address lookup table hashed address[9:0].
ROUTING DECISION
record empty, packet broadcast treated unknown frame. Otherwise, record read, compared with current addresses same, port number decided, packet forwarded assigned port. address collision occurred, different address, incoming packet considered unknown packet.
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AC206
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LEARNING PROCESS
address learning process composed packets addressing algorithm described above. switch checks each incoming packets integrity buffers availability. packet error-free buffer available, port number pair packet written into address lookup table. Figure describes general operations address learning recognition.
Hashing Function
[9:0] Address Entry Point
AAA-1 AAA+1
Address Lookup Table
Figure
Address Learning Recognition
AGING TIME
switch automatically examines status address lookup table. round robin speed checking timer dependent aging time. switch aging time seconds. When aging timer started after power switch guaranties that free spaces released from occupied address entries.
FORWARDING SCHEME
store-and-forward algorithm used. incoming packet completely stored buffer verified errorfree before forwarding operations take place.
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AC206
BUFFER MANAGEMENT QUEUES
switch buffering management continues store received packets into memory. buffer size 100M port bytes, bytes port.
Start Address Read Point Write Point Free buffer Address
Port Buffer Management
Figure
Basic Memory Management Concept
switch uses pointers control port buffer status. Start Address point beginning memory address each port Address point last address memory each port. Read/Write shadow Read/Write pointers dynamically changed depending current outgoing incoming packets storage. Write pointer reaches Read pointer size between write read pointers smaller than bytes, buffer full. other hand, when read/write pointers equal, buffer empty.
Table Embedded Memory Structure
0x0000 0x07FF 0x0800 0x17FF 0x1800 0x1FFF address lookup table 100M Bridge Port Bridge Port
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AC206
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AC206
DESCRIPTIONS
Many these device pins have multiple functions. separate descriptions each listed proper sections. Designers must assure that they have identified modes operation prior final design. assignment shown below description table subjected change without notice. user advised contact Altima Communications Inc. before implementing design based information provided this data sheet. Signals types: Input Output High impedance Pull with Pull down with Schimitt Trigger Analog signal Power Ground Active Signal
Table (Media Dependent Interface) Pins (TX) Name
RXIP_4 RXIP_3 RXIP_2 RXIP_1 RXIP_0 RXIN_4 RXIN_3 RXIN_2 RXIN_1 RXIN_0 TXOP_4 TXOP_3 TXOP_2 TXOP_1 TXOP_0
Type
Description
Receiver Input Positive both 10BASE-T 100BASE-TX.
Receiver Input Negative both 10BASE-T 100BASE-TX.
Transmitter Output Positive both 10BASE-T 100BASE-TX.
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AC206
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Table (Media Dependent Interface) Pins (TX)(Cont.) Name
TXON_4 TXON_3 TXON_2 TXON_1 TXON_0
Type
Description
Transmitter Output Negative both 10BASE-T 100BASE-TX.
Table (Media Independent Interface) Pins Name
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 MII_TXCLK
Type
Description
Transmit Data. sources MII_TXD[3:0] synchronous with MII_TXCLK when MII_TXEN asserted.
O,D,S
Transmit Clock. Continuous (25MHz/2.5MHz) clock output used synchronize MII_TXEN, MII_TXD[3:0], MII_TXER. Transmit Enable. Indicates presented valid data MII_TXD[3:0]. Receive Data. sources MII_RXD[3:0] synchronous with MII_RXCLK when MII_RXDV asserted. After power MII_SPDSEL latched port speed selection. 1=100Mb, 0=10Mb Transmit Clock. Continuous (25MHz/2.5MHz) clock output used synchronize MII_RXDV, MII_RXD[3:0], MII_RXER. Receive Data-Valid. presented valid recovered MII_RXD[3:0]. Carrier Sense. Active when carrier been sensed. Receive Error. Indicates received invalid symbol data. Collision Detection. Active when collision detected.
MII_TXEN MII_RXD3/MII_SPDSEL MII_RXD2/MODE3 MII_RXD1/TP125 MII_RXD0 MII_RXCLK
I/O,U I/O,D I/O,U O,D,S
MII_RXDV MII_CRS MII_RXER MII_COL
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AC206
Table Reverse (Media Independent Interface) Pins Name
RvMII_TXD3 (MII_RXD3) RvMII_TXD2 (MII_RXD2) RvMII_TXD1 (MII_RXD1) RvMII_TXD0 (MII_RXD0) RvMII_TXCLK (MII_TXCLK) RvMII_TXEN (MII_RXDV) RvMII_RXD3 (MII_TXD3) RvMII_RXD2 (MII_TXD2) RvMII_RXD1 (MII_TXD1) RvMII_RXD0 (MII_TXD0) RvMII_RXCLK (MII_RXCLK) RvMII_RXDV (MII_TXEN) RvMII_CRS (MII_CRS) RvMII_RXER (MII_RXER) RvMII_COL (MII_COL)
Type
Description
Transmit Data. sources RvMII_TXD[3:0] synchronous with RvMII_TXCLK when RvMII_TXEN asserted.
I,D,S
Transmit Clock. Continuous (25MHz/2.5MHz) clock output used synchronize RvMII_TXEN, RvMII_TXD[3:0], RvMII_TXER. Transmit Enable. Indicates presented valid data RvMII_TXD[3:0]. Receive Data. sources RvMII_RXD[3:0] synchronous with RvMII_RXCLK when RvMII_RXDV asserted.
I,D,S
Transmit Clock. Continuous (25MHz/2.5MHz) clock output used synchronize RvMII_RXDV, RvMII_RXD[3:0], RvMII_RXER. Receive Data-Valid. presented valid recovered RvMII_RXD[3:0]. RvMII Carrier Sense. Active when carrier been sensed. RvMII Receive Error. Indicates received invalid symbol data. RvMII Collision Detection. Active when collision detected.
Table 7-wire (Serial Network Interface) Pins Name
SNI_TXD (MII_TXD0) SNI_TXCLK (MII_TXCLK) SNI_TXEN (MII_TXEN) SNI_RXD (MII_RXD0) SNI_RXCLK (MII_RXCLK) SNI_CRS (MII_CRS)
Type
Description
Serial Transmit Data. sources SNI_TXD synchronous with SNI_TXCLK when SNI_TXEN asserted. Serial Transmit Clock. Continuous (10MHz) clock output used synchronize SNI_TXEN SNI_TXD. Serial Transmit Enable. Indicates presented valid data SNI_TXD. Serial Receive Data. sources SNI_RXD synchronous with SNI_RXCLK when SNI_CRS asserted. Serial Receive Clock. Continuous (10MHz) clock output used synchronize SNI_CRS SNI_RXD. Serial Carrier Sense. Active when carrier been sensed.
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Table 7-wire (Serial Network Interface) Pins (Cont.) Name
SNI_COL (MII_COL)
Type
Description
Serial Collision Detection. Active when collision detected.
Table Serial Configuration Prom Name
PROM_CS PROM_CLK (LED_D[6]) PROM_OUT (LED_D[5]) PROM_IN (LED_D[7])
Type
Description
PROM chip select. Connected Chip Select 93C46 serial EEPROM. PROM Clock. Connected 93C46 serial EEPROM. PROM Data Out. Connected Data_In 93C46 serial EEPROM. PROM Data Connected Data_Out 93C46 serial EEPROM.
Table Serial Management Interface Name
(PROM_CS) MDIO
Type
I/O,D
Description
Management Data Clock. Serial management clock which uses clock MDIO data. Management Data Input/Output. bi-directional data interface used external manager access internal registers within AC207. This internal pull-down register.
Table 100Mbps Internal Repeater Name
M100COL_LOCAL* M100ACTO*
Type
I/O,
Description
100M Local Collision. Input when ChipID Active indicate collision other ChipIds. Output ChipID=00 ChipID00 signal local activity. This signal pure combinational logic sync with clock source. (Refer next signals). Input ChipID=00 from ChipID00 M100ACTO* pins indicate activities. Open other ChipIDs. Connected from ChipID=00 ChipID=10 M100ACTO* sense activities. Open other ChipIDs. Connected from ChipID=00 ChipID=11 M100ACTO* sense activities. Open other ChipIDs. ChipID=00 drives this same 100COLBP* indicate local collision.
M100ACTI_0* (M100ACTO*) M100ACTI_1* M100ACTI_2* M100COL_SYS*
I/O,U
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AC206
Table 100Mbps Internal Repeater Bus(Cont.) Name
M100CRS_SYS* MS100D4 MS100D3 MS100D2 MS100D1 MS100D0 MS100D_EN*
Type
I/O,U I/O,D I/O,D I/O,D I/O,D I/O,D I/O,U
Description
ChipID=00 drives this same 100CRSBP* indicate local activity. Multiple/Stacked Data Group. Transmit receive data descrambled data groups multiple devices. Data sampled rising edge MS100D_CLK driven falling edge MS100D_CLK.
Multiple/Stacked Data Enable. Active-low when data valid. Signal driven falling edge MS100D_CLK, sampled rising edge MS100D_CLK. Multiple/Stacked Data Clock. bi-directional non-continuous recovered clock synchronizing with MS100D[4:0], MS100D_EN*.
MS100D_CLK
I/O,
Table 10Mbps Internal Repeater Name
M10COL_LOCAL*
Type
I/O,
Description
Local Collision. Input when ChipID Active indicate collision other ChipIds. M10COL_LOCAL# (local_collision). Output ChipID ChipID signal local activity. (Refer next signals). Connected from ChipID from ChipID M10ACTO* sense activities. Open other ChipIDs. Connected from ChipID ChipID M10ACTO* sense activities. Open other ChipIDs. Connected from ChipID ChipID M10ACTO* sense activities. Open other ChipIDs. ChipID drives this same 10COLBP* indicate system collision. ChipID drives this same 10CRSBP* indicate system activity. Multiple/Stacked Data Group. Transmit receive data 10BT multiple devices. Data sampled rising edge MS10D_CLK driven falling edge MS10D_CLK. Multiple/Stacked Data Enable. Active when data valid. Multiple/Stacked Data Clock. bi-directional non-continuous recovered clock synchronizing with MS10D MS10D_EN*.
M10ACTO* M10ACTI_0* (M10ACTO*) M10ACTI_1* M10ACTI_2* M10COL_SYS* M10CRS_SYS* MS10D
I/O,U I/O,U I/O,D
MS10D_EN* MS10D_CLK
I/O,U I/O,
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DISPLAY/CONFIGURATION/PROM INTERFACE
pins shared with reset-read configuration pins, test pins EEPROM interface. value applied reset-read pins only valid reset cycle. EEPROM interface active after reset cycle. Once data EEPROM read, same pins used display. outputs available through matrix.
Table Pins Name
LED_LN[5] LED_LN[4] LED_LN[3] LED_LN[2] LED_LN[1] LED_LN[0]
Type
Description
Enable corresponding display line display matrix, active output. detail program connect LEDs Setup section. LED_LN*[5]: Display 10BT Collision rate segment collision status. LED_LN*[4]: Display 100Mbps Collision rate segment collision status LED_LN*[3]: Display segment utilization rate LED_LN*[2]: Display 100M segment utilization rate LED_LN*[1]: Programmable display. default display Link/Activity information each port. LED_LN*[0]: Programmable display. default display 100M Link/Activity information each port. Output display information each column display matrix. Active high output.
LED_D[7] LED_D[6] LED_D[5] LED_D[4] LED_D[3] LED_D[2] LED_D[1] LED_D[0]
I/O,
Table Control Set-up Name
Mode[3] (MII_RXD2) Mode[2] (LED_D[4]) Mode[1] (LED_D[1]) Mode[0] (LED_D[0])
Type
Description
Mode[1:0] Mode[3:2] Domain Domain 100M Rptr Rptr (Master) 100M Rptr Rptr (Slave, Bridge disable) 100M Port Reserved Digital Interface 7-wire Reverse
TP125 (MII_RXD1) ChipID[1] (LED_D[2]) ChipID[0] (LED_D[3])
1:select 1:1.25 xformer device must assigned with ChipID=0
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AC206
Table Control Set-up(Cont.) Name
IBREF
Type
Description
Reference bias resistor. Connected analog ground through (1%) resistor.
Table Clock Reset Name
RESET*
Type
Description
Reset initial defaulted state. 25MHz-System-clock reference input. This connected external 25MHz-clock source. Multiple devices synchronous same external clock source.
Table Power Ground Name
DVCC DGND AVCC AGND GAVDD GAGND
115, 126, 114, 116, 117, 108, 109, 110, 105, 101, 111,
Type
Description
2.5V power digital circuit, total pins. Ground digital circuit, total pins. 2.5V power analog circuit, total pins. Ground analog circuit, total pins 2.5V power supply common analog circuit Ground common analog circuit
Table Connects Name
103, 104, 106,
Type
Description
Connects
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AC206
Section egis iptions
There reserved registers and/or bits that Altima internal only. following standard registers supported. (Register numbers Decimal format, values format). NOTE: When writing registers, recommended that read/modify/write operation performed, unintended bits unwanted states. This applies registers, including those with reserved bits.
REGISTER DESCRIPTION
AC206 register sets listed below. Each register contains 16-bit data. addresses shown below hexadecimal.
Table Register Addr
Register Addr
Definition
Registers Control Register Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto Negotiation Next Page Transmit Register Reserved Control Register Interrupt Control/Status Register Diagnostic Register Test Register Cable Length Register Receive Error Count Power Management Register Operation Mode Register Reserved Registers Registers Registers
Type
Default
3000 2849 0022 5541 00A1 0001 0004 2001 0000
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Table Register (Cont.) Addr
Register Addr
Definition
Registers Port Link Status Port Polarity Status Port Partition Status 100Mb Port Partition Status 10Mb Port Speed Status Port Isolation Status Initial Repeater Configuration Register Bridge Control Register Device Revision Number Effect with Partition/Isolation Event Effect with Link Event Effect with Activity (CRS) Event Effect with AutoNeg Event Effect with Speed100 Event Register Control Mode
Type
Default
PORT STATUS REGISTER
Table Port Status Register Name
Port Link Status Port Polarity Status Port Partition Status 100Mb Port Partition Status 10Mb Port Speed Status Port Isolation Status (Fast Ethernet only)
Type
Address
Description
Link good, default polarity been crossed, default port been partitioned, default port been partitioned, default 100M, 0:10M, default port been isolated, default
Table Port Status 15:9
Port
Port
Port
Port
Port
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AC206
INITIAL REPEATER CONFIGURATION REGISTER
Table Initial Repeater Configuration Register Name
Repeater Configuration
Type
Address
Description
Used give status port. Default pin.
Name
Type
Description
Mode[3:2] Mode[1:0] Digital Interface 7-wire Reverse Reserved Master mode, Bridge enable Slave mode, Bridge disable Slave mode, Uplink Port connected bridge port this mode. other bridge port connected segment. Reserved
Default
MODE pins
15:12
Mode
Reserved (Write clear enable) Reserved (MIB enable) Disable partition External transform selec- tion MIIB Speed Select Switch debug 100M repeater Partition Alternative
Reserved
1:disable partition function interface 1:external transform 1:1.25, 0:external transform 1:100M interface, 0:10M interface Selection control debugging signals normal, un-partition port only when data transmitted from port bit-time without collision. alternate, un-partition port when data either transmitted from port received from port bit-time without collision. normal, un-partition port when data either transmitted from port received from port bit-time without collision. alternate, un-partition port only when data received from port bit-time without collision 00000
repeater Partition Alternative
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BRIDGE CONTROL REGISTER
Table Bridge Control Register Name
Bridge Control Register
Type
Address
Description
Used configure Bridge.
Name
Watch Reset Loose Length
Type
Description
1:reset when WDOG even occur. 0:dosen't reset when WDOG even occur. 1:receives frame with length from 1519 1548. 0:rejects frame with length over 1518. 1:enable, 0:disable receive dribble error packets. 1:disable, 0:enable address table init. While this address table only contains entries speed function verification. 1:enable, 0:disable aging speed 1:enable, 0:disable back pressure function. 1:enable, 0:dieable 100M back pressure function. 1:enable, 0:disable collision test.
Default
Dribble Error Address Table Initialization Disable Aging Speed Back Pressure 100M Back Pressure Collision Test Reserved
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AC206
REGISTERS
following registers defined each port. base addresses respectively.
CONTROL REGISTER
Table Control Register
0.15
Name
Reset
Definition
reset This self-clearing. Loopback mode, which internally loop transmit AC206 receive, thus will ignore activity cable media. Normal operation. 100Mbps 10Mbps. This will ignored Auto-Negotiation enabled. will longer reflect auto-negotiation result. Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. force mode, speed selected 0.13. Power down mode, which puts AC206 low-power stand-by mode, which only react management transaction. Normal operation. Electrical isolation from cable media. Normal operation. Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. Full duplex supported this chip. will longer reflect auto-negotiation result. Enable collision test, which issues signal response assertion TX_EN signal. Disable test.
Mode
RW/SC
Default
0.14
Loopback
0.13
Speed Select
0.12
Auto-Neg Enable
0.11
Power Down
0.10
Isolate
Restart Auto-Negotiation Duplex Mode
Collision Test
0.6:0
Reserved
000000
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STATUS REGISTER
Table Status Register
1.15 1.14 1.13
Name
100BASE-T4 100BASE-TX Full Duplex 100BASE-TX Half Duplex 10BASE-T Full Duplex 10BASE-T Half Duplex Reserved Auto-Negotiate Complete
Definition
Tied zero indicates 100BASE-T4 capability. Tied zero indicates 100BASE-TX full duplex support. 100BASE-TX with half duplex. Half-Duplex ability. Tied zero indicates 10BASE-T full duplex support. 10BASE-T with half duplex. 10BASE-T Half-Duplex ability.
Mode
Default
1.12 1.11
1.10:6
Auto-negotiate process completed, indicates Reg. valid. Auto-negotiate process completed. Remote fault condition detected. remote fault. After this set, remains until cleared reading register management interface. Able perform auto-negotiation function, value determined ANEGA pin. Unable perform auto-negotiation function. Link established, however, AC206 link fails, this cleared remains cleared until register read management interface. Link down, have been dropped. Jabber condition detect. Jabber condition detected. Extended register capable. This tied permanently one.
00001
Remote Fault
SC/LH
Auto-Negotiate Ability
Link Status
SC/LL
Jabber Detect
SC/LH
Extended Capability
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AC206
IDENTIFIER REGISTER
Table Identifier Register Reg.
2.15:0
Name
OUI*
Description
Assigned tifier (OUI), respectively.
Mode
through 18th bits Organizationally Unique Iden-
Default
0022 (HEX)
IDENTIFIER REGISTER
Table Identifier Register Reg.
3.15:10 3.9:4 3.3:0
Name
Description
Mode
24th
Default
010101 010100 0001
bits OUI. Assigned through Model Number manufacturer's model number; encoded 010001. Revision Number Four bits manufacturer's revision number. 0001 stands Rev. etc.
AUTO-NEGOTIATION ADVERTISEMENT REGISTER
Table Auto-Negotiation Advertisement Register
4.15
Name
Next Page
Definition
Desire Next Page. Next Page desired. This internally after receiving consecutive consistent bursts. Remote fault detected. remote fault. future technology. Tied zero indicates 100BASE-T4 support. 100BASE-TX with full duplex. 100BASE-TX full duplex ability. 100BASE-TX capable. 100BASE-TX capability. 10Mbps with full duplex. 10Mbps with full duplex capability. 10Mbps capable. 10Mbps capability. [00001] IEEE 802.3.
Mode
Default
4.14 4.13
Acknowledge Remote Fault
4.12:10
Reserved 100BASE-T4 100BASE-TX Full Duplex 100BASE-TX
10BASE-T Full Duplex 10BASE-T
4.4:0
Selector Field
00001
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AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER
Table Auto-Negotiation Link Partner Ability Register Reg.
5.15:0
Name
Technology
Description
Mode
Default
0001(H)
Technology capability field, which indicates technology capability link partner. definition same Reg. 4.15:0.
AUTO-NEGOTIATION EXPANSION REGISTER
Table Register Auto-Negotiation Expansion Register Reg.
6.15:5
Name
Reserved Parallel Detection Fault
Description
Mode
Default
0000 0000
Fault detected parallel detection logic. This caused SC/LH stable link, concurrent link condition. fault detected parallel detection logic. Link Partner Next Link partner supports next page function. Page Able Link partner does support next page function. Next Page Able Page Received link code word been received. contains SC/LH ceived link code word located Register Link Partner Auto- Link partner auto-negotiation able. Negotiation Able Link partner auto-negotiation able.
AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER
Table Auto-Negotiation Next Page Transmit Register Reg.
7.15 7.14 7.13 7.12
Name
Description
Mode
Default
7.11 7:10:0
Another Next Page desired. Reserved Message Page Message page. Un-formatted Page. ACK2 Acknowledge2. Will comply with message. comply with message. Toggle Previous value transmitted Link Code Word equal Previous value transmitted Link Code Word equal Code Message/Un-formatted Code Field.
0001
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AC206
CONTROL REGISTER
Table Control Register Reg. Name
16.15 Repeater
Description
Mode Default
16.14 16.13 16.12
Reserved TXJAM Disable
16.11
Test Inhibit
16.10 16.[9:6] 16:5 16.4
Normal Loop Back Reserved Auto polarity disable Reverse Polarity
16:[3:0]
Reserved
Repeater mode. Full-duplex inactive, only responds receive activity. test function also disabled. mode. 1=Force send pattern. 0=Normal operation mode Disable carrier integrity monitor function. Enable carrier integrity monitor function. Default Disable 10BASE-T testing. Enable 10BASE-T testing, which generates pulse following completion packet transmission. Enable 10BASE-T normal loop back. Disable 10BASE-T normal loop back. Disable auto polarity detection/correction. Enable auto polarity detection/correction. When Reg16.5 this sets Reverse Polarity detected media, otherwise zero. When Reg16.5 writing reverses polarity transmitter. Note: reverse polarity detected either through inverted through burst inverted FLP.
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INTERRUPT CONTROL/STATUS REGISTER
Table Interrupt Control/Status Register Reg. Name
17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 Jabber_IE Rx_Er_IE Page_Rx_IE PD_Fault_IE LP_Ack_IE Link_Schange_ R_Fault_IE Aneg_Comp_IE Jabber_Int Rx_Er_Int Page_Rx_Int
Description
Mode Default
Jabber Interrupt Enable. Receive Error Interrupt Enable. Page Received Interrupt Enable. Parallel Detection Fault Interrupt Enable. Link Partner Acknowledge Interrupt Enable. Link Status Changed Interrupt Enable. Remote Fault Interrupt Enable. Auto-Neg Complete Interrupt Enable. This when jabber event detected. This when RX_ER transitions high. This when page received from link partner during AutoNegotiation. PD_Fault_Int This when parallel detect fault detected. LP_Ack_Int This when with acknowledge received. Link_Schanged This when link status changed. R_Fault_Int This when remote fault detected. A_Neg_Comp This when Auto-Neg completed.
DIAGNOSTIC REGISTER
Table Diagnostic Register Reg.
18.15 18.14 18.13 18.12 18.11 18.10 18.9
Name
Lp_lpbk
Description
Mode
Default
18.8
18.[7:4] 18.[3:0]
Link pulse loopback. loopback link pulse auto-negotiation testing Send_nlp force link pulse generator send event auto-negotiation mode. Force link pass force base link pass Force link pass force link pass DPLX This indicates result Auto-Neg duplex arbitration. Speed This indicates result Auto-Neg data speed arbitration. RX_PASS 10BT mode, this indicates that Manchester data been detected. 100BT mode, indicates valid signal been received necessarily locked RX_LOCK Indicates receive locked onto received signal lected speed operation (10BASE-T 100BASE-TX). This whenever cycle-slip occurs, will remain until read. ARB_STATE Highest state Auto-Negotiation state machine since reset last read operation. HIGHEST ARB_STATE Lowest state Auto-Negotiation state machine since reset last read operation. LOWEST
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AC206
TEST REGISTER
Table Test Register Reg.
19.[15:9] 19.8 19.7 19.6 19.5 19.4 19.3 19.2 19.1 19.0
Name
Description
Mode
Default
00000
Reserved Reserved Error counter full Error count full. When indicates rx_error counter full receiver circuit. This event causes de-scrambler reset. disable disable error counter receiver module. Watch timer disable watch timer. Packet 10000 Byte causes scramdisable bler look seed. Low_pwr_mode disable power management disable enable power management Digital loop back enable digital loop back Test loop back enable test loop back Remote loop back enable remote loop back Jabber disable disable base jabber function
CABLE LENGTH REGISTER
Table Cable Length Register Reg.
20.[15:9] 20.8 20.[7:4]
Name
Description
Mode
Default
0000000 XXXX
20.[3:0]
Reserved Adaptation Disable adaptation disable Cable Length These bits indicate cable length from meters. Each Indication represents meters. example, cable length meters then bits [7:4] 1010. These bits only applicable 100TX mode. Adaptation Adaptation setting, when signal first detected. limit
XXXX
RECEIVE ERROR COUNT
Table Receive Error Count Reg.
21.[15:0]
Name
Description
Mode
Default
0000
Receive Error Count Count number receiving packets with error. This register only cleared reset (software hardware).
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POWER MANAGEMENT REGISTER
Table Power Management Register Reg.
22.[15:14] 22.13 22.12 22.11 22.10 22.9 22.8 22.[7:6] 22.5 22.4 22.3 22.2 22.1 22.0
Name
Description
Mode
Default
Reserved PD_PLL 1=Power down circuit PD_EQUAL 1=Power down equalizer circuit PD_BT_RCVR 1=Power down base receiver PD_LP 1=Power down link pulse receiver PD_EN_DET 1=Power down energy detect circuit PD_FX 1=Power down circuit Reserved MSK_PLL 0=Force power circuit MSK_EQUAL 0=Force power equalizer circuit MSK_BT_RCVR 0=Force power base receiver MSK_LP 0=Force power link pulse receiver MSK_EN_DET 0=Force power energy detect circuit MSK_FX 0=Force power circuit
OPERATION MODE REGISTER
Table Operation Mode Register Reg.
23.15 23.14 23.13 23.12 23.11 23.10 23.9 23:8 23.7 23:6 23.5
Name
Description
Mode
Default
23.[4:0]
Reserved Reserved Clk_rclk_save rclk save mode. Rclk shuts after cycles each packet Reserved Scramble disable disable scrambler Serial enable enable serial mode Pcsbp enable bypass mode timer enable timer adaptation disable timer adaptation. Reserved Reserved Force re-adapt force adaptation re-adapt Write this forces adaptation re-adapt. This always read Dlock drop lock drop counter counter
XXXXX
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AC206
RECENT RECEIVED PACKET
Table Recent Received Packet Reg.
24.[15:0]
Name
CRC16
Description
CRC16 value displayed. system level test purpose.
Mode
Default
0000H
EFFECT REGISTER
This registers defined whole chip. base address
EFFECT WITH PARTITION/ISOLATION EVENT
Table Effect with Partition/Isolation Event Reg.
15:12
Name
Blink Rate [7:4]
Description
Mode
Default
0001
11:10
Reserved with Part/ Event Reserved Blink with Part/ When Partition/Isolation, blink corresponding 1:0. Event Reserved with Part/ When Partition/Isolation, turn corresponding 1:0. Event
blink rate bits [7:0] with Effect with Partition/Isolation Event Register (PHY Addr Addr 18), abbreviated REG_LED_EFFECT following equation. Blink Rate (16ms {REG_LED_EFFECT[15:12], 4`b0000} When Partition/Isolation, turn corresponding 1:0.
EFFECT WITH LINK EVENT
Table Effect with Link Event Reg.
15:10
Name
Description
Mode
Default
00000
Reserved with Link Event When Link turn corresponding 1:0. Reserved Blink with Link When Link blink corresponding 1:0. Event Reserved with Link Event When Link turn corresponding 1:0.
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EFFECT WITH ACTIVITY (CRS) EVENT
Table Effect with Activity (CRS) Event Reg.
15:10
Name
Description
Mode
Default
00000
Reserved with Activity When Activity, turn corresponding 1:0. Event Reserved Blink with Activity When Activity, blink corresponding 1:0. Event Reserved with Activity When Activity, turn corresponding 1:0. Event
EFFECT WITH AUTO-NEGOTIATING EVENT
Table Effect with Auto-Negotiating Event Reg.
15:10
Name
Description
Mode
Default
00000
Reserved with Auto-ne- When Auto-negotiating, turn corresponding 1:0. gotiating Event Reserved Blink with Auto- When Auto-negotiating, blink corresponding 1:0. negotiating Event Reserved with Auto-ne- When Auto-negotiating, turn corresponding 1:0. gotiating Event
EFFECT WITH SPEED100 EVENT
Table Effect with Speed100 Event Reg.
15:10
Name
Reserved with Speed100 Event Reserved Blink with Speed100 Event Reserved with Speed100 Event
Description
When Speed100, turn corresponding 1:0.
Mode
Default
00000
When Speed100, blink corresponding 1:0.
When Speed100, turn corresponding 1:0.
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AC206
REGISTER CONTROL MODE
Table Register Control Mode Reg.
15:8
Name
Data Reserved Column
Description
value shown LED_D[7:0]. Control which lane LED_D should turned
Mode
Default
000000 000000
EEPROM TABLE
EEPROM used configure initial setting Bridge, Repeater, Transceiver.
Table EEPROM Address
Description
First Word Test Control Register0 Initial Repeater Configuration Register Bridge Control Register Reserved Reserved Initialize Port Control Register Initialize Port Control Register Initialize Port Control Register Initialize Port Control Register Initialize Port Control Register Reserved Effect with Partition/Isolation Event Effect with Link Event Effect with Activity (CRS) Event Effect with AutoNeg Event Effect with Speed Event
Default
5A3C 0080 0180 D000 3000 3000 3000 3000 3000 3000 3000 3000 1000 0330 0030 0000 0200
Assign
PHY=8, Reg=28 PHY=8, Reg=6 PHY=8, Reg=7
PHY=2, Reg=0 PHY=3, Reg=0 PHY=4, Reg=0 PHY=5, Reg=0 PHY=6, Reg=0 PHY=8, Reg=18 PHY=8, Reg=19 PHY=8, Reg=20 PHY=8, Reg=21 PHY=8, Reg=22
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4B/5B CODE-GROUP TABLE
Table 4B/5B Code-Group Table Code Group[4:0] SYMBOL Name
11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101
(TXD/RXD [3:0])
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0101 0101 Undefined Undefined
Description
Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Inter-Packet Idle; used inter-stream fill code. Start stream delimiter, part always pair with symbol. Start stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. Transmit Error; used send HALT code-group Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code
Idle Control Code
11111 11000 10001 01101 00111
Invalid Code
00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
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AC206
DISPLAY MATRIX
Display uses refresh technique. using display matrix, number ports drive significantly reduced. LED's assigned each port. Off, Flash states used indicate different information. With reduced counts, reduced number signals, display will easier route board, less costly.
LED_D[7]
LED_D[6]
LED_D[5]
LED_D[4]
LED_D[3]
LED_D[2]
LED_D[1]
LED_D[0]
LED_LN[5]
LED_LN[4]
LED_LN[3]
LED_LN[2]
LED_LN[1]
LED_LN[0]
Port
Figure
Port
Port
Port
Port
Display Matrix
SYSTEM CONSIDERATIONS
design chip optimized cost 10/100 repeater application. also provides flexibility more advanced systems with simple configurable architecture.
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AC206
ction Electr ristics
following electrical characteristics design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. -55oC +150oC Supply Referenced GND. -0.5V 2.5V Digital Input Voltage. -0.5V 3.3V Output Voltage. -0.5V
OPERATING RANGE
Operating Temperature (Ta). 70oC Supply Voltage Range (Vcc). 2.375V 2.625V
Table Total Power Consumption Parameter
Supply Current (per port)
Symbol
Conditions
BASE-T, Idle BASE-T, Normal activity BASE-TX 10/100 BASE-TX, power without cable Power down Mode Mode Mode Mode Master Slave, Bridge disabled Slave, Uplink Slave, Bridge enabled
Units
Supply Current (dual speed hub)
Table Characteristics Parameter
Input Voltage High Input Voltage Input Current Output Voltage High Output Voltage Output Current High Output Current
Symbol
Conditions
Units
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Table Characteristics (Cont) Parameter
Input Capacitance Output Transition Time Tristate Leakage Current |Ioz|
Symbol
Conditions
Units
2.375V VCC2.625
REFCLK PINS
Table REFCLK Pins Parameter
Input Voltage Input Voltage High Input Clock Frequency Tolerance Input Clock Duty Cycle Input Capacitance
Symbol
Conditions
Units
CHARACTERISTICS PINS
Table Characteristics Pins Parameter
Output Voltage Output High Voltage Input Current Output Current
Symbol
Conditions
Units
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AC206
BASE-TX TRANSCEIVER CHARACTERISTICS
Table BASE-TX Transceiver Characteristics Parameter
Peak Peak Differential Output Voltage Output Voltage Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot/Undershoot Output Jitter Receive Jitter Tolerance Output Current High Output Current High Common Mode Input Voltage Differential Input Resistance Note resistor each output Transformer 1.25:1 Transformer 1.25
Symbol
Trfs
Conditions
Note Note Note Note
0.98
1.02
Units
Scrambled Idle
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BASE-T TRANSCEIVER CHARACTERISTICS
Table BASE-T Transceiver Characteristics Parameter
Peak Peak Differential Output Voltage Start Idle Pulse Width Output Jitter Receive Jitter Tolerance Differential Squelch Threshold Common Mode Rejection Note resistor each output
Symbol
Conditions
Note
Units
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AC206
ction Digital Char acte ristics
POWER RESET
Table Power Reset Parameter
RST* Period Configuration
tRST tCONF
Conditions
Units
tRST
RST* Configuration Pins
tCONF
Figure
Power Reset
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MANAGEMENT DATA INTERFACE
Table Management Data Interface Parameter
Period High Period Receive Data Setup Time Receive Data Hold Time Transmit Data Delay Time
tMDCL tMDCH tRDS tRDH tTDD
Conditions
Units
Setup Read Cycle Hold Read Cycle Delay Write Cycle
tMDCL
tMDCH
tRDS
tRDH
MDIO (IN) MDIO
tTDD
Figure
Management Data Interface Timing
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AC206
7-WIRE INPUT TIMING
Table 7-Wire Input Timing Parameter
SNI_TXCLK Period SNI_TXCLK High Period SNI_TXCLK Period SNI_TXD/SNI_TXEN SNI_TXCLK Rising Setup Time SNI_TXD/SNI_TXEN SNI_TXCLK Rising Hold Time
tCKH tCKL
Units
tCKH SNI_TXCLK SNI_TXD
tCKL
SNI_TXEN
Figure 7-Wire Input Timing
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7-WIRE OUTPUT TIMING
Table 7-Wire Output Timing Parameter
SNI_RXCLK Period SNI_RXCLK High Period SNI_RXCLK Period SNI_RXCLK Rising SNI_RXD/ SNI_CRS/SNI_COL Output Delay
tCKH tCKL
Units
tCKH
SNI_RXCLK
tCKL
SNI_RXD
SNI_CRS/ SNI_COL
Figure
7-Wire Output Timing
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AC206
100BASE-TX INPUT TIMING
Table 100BASE-TX Input Timing Parameter
MII_TXCLK Period MII_RXCLK High Period MII_RXCLK Period MII_TXD, MII_TXEN MII_TXCLK Rising Setup Time MII_TXD, MII_TX_EN MII_TXCLK Rising Hold Time
tCKH tCKL tTXS tTXH
Units
tCKH
MII_TXCLK
Start Packet tCKL
Packet
tTXS
MII_TXEN
tTXH
MII_TXD
Figure
100BASE-TX Input Timing
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100BASE-TX OUTPUT TIMING
Table 100BASE-TX Output Timing Parameter
MII_RXCLK Period MII_RXCLK High Period MII_RXCLK Period MII_CRS Rising MII_RXDV Rising MII_RXCLK Rising MII_RXD, MII_RXDV, MII_CRS Output Delay
tCKH tCKL tCSVA tRXOD
Units
tCKH
MII_RXCLK
Start Packet tCKL
Packet
tRXOD
MII_RXDV
tCSVA
MII_RXD
MII_CRS
Figure
100BASE-TX Output Timing
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AC206
10BASE-TX INPUT TIMING
Table 10BASE-TX Input Timing Parameter
MII_TXCLK Period MII_RXCLK High Period MII_RXCLK Period MII_TXD, MII_TXEN MII_TXCLK Rising Setup Time MII_TXD, MII_TX_EN MII_TXCLK Rising Hold Time
tCKH tCKL tTXS tTXH
Units
tCKH
MII_TXCLK
Start Packet tCKL
Packet
tTXS
MII_TXEN
tTXH
MII_TXD
Figure
10BASE-TX Input Timing
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10BASE-TX OUTPUT TIMING
Table 10BASE-TX Output Timing Parameter
MII_RXCLK Period MII_RXCLK High Period MII_RXCLK Period MII_CRS Rising MII_RXDV Rising MII_RXCLK Rising MII_RXD, MII_RXDV, MII_CRS Output Delay
tCKH tCKL tCSVA tRXOD
Units
tCKH
MII_RXCLK
Start Packet tCKL
Packet
tRXOD
MII_RXDV
tCSVA
MII_RXD
MII_CRS
Figure
10BASE-TX Output Timing
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AC206
100MBPS REPEATER BACKPLANE RECEIVE/TRANSMIT TIMING
Table 100Mbps Repeater BackPlane Receive/Transmit Timing Parameter
MS100D_CLK Period MS100D_CLK High period MS100D_CLK period RXIP/N Control Assert RXIP/N Control De-assert RXIP/N M100COL_SYS* Assert Control Falling MS100CRS_SYS*/ MS100D_EN Falling Delay Time MS100D MS100D_CLK Rising Setup Time MS100D MS100D_CLK Rising Hold Time Control Assert TXOP/N Valid Control De-assert TXOP/N Invalid
tCKH tCKL tCCS tCSC tCLT tCHT
Units
Control combination following signals: M100ACT0*, M100ACT1_0*, M100ACT1_1*, M100ACT1_2*
Start Packet RXIP/N Control* tCCS M100COL_SYS* MS100CRS_SYS*/ MS100D_EN* tCSC tCKH MS100D_CLK MS100D tCLT TXOP/N
Packet
tCKL
tCHT
Figure
100Mbps Receive/Transmit Timing
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10MBPS REPEATER BACKPLANE RECEIVE/TRANSMIT TIMING
Table 10Mbps Repeater BackPlane Receive/Transmit Timing Parameter
MS10D_CLK Period MS10D_CLK High Period MS10D_CLK Period RXIP/N Control Assert RXIP/N Control De-assert RXIP/N C10COL_SYS* Assert Control Falling MS10CRS_SYS*/MS10D_EN* Falling Delay Time MS10D M10D_CLK Rising Setup Time MS10D MS10D_CLK Rising Hold Time Control Assert TXOP/N Valid Control De-assert TXOP/N Invalid
tCKH tCKL tCCS tCLT tCHT
Units
4000
Control combination following signals: M10ACT0*, M10ACT1_0*, M10ACT1_1*, M10ACT1_2*
RXIP/N Control* tCCS M10COL_SYS* MS10CRS_SYS*/ MS10D_EN*
tCSC tCKH
tCKL
MS10D_CLK MS10D tCLT TXOP/N tCHT
Figure
10Mbps Receive/Transmit Timing
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AC206
EEPROM INTERFACE TIMING
Table EEPROM Interface Timing Parameter
PROM_CLK Period PROM_CLK Period PROM_CLK High Period PROM_IN PROM_CLK Rising Hold Time PROM_IN PROM_CLK Rising Hold Time PROM_CLK Falling PROM_OUT Output Delay Time
tECK tECKL tECKH tERDS tERDH tEWDD
2550 2550
5120
2570 2570
Units
PROM_CS tECKH PROM_CLK tEWDD tECK PROM_OUT tERDS PROM_IN tERDH tECKL
Figure EEPROM Interface Timing
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10/100BASE-TX REVERSE OUTPUT TIMING
Table 10/100BASE-TX Reverse Output Timing Parameter
RvMII_TXCLK Rising RvMII_TXD, RvMII_TXEN Output Delay TIme
tTXOD
Units
RvMII_TXCLK tTXOD RvMII_TXEN
RvMII_TXD
Figure
10/100BASE-TX RvMII Output Timing
10/100BASE-TX REVERSE INPUT TIMING
Table 10/100BASE-TX Reverse Input Timing Parameter
RvMII_RXD, RvMII_RXDV, RvMII_CRS RvMII_RXCLK Rising Setup Time RvMII_RXD, RvMII_RXDV, RvMII_CRS RvMII_RXCLK Rising Hold Time
tRDS
Units
tRDH
RvMII_RXCLK tRDH RvMII_RXDV tRDS RvMII_RXD
Figure
10/100BASE-TX RvMII Input Timing
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AC206
TIMING
Table Timing Parameter
Pulse Width LED_D[n] Falling LED_D[n+1] Falling LED_D[n] Falling LED_D[n] Falling
Conditions
Units
LED_LN[5:0] LED_D[7] LED_D[6] LED_D[5] LED_D[4] LED_D[3] LED_D[2] LED_D[1] LED_D[0]
Figure Timing
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APPLICATION TERMINATION
2.5V
49.9
49.9
AC206 Transformer TXON TXOP TXC_P TX+_P TX-_P RX+_P RX-_P RXC_P
RJ45 Unused Unused Unused Unused
TXC_S TX+_S TX-_S RX+_S RX-_S RXC_S
IBREF
RXIP
RXIN
1000
Chassis
Figure
Application Termination
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AC206
Table Package Dimensions AC206
3.40
0.25
0.50
0.88
1.60 0.12
2.70 0.200 23.20 20.00 18.5 17.20 14.00 12.50 0.25 0.10 0.10 0.25 0.10 0.10
Figure
128-pin PQFP
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AC206
ction rdering nforma tion
PART NUMBER
AC206KQM
PACKAGE
128-pin PQFP
AMBIENT TEMPERATURE
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AC206
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Altima Communications, Inc.
Wholly Owned Subsidiary Broadcom Corporation P.O. 57013 16215 Alton Parkway Irvine, California 92619-7013
Phone: 949-450-8700 Fax: 949-450-8710
Broadcom Corporation reserves right make changes without further notice products data herein improve reliability, function, design. Information furnished Broadcom Corporation believed accurate reliable. However, Broadcom Corporation does assume liability arising application this information, application product circuit described herein, neither does convey license under patent rights rights others.
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2.5V 10/100-TX 5-Port Repeater/4+1 Uplink Port with Bridge Controller

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