2.5V 10/100-TX 5-Port Repeater with Bridge Controller GENERAL DES

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2.5V 10/100-TX 5-Port Repeater with Bridge Controller GENERAL DES

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AC205
2.5V 10/100-TX 5-Port Repeater with Bridge Controller
GENERAL DESCRIPTION AC205 5-port 10/100Mbps integrated repeater with bridge controller. AC205 provides cost integrated solution unmanaged repeater applications. AC205 Class Repeater that fully compliant with IEEE 802.3 standards. device provides five 10/100 Mbps copper media ports. AC205 also provides selectable MII/7-wire interface. MII/7-wire interface connected Switch managed repeater stack hybrid Switch/Repeater Applications. AC205 provides 10/100 Mbps auto-negotiation parallel detection ports. However, option configure technology each port EEPROM interface available. AC205 provides internal repeater state machines, operating Mbps other Mbps. Once technology set, device automatically connects each port appropriate repeater segment. AC205 integrates repeater controller switch engine technologies with "store forward" forwarding mechanisms. FEATURES power (<1A total current consumption when used with 1.25;1 transfor mer) five 10/100 Mbps integrated repeater controller with built-in bridge function. MDC/MDIO control/status. Five integrated 10/100 Mbps IEEE 802.3u compliant transceivers. Fully integrated adaptive equalizer provides phase/ amplitude compensation various cable lengths 30dB 100MHz. Patent-pending restoration technique reduces offset/baseline wander. IEEE 802.3u-compliant auto-negotiation. Unique scrambler seed port better EMI. Supports media independent interface (MII) 7-wire interface connect MAC. Non-blocking 10/100M bridge with controller switching engine. segment bridge fixed Mbps while other segment configured Mbps. Bridge functions include: Embedded bytes memory address table packet buffer. Local address filtering. hashing scheme. Short routing decision time. Forwarding schemes: store-and-forward. Address table entries. Programmable display activity, link, speed, partition, utilization, collision rate. Advanced power management includes: Each port turned independently. Standby mode, which reduces power when port connected. power 2.5V 0.25µm CMOS implementation with 100-pin package. Input Tolerance 3.3V
256Kbits
Bridge
100M
R_100
R_10
MII/ 7-Wire
100M
7Wire
(TX0)
(TX1)
(TX2)
(TX3)
(TX4)
Figure
Functional Block Diagram
AC205-DS03-R 09/21/01
16215 Alton Parkway P.O. 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
REVISION HISTORY
Revision
AC205-DS00-R AC205-DS01-R
Date
10/9/00 02/08/01
Change Description
Initial release Changed "DGND" Table Power Ground. Updated text "Scrambler" subsection "Functional Description" read that "When Control register 23.11 data scrambling function disabled, 5-bit data stream clocked directly device's sublayer." Updated Section "Electrical Characteristics", Section Digital Timing Characteristics. Added Section "Mechanical Information", outlining packaging specifications. Updated Digital Input Voltage from "-0.5V Vcc" "-0.5V 3.3V" Section Electrical Characteristics. Updated Timing Information. Updated Figure Removed Table MII-A (Media Independent Interface) Pins. Updated Table Connects, include pins Updated "Functional Description" page Various text changes. Updated Figure Display Matrix. Updated Table Connections. Updated Table Power Ground. Updated Table Register Set. Updated Table Bridge Control Register. Updated Table Control Register. Updated Table Effect with Partition/Isolation Event. Updated Table EEPROM. Updated Table "Power Ground," page
AC205-DS02-R 06/19/01
AC205-DS03-R
09/21/01
Altima Communications, Inc. Wholly Owned Subsidiary Broadcom Corporation P.O. 57013 16215 Alton Parkway Irvine, California 92619-7013 2001 Altima Communicaitons, Inc. rights reserved Printed U.S.A.
Broadcom®, pulse logo®, QAMLink® registered trademarks Broadcom Corporation and/or subsidiaries United States certain other countries. other trademarks property their respective owners.
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AC205
TABLE CONTENTS
Section Functional Description.
Functional Description Clocks, Reset Power Management Functions Transceiver Transmit Function Scrambler. Parallel Serial NRZI MLT-3 Conversion. Multimode Transmit Driver Clock Synthesizer. Receive Function Adaptive Equalizer Link Monitor Baseline Wander Compensation Clock/Data Recovery Decoder/Descrambler Auto-Negotiation Miscellaneous Functions Parallel Detection. Carrier Sense/RXDV Port Only. Cable Length Monitor Bridge Function. Interface Address Recognition. Reset Restart Media Access Control Initialization Setup Hardware Configuration Software Configuration LEDs Addressing Algorithm, Routing, Learning Aging Address Table. Address Recognition. Routing Decision. Learning Process
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Aging Time Forwarding Scheme Buffer Management Queues
Section Pins.
Descriptions Display/Configuration/PROM Interface.14
Section Register Descriptions
Register Description.17 Port Status Register Initial Repeater Configuration Register.18 Bridge Control Register Registers Control Register.20 Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register.23 Auto-Negotiation Next Page Transmit Register.23 Control Register Interrupt Control/Status Register Diagnostic Register Test Register Cable Length Register.26 Receive Error Count Power Management Register Operation Mode Register Recent Received Packet Test Effect Register Effect with Partition/Isolation Event Effect with Link Event Effect with Activity (CRS) Event Effect with Auto-Negotiating Event
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AC205
Effect with Speed100 Event. Register Control Mode EEPROM Table 4B/5B Code-Group Table Display Matrix. System Considerations
Section Electrical Characteristics.
Absolute Maximum Ratings Operating Range REFCLK Pins. Characteristics LED/CFG Pins BASE-TX Transceiver Characteristics BASE-T Transceiver Characteristics.
Section Digital Timing Characteristics
Power Reset 7-Wire Input Timing. 7-Wire Output Timing. 100BASE-TX Input Timing 100BASE-TX Output Timing 10BASE-TX Input Timing 10BASE-TX Output Timing EEPROM Interface Timing Timing Application Termination
Section Mechanical Information. Section Ordering Information.49
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AC205
LIST FIGURES
Figure Functional Block Diagram Figure Exclusive Hashing Algortithm. Figure Address Learning Recognition Figure Basic Memory Management Concept Figure Display Matrix. Figure Power Reset. Figure 7-Wire Input Timing Figure 7-Wire Output Timing Figure 100BASE-TX Input Timing Figure 100BASE-TX Output Timing Figure 10BASE-TX Input Timing Figure 10BASE-TX Output Timing Figure EEPROM Interface Timing Figure Timing. Figure Application Termination. Figure 100-pin PQFP.
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AC205
LIST TABLES
Table Connections. Table Content Address Lookup Table Table Embedded Memory Structure. Table (Media Dependent Interface) Pins (TX) Table MII-B (Media Independent) Pins Table 7-wire (Serial Network Interface) Pins Table Serial Configuration Prom Table Serial Management Interface Table Pins. Table Control Set-up Table Clock Reset Table Power Ground Table Connects. Table Register Set. Table Port Status Register Table Port Status. Table Initial Repeater Configuration Register. Table Bridge Control Register Table Control Register Table Status Register Table Identifier Register Table Identifier Register Table Auto-Negotiation Advertisement Register Table Auto-Negotiation Link Partner Ability Register Table Register Auto-Negotiation Expansion Register Table Auto-Negotiation Next Page Transmit Register. Table Control Register Table Interrupt Control/Status Register Table Diagnostic Register Table Test Register Table Cable Length Register. Table Receive Error Count
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Table Power Management Register Table Operation Mode Register Table Recent Received Packet.28 Table Effect with Partition/Isolation Event.28 Table Effect with Link Event.28 Table Effect with Activity (CRS) Event Table Effect with Auto-Negotiating Event Table Effect with Speed100 Event Table Register Control Mode Table EEPROM Table 4B/5B Code-Group Table Table Total Power Consumption.33 Table Characteristics Table REFCLK Pins Table Characteristics LED/CFG Pins Table BASE-TX Transceiver Characteristics Table BASE-T Transceiver Characteristics.35 Table Power Reset Table 7-Wire Input Timing.38 Table 7-Wire Output Timing Table 100BASE-TX Input Timing Table 100BASE-TX Output Timing Table 10BASE-TX Input Timing Table 10BASE-TX Output Timing Table EEPROM Interface Timing.44 Table Timing Table Package Dimensions AC205
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AC205
FUNCTIONAL DESCRIPTION
AC205 integrated 10/100Mbps repeater with bridge function. device provides five 10/100BASE-TX twisted pair interface ports interface. interface selected 7-wire used connect Switch managed repeater stack hybrid Switch/Repeater Applications. AC205 also includes built-in 2segment switch 10/100Mbps connection. AC205 provides highest integration chip solution dual speed system. result ultra power consumption that consumes less than maximum when ports running 100BASE-TX full-speed. built-in power management function powers down individual port when used cable detected) which further drives down power consumption improves long-term reliability.
CLOCKS, RESET POWER MANAGEMENT FUNCTIONS
AC205 requires single clock signal input pin. internal generates clock frequencies needed device from single clock input. AC205 reset ways: During initial power Hardware reset: logic signal pulse width applies pin.
During reset, mode pins latch internal address table initialized, internal state machine reset known states. completion reset sequence, ports enabled frame reception transmission. AC205 offers following power management: Power down mode: This achieved writing register 0.11 plus port based address. example, port based address During power down, device able respond through serial management interface. Energy detects mode: device powers down unused circuitry when cable installed. Energy Detect (ED) circuit stays monitor incoming signals from media. portion turned response management transaction. transmit circuit sends link pulse with minimum power consumption. valid signal received from media, device powered resumes normal transmit/receive operation.
TRANSCEIVER TRANSMIT FUNCTION
100BASE-TX mode, Transceiver transmits MLT-3 signal cable isolation transformer. MLT-3 data three level signal data. This data scrambled when transmitted media. MLT-3 data synchronous clock. 10BASE-T mode, Manchester code generated 10Base-T core logic, which synthesizes through output waveshaping driver. This helps reduce emission, which eliminates need external filter.
transmit data interface 4-bit nibbles 25/2.5 rate. This data transferred from controller into repeater controller lines. controller asserts TX_EN during transmission, forces error encoded data using TX_ER.
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SCRAMBLER
100BASE-TX mode, internal 5-bit transmit data stream scrambled defined TP-PMD Stream Cipher function order reduce radiated emissions twisted pair cable. scrambler encodes plain text stream using stream periodic sequence 2047 bits generated recursive linear function: [n-11] [n-9] (modulo scrambler reduces peak emissions randomly spreading signal energy over transmit frequency range, thus eliminating peaks single frequency. emission further reduced assigning unique scrambled seed each port. When Control register 23.11 data scrambling function disabled, 5-bit data stream clocked directly device's sublayer.
PARALLEL SERIAL NRZI MLT-3 CONVERSION
internal 5-bit data clocked into Transceiver's shift register with clock, clocked with clock convert into serial stream. Both clocks generated on-chip clock synthesizer, they sync each other. serialized data further converted from NRZI format, which produces transition every Logic transition Logic further reduce emission, NRZI data converted MLT-3 signal. effect offers reduction emissions over un-converted NRZI signals, thus increases output signals' margin operating within Class limit. When there transition occurring NRZI data, there corresponding transition MLT-3 data. NRZI data, changes count up/down direction after every single transition. MLT-3 data, changes count up/down direction after every transitions. NRZI MLT-3 data conversion implemented without reference timing clock information. conversion requires detecting transition incoming NRZI data count up/down direction MLT-3 data. Asserting FX_SEL high bypasses this encoding.
MULTIMODE TRANSMIT DRIVER
multimode driver transmits MLT-3 coded signal 100BASE-TX mode Manchester coded signal 10BASE-T mode. slew rate transmitted MLT-3 signal controlled eliminate high frequency component. MLT-3 signal after magnetic typical rise/fall time approximately which within target range specified ANSI standard. 10BASE-T mode, high frequency pre-emphasis performed which extends cable-driving distance without need external filter. FLP/NLP also drive through 10BASe-T driver. 10BASE-T 100BASE-TX transmit signals multiplexed transmit output driver. This arrangement results using same external transformer both 10BASE-T 100BASE-TX. driver output level built-in bandgap reference external resistor connected RIBB output pin. resistor sets output current modes operation. Each TXOP/N outputs open drain device which source resistance maximum current rating Vp-p MLT3 signal, 5Vp-p Manchester signal when used transformer.
CLOCK SYNTHESIZER
Transceiver also includes on-chip clock synthesizer that generates 125MHz 25MHz clock 100BASETX 100MHz 20MHz clock 10BASE-T Auto-Negotiation operations. clock generator uses fully differential cell that induces very jitter. Zero Dead Zone Phase Detection method implemented this design provides excellent phase tracking. charge pump with charge sharing compensation also included further reduce jitter different loop filter voltages. On-chip loop filter eliminates need external components avoids external noise pickup. Only external 25MHz crystal signal source required reference clock.
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AC205
RECEIVE FUNCTION
100BASE-TX mode, receive function implements reverse order function transmit path. includes receiver with adaptive equalization restoration, MLT-3 NRZI conversion, data clock recovery 125MHz, NRZI conversion, Serial-to-Parallel conversion, de-scrambling, decoding. receiver circuit starts with bias differential RX+/- inputs, follows with low-pass filter filter high frequency noise from transmission channel media. energy detect circuit also added determine whether there signal energy media. This useful power-saving mode. amplification ratio slicer threshold on-chip bandgap reference. 10BASE-T mode, signal first passes through order lowpass filter, which filters noise from cable, board, transformer. This eliminates need 10BASE-T external filter. Manchester decoder Serial-to Parallel follows generate 4-bit data mode.
ADAPTIVE EQUALIZER
Each eight transceivers designed accommodate maximum cable length meters CAT5 cable. meters CAT-5 cable, such AT&T 1061, attenuation MHz. typical attenuation 100-meter cable worst case attenuation around 24-26 defined TP-PMD. amplitude phase distortion from cable causes inter-symbol interference (ISI) which makes clock data recovery impossible. Adaptive equalizer done matching inverse transfer function twist-pair cable. This variable equalizer that changes equalizer frequency response accordance cable length. cable length estimated based comparisons incoming signal strength against some known cable characteristics. equalizer monotonically frequency response, tunes itself automatically cable length compensate amplitude phase distortion incurred from cable.
LINK MONITOR
Signal levels detected through squelch detection circuitry. signal detect (SD) circuit follows equalizer asserted high when peak detector detects post-equalized signal with peak ground voltage level larger than This approximately normal signal voltage level. addition, energy level must sustained longer than order signal detects asserted. gets de-asserted approximately after energy level consistently less than from peak ground. 100BASE-TX mode, when signal invalid signal detected receive pair, link monitor enters link fail state where only scrambled idle code transmitted. When valid signal detected minimum period time, link monitor enters link pass state transmit receive functions entered. 10BASe-T mode, link-pulse detection circuit constantly monitors RXIP/RXIN pins presence valid link pulses.
BASELINE WANDER COMPENSATION
100BASE-TX data stream always balanced. transformer blocks component incoming signal, thus offset differential receives inputs wander. shift signal levels, coupled with non-zero rise fall times serial stream cause pulse-width distortion, creating jitter possible increases error rates. Therefore, restoration circuit needed compensate attenuation component. Transceiver implemented patent-pending restoration circuit, unlike traditional implementation; does need feedback information from slicer clock recovery. This only simplifies system/circuit design also eliminates random/systematic offset receive path. 10BASE-T mode, baseline wander correction circuit required bypassed.
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CLOCK/DATA RECOVERY
equalized MLT-3 signal passes through slicer circuit that converts NRZI format. Transceiver uses mixedsignal phase locked loop (PLL) extract clock information incoming NRZI data. extracted clock used re-time data stream data boundaries. transmit clock locked 25MHz clock input while receive clock locked incoming data streams. When initial lock achieved, switches lock data stream, extracts 125MHz clock uses that framing recover data. recovered 125MHz clock also used generate internal 25MHz RX_CLK. requires external components operation high noise immunity jitter. provides fast phase align (lock) data transition data/clock acquisition time after power-on less than transitions. maintain lock run-lengths data bits absence signal transitions. When valid data present, i.e. when de-asserted, switches back lock with TX_CLK, provides continuously running RX_CLK.
DECODER/DESCRAMBLER
descrambler detects state transmit Linear Feedback Shift Register (LFSR) looking sequence representing consecutive idle codes. descrambler acquires lock with data stream recognizing IDLE bursts more bits locking de-ciphering Linear Feedback Shift Register (LFSR). Once lock acquired, device operates with inter-packet-gap (IPG) Before lock occurs, descrambler requires minimum idle between packet order acquire lock. deciphering logic also tracks number consecutive receive errors detected while RX_DV asserted. Once error counter exceeds limit (currently consecutive errors), logic assumes that lock been lost, decipher circuit resets itself. process regaining lock begins again. Stream cipher de-scrambler used 10BASE-T mode.
AUTO-NEGOTIATION MISCELLANEOUS FUNCTIONS
Each Transceiver contains ability negotiate mode operation over twisted pair using auto-negotiation mechanism defined clause IEEE 802.3u specification. Auto-negotiation disabled software EEPROM. Transceiver automatically chooses mode operation detecting incoming signal. During auto-negotiation, auto-negotiation advertisement register sent link partner through series fast link pulse (FLP). When auto-negotiation enabled, Transceiver sends during following conditions: power link loss, restart command. same time, device monitors incoming data determine mode operation. Parallel detection circuit enabled soon 10BASE-T idle 100Base-TX idle detected. mode operation configured based technology incoming signal. When device receives burst from link partner with identical link code words (ignoring acknowledge bit), stores these code words auto-negotiation link partner ability register waits next identical code word. Once device detects second code word, configures itself highest technology that common both ends. technology priorities 100BASE-TX, half-duplex, 10BASE-T half-duplex. Once auto-negotiation complete, status register reflects actual speed that chosen.
PARALLEL DETECTION
Transceiver also checks 10BASE-T 100BASE-TX idle symbols. either detected, device automatically configures match detected operating speed half-duplex mode. This ability allows device communicate with legacy 10BASE-T 100BASE-TX systems.
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AC205
CARRIER SENSE/RXDV PORT ONLY
Carrier sense asserted asynchronously pins soon activity detected receive data stream. RX_DV asserted soon valid (Start-of-Stream Delimiter) detected. Carrier sense RX_DV deasserted synchronously upon detection valid stream delimiter consecutive idle code groups receive data stream. carrier sense asserted valid detected immediately, RX_ER asserted instead RX_DV. 10BASe-T mode, carrier sense asserted asynchronously when valid preamble activity detected RXIP/RXIN pins. half duplex mode, activated during transmit receive data.
CABLE LENGTH MONITOR
AC205 also detect length cable display result interrupt control/status register, i.e., 0000 stands cable used, 0001 stands meter cable, 1111 stands meter cable. This especially useful management functions. detects proper connectivity cable helps manage cable distribution.
BRIDGE FUNCTION
INTERFACE
Switch engine supports 10/100Mbps. Port switch engine support either 100, while port supports only Mbps. Refer mode table configure port
FORWARDING SCHEME
switch supports store-and-forward scheme only. does support cut-through-forward. With store-and-forward, incoming packet should completely received buffer without error before sent out.
ADDRESS RECOGNITION
self-learning bridge function based source address field packets. switch uses hashing algorithm address look-up table. Programmable aging time fast aging control supported.
RESET RESTART
When switch engine power initially goes SRAM self-test mode. generates patterns evaluate SRAM status.
MEDIA ACCESS CONTROL
switch engine implements functions IEEE 802.3 protocol such frame formatting, collision handling. generates 56-bit preamble start frame delimiter while packet sending. half duplex mode, device listens before transmitting, prevent traffic jam. During collision, packet retransmitted random time.
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INITIALIZATION SETUP
HARDWARE CONFIGURATION
Several different states operation chosen through hardware configuration. External pins pulled high reset time. combination high values determines power state device. Many these pins multi-function pins which change their meaning when reset ends.
SOFTWARE CONFIGURATION
Several different states operation chosen through MDC/MDIO interface. Refer Section "Register Descriptions".
LEDS
Using display matrix with refresh technique, only pins required drive LEDs with unique information. Off, Flash states used indicate different information. With reduced number signals, display easier route board, less costly. active-low data driven LED_D[0:7] pins each port corresponding functions LED_LN[5:0] pin. Refer to"LED Display/Configuration/PROM Interface" "LED Display Matrix" details. AC205 supports LEDs port. following table describes each connected. Signals LED_D[2:6] indicators port through Signals LED_LN[0:5] events driven port through
Table Connections Signals
LED_LN[0] LED_LN[1] LED_LN[2]
Events
Link Status/Activity Speed/Partition Display utilization bridge segment (100 Mbps)
Descriptions
Active indicates 100M link good. Blinking indicates 100M activity. Active indicates link good. Blinking indicates activity. LED_LN[2] active low, indicating 100M utilization. Utilization indicator port basis, rather segment basis. LED_D[0:7] indicates percentage utilization. LED_D[0:7] Percent Util.
LED_LN[3]
Display utilization bridge segment Mbps)
LED_LN[3] active low, indicating utilization. Utilization indicator port basis, rather segment basis. LED_D[0:7] indicates percentage utilization. LED_D[0:7] Percent Util.
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AC205
Table Connections (Cont.) Signals
LED_LN[4]
Events
Display collision bridge segment (100 Mbps)
Descriptions
LED_LN[4] active low, indicating collision. Collision indicator port basis, rather segment basis. LED_D[1:7] indicates percentage collision. However, LED_D0 only indicates collision occurrence. LED_D[0:7] Percent Col.
LED_LN[5]
Display collision bridge segment Mbps)
LED_LN[5] active low, indicating collision. Collision indicator port basis, rather segment basis. LED_D[1:7] indicates percentage collision. However, LED_D0 only indicates collision occurrence. LED_D[0:7] Percent Col.
ADDRESSING ALGORITHM, ROUTING, LEARNING AGING
ADDRESS TABLE
address table store entries each entry consists 48-bit address, 8-bit port identifier, 1-bit indication flag 6-bit aging timer.
Table Content Address Lookup Table 3130
MAC#3 Timer Port# MAC#4 MAC#1 MAC#5 MAC#2 MAC#6
Entry valid empty indication, valid entry, empty entry. 29-24: Aging timer. 23-16: Port number
ADDRESS RECOGNITION
exclusive addressing algorithm used address lookup table addressing. Refer Figure
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MAC#6
MAC#4
MAC#2
Hashed address[15:0]
MAC#5
MAC#3
MAC#1
Figure
Exclusive Hashing Algortithm
final address address lookup table hashed address[9:0].
ROUTING DECISION
record empty, packet broadcast treated unknown frame. Otherwise, record read, compared with current addresses same, port number decided, packet forwarded assigned port. address collision occurred, different address, incoming packet considered unknown packet.
LEARNING PROCESS
address learning process composed packets addressing algorithm described above. switch checks each incoming packets integrity buffers availability. packet error-free buffer available, port number pair packet written into address lookup table. Figure describes general operations address learning recognition.
Hashing Function
[9:0] Address Entry Point
AAA-1 AAA+1
Address Lookup
Figure Address Learning Recognition
AGING TIME
switch automatically examines status address lookup table. round robin speed checking timer dependent aging time. switch aging time seconds. When aging timer started after power switch guaranties that free spaces released from occupied address entries.
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AC205
FORWARDING SCHEME
store-and-forward algorithm used. incoming packet completely stored buffer verified errorfree before forwarding operations take place.
BUFFER MANAGEMENT QUEUES
switch buffering management continues store received packets into memory. buffer size 100M port bytes, bytes port.
Start Address Read Point Write Point Free buffer Address
Port Buffer Management
Figure
Basic Memory Management Concept
switch uses pointers control port buffer status. Start Address point beginning memory address each port Address point last address memory each port. Read/Write shadow Read/Write pointers dynamically changed depending current outgoing incoming packets storage. Write pointer reaches Read pointer size between write read pointers smaller than bytes, buffer full. other hand, when read/write pointers equal, buffer empty.
Table Embedded Memory Structure
0x0000 0x07FF 0x0800 0x17FF 0x1800 0x1FFF address lookup table 100M Bridge Port
Bridge Port
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AC205
Section Pins
DESCRIPTIONS
Many these device pins have multiple functions. separate descriptions each listed proper sections. Designers must assure that they have identified modes operation prior final design. assignment shown below description table subjected change without notice. user advised contact Altima Communications Inc. before implementing design based information provided this data sheet. Signals types: Input Output High impedance Pull with Pull down with Schimitt Trigger Analog signal Power Ground Active Signal
Table (Media Dependent Interface) Pins (TX) Name
RXIP_4 RXIP_3 RXIP_2 RXIP_1 RXIP_0 RXIN_4 RXIN_3 RXIN_2 RXIN_1 RXIN_0 TXOP_4 TXOP_3 TXOP_2 TXOP_1 TXOP_0
Type
Description
Receiver Input Positive both 10BASE-T 100BASE-TX.
Receiver Input Negative both 10BASE-T 100BASE-TX.
Transmitter Output Positive both 10BASE-T 100BASE-TX.
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Table (Media Dependent Interface) Pins (TX) (Cont.) Name
TXON_4 TXON_3 TXON_2 TXON_1 TXON_0
Type
Description
Transmitter Output Negative both 10Base-T 100Base-TX.
Table MII-B (Media Independent) Pins Name
MIIB_TXD3 MIIB_TXD2 MIIB_TXD1 MIIB_TXD0 MIIB_TXCLK
Type
Description
Transmit Data. will source MIIB_TXD[3:0] synchronous with MIIB_TXCLK when MIIB_TXEN asserted.
O,D,S
Transmit Clock. Continuous (25MHz/2.5MHz) clock output used synchronize MIIB_TXEN, MIIB_TXD[3:0], MIIB_TXER. Transmit Enable. Indicates presented valid data MIIB_TXD[3:0]. Receive Data. will source MIIB_RXD[3:0] synchronous with MIIB_RXCLK when MIIB_RXDV asserted. After power MIIB_SPDSEL latched port speed selection. 1=100Mb, 0=10Mb Transmit Clock. Continuous (25MHz/2.5MHz) clock output used synchronize MIIB_RXDV, MIIB_RXD[3:0], MIIB_RXER. Receive Data-Valid. presented valid recovered MIIB_RXD[3:0]. Carrier Sense. Active when carrier been sensed. Receive Error. Indicates received invalid symbol data. Collision Detection. Active when collision detected.
MIIB_TXEN MIIB_RXD3/MIIB_SPDSEL MIIB_RXD2/MODE3 MIIB_RXD1/TP125 MIIB_RXD0 MIIB_RXCLK
I/O,U I/O,D I/O,U O,D,S
MIIB_RXDV MIIB_CRS MIIB_RXER MIIB_COL
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AC205
Table 7-wire (Serial Network Interface) Pins Name
SNI_TXD (MIIB_TXD0) SNI_TXCLK (MIIB_TXCLK) SNI_TXEN (MIIB_TXEN) SNI_RXD (MIIB_RXD0) SNI_RXCLK (MIIB_RXCLK) SNI_CRS (MIIB_CRS) SNI_COL (MIIB_COL)
Type
Description
Serial Transmit Data. will source SNI_TXD synchronous with SNI_TXCLK when SNI_TXEN asserted. Serial Transmit Clock. Continuous (10MHz) clock output used synchronize SNI_TXEN SNI_TXD. Serial Transmit Enable. Indicates presented valid data SNI_TXD. Serial Receive Data. will source SNI_RXD synchronous with SNI_RXCLK when SNI_CRS asserted. Serial Receive Clock. Continuous (10MHz) clock output used synchronize SNI_CRS SNI_RXD. Serial Carrier Sense. Active when carrier been sensed. Serial Collision Detection. Active when collision detected.
Table Serial Configuration Prom Name
PROM_CS PROM_CLK (LED_D[6]) PROM_OUT (LED_D[5]) PROM_IN (LED_D[7])
Type
Description
PROM chip select. Connected Chip Select 93C46 serial EEPROM PROM Clock. Connected 93C46 serial EEPROM PROM Data Out. Connected Data_In 93C46 serial EEPROM PROM Data Connected Data_Out 93C46 serial EEPROM
Table Serial Management Interface Name
(PROM_CS) MDIO
Type
I/O,D
Description
Management Data Clock. Serial management clock which uses clock MDIO data. Management Data Input/Output. bi-directional data interface used external manager access internal registers within AC205. This internal pull-down register.
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DISPLAY/CONFIGURATION/PROM INTERFACE
pins shared with reset-read configuration pins, test pins EEPROM interface. value applied reset-read pins only valid reset cycle. EEPROM interface active after reset cycle. Once data EEPROM read, same pins used display. outputs available through matrix.
Table Pins Name
LED_LN[5] LED_LN[4] LED_LN[3] LED_LN[2] LED_LN[1] LED_LN[0]
Type
Description
Enable corresponding display line display matrix, active output. detail program connect LEDs Setup section. LED_LN*[5]: Display 10BT Collision rate segment collision status. LED_LN*[4]: Display 100Mbps Collision rate segment collision status LED_LN*[3]: Display segment utilization rate LED_LN*[2]: Display 100M segment utilization rate LED_LN*[1]: Programmable display. default display Link/Activity information each port. LED_LN*[0]: Programmable display. default display 100M Link/Activity information each port. Output display information each column display matrix. Active high output.
LED_D[7] LED_D[6] LED_D[5] LED_D[4] LED_D[3] LED_D[2] LED_D[1] LED_D[0]
I/O,
Table Control Set-up Name
Mode[3] (MIIB_RXD2) Mode[2] (LED_D[4]) Mode[1] (LED_D[1]) Mode[0] (LED_D[0]) TP125 (MIIB_RXD1) ChipID[1] (LED_D[2]) ChipID[0] (LED_D[3])
Type
Description
Mode[3:2] Mode[1:0] MIIB 7-wire External pull-up
1:select 1:1.25 xformer device must assigned with ChipID=0 Reference bias resistor. Connected analog ground through (1%) resistor.
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AC205
Table Clock Reset Name
RESET*
Type
Description
Reset initial defaulted state. 25MHz-System-clock reference input. This shall connected external 25MHz-clock source. Multiple devices should synchronous same external clock source.
Table Power Ground Name
DVCC DGND AVCC AGND GAVDD GAGND
Type
Description
2.5V power digital circuit, total pins. Ground digital circuit, total pins. 2.5V Power analog circuit, total pins. Ground analog circuit, total pins +2.5V power supply common analog circuit Ground common analog circuit
Table Connects Name
Type
Description
Connects
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AC205
Section egis iptions
There reserved registers and/or bits that Altima internal only. following standard registers supported. (Register numbers Decimal format, values format). NOTE: When writing registers, recommended that read/modify/write operation performed, unintended bits unwanted states. This applies registers, including those with reserved bits.
REGISTER DESCRIPTION
AC205 register sets listed below. Each register contains 16-bit data. addresses shown below hexadecimal.
Table Register Addr
Offset Addr
Definition
Port Status Registers Port Link Status Port Polarity Status Port Partition Status 100Mb Port Partition Status 10Mb Port Speed Status Port Isolation Status Initial Repeater Configuration Register Bridge Control Register Device Revision Number Registers Control Register Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto Negotiation Next Page Transmit Register Reserved Control Register Interrupt Control/Status Register Diagnostic Register Test Register Cable Length Register Receive Error Count Power Management Register Operation Mode Register
Type
Default
3000 2849 0022 5541 00A1 0001 0004 2001 0000
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Table Register (Cont.) Addr
Offset Addr
Definition
Reserved Registers Registers Registers Registers Effect Registers Reserved Reserved Effect with Partition/Isolation Event Effect with Link Event Effect with Activity (CRS) Event Effect with AutoNeg Event Effect with Speed100 Event Register Control Mode
Type
Default
0000
PORT STATUS REGISTER
Table Port Status Register Name
Port Link Status Port Polarity Status Port Partition Status 100Mb Port Partition Status 10Mb Port Speed Status Port Isolation Status (Fast Ethernet only)
Type
Address
Description
Link good, default polarity been crossed, default port been partitioned, default port been partitioned, default 100M, 0:10M, default port been isolated, default
Table Port Status 15:9
Port
Port
Port
Port
Port
INITIAL REPEATER CONFIGURATION REGISTER
Table Initial Repeater Configuration Register Name
Repeater Configuration
Type
Address
Description
Used give status port. Default pin.
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Name
Type
Description
Mode[3:2] Mode[1:0] MII-B 7-wire Reserved Reserved external pull-up
Default
MODE pins
15:12
Mode
Reserved (Write clear enable) Reserved (MIB enable) Disable partition External transform selection MIIB Speed Select Switch debug 100M repeater Partition Alternative
Reserved 1:disable partition function interface 1:external transform 1:1.25, 0:external transform 1:100M interface, 0:10M interface Selection control debugging signals normal, un-partition port only when data transmitted from port bit-time without collision. alternate, un-partition port when data either transmitted from port received from port bit-time without collision. normal, un-partition port when data either transmitted from port received from port bit-time without collision. alternate, un-partition port only when data received from port bit-time without collision 00000
repeater Partition Alternative
BRIDGE CONTROL REGISTER
Table Bridge Control Register Name
Bridge Control Register
Type
Address
Description
Used configure Bridge.
Name
Watch Reset Loose Length Dribble Error
Type
Description
1:reset when WDOG even occur 0:dosen't reset when WDOG even occur 1:receives frame with length from 1519 1548 0:rejects frame with length over 1518 1:enable, 0:disable receive dribble error packets
Default
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Name
Address Table Initialization Disable Aging Speed Back Pressure 100M Back Pressure Collision Test Reserved Name
Type
Description
1:disable, 0:enable address table init. While this address table only contains entries speed function verification. 1:enable, 0:disable aging speed 1:enable, 0:disable back pressure function 1:enable, 0:dieable 100M back pressure function 1:enable, 0:disable collision test Description
Default
Type
Default
REGISTERS
following registers defined each port. base addresses respectively.
CONTROL REGISTER
Table Control Register
0.15 0.14
Name
Reset Loopback
Definition
reset This self-clearing. Loopback mode, which internally loop transmit AC205 receive, thus will ignore activity cable media. Normal operation. 100Mbps 10Mbps. This will ignored Auto-Negotiation enabled. will longer reflect auto-negotiation result. Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. force mode, speed selected 0.13. Power down mode, which puts AC205 low-power stand-by mode, which only react management transaction. Normal operation. Electrical isolation from cable media. Normal operation. Restart Auto-Negotiation process. Normal operation.
Mode
RW/SC
Default
0.13
Speed Select
0.12
Auto-Neg Enable
0.11
Power Down
0.10
Isolate Restart AutoNegotiation
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Table Control Register (Cont.)
Name
Duplex Mode
Definition
Full duplex. Half duplex. Full duplex supported this chip. will longer reflect auto-negotiation result. Enable collision test, which issues signal response assertion TX_EN signal. Disable test.
Mode
Default
Collision Test
0.6:0
Reserved
000000
STATUS REGISTER
Table Status Register
1.15 1.14 1.13 1.12 1.11 1.10:6
Name
100Base-T4 100Base-TX Full Duplex 100Base-TX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex Reserved Auto-Negotiate Complete Remote Fault
Definition
Tied zero indicates 100BaseT4 capability. Tied zero indicates 100BaseTX full duplex support. 100BaseTX with half duplex. Half-Duplex ability. Tied zero indicates 10Base-T full duplex support. 10BaseT with half duplex. 10BaseT Half-Duplex ability. Auto-negotiate process completed, indicates Reg. valid. Auto-negotiate process completed. Remote fault condition detected. remote fault. After this set, will remain until clear reading register management interface. Able perform auto-negotiation function, value determined ANEGA pin. Unable perform auto-negotiation function. Link established, however, AC205 link fails, this will become cleared remain cleared until register read management interface. Link down, have been dropped. Jabber condition detect. Jabber condition detected. Extended register capable. This tied permanently one. Tied zero indicates 100BaseT4 capability.
Mode
Default
00001
SC/LH
Auto-Negotiate Ability Link Status
SC/LL
1.15
Jabber Detect Extended Capability 100Base-T4
SC/LH
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IDENTIFIER REGISTER
Table Identifier Register Reg.
2.15:0
Name
OUI*
Description
Assigned through bits Organizationally Unique Identifier (OUI), respectively.
Mode
Default
0022 (HEX)
IDENTIFIER REGISTER
Table Identifier Register Reg.
3.15:10 3.9:4 3.3:0
Name
Model Number Revision Number
Description
Assigned through bits OUI. manufacturer's model number; encoded 010001. Four bits manufacturer's revision number. 0001 stands Rev. etc.
Mode
Default
010101 010100 0001
AUTO-NEGOTIATION ADVERTISEMENT REGISTER
Table Auto-Negotiation Advertisement Register
4.15 4.14 4.13 4.12:10 4.4:0
Name
Next Page Acknowledge Remote Fault Reserved 100Base-T4 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T Selector Field
Definition
Desire Next Page. Next Page desired. This will internally after receiving consecutive consistent bursts. Remote fault detected. remote fault. future technology. Tied zero indicates 100Base-T4 support. 100BaseTX with full duplex. 100BaseTX full duplex ability. 100BaseTX capable. 100BaseTX capability. 10Mbps with full duplex. 10Mbps with full duplex capability. 10Mbps capable. 10Mbps capability. [00001] IEEE 802.3.
Mode
Default
00001
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AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER
Table Auto-Negotiation Link Partner Ability Register Reg.
5.15:0
Name
Technology
Description
Technology capability field, which indicates technology capability link partner. definition same Reg. 4.15:0.
Mode
Default
0001(H)
AUTO-NEGOTIATION EXPANSION REGISTER
Table Register Auto-Negotiation Expansion Register Reg.
6.15:5
Name
Reserved
Description
Mode
Default
0000 0000
Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Link Partner Auto-Negotiation Able
Fault detected parallel detection logic. This caused unstable link, concurrent link condition. fault detected parallel detection logic. Link partner supports next page function. Link partner does support next page function. link code word been received. contains received link code word located Register Link partner auto-negotiation able. Link partner auto-negotiation able.
SC/LH
SC/LH
AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER
Table Auto-Negotiation Next Page Transmit Register Reg.
7.15 7.14 7.13 7.12
Name
Reserved Message Page ACK2
Description
Another Next Page desired. Message page. Un-formatted Page. Acknowledge2. Will comply with message. comply with message. Previous value transmitted Link Code Word equal Previous value transmitted Link Code Word equal Message/Un-formatted Code Field.
Mode
Default
7.11 7:10:0
Toggle Code
0001
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CONTROL REGISTER
Table Control Register Reg.
16.15
Name
Repeater
Description
Repeater mode. Full-duplex will inactive, only responses receive activity. test function also disabled. mode. 1=Force send pattern. 0=Normal operation mode Disable carrier integrity monitor function. Enable carrier integrity monitor function. Default `0'. Disable 10BaseT testing. Enable 10BaseT testing, which will generate pulse following completion packet transmission. Enable 10BaseT normal loop back. Disable 10BaseT normal loop back. Disable auto polarity detection/correction. Enable auto polarity detection/correction. When Reg16.5 this will Reverse Polarity detected media, otherwise will zero. When Reg16.5 writing will reverse polarity transmitter. Note: reverse polarity detected either through inverted through burst inverted FLP.
Mode
Default
16.14 16.13 16.12
Reserved TXJAM Disable
16.11
Test Inhibit
16.10 16.[9:6] 16:5 16.4
Normal Loop Back Reserved Auto polarity disable Reverse Polarity
16:[3:0]
Reserved
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INTERRUPT CONTROL/STATUS REGISTER
Table Interrupt Control/Status Register Reg. Name
17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 Jabber_IE Rx_Er_IE Page_Rx_IE PD_Fault_IE LP_Ack_IE Link_Schange_ R_Fault_IE Aneg_Comp_IE Jabber_Int Rx_Er_Int Page_Rx_Int PD_Fault_Int LP_Ack_Int Link_Schanged R_Fault_Int A_Neg_Comp
Description
Jabber Interrupt Enable. Receive Error Interrupt Enable. Page Received Interrupt Enable. Parallel Detection Fault Interrupt Enable. Link Partner Acknowledge Interrupt Enable. Link Status Changed Interrupt Enable. Remote Fault Interrupt Enable. Auto-Neg Complete Interrupt Enable. This when jabber event detected. This when RX_ER transitions high. This when page received from link partner during AutoNegotiation. This when parallel detect fault detected. This when with acknowledge received. This when link status changed. This when remote fault detected. This when Auto-Neg completed.
Mode Default
DIAGNOSTIC REGISTER
Table Diagnostic Register Reg.
18.15 18.14 18.13 18.12 18.11 18.10 18.9
Name
Lp_lpbk Send_nlp Force link pass Force link pass DPLX Speed RX_PASS
Description
Link pulse loopback. loopback link pulse auto-negotiation testing force link pulse generator send event auto-negotiation mode. force base link pass force link pass This indicates result Auto-Neg duplex arbitration. This indicates result Auto-Neg data speed arbitration. 10BT mode, this indicates that Manchester data been detected. 100BT mode, indicates valid signal been received necessarily locked Indicates receive locked onto received signal selected speed operation (10Base-T 100Base-TX). This whenever cycle-slip occurs, will remain until read. Highest state Auto-Negotiation state machine since reset last read operation. Lowest state Auto-Negotiation state machine since reset last read operation.
Mode
Default
18.8
RX_LOCK
18.[7:4] 18.[3:0]
ARB_STATE HIGHEST ARB_STATE LOWEST
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TEST REGISTER
Table Test Register Reg.
19.[15:9] 19.8 19.7 19.6 19.5 19.4 19.3 19.2 19.1 19.0
Name
Reserved Reserved Error counter full disable Watch timer disable Low_pwr_mode disable Digital loop back Test loop back Remote loop back Jabber disable
Description
Mode
Default
00000
Error count full. When indicates rx_error counter full receiver circuit. This event will cause de-scrambler reset. disable error counter receiver module. disable watch timer. Packet 10000 Byte will cause scrambler look seed. disable power management enable power management enable digital loop back enable test loop back enable remote loop back disable base jabber function
CABLE LENGTH REGISTER
Table Cable Length Register Reg.
20.[15:9] 20.8 20.[7:4]
Name
Reserved Adaptation disable Cable Length Indication Adaptation limit
Description
Disable adaptation These bits indicate cable length from meters. Each represents meters. example, cable length meters then bits [7:4] 1010. These bits only applicable 100TX mode. Adaptation setting, when signal first detected.
Mode
Default
0000000 XXXX
20.[3:0]
XXXX
RECEIVE ERROR COUNT
Table Receive Error Count Reg.
21.[15:0]
Name
Receive Error Count
Description
Count number receiving packets with error. This register only cleared reset (software hardware).
Mode
Default
0000
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POWER MANAGEMENT REGISTER
Table Power Management Register Reg.
22.[15:14] 22.13 22.12 22.11 22.10 22.9 22.8 22.[7:6] 22.5 22.4 22.3 22.2 22.1 22.0
Name
Reserved PD_PLL PD_EQUAL PD_BT_RCVR PD_LP PD_EN_DET PD_FX Reserved MSK_PLL MSK_EQUAL MSK_BT_RCV MSK_LP MSK_EN_DET MSK_FX
Description
1=Power down circuit 1=Power down equalizer circuit 1=Power down base receiver 1=Power down link pulse receiver 1=Power down energy detect circuit 1=Power down circuit 0=Force power circuit 0=Force power equalizer circuit 0=Force power base receiver 0=Force power link pulse receiver 0=Force power energy detect circuit 0=Force power circuit
Mode
Default
OPERATION MODE REGISTER
Table Operation Mode Register Reg.
23.15 23.14 23.13 23.12 23.11 23.10 23.9 23:8 23.7 23:6 23.5
Name
Reserved Reserved Clk_rclk_save Reserved Scramble disable Serial enable Pcsbp timer Reserved Reserved Force re-adapt
Description
Mode
Default
rclk save mode. Rclk will shut after cycles each packet disable scrambler enable serial mode enable bypass mode enable timer adaptation disable timer adaptation.
23.[4:0]
Dlock drop counter
force adaptation re-adapt Write this will force adaptation re-adapt. This will always read lock drop counter
XXXXX
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RECENT RECEIVED PACKET
Table Recent Received Packet Reg.
24.[15:0]
Name
CRC16
Description
CRC16 value displayed. system level test purpose.
Mode
Default
0000H
TEST EFFECT REGISTER
This registers defined whole chip. base address
EFFECT WITH PARTITION/ISOLATION EVENT
Table Effect with Partition/Isolation Event Reg.
15:12
Name
Blink Rate [7:4]
Description
blink rate bits [7:0] with Effect with Partition/Isolation Event Register (PHY Addr Addr 18), abbreviated REG_LED_EFFECT following equation. Blink Rate (16ms {REG_LED_EFFECT[15:12], 4`b0000 When Partition/Isolation, turn corresponding 1:0.
Mode
Default
0001
11:10
Reserved with Part/ Event Reserved Blink with Part/ISO Event Reserved with Part/ Event
When Partition/Isolation, blink corresponding 1:0.
When Partition/Isolation, turn corresponding 1:0.
EFFECT WITH LINK EVENT
Table Effect with Link Event Reg.
15:10
Name
Reserved with Link Event Reserved Blink with Link Event Reserved with Link Event
Description
When Link turn corresponding 1:0.
Mode
Default
00000
When Link blink corresponding 1:0.
When Link turn corresponding 1:0.
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EFFECT WITH ACTIVITY (CRS) EVENT
Table Effect with Activity (CRS) Event Reg.
15:10
Name
Reserved with Activity Event Reserved Blink with Activity Event Reserved with Activity Event
Description
When Activity, turn corresponding 1:0.
Mode
Default
00000
When Activity, blink corresponding 1:0.
When Activity, turn corresponding 1:0.
EFFECT WITH AUTO-NEGOTIATING EVENT
Table Effect with Auto-Negotiating Event Reg.
15:10
Name
Reserved with Autonegotiating Event Reserved Blink with Autonegotiating Event Reserved with Autonegotiating Event
Description
When Auto-negotiating, turn corresponding 1:0.
Mode
Default
00000
When Auto-negotiating, blink corresponding 1:0.
When Auto-negotiating, turn corresponding 1:0.
EFFECT WITH SPEED100 EVENT
Table Effect with Speed100 Event Reg.
15:10
Name
Reserved with Speed100 Event Reserved Blink with Speed100 Event Reserved with Speed100 Event
Description
When Speed100, turn corresponding 1:0.
Mode
Default
00000
When Speed100, blink corresponding 1:0.
When Speed100, turn corresponding 1:0.
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REGISTER CONTROL MODE
Table Register Control Mode Reg.
15:8
Name
Data Reserved Column
Description
value shown LED_D[7:0]. Control which lane LED_D should turned
Mode
Default
000000 000000
EEPROM TABLE
EEPROM used configure initial setting Bridge, Repeater, Transceiver.
Table EEPROM Address
Description
First Word Test Control Register0 Initial Repeater Configuration Register Bridge Control Register Reserved Reserved Initialize Port Control Register Initialize Port Control Register Initialize Port Control Register Initialize Port Control Register Initialize Port Control Register Reserved Effect with Partition/Isolation Event Effect with Link Event Effect with Activity (CRS) Event Effect with AutoNeg Event Effect with Speed Event
Default
5A3C 0080 0180 D000 3000 3000 3000 3000 3000 3000 3000 3000 1000 0330 0030 0000 0200
Assign
PHY=8, Reg=28 PHY=8, Reg=6 PHY=8, Reg=7
PHY=2, Reg=0 PHY=3, Reg=0 PHY=4, Reg=0 PHY=5, Reg=0 PHY=6, Reg=0 PHY=8, Reg=18 PHY=8, Reg=19 PHY=8, Reg=20 PHY=8, Reg=21 PHY=8, Reg=22
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AC205
4B/5B CODE-GROUP TABLE
Table 4B/5B Code-Group Table Code Group[4:0] SYMBOL Name
11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101
(TXD/RXD [3:0])
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0101 0101 Undefined Undefined
Description
Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Inter-Packet Idle; used inter-stream fill code. Start stream delimiter, part always pair with symbol. Start stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. Transmit Error; used send HALT code-group Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code
Idle Control Code
11111 11000 10001 01101 00111
Invalid Code
00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
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DISPLAY MATRIX
Display uses refresh technique. using display matrix, number ports drive significantly reduced. LED's assigned each port. Off, Flash states used indicate different information. With reduced counts, reduced number signals, display will easier route board, less costly.
LED_D[7]
LED_D[6]
LED_D[5]
LED_D[4]
LED_D[3]
LED_D[2]
LED_D[1]
LED_D[0]
LED_LN[5]
LED_LN[4]
LED_LN[3]
LED_LN[2]
LED_LN[1]
LED_LN[0]
Port
Port
Port
Port
Port
Figure Display Matrix
SYSTEM CONSIDERATIONS
design chip optimized cost 10/100 repeater application. also provides flexibility more advanced systems with simple configurable architecture.
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AC205
ction Electr ristics
following electrical characteristics design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. -55oC +150oC Supply Referenced GND. -0.5V 2.5V Digital Input Voltage. -0.5V 3.3V Output Voltage. -0.5V
OPERATING RANGE
Operating Temperature (Ta) 70oC Supply Voltage Range (Vcc). 2.375V 2.625V
Table Total Power Consumption Parameter
Supply Current (per port)
Symbol
Conditions
Base-T, Idle Base-T, Normal activity Base-TX 10/100 Base-TX, power without cable Power down Mode Master
Units
Supply Current (dual speed hub)
Table Characteristics Parameter
Input Voltage High Input Voltage Input Current Output Voltage High Output Voltage Output Current High Output Current Input Capacitance
Symbol
Conditions
Units
VCC-0.4
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Table Characteristics (Cont.) Parameter
Output Transition Time Tristate Leakage Current |Ioz|
Symbol
Conditions
2.375V 2.625
Units
REFCLK PINS
Table REFCLK Pins Parameter
Input Voltage Input Voltage High Input Clock Frequency Tolerance Input Clock Duty Cycle Input Capacitance
Symbol
Conditions
Units
CHARACTERISTICS LED/CFG PINS
Table Characteristics LED/CFG Pins Parameter
Output Voltage Output High Voltage Input Current Output Current
Symbol
Conditions
Units
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BASE-TX TRANSCEIVER CHARACTERISTICS
Table BASE-TX Transceiver Characteristics Parameter
Peak Peak Differential Output Voltage Output Voltage Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot/Undershoot Output Jitter Receive Jitter Tolerance Output Current High Output Current High Common Mode Input Voltage Differential Input Resistance Note resistor each output Transformer 1.25:1 Transformer 1.25
Symbol
Trfs
Conditions
Note Note Note Note
0.98
1.02
Units
Scrambled Idle
BASE-T TRANSCEIVER CHARACTERISTICS
Table BASE-T Transceiver Characteristics Parameter
Peak Peak Differential Output Voltage Start Idle Pulse Width Output Jitter Receive Jitter Tolerance Differential Squelch Threshold Common Mode Rejection Note resistor each output
Symbol
Conditions
Note
Units
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POWER RESET
Table Power Reset Parameter
RST* Period Configuration
tRST tCONF
Conditions
Units
tRST
RST* Configuration Pins
tCONF
Figure Power Reset
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7-WIRE INPUT TIMING
Table 7-Wire Input Timing Parameter
SNI_TXCLK Period SNI_TXCLK High Period SNI_TXCLK Period SNI_TXD/SNI_TXEN SNI_TXCLK Rising Setup Time SNI_TXD/SNI_TXEN SNI_TXCLK Rising Hold Time
tCKH tCKL
Units
tCKH SNI_TXCLK SNI_TXD
tCKL
SNI_TXEN
Figure 7-Wire Input Timing
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7-WIRE OUTPUT TIMING
Table 7-Wire Output Timing Parameter
SNI_RXCLK Period SNI_RXCLK High Period SNI_RXCLK Period SNI_RXCLK Rising SNI_RXD/ SNI_CRS/SNI_COL Output Delay
tCKH tCKL
Units
tCKH SNI_RXCLK SNI_RXD
tCKL
SNI_CRS/ SNI_COL
Figure 7-Wire Output Timing
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100BASE-TX INPUT TIMING
Table 100BASE-TX Input Timing Parameter
MII_TXCLK Period MII_RXCLK High Period MII_RXCLK Period MII_TXD, MII_TXEN MII_TXCLK Rising Setup Time MII_TXD, MII_TX_EN MII_TXCLK Rising Hold Time
tCKH tCKL tTXS tTXH
Units
tCKH MII_TXCLK tTXS MII_TXEN tTXH
Start Packet tCKL
Packet
MII_TXD
Figure 100BASE-TX Input Timing
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AC205
100BASE-TX OUTPUT TIMING
Table 100BASE-TX Output Timing Parameter
MII_RXCLK Period MII_RXCLK High Period MII_RXCLK Period MII_CRS Rising MII_RXDV Rising MII_RXCLK Rising MII_RXD, MII_RXDV, MII_CRS Output Delay
tCKH tCKL tCSVA tRXOD
Units
tCKH
MII_RXCLK
Start Packet tCKL
Packet
tRXOD
MII_RXDV
tCSVA
MII_RXD
MII_CRS
Figure 100BASE-TX Output Timing
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10BASE-TX INPUT TIMING
Table 10BASE-TX Input Timing Parameter
MII_TXCLK Period MII_RXCLK High Period MII_RXCLK Period MII_TXD, MII_TXEN MII_TXCLK Rising Setup Time MII_TXD, MII_TX_EN MII_TXCLK Rising Hold Time
tCKH tCKL tTXS tTXH
Units
tCKH
MII_TXCLK
Start Packet tCKL
Packet
tTXS
MII_TXEN
tTXH
MII_TXD
Figure 10BASE-TX Input Timing
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10BASE-TX OUTPUT TIMING
Table 10BASE-TX Output Timing Parameter
MII_RXCLK Period MII_RXCLK High Period MII_RXCLK Period MII_CRS Rising MII_RXDV Rising MII_RXCLK Rising MII_RXD, MII_RXDV, MII_CRS Output Delay
tCKH tCKL tCSVA tRXOD
Units
tCKH
MII_RXCLK
Start Packet tCKL
Packet
tRXOD
MII_RXDV
tCSVA
MII_RXD
MII_CRS
Figure 10BASE-TX Output Timing
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AC205
Advance Data Sheet
09/21/01
EEPROM INTERFACE TIMING
Table EEPROM Interface Timing Parameter
PROM_CLK Period PROM_CLK Period PROM_CLK High Period PROM_IN PROM_CLK Rising Hold Time PROM_IN PROM_CLK Rising Hold Time PROM_CLK Falling PROM_OUT Output Delay Time
tECK tECKL tECKH tERDS tERDH tEWDD
2550 2550
5120
2570 2570
Units
PROM_CS tECKH PROM_CLK tEWDD tECK PROM_OUT tERDS PROM_IN tERDH tECKL
Figure EEPROM Interface Timing
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Advance Data Sheet
09/21/01
AC205
TIMING
Table Timing Parameter
Pulse Width LED_D[n] Falling LED_D[n+1] Falling LED_D[n] Falling LED_D[n] Falling
Conditions
Units
LED_LN[5:0] LED_D[7] LED_D[6] LED_D[5] LED_D[4] LED_D[3] LED_D[2] LED_D[1] LED_D[0]
Timing
Figure Timing
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AC205
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09/21/01
APPLICATION TERMINATION
2.5V
49.9
49.9
AC205 Transformer TXON TXOP TXC_P TX+_P TX-_P RX+_P RX-_P RXC_P
RJ45 Unused Unused Unused Unused
TXC_S TX+_S TX-_S RX+_S RX-_S RXC_S
IBREF
RXIP
RXIN
1000
Chassis
Figure Application Termination
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09/21/01
AC205
echa nica Info ation
Table Package Dimensions AC205
3.40
0.25
2.70
23.20 0.25
20.00 0.10
17.20 0.25
14.00 0.10
0.65
0.88
1.60 0.12
Figure 100-pin PQFP
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Document AC205-DS03-R Mechanical Information Page
AC205
Advance Data Sheet
09/21/01
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Advance Data Sheet
09/21/01
AC205
Part Number
AC205KQM
Package
100-pin PQFP
Ambient Temperature
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Document AC205-DS03-R Ordering Information Page
AC205
Advance Data Sheet
09/21/01
Broadcom Corporation
16215 Alton Parkway P.O. 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
Broadcom® Corporation reserves right make changes without further notice products data herein improve reliability, function, design. Information furnished Broadcom Corporation believed accurate reliable. However, Broadcom Corporation does assume liability arising application this information, application product circuit described herein, neither does convey license under patent rights rights others.
Document AC205-DS03-R

2.5V 10/100-TX 5-Port Repeater with Bridge Controller GENERAL DES

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