GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER JEDEC compatible LVTTL l

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GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER JEDEC compatible LVTTL l

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QS532807 3.3V GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
JEDEC compatible LVTTL level skew clock outputs Clock input tolerant Pinout function compatible with QS5807 on-chip resistors available noise Input hysteresis better noise margin Guaranteed skew 0.5ns (max.) between outputs: Available QSOP SOIC packages
QS532807
DESCRIPTION:
QS532807 clock driver/buffer circuit used clock buffering schemes where skew parameter. QS532807 offers non-inverting outputs. Designed IDT's proprietary QCMOS process, these devices provide propagation delay buffering with less than 0.5ns on-chip skew. QS532807 on-chip series termination resistors lower noise clock signals. QS532807 series resistor version recommended driving unterminated lines with capacitive loading other noise sensitive clock distribution circuits. These clock buffer products designed high-performance workstations, embedded personal computing systems. Several devices used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks.
FUNCTIONAL BLOCK DIAGRAM
2001 Integrated Device Technology, Inc.
OCTOBER 2001
5848/1
QS532807 3.3V GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
CONFIGURATION
20-2 20-8
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) IOUT TSTG Description Supply Voltage Ground Output Voltage VOUT Input Voltage Input Voltage (pulse width 20ns) Output Current Output Current Max. Sink Current/Pin Storage Temperature Junction Temperature
Unit
Max. +4.6 VCC+0.5 +150
QSOP/ SOIC VIEW
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Terminals. terminals except Vcc.
CAPACITANCE
QSOP Pins Typ.
+25OC, 1.0MHz,
SOIC Typ. Max. Unit Max.
NOTE: This parameter guaranteed production tested.
DESCRIPTION
Names Description Clock Input Clock Outputs
QS532807 3.3V GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, 3.3V 0.3V
Symbol Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA Min., -100µA Min., -8mA Min., 100µA IOFF IODH IODL ROUT Output Voltage Input Leakage Current Input Power Leakage Short Circuit Current Output HIGH Current Output Current Input Hysteresis Output Resistance
(2,3)
Min. -0.5
Typ.(1) -0.7
Max. -1.2
Unit
Min., Min., Max., Max., VOUT 3.3V, VIL, 1.5V 3.3V, VIL, 1.5V VTLH VTHL Inputs Min., 12mA
-195
-200
NOTES: Typical values 3.3V, 25°C. more than output should used test this high power condition. Duration less than second. Guaranteed design tested. Output resistance represents total output impedance logic device includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol ICCD Parameter Quiescent Power Supply Current Supply Current Input HIGH Dynamic Power Supply Current Output Total Power Supply Current Examples
(1,3)
Test Conditions Max., Max., Input toggling duty cycle Max., outputs Enabled Max., Input duty cycle 10MHz Max., Input duty cycle 2.5MHz
Typ. 0.01
Max.
Unit µA/MHz
NOTES: Guaranteed design tested. 0pF. Typical values reference only. Conditions 3.3V, 25°C. (ICC)(DH)(NT) ICCD (fO)(NO) where: Input Duty Cycle Number HIGH inputs (one) Output Frequency Number outputs (ten)
QS532807 3.3V GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 3.3V 0.3V CLOAD 50pF resistor)
Symbol tSK(01) tSK(P) tSK(T) tPLH tPHL Parameter Skew between outputs, same transition Pulse Skew; skew between opposite transitions same output (tPHL tPLH) Part-to-part skew Propagation Delay Output Rise Time, 0.8V Output Fall Time, 0.8V Min. Max. Unit
NOTES: Skew parameters guaranteed across temperature range, tested. tSK(T) only applies devices same transition, part type, temperature, power supply voltage, loading, package. propagation delay range indicated Min. Max. specifications results from process environmental variables. These propagation delays imply limit skew.
QS532807 3.3V GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
TEST CIRCUITS WAVEFORMS
Pulse Generator
50pF
Pulse generator puls 1.0M 2.5ns; 2.5ns
PROPAGATION DELAY
PULSE SKEW tSK(P)
INPUT
1.5V
INPU
1.5V
1.5V
OUTPUT
1.5V
OUTPUT
0.8V
tSK(p) PLHL
OUTPUT SKEW tSK(O1)
PART-TO-PART SKEW tSK(T)
INPUT
1.5V
INPU
1.5V
PART UTPUT
1.5V
OUTPUT
1.5V
(01) SK(0 tSK(t) tSK(t)
1.5V
1.5V
PART UTPUT
OUTPUT
SK(01) PLH2 PLH1 PHL1
SK(t) PLH2 PLH1 PHL1
QS532807 3.3V GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
XXXX Device Type Package
Small Outline (300 mil) (SO20-2) Quarter-size Small Outline Package (SO20-8)
532807
Guaranteed Skew CMOS Clock Driver/Buffer
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-6116 fax: 408-492-8674 www.idt.com
Tech Support: logichelp@idt.com (408) 654-6459

GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER JEDEC compatible LVTTL l

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