16COM 40SEG CONTROLLER DRIVER MATRIX INTRODUCTION KS0072 matrix d
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KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
INTRODUCTION KS0072 matrix driver controller which fabricated power CMOS technology. capable displaying line characters line characters with dots format.
FUNCTIONS Character type matrix driver controller. Easy interface with 4-bit 8-bit MPU. Internal driver common segment signal output. Display character pattern dots format (240 kinds) Direct programming special character patterns character generator RAM. Mask option programming customer character patterns Various instruction functions. Automatic power reset.
FEATURES Internal Memory Character Generator (CGROM) 9600 bits (240 characters dot) Character Generator (CGRAM) bits characters dot) Display Data (DDRAM) bits characters 8bits) power operation Power supply voltage range 5.5V(VDD) drive voltage range 11.0(VDD-V5) CMOS process Duty cycle 1/16 Built-in oscillator power consumption Internal divide resistor driving voltage Available
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
BLOCK DIAGRAM
TEST
Oscillator Power Reset (POR) EXT_INT RESETB
EXTCLK
Timing generator
Input buffer
Instruction register (IR)
Instruction decoder
Address counter Data register (DR)
Display data (DDRAM) 16x8 bits 40-bit shift register (Bidir.)
16-bit shift register
Common driver
C1~C16
40-bit latch circuit
Segment driver
S1~S40
Cursor blink control circuit Parallel Serial converter (VSS)
Character generator (CGRAM) bytes
Character generator (CGROM) 9600 bits
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
DIAGRAM
DUMMY TEST DUMMY DUMMY DUMMY DUMMY
DUMMY
KS0072
DUMMY
EXT_INT EXTCLK DUMMY
RESET
KS0072 CHIP SIZE 7600 2160 PITCH min. CHIP THICKNESS SPECIFICATIONS SIZE SIDE SIZE SIDE BUMP SPECIFICATIONS BUMP SIZE SIDE BUMP SIZE SIDE BUMP HEIGHT
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
LOCATION UNIT (µm)
NAME DUMMY DUMMY EXTCLK EXT_INT RESETB DUMMY COORDINATE -3642 -3032 -2632 -2232 -1832 -1707 -1582 -1182 -1057 -932 -532 -407 -282 1317 1717 2117 2521 2697 2871 3047 3643 3643 3643 3643 3643 3643 3643 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -717 -591 -467 -341 -184 NAME DUMMY COORDINATE 3643 3643 3643 3643 3643 3643 3643 2464 2329 2204 2079 1954 1829 1704 1579 1454 1329 1204 1079 -205 -330 NAME DUMMY TEST DUMMY DUMMY DUMMY COORDINATE -455 -580 -705 -830 -955 -1080 -1205 -1330 -1455 -1580 -1705 -1830 -1955 -2080 -2205 -2330 -2463 -3642 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -184 -341 -467 -592 -717
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
DESCRIPTION VSS(GND) EXTCLK Output Output Input Segment output Common output External clock Input External/Internal oscillator clock select Register select Input/Output Power Name Power supply Bias Description logical circuit (+3V, +5V) (GND) Bias voltage level driving Segment signal output driving Common signal output driving When using external clock, used clock input pin. When using internal oscillator, connect VSS. When EXT_INT "High", external clock used. When "Low", internal oscillator used. Used register selection input. When "High", Data register selected. When "Low", Instruction register selected. Used read/write selection input. When R/W="High",read operation. When R/W="Low", write operation. Used read/write enable signal. When 8-bit mode, used order bidirectional data bus. During 4-bit mode open these pins. When 8-bit mode, used high order bidirectional data bus. case 4-bit mode, used both high order. used Busy Flag output during read instruction operation. Input Reset necessary initialize system hardware, force "Low", level signal this terminal about Internal oscillator test pin. Open this pin. OPEN External clock Interface Power Supply
EXT_INT
Input Input
VDD/VSS
Input
Read/Write
Input Input/Output
Read/Write enable Data
RESETB
TEST
Output
Test
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
FUNCTION DESCRIPTION System Interface This chip consists kinds interface type with 4-bit 8-bit bus. 4-bit 8-bit selected function instruction register. During read write operation, 8-bit registers used. data register (DR), other instruction register (IR). data register (DR) used temporary data storage place being written into read from DDRAM/CGRAM, target selected address setting instruction. Each internal operation, reading from writing into RAM, done automatically. Thus, after reads data, data next DDRAM/CGRAM address transferred into automatically. Also after writes data data transferred into DDRAM/CGRAM automatically. Instruction register (IR) used only store instruction code transferred from MPU. cannot read data from instruction register. register selection depends input setting both 4-bit mode. Table Various kinds operations according bits. Operation Instruction Write operation (MPU writes Instruction code into Read Busy flag (DB7) address counter (DB0 DB6) Data Write operation (MPU writes data into Data Read operation (MPU reads data from
Busy Flag (BF) "High" indicates that internal operation being processed. during this time next instruction cannot accepted. read, when High (Read instruction Operation), through port. Before excuting next instruction, sure that High.
Address Counter (AC) Address Counter (AC) stores address DDRAM/CGRAM that transferred from After writing into (reading from) DDRAM/CGRAM data, increased (decreased) automatically. When "Low", "High", value read through ports.
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Display Data (DDRAM) DDRAM stores 8bits character code CGROM/CGRAM maximum number Characters). DDRAM address address counter (AC) hexadecimal number.
relations DDRAM address display position follows.
DDRAM addressing mode (A=0) this addressing mode, address range DDRAM 0FH.
Display Position DDRAM Address
COM1 COM8
COM9 COM16
COM1 After shift left COM8
COM9 COM16
COM1 After shift right: COM8
COM9 COM16
DDRAM addressing mode (A=1) this addressing mode, address range DDRAM 47H.
Display Position DDRAM Address
COM1 COM8
COM9 COM16
COM1 After shift left COM8
COM9 COM16
COM1 After shift right: COM8
COM9 COM16
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Character Generator (CGRAM) CGRAM used user defined character pattern. format character pattern dots except cursor position maximum characters. character pattern CGRAM write character code into DDRAM shown table Table Relationship between Character Code (DDRAM) Character Pattern (CGRAM) Character Code (DDRAM data) CGRAM Address NOTE means "don't care". Character Generator (CGROM) CGROM generates character pattern from character generate code DDRAM. CGROM 8-dot character pattern including cursor position. data cursor position high, data included character pttern. selected positions always "ON" regardless cursor position relationship between character code character pattern referred table CGRAM Data cursor position cursor position pattern Pattern Number pattern
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Timing Generation Circuit Timing generation circuit generates clock signals internal operations.
Driver Circuit driver circuit common segment output signals driving. Data from CGRAM/CGROM transferred 40-bit segment shift register serially, then stored 40-bit segment output latch. When each selected 16-bit common register, segment data also outputs through segment driver from 40-bit segment output latch. Cursor/Blink Control Circuit controls cursor/blink ON/OFF cursor position.
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
INSTRUCTION DESCRIPTION OUTLINE overcome speed difference between internal clock KS0072 clock, KS0072 performs internal operation storing control information internal operation determined according signal from MPU, composed read/write data bus. Instruction divided into four types:
KS0072 function instructions (set display methods, data length, etc.) Address instructions internal Data transfer instructions with internal Others address internal automatically increased decreased Note During internal operation, Busy Flag (DB7) High. Busy Flag check must preceede next instruction. When program with Busy Flag (DB7) checking made, 1/2Fosc necessary executing next instruction falling edge signal after Busy Flag (DB7) goes "Low".
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Table Instruction Table
Instruction Code Instruction
Description
Device test mode (When 4-bit interface mode) operation (When 8-bit interface mode) Write "20H" DDRAM DDRAM address "00H" from DDRAM address "00H" from return cursor original position shifted. contents DDRAM changed. Assign cursor moving direction enable entire display shift. display(D), cursor(C), blinking cursor position character on/off control bit(B). Cursor Display shift their direction control without changing DDRAM data. interface data length(DL), DDRAM addressing mode COM/SEG output pattern(M0,M1). CGRAM address address counter. DDRAM address address counter. Whether internal operation known reading contents address counter also read. Write data into internal (DDRAM/ CGRAM). Read data from internal (DDRAM/CGRAM).
Execution time (fosc=270 kHZ)
Test Mode
Clear Display
629µs
Return Home
629µs
Entry Mode
37µs
Display ON/OFF Control
37µs
Cursor Display Shift
37µs
Function
37µs
CGRAM Address DDRAM Address
DDRAM
37µs 37µs
Read Busy flag Address
CGRAM
Write Data Read Data from
DDRAM
43µs
CGRAM DDRAM CGRAM
43µs
NOTE asterisk means "don't care".
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Increment, Shift enable, Display shift, Shift right, interface, DDRAM addressing mode COM/SEG output pattern line characters, System operation
Decrement Shift disable Move cursor Shift left interface DDRAM addressing mode1 COM/SEG output pattern line characters System ready
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Contents Test Mode
After setting 4-bit data interface mode (DL=0), writing this code twice makes system test mode. when 8-bit interface mode (DL=1) set, normal function mode returned. System unaffected this code 8-bit interface, other than consuming some time. (37µs fosc=270KHz) Clear Display
Clear display data writing "20H" (space code CGROM) DDRAM address, DDRAM address "00H" into (Address Counter). this instruction, CGROM address "20H" space code. Shifting display position returns original position. Namely, when display data shifted cursor blinking displayed, bring cursor left edge first line display. makes entry mode increment (I/D=1) Return Home
Don't care DDRAM address "00H" into address counter. Shifting display position returns original position. When cursor blinking displayed, bring cursor left edge first line display. data DDRAM does change. Entry Mode
moving direction cursor display. Increment/decrement DDRAM/CGRAM address (cursor blink) When I/D="High", cursor/blink moves right DDRAM address increased When I/D="Low", cursor/blink moves left DDRAM address decresed Shift entire display When DDRAM read (CGRAM read/write)operation S="Low", entire display shift. S="High", DDRAM write operation, entire display shifted according value (I/D="1" shift left, I/D="0" shift right).
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Display ON/OFF Control
Control display /cursor/blink ON/OFF register. Display ON/OFF control When "High", entire display turned When "Low", entire display turned off, display data remains DDRAM. Cursor ON/OFF control When "High", cursor turned When "Low", cursor disappeared current display, register preserves data. Cursor Blink ON/OFF control When "High", cursor blink performs alternately between high data (black pattern)and display character cursor position. When ="Low", blink off.
Cursor Display Shift
Don't care Without writing reading display data, shift right/left cursor position display. This instruction used correct search display data. (Refer Table During 2-line mode display, cursor moves line after digit line. Note that display shift performed simultaneously line. When displayed data shifted repeatedly, each line shifted individually. When display shift performed, contents address counter changed. Table Shift patterns accoring bits Operation Shift cursor left, decreased Shift cursor right, increased Shift display left, cursor moves according display Shift display right, cursor moves according display
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Function
Don't care Interface data length control When "High", 8-bit mode with MPU. When "Low", 4-bit mode with MPU. Thus, signal select 8-bit 4-bit mode. 4-bit mode, 4-bit data transferred twice. display data addressing mode When "Low", DDRAM addressing mode When "High", DDRAM addressing mode COM/SEG output rotation When "Low", COM/SEG output rotation mode When "High", COM/SEG output rotation mode display line character mode When "Low", line character display mode. When "High", 2line character display mode. (Refer Application information) CGRAM Address
Don't care
CGRAM address This instruction allows access CGRAM data user defined character pattern. Available CGRAM Address lower bits (DB4 DB0). DDRAM Address
DDRAM address This instruction allows access DDRAM data. When DDRAM addressing mode (A=0), DDRAM address from "00H" "0FH". DDRAM addressing mode (A=1), DDRAM address range character "00H" "07H", DDRAM address range character "40H" "47H".
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Read Busy Flag Address
DDRAM
CGRAM
Don't care
This instruction shows whether KS0072 internal operation not. resultant High, internal operation progress should wait until Low, which then next instruction performed. instruction read also value address counter. Write data
(DDRAM)
(CGRAM)
Don't care
Write binary data DDRAM/CGRAM. selection from DDRAM/CGRAM previous address instruction (DDRAM address set, CGRAM address set). After writing operation, address automatically increased/decreased according entry mode.
Read data from
(DDRAM)
(CGRAM)
Don't care
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Read binary from DDRAM/CGRAM. selection previous address instruction. address instruction performed before this instruction, data that read first becomes invalid, direction determined. data read several times without address instruction before read operation, correct data detained from second, first data would incorrect, there time margin transfer data. case DDRAM reading operation, cursor shift instruction plays same role DDRAM address instruction also transfers data output data register. After read operation address counter automatically increased/decreased according entry mode. After CGRAM read operation, display shift executed correctly. case write operation, increased/decreased like read operation (after this operation). this time, indicates next address position, only previous data read read instruction.
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
INTERFACE WITH Interface with 8-bit With 8-bit interfacing data length transfer performed time through ports, from DB7. Example timing sequence shown below.
Internal signal
Internal operation DATA
Busy
Busy
Busy
DATA
INSTRUCTION
Busy Flag Check
Busy Flag Check
Busy Flag Check
INSTRUCTIO
Example 8-bit Mode Timing Diagram Interface with 4-bit When interfacing data length 4-bit, only ports, from DB7, used data bus. first higher 4-bit case 8-bit mode, contents DB4-DB7) transferred, then lower 4-bit case 8-bit mode, contents DB0-DB3) transferred. transfer performed twice. Busy Flag outputs "High" after second transfer ended. Example timing sequence shown below.
Internal signal
Internal operation
Busy Busy
INSTRUCTION
Busy Flag Check
Busy Flag Check
INSTRUCTION
Example 4-bit Mode Timing Diagram
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
APPLICATION INFORMATION COM/SEG output rotation mode DDRAM address mode (A=0)
-S40 -S40 -S20
-S1-S20
-S21-S40
KS0072 BOTTOM VIEW
M0=0, M1=0
DDRAM address mode (A=1)
-S20 1-S4
KS0072 BOTTOM VIEW
M0=0, M1=1
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
APPLICATION INFORMATION COM/SEG output rotation mode DDRAM address mode (A=0)
-S40 -S21
-S40-S21
-S20-S1
KS0072 VIEW
M0=1, M1=0
DDRAM address mode (A=1)
SEG40
SEG61
SEG80
S40-S21 S20-S1
KS0072 VIEW
M0=1, M1=1
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
POWER SUPPLY DRIVING PANEL
KS0072
1.5K(Typ)
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
INITIALIZING Initialize internal power-on-reset circuit When power turned KS0072 initialized automatically power reset circuit. During initialization, following instructions executed, (Busy Flag) kept "High" (busy state) initialization. Initialize flow Display Clear Write "20H" DDRAM Functions 8-bit mode DDRAM addressing mode COM/SEG output rotation mode line character display mode Control Display ON/OFF instruction Display Cursor Blink Entry Mode Increment entire display shift
Initialize external hardware reset "Low" signal forced reset terminal over period then system will initialized. (Busy Flag) kept "High" (busy state) after releasing initializing sequence.
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Initializing instruction 8-bit interface mode
Power
Condition fOSC 270KHz
4-bit interface 8-bit interface DDRAM Addressing mode DDRAM Addressing mode COM/SEG output rotation mode COM/SEG output rotation mode line character display mode line character display mode
Wait more than 20ms after rises 4.5V
Function
DL(1)
Wait more than 37us Display ON/OFF Control
display display cursor cursor blink blink
Wait more than 37us Clear Display
Wait more than 629us
decrement mode increment mode entire shift entire shift
Entry Mode
Initialization
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
4-bit interface mode
Power
Wait more than after rises 4.5V
Condition fOSC 270KHz
4-bit interface 8-bit interface DDRAM Addressing mode DDRAM Addressing mode COM/SEG output rotation mode COM/SEG output rotation mode 1line character display mode 2line character display mode
Function (4-bit mode change)
DL(0)
Wait more than 37µs
Function (display mode set)
Wait more than 37µs
Display ON/OFF Control
display display cursor cursor blink blink
Wait more than 37µs
Clear Display
Wait more than 629µs
Entry Mode
decrement mode increment mode entire shift entire shift
Initialization
"X": open "*": don' care
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
FRAME FREQUENCY 1/16 duty cycle
1-line selection period 1FRAME 1FRAME COM1
1-Line selection period clocks Frame 3.7µs 9.472ms CLOCK 3.7µs fosc=270KHz) Frame frequency 9.472ms 105.6Hz
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
MAXIMUM ABSOLUTE LIMIT Maximum absolute Power Ratings Characteristic Power supply voltage Power supply voltage Input voltage Symbol VLCD Value -0.3 -0.3 -0.3 Unit
Voltage greater than above damage circuit (VDD VLCD VDD-V5)
Temperature Characteristics Characteristic Operating temperature Storage temperature Symbol TOPR TSTG Value Unit
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
ELECTRICAL CHARACTERISTICS Characteristics (VDD 5.5V, 85°C) Characteristic Operating Voltage Supply Current Input Voltage (except EXTCLK) Input Voltage (EXTCLK) Input Voltage pin) Output Voltage (DB0 DB7) Voltage Drop Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VdCOM VdSEG Input Leakage Current Input Current Driving Voltage Divide Resistor (PULL output port VDD-V5=5V RB=(VDD-V5) Divide Resistor Current Condition Internal oscillation (VDD 5.0V, fosc=270KHz) -0.205 (mA) (mA) (mA) 0.7VDD -0.3 VDD-1.0 -0.2 0.8VDD -125 0.2VDD -250 11.5 Unit
Internal Clock (internal Driving Voltage
VLCD
11.0
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
(VDD 4.5V, 85°C) Characteristic Operating Voltage Supply Current Input Voltage (except EXTCLK) Input Voltage (EXTCLK) Input Voltage pin) Output Voltage (DB0 DB7) Voltage Drop Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VdCOM VdSEG Input Leakage Current Input Current Driving Voltage Divide Resistor Condition Internal oscillation (VDD 3.0V, fosc=270KHz) -0.1 (mA) (mA) (mA) VLCD (PULL output port VDD-V5=5V RB=(VDD-V5) Divide Resistor Current 0.7VDD -0.3 VDD-1.0 -0.2 0.8VDD 0.75VDD -0.3 0.2VDD 0.2VDD -120 11.5 Unit
Internal Clock (internal Driving Voltage
VLCD
11.0
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Characteristics (VDD 5.5V, 85°C) Mode Write Mode (Refer Fig-3) Characteristic Cycle Time Rise Fall Time Pulse Width (High, Low) Setup Time Hold Time Data Setup Time Data Hold Time Read Mode (Refer Fig-4) Cycle Time Rise Fall Time Pulse Width (High, Low) Setup Time Hold Time Data Output Delay Time Data Hold Time Symbol tsu1 tsu2 Unit
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
(VDD 4.5V, 85°C) Mode Write Mode (Refer Fig-3) Characteristic Cycle Time Rise Fall Time Pulse Width (High, Low) Setup Time Hold Time Data Setup Time Data Hold Time Read Mode (Refer Fig-4) Cycle Time Rise Fall Time Pulse Width (High, Low) Setup Time Hold Time Data Output Delay Time Data Hold Time Symbol tsu1 tsu2 1000 1000 Unit
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
VIH1 VIL1
VIL1
VIH1 VIL1
DB0~DB7
Valid
VIH1 VIL1
Fig-3. Write Mode Timing Diagram
VOH1 VOL1 VOH1 Valid VOL1 VIL1
VIH1 VIL1
DB0~DB7
Fig-4. Read Mode Timing Diagram
KS0072
16COM 40SEG CONTROLLER DRIVER MATRIX
Table CGROM Character Code Table
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