XE88LC01/01A Sensing Machine Data Acquisition with 16+10 ZoomingA
|
|
|
Top Searches for this datasheet
Datasheet XE88LC01/01A Sensing Machine Data Acquisition with ZoomingADC
XE88LC01/01A Sensing Machine
Data Acquisition with 16+10 ZoomingADCXE88LC01A data acquisition ultra lowpower low-voltage system chip (SoC) with high efficiency embedded microcontroller unit (MCU), allowing MIPS 300uA multiplying clock cycle. XE88LC01A includes high resolution acquisition path with16+10 bits. XE88LC01A available with chip Multiple-Time-Programmable (MTP) program memory.
product Features
Low-power, high resolution ZoomingADC
1000 gain with offset cancellation bits analog digital converter inputs multiplexer MIPS with operation MIPS over voltage range
Low-voltage low-power controller operation kByte kInstruction) Byte data memory crystal oscillators reset, interrupt, event sources years Flash retention 55°C
Applications
Portable, battery operated instruments Current loop powered instruments Wheatstone bridge interfaces Pressure chemical sensors HVAC control Metering Sports watches, wrist instruments
Ordering Information
Product XE88LC01MI027* XE88LC01AMI000 XE88LC01AMI027 XE88LC01ARE000 XE88LC01ARE027 *Not designs Temperature range -40°C -40°C -40°C -40°C -40°C Memory type Package LQFP44 LQFP44 LQFP44
Solu tion eles
XEMICS e-mail: info@xemics.com web: www.xemics.com
Datasheet XE88LC01/01A Sensing Machine Data Acquisition with ZoomingADC
TABLE CONTENTS
Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter XE88LC01/01A Overview XE88LC01/01A Performance XE88LC01/01A XE88LC01/01A Memory System Block Reset generator Clock generation Interrupt handler Event handler power Port Port Port Universal Asynchronous Receiver/Transmitter (UART) Universal Synchronous Receiver/Transmitter (USRT) Acquisition Chain Voltage multiplier Counters/Timers/PWM Voltage Level Detector XE88LC01/01A Dimensions
D0304-60
Datasheet XE88LC01/01A
General overview
CONTENTS
schematic 1.1.1 General description 1.1.2 XE88LC01 XE88LC01A 1.2.1 Bare 1.2.2 LQFP-44 package assignment
LC01 avril 2003
D0304-60
Datasheet XE88LC01/01A
schematic
1.1.1 General description level block schematic circuit shown Figure 1-1. heart circuit consists Coolrisc816® core. This core includes multiplier internal registers. controller generates control signals access data registers other than internal registers. reset block generates adequate reset signals rest circuit function setup contained control registers. Possible reset sources power-on-reset (POR), external RESET, watchdog (WD), error detected controller programmable pattern Port Different power modes implemented. clock generation power management block sets clock signals generates internal supplies different blocks. clock generated from oscillator (this start-up condition), crystal oscillator (XTAL) external clock source (given OSCIN pin). test controller generates set-up signals different test modes. normal operation, used power data registers. power consumption important application, variables that need accessed very often should stored these registers rather than RAM. handler routes interrupt signals different peripherals inputs core. allows masking interrupt sources flags which interrupt source active. Events generally used restart processor after HALT period without jumping specified address, i.e. program execution resumes with instruction following HALT instruction. handler routes event signals different peripherals inputs core. allows masking interrupt sources flags which interrupt source active. Port parallel port with analog capabilities. URST, UART, block also make this port. instruction memory 22-bit wide flash memory depending circuit version. Flash versions have both instruction memory. data memory this product byte SRAM. Acquisition Chain high resolution acquisition path with 16+10 bits ZoomingADC. VMULT (voltage multiplier) powers part Acquisition Chain. Port parallel input port. also generate interrupts, events reset. used input external clocks timer/counter/PWM block. Port general purpose parallel port. USRT (universal synchronous receiver/transmitter) contains some simple hardware functions order simplify software implementation synchronous serial link. UART (universal asynchronous receiver/transmitter) contains full hardware implementation asynchronous serial link. counters/timers/PWM take clocks from internal external sources Port generate interrupts events. output Port D0304-60
Datasheet XE88LC01/01A
(voltage level detector) detects battery life with respect programmable threshold.
INSTRUCTION MEMORY
VPP/TEST
DATA MEMORY
COOLRISC816
VBAT
MULTIPLIER
address control datain
PORT
PA(7:0)
dataout
PORT
PC(7:0)
REGISTERS
RESET
RESET BLOCK
reset control
ACQUISITION CHAIN
AC_R(3:0)
ZoomingADC
XTAL
VREG
TEST CONTROLLER
OSCIN OSCOUT VREG
CLOCK GENERATION/ POWER MANAGEMENT
clocks
AC_A(7:0)
test control
DATA REGISTERS
HANDLING
VMULT
USRT
PB(5:4)
VMULT
HANDLING
UART
PORT
PB(7:0)
Figure 1-1. Block schematic XE88LC01/01A circuit.
D0304-60
PB(1:0) PA(3:0)
COUNTERS TIMERS
PB(7:6)
Datasheet XE88LC01/01A 1.1.2 XE88LC01 XE88LC01A XE88LC01A RESET function. action RESET XE88LC01A resets clock registers creates additional short delay. RESET chapter more information.
1.2.1 Bare
(1477.6, 4453.4) (2007.6, 4453.4) (1212.6, 4453.4) (1742.6, 4453.4) (2537.0, 4453.4) (2802.6, 4453.4) (3067.6, 4453.4) (3332.6, 4453.4) (3597.6, 4453.4) VBAT 417.6, 4453.4) 682.6, 4453.4) 947.6, 4453.4)
OSCOUT
VMULT
RESET
OSCIN
(52.6,4075.5) (52.6, 3795.5) (52.6,3515.5) (52.6, 3235.5) (52.6, 2955.5) (52.6, 2675.5) (52.6, 2395.5) (52.6, 2115.5) (52.6, 1835.5) (52.6, 1555.5) (52.6, 1275.5) (52.6, 995.5) (52.6, 715.5) (52.6, 435.5)
PA(4) PA(5) VBAT PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) AC_R(0) AC_R(1) AC_A(0) AC_A(1) AC_A(2) AC_A(3) AC_A(4) AC_A(5) (3958.4, 3657.4) (3958.4, 3657.4) (3958.4, 3372.4) (3958.4, 3087.4) (3958.4, 2802.4) (3958.4, 2517.4) (3958.4, 2232.4) (3958.4, 1947.4) (3958.4,1662.4) (3958.4, 1377.4) (3958.4, 1092.4) (3958.4, 807.4) (3958.4, 522.4)
4600
PC(4) PC(5) PC(6) PC(7)
VREG
PA(3)
PA(2)
PA(1)
PA(0)
AC_A(6) VBAT
4100
AC_A(7)
PB(0) PB(1) PB(2) PB(3) PB(4) VBAT PB(5) PB(6) PB(7)
AC_R(3) (2854.1, 47.6)
(1934.1, 47.6)
Figure 1-2. dimensions coordinates µm).
(2394.1, 47.6)
398.5, 47.6) 533.5, 47.6) 668.5, 47.6) 798.5, 47.6) 933.5, 47.6) (1063.5, 47.6) (1198.5, 47.6) (1328.5, 47.6) (1463.5, 47.6)
(2854.1, 47.6)
AC_R(2)
TEST
D0304-60
Datasheet XE88LC01/01A
1.2.2 LQFP-44 package XE88LC01/01A delivered LQFP-44 package. given below.
VPP/TEST AC_R(2) AC_R(3) PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0)
AC_A(7) AC_A(6) AC_A(5) AC_A(4) AC_A(3) AC_A(2) AC_A(1) AC_A(0) AC_R(1) AC_R(0)
PC(7) PC(6) PC(5) PC(4) PC(3) PC(2) PC(1) PC(0) PA(7) PA(6) PA(5)
OSCIN
VBAT
VREG
PA(0)
PA(1) PA(2)
PA(3)
Figure 1-3. LQFP-44
Package
name PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7) PB(0) PB(1) PB(2) PB(3) PB(4) PB(5) PB(6) PB(7) VPP/TEST AC_R(3) AC_R(2)
Package
OSCOUT
RESET
VMULT
Table 1-1. Bonding plan LQFP-44 package (LQFP 10x10mm thick
PA(4)
name AC_A(7) AC_A(6) AC_A(5) AC_A(4) AC_A(3) AC_A(2) AC_A(1) AC_A(0) AC_R(1) AC_R(0) VBAT VREG RESET VMULT OSCIN OSCOUT PA(0) PA(1) PA(2) PA(3) PA(4)
D0304-60
Datasheet XE88LC01/01A
assignment
table below gives short description different assignments.
VBAT VREG VPP/TEST RESET OSCIN/OSCOUT PA(7:0) PB(7:0) PC(7:0) AC_A(7:0) AC_R(3:0) VMULT
Assignment
Positive power supply Negative power supply Connection mandatory external capacitor voltage regulator High voltage supply flash memory programming versions) Resets circuit when voltage high Quartz crystal connections, also used flash memory programming Parallel input port pins Parallel port pins Parallel port pins Acquisition chain input pins Acquisition chain reference pins Connection external capacitor VBAT below
Table 1-2. assignment Table gives more detailed different pins. also indicates possible configuration these pins. indications blue bold configuration start-up. pins CNTx pins possible counter inputs, PWMx possible outputs. lqfp-44 function second configuration POWER D0304-60
third
first
PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7) PB(0) PB(1) PB(2) PB(3) PB(4) PB(5) PB(6) PB(7) AC_R(3) AC_R(2) AC_A(7) AC_A(6) AC_A(5) AC_A(4) AC_A(3)
PWM0 PWM1
USRT_S0 USRT_S1 UART_Tx UART_Rx TEST
Datasheet XE88LC01/01A AC_A(2) AC_A(1) AC_A(0) AC_R(1) AC_R(0) VBAT VREG RESET VMULT OSCIN OSCOUT PA(0) PA(1) PA(2) PA(3) PA(4) CNTA CNTB CNTC CNTD
table legend: blue bold: configuration start analog input analog output digital input digital output nMOS open drain output pull-up resistor POWER: power supply
Table 1-3. description table
D0304-60
Datasheet XE88LC01/01A
XE88LC01/01A performance
Absolute maximum ratings Operating range
Supply configurations 2.3.1 Flash circuit 2.3.2 circuit Current consumption
Operating speed 2.5.1 Flash version 2.5.2 circuit version
LC01 october 2002
D0304-60
Datasheet XE88LC01/01A
Absolute maximum ratings
Table 2-1. Absolute maximal ratings Min. Voltage applied VBAT with respect Voltage applied with respect Voltage applied pins except VBAT Storage temperature (ROM device unprogrammed flash device) Storage temperature (programmed flash device) -0.3 VBAT-0.3 VSS-0.3 Max. VBAT+0.3 Note
Stresses beyond absolute maximal ratings cause permanent damage device. Functional operation absolute maximal ratings implied. Exposure conditions beyond absolute maximal ratings affect reliability device.
Operating range
Table 2-2. Operating range flash device Min. Voltage applied VBAT with respect Voltage applied VBAT with respect during flash programming Voltage applied with respect Voltage applied pins except VBAT Operating temperature range Capacitor VREG (flash version) Capacitor VMULT VBAT Max. 11.5 VBAT Note
During programming device, supply voltage should least equal supply voltage used during normal operation. capacitor VREG mandatory. capacitor VMULT optional. capacitor present multiplier enabled. multiplier enabled VBAT<3.0V.
Table 2-3. Operating range device Min. Voltage applied VBAT with respect Voltage applied pins except VBAT Operating temperature range Capacitor VREG Capacitor VMULT Max. VBAT Note
capacitor omitted when VREG connected VBAT. capacitor VMULT optional. capacitor present multiplier enabled. multiplier enabled VBAT<3.0V.
specifications this document valid complete operating range unless otherwise specified.
D0304-60
Datasheet XE88LC01/01A
Table 2-4. Operating range Flash memory Min. Retention time 85°C Retention time 55°C Number programming cycles Max. years years Note
Valid only programmed using programming tool that qualified Circuits programmed more than times that case, retention time longer guaranteed.
2.3.1
Supply configurations
Flash circuit
flash version circuit from supply between 2.4V 5.5V (Figure 2-1). capacitor VREG connected times (value Table 2-2) guarantee proper operation device. capacitor VMULT only required circuit operated below
VBAT
VREG VMULT Cvreg Cvmult
2.4V 5.5V
Figure 2-1. Supply configuration flash circuit. 2.3.2 circuit
version, possible operating modes exist: with without voltage regulator. Using voltage regulator, power consumption will obtained even with supply voltages above 2.4V. Without voltage regulator (i.e. VREG short-circuited VBAT), higher speed obtained. 2.1.3.1 power operation
this case, internal voltage regulator used order maintain power consumption independent from supply voltage. capacitor VREG connected times (value Table 2-3) guarantee proper operation device. capacitor VMULT connected only when VBAT<3V.
D0304-60
Datasheet XE88LC01/01A
VBAT
VREG VMULT Cvreg Cvmult
2.4V 5.5V
Figure 2-2. Supply voltage connections power operation version. 2.1.3.2 High speed operation
this case, internal voltage regulator used. operation speed circuit increased with increasing supply voltage supply current will also increase. capacitor VMULT connected only when VBAT<3V. this case, supply voltage decrease down 2.15V. Beware however that ZoomingADCwill below 2.4V (see Figure 2-4). this configuration, circuit used above 3.3V.
VBAT
VREG VMULT Cvmult
2.15V 3.3V
Figure 2-3. Supply voltage connections high speed operation version.
D0304-60
Datasheet XE88LC01/01A
acquisition chain voltage multiplier parallel serial ports crystal oscillator Counters
2.15
VBAT
Figure 2-4. Operation range different circuit blocks
Current consumption
tables below give current consumption circuit different configurations. figures indicative only change function actual software implemented circuit. Table gives current consumption flash version circuit. peripherals disabled. parallel ports configured input with pull parallel port configured output. Their pins connected externally. RESET connected VPP/TEST connected VBAT. inputs acquisition chain connected VSS. Table 2-5. Typical current consumption XE88LC01M version instructions flash memory) Operation mode High speed power power time keeping Fast wake-up time keeping Immediate wakeup time keeping static current resolution data acquisition gain 100, data acquisition MIPS kIPS HALT HALT HALT Ready Xtal 32kHz Consumption comments 2.4V<>5.5V, 27°C 2.4V <>5.5V, 27°C 2.4V <>5.5V, 27°C 2.4V <>5.5V, 27°C 2.4V <>5.5V, 27°C 2.4V <>5.5V, 27°C 3.0V, 27°C 3.0V, 27°C Note
HALT HALT
disabled, enabled, resolution disabled, enabled, enabled, resolution more information concerning current consumption ZoomingADCTM, chapter power consumption acquisition chain documentation which shows current consumption this block function temperature voltage different configurations ADC. power consumption version circuit identical configured shown Figure 2-2. high speed configuration, current consumption will increase proportional with VBAT.
D0304-60
Datasheet XE88LC01/01A
2.5.1
Operating speed
Flash version
speed devices highly dependent upon supply voltage. However, limiting temperature range, speed increased. minimal guaranteed speed function supply voltage maximal temperature operating temperature given Figure 2-5.
speed (MIPS)
supply voltage VBAT
85°C
45°C
Figure 2-5. Guaranteed speed function supply voltage maximal temperature. 2.5.2 2.1.5.1 circuit version power supply configuration
power supply configuration shown Figure 2-2, operating speed does depend highly supply voltage shown Figure 2-6.
85°C supply voltage VBAT speed (MIPS) 45°C 125°C
Figure 2-6. Guaranteed speed function supply voltage different maximal temperatures using voltage regulator. 2.1.5.2 High speed supply configuration
high speed supply configuration Figure 2-3, guaranteed speed circuit shown Figure 2-7.
D0304-60
Datasheet XE88LC01/01A
85°C speed (MIPS)
45°C
125°C
supply voltage VBAT
Figure 2-7. Guaranteed speed function supply voltage three temperature ranges when VREG=VBAT.
D0304-60
Datasheet XE88LC01/01A
CONTENTS
description internal registers instruction short reference
D0304-60
Datasheet XE88LC01/01A
description
XE8000 series power RISC core. internal registers efficient implementation compiler. instruction made generic instructions, coded bits, with addressing modes. instructions executed clock cycle, including conditional jumps multiplication. circuit therefore runs MIPS 1MHz clock. hardware software description given document "Coolrisc816 Hardware Software Reference Manual". short summary given following paragraphs. good code efficiency core makes possible compute polynomial like less than clock cycles (software code generated XEMICS C-compiler, numbers signed integers bits).
internal registers
shown Figure 3-1, internal 8-bit registers. Some these registers concatenated 16-bit word some instructions. function these registers defined Table 3-1. status register stat (Table 3-2) used manage different interrupt event levels. interrupt event both used wake after HALT instruction. difference that interrupt jumps special interrupt function whereas event continues software execution with instruction following HALT instruction. program counter (PC) register that indicates address instruction that executed. stack (STn) used memorise return address when executing subroutines interrupt routines.
program counter stack instruction
stat data internal registers
Instruction memory 22bit
Data memory
Figure 3-1. internal registers
D0304-60
Datasheet XE88LC01/01A
Register name stat
Register function general purpose general purpose general purpose data memory offset data memory index data memory index data memory index data memory index data memory index data memory index data memory index data memory index program memory index program memory index status register accumulator
Table 3-1. internal register definition name function enables (when interrupt request level enables (when interrupt request level enables (when interrupt request levels interrupt request level interrupts labelled "low" interrupt handler routed this interrupt level. This cleared when interrupt served. interrupt request level interrupts labelled "mid" interrupt handler routed this interrupt level. This cleared when interrupt served. interrupt request level interrupts labelled "hig" interrupt handler routed this interrupt level. This cleared when interrupt served. event request level events labelled "low" event handler routed this event level. This cleared when event served. event request level events labelled "hig" event handler routed this event level. This cleared when event served.
Table 3-2. Status register description also number flags that used conditional jumps. These flags defined Table 3-3. symbol name zero carry function when accumulator content zero This flag used shift arithmetic operations. shift operation, value that shifted (LSB shift right, shift left). arithmetic operation with unsigned numbers: occurrence overflow during addition equivalent). occurrence underflow during subtraction equivalent). This flag used shift arithmetic operations. arithmetic shift operations with signed numbers, overflow underflow occurs.
overflow
Table 3-3. Flag description
D0304-60
Datasheet XE88LC01/01A
instruction short reference
Table shows short description different instructions available Coolrisc816. notation conditional jump instruction refers condition description given Table 3-6. notation reg, reg1, reg2, reg3 refers internal registers Table 3-1. notation eaddr DM(eaddr) refer extended address modes defined Table 3-5. notation DM(xxx) refers data memory location with address xxx.
Instruction
Jump addr[15:0] Jump addr[15:0] Call addr[15:0] Call Calls addr[15:0] Calls Rets Reti Push Move reg,#data[7:0] Move reg1, reg2 Move reg, eaddr Move eaddr, Move addr[7:0],#data[7:0] Cmvd reg1, reg2 Cmvd reg, eaddr Cmvs reg1, reg2 Cmvs reg, eaddr reg1, reg2 reg, eaddr Shlc reg1, reg2 Shlc Shlc reg, eaddr reg1, reg2 reg, eaddr Shrc reg1, reg2 Shrc Shrc reg, eaddr Shra reg1, reg2 Shra Shra reg, eaddr Cpl1 reg1, reg2 Cpl1 Cpl1 reg, eaddr Cpl2 reg1, reg2 Cpl2 Cpl2 reg, eaddr Cpl2c reg1, reg2 Cpl2c Cpl2c reg, eaddr reg1, reg2 reg, eaddr Incc reg1, reg2 Incc Incc reg, eaddr reg1, reg2
Modification
-,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-, -,-, -,-, -,-,-, -,-,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-,
Operation
addr[15:0] true then addr[15:0] true then STn+1 (n>1); PC+1; addr[15:0] STn+1 (n>1); PC+1; PC+1; addr[15:0] PC+1; ST1; STn+1 (n>1) ST1; STn+1 (n>1); PC+1; STn+1 (n>1); PC+1; ST1; STn+1 (n>1) data[7:0]; data[7:0] reg2; reg1 reg2 DM(eaddr); DM(eaddr) DM(eaddr) DM(addr[7:0]) data[7:0] reg2; then reg1 DM(eaddr); then reg2; then reg1 DM(eaddr); then reg2<<1; a[0] reg2[7]; reg1 reg<<1; a[0] reg[7]; DM(eaddr)<<1; a[0] :=0; DM(eaddr)[7]; reg2<<1; a[0] reg2[7]; reg1 reg<<1; a[0] reg[7]; DM(eaddr)<<1; a[0] DM(eaddr)[7]; reg2>>1; a[7] reg2[0]; reg1 reg>>1; a[7] reg[0]; DM(eaddr)>>1; a[7] DM(eaddr)[0]; reg2>>1; a[7] reg2[0]; reg1 reg>>1; a[7] reg[0]; DM(eaddr)>>1; a[7] DM(eaddr)[0]; reg2>>1; a[7] reg2[7]; reg2[0]; reg1 reg>>1; a[7] reg[7]; reg[0]; DM(eaddr)>>1; a[7] DM(eaddr)[7]; DM(eaddr)[0]; NOT(reg2); reg1 NOT(reg); NOT(DM(eaddr)); NOT(reg2)+1; then C:=1 else reg1 NOT(reg)+1; then C:=1 else NOT(DM(eaddr))+1; then C:=1 else NOT(reg2)+C; then C:=1 else reg1 NOT(reg)+C; then C:=1 else NOT(DM(eaddr))+C; then C:=1 else reg2+1; then else reg1 reg+1; then else DM(eaadr)+1; then else reg2+C; then else reg1 reg+C; then else DM(eaadr)+C; then else reg2-1; a=hFF then else reg1
D0304-60
Datasheet XE88LC01/01A
reg, eaddr Decc reg1, reg2 Decc Decc reg, eaddr reg,#data[7:0] reg1, reg2, reg3 reg1, reg2 reg, eaddr reg,#data[7:0] reg1, reg2, reg3 reg1, reg2 reg, eaddr reg,#data[7:0] reg1, reg2, reg3 reg1, reg2 reg, eaddr reg,#data[7:0] reg1, reg2, reg3 reg1, reg2 reg, eaddr Addc reg,#data[7:0] Addc reg1, reg2, reg3 Addc reg1, reg2 Addc reg, eaddr Subd reg,#data[7:0] Subd reg1, reg2, reg3 Subd reg1, reg2 Subd reg, eaddr Subdc reg,#data[7:0] Subdc reg1, reg2, reg3 Subdc reg1, reg2 Subdc reg, eaddr Subs reg,#data[7:0] Subs reg1, reg2, reg3 Subs reg1, reg2 Subs reg, eaddr Subsc reg,#data[7:0] Subsc reg1, reg2, reg3 Subsc reg1, reg2 Subsc reg, eaddr reg,#data[7:0] reg1, reg2, reg3 reg1, reg2 reg, eaddr Mula reg,#data[7:0] Mula reg1, reg2, reg3 Mula reg1, reg2 Mula reg, eaddr Mshl reg,#shift[2:0] Mshr reg,#shift[2:0] Mshra reg,#shift[2:0] reg,#data[7:0] reg1, reg2 reg, eaddr Cmpa reg,#data[7:0] Cmpa reg1, reg2 Cmpa reg, eaddr Tstb reg,#bit[2:0] Setb reg,#bit[2:0] Clrb reg,#bit[2:0] Invb reg,#bit[2:0]
-,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-, -,-,
reg-1; a=hFF then else DM(eaddr)-1; a=hFF then else reg2-(1-C); a=hFF then else reg1 reg-(1-C); a=hFF then else DM(eaddr)-(1-C); a=hFF then else data[7:0]; reg2 reg3; reg1 reg1 reg2; reg1 DM(eaddr); data[7:0]; reg2 reg3; reg1 reg1 reg2; reg1 DM(eaddr); data[7:0]; reg2 reg3; reg1 reg1 reg2; reg1 DM(eaddr); reg+data[7:0]; overflow then C:=1 else reg2+reg3; overflow then C:=1 else reg1 reg1+reg2; overflow then C:=1 else reg1 reg+DM(eaddr); overflow then C:=1 else reg+data[7:0]+C; overflow then C:=1 else reg2+reg3+C; overflow then C:=1 else reg1 reg1+reg2+C; overflow then C:=1 else reg1 reg+DM(eaddr)+C; overflow then C:=1 else data[7:0]-reg; underflow then else reg2-reg3; underflow then else reg1 reg2-reg1; underflow then else reg1 DM(eaddr)-reg; underflow then else data[7:0]-reg-(1-C); underflow then else reg2-reg3-(1-C); underflow then else reg1 reg2-reg1-(1-C); underflow then else reg1 DM(eaddr)-reg-(1-C); underflow then else reg-data[7:0]; underflow then else reg3-reg2; underflow then else reg1 reg1-reg2; underflow then else reg1 reg-DM(eaddr); underflow then else reg-data[7:0]-(1-C); underflow then else reg3-reg2-(1-C); underflow then else reg1 reg1-reg2-(1-C); underflow then else reg1 reg-DM(eaddr)-(1-C); underflow then else (data[7:0]*reg)[7:0]; (data[7:0]*reg)[15:8] (reg2*reg3)[7:0]; reg1 (reg2*reg3)[15:8] (reg2*reg1)[7:0]; reg1 (reg2*reg1)[15:8] (DM(eaddr)*reg)[7:0]; (DM(eaddr)*reg)[15:8] (data[7:0]*reg)[7:0]; (data[7:0]*reg)[15:8] (reg2*reg3)[7:0]; reg1 (reg2*reg3)[15:8] (reg2*reg1)[7:0]; reg1 (reg2*reg1)[15:8] (DM(eaddr)*reg)[7:0]; (DM(eaddr)*reg)[15:8] (reg*2 )[7:0]; (reg*2 )[15:8] (8-shift (8-shift (reg*2 )[7:0]; (reg*2 )[15:8] (8-shift (8-shift (reg*2 )[7:0]; (reg*2 )[15:8] data[7:0]-reg; underflow then else C:=1; (not reg2-reg1; underflow then else C:=1; (not DM(eaddr)-reg; underflow then else C:=1; (not data[7:0]-reg; underflow then else C:=1; (not reg2-reg1; underflow then else C:=1; (not DM(eaddr)-reg; underflow then else C:=1; (not a[bit] reg[bit]; other bits reg[bit] other bits unchanged; reg[bit] other bits unchanged; reg[bit] reg[bit]; other bits unchanged;
shift shift
D0304-60
Datasheet XE88LC01/01A
Sflag Rflag Rflag eaddr Freq divn Halt
-,-,-, -,-,-, -,-,-, -,-,-,
a[7] a[6] a[5] full; a[4] empty a[0] reg[7] DM(eaddr)<<1; a[0] :=0; DM(eaddr)[7] reduces frequency (divn=nodiv, div2, div4, div8, div16) halts operation
unchanged, undefined, *MSHR reg,# doesn't shift
Table 3-4. Instruction short reference Coolrisc816 different addressing modes. These modes described Table 3-5. this table, notation refers data memory index registers Using eaddr instruction Table will access data memory address DM(eaddr) will simultaneously execute index operation.
extended address eaddr addr[7:0] (ix) (ix, offset[7:0]) (ix,r3) (ix)+ (ix,offset[7:0])+ -(ix) -(ix,offset[7:0]) accessed data memory location DM(eaddr) DM(h00&addr[7:0]) DM(ix) DM(ix+offset) DM(ix+r3) DM(ix) DM(ix+offset) DM(ix-1) DM(ix-offset) index operation ix+1 ix+offset ix-1 -offset direct addressing indexed addressing indexed addressing with immediate offset indexed addressing with register offset indexed addressing with index post-increment indexed addressing with index post-increment offset indexed addressing with index pre-decrement indexed addressing with index pre-decrement offset
Table 3-5. Extended address mode description Eleven different jump conditions implemented shown Table 3-6. contents column this table should replace notation instruction description Table 3-4.
condition
(EV1 EV0)=1
After op1,op2
op1=op2 op1op2 op1>op2 op1op2 op1<op2 op1op2
Table 3-6. Jump condition description
D0304-60
Datasheet XE88LC01/01A
Memory mapping
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.2.11 4.2.12 4.2.13 4.2.14 4.2.15
Memory organisation Quick reference data memory register power data registers (h0000-h0007) System, clock configuration reset configuration (h0010-h001F) Port (h0020-h0027) Port (h0028-h002F) Port (h0030-h0033) Flash programming (h0038-003B) Event handler (h003C-h003F) Interrupt handler (h0040-h0047) USRT (h0048-h004F) UART (h0050-h0057) Counter/Timer/PWM registers (h0058-h005F) Acquisition chain registers (h0060-h0067) Voltage multiplier (h007C) Voltage Level Detector registers (h007E-h007F) (h0080-h027F)
LC01 october 2002
D0304-60
Datasheet XE88LC01/01A
Memory organisation
XE88LC01 built with Harvard architecture. Harvard architecture uses separate instruction data memories. instruction data also separated. advantage such structure that instruction read/write data simultaneously. circuit configuration shown Figure 4-1. internal registers. instruction memory capacity 8192 22-bit instructions. data memory space power registers, peripheral register space bytes RAM.
0h1FFF
0h027F
instruction
capacity: bytes
stat data internal registers
capacity: 22bit
0h0080 0h007F Peripheral registers 0h0008 power 0h0000
0h0000
Figure 4-1. Memory mapping internal registers described chapter. short reference power registers peripheral registers given 4.2.
Quick reference data memory register
data register given tables below. more detailed description different registers given detailed description different peripherals. tables give following information: register name register address different bits register access mode different bits (see Table 4-4-1 code description) reset source reset value different bits
D0304-60
Data memory
Instruction memory
Datasheet XE88LC01/01A
reset source coding given Table 4-4-2. full description reset sources, please refer reset block chapter. code access mode read written always reads always reads cleared writing value cleared writing cleared after reading special function, verify detailed description respective peripherals Table 4-4-1. Access mode codes used register definitions code cold pconf sleep reset source resetsystem resetcold resetpconf resetsleep
Table 4-4-2. Reset source coding used register definitions 4.2.1
Address Reg00 h0000 Reg01 h0001 Reg02 h0002 Reg03 h0003 Reg04 h0004 Reg05 h0005 Reg06 h0006 Reg07 h0007
power data registers (h0000-h0007)
Name Reg00[7:0] xxxxxxxx,Reg01[7:0] rw,xxxxxxxx,Reg02[7:0] rw,xxxxxxxx,Reg03[7:0] rw,xxxxxxxx,Reg04[7:0] rw,xxxxxxxx,Reg05[7:0] rw,xxxxxxxx,Reg06[7:0] rw,xxxxxxxx,Reg07[/:0] rw,xxxxxxxx,2
Table 4-4-3. power data registers
D0304-60
Datasheet XE88LC01/01A
4.2.2
System, clock configuration reset configuration (h0010-h001F)
EnResPConf rw,0,cold ExtClk r,0,cold EnBusError rw,0,cold EnResWD rw,0,cold ResetWD cold BiasRC rw,1,cold
ResetfromportA
Name Address RegSysCtrl SleepEn h0010 rw,0,cold RegSysReset Sleep h0011 rw,0,sys RegSysClock CpuSel h0012 rw,0,sleep RegSysMisc h0013 RegSysWd h0014 RegSysPre0 h0015 RegSysRcTrim1 h001B RegSysRcTrim2 h001C
ResPad ResPadSleep cold cold rc,0,cold rc,0,cold EnExtClock ColdXtal ColdRC EnableXtal EnableRC rw,0,cold r,1,sleep r,1,sleep rw,0,sleep rw,1,sleep RCOnPA0 DebFast OutputCkXtal OutputCpuCk rw,0,sleep rw,0,sleep rw,0,sleep rw,0,sleep WatchDog[3:0] s,0000,cold ResPre c1r0,0,Reserved RcFreqRange RcFreqCoarse[3:0] rw,0,cold rw,0000,cold rw,0,cold RcFreqFine[5:0] rw,10000,cold
ResetBusError
Table 4-4-4. Reset block clock block registers 4.2.3
Address RegPAIn h0020 RegPADebounce h0021 RegPAEdge h0022 RegPAPullup h0023 RegPARes0 h0024 RegPARes1 h0025
Port (h0020-h0027)
Name PAIn[7:0] PADebounce[7:0] rw,00000000,pconf PAEdge[7:0] rw,00000000,sys PAPullup[7:0] rw,00000000,pconf PARes0[7:0] 00000000, PARes1[7:0] rw,00000000,sys
Table 4-4-5. Port registers 4.2.4
Address RegPBOut h0028 RegPBIn h0029 RegPBDir h002A RegPBOpen h002B RegPBPullup h002C RegPBAna h002D
Port (h0028-h002F)
Name PBOut[7:0] rw,00000000,pconf PBIn[7:0] PBDir[7:0] rw,00000000,pconf PBOpen[7:0] rw,00000000,pconf PBPullup[7:0] rw,00000000,pconf
PBAna[3:0] rw,0000,pconf
Table 4-4-6. Port registers
D0304-60
Datasheet XE88LC01/01A
4.2.5
Address
Port (h0030-h0033)
Name RegPCOut RegPCIn PCOut[7:0] rw,00000000,pconf PCIn[7:0] r,-,PD1Dir[7:0] rw,00000000,pconf
h0030 h0031 RegPCDir h0032
Table 4-4-7. Port registers 4.2.6 Flash programming (h0038-003B)
These four registers used during flash programming only. Refer flash programming algorithm documentation more details. 4.2.7
Address RegEvn h003C RegEvnEn h003D RegEvnPriority h003E RegEvnEvn h003F
Event handler (h003C-h003F)
Name CntIrqA rc1,0,sys CntIrqC rc1,0,sys 128Hz rc1,0,sys PAEvn[1] CntIrqB rc1,0,sys rc1,0,sys EvnEn[7:0] rw,00000000,sys EvnPriority[7:0] r,11111111,sys CntIrqD rc1,0,sys rc1,0,sys PAEvn[0] rc1,0,sys
EvnHigh r,0,sys
EvnLow r,0,sys
Table 4-4-8. Event handler registers origin different events summarised table below. Event CntIrqA CntIrqB CntIrqC CntIrqD 128Hz PAEvn[1:0] Event source Counter/Timer (counter block) Counter/Timer (counter block) Counter/Timer (counter block) Counter/Timer (counter block) prescaler (clock block) prescaler (clock block) Port
Table 4-4-9. Event source description
D0304-60
Datasheet XE88LC01/01A
4.2.8
Address
Interrupt handler (h0040-h0047)
Name 128Hz rc1,0,sys UrstCond2 rc1,0,sys PAIrq[6] rc1,0,sys PAIrq[5] rc1,0,sys CntIrqB rc1,0,sys CntIrqA CntIrqC rc1,0,sys rc1,0,sys PAIrq[4] rc1,0,sys rc1,0,sys CntIrqD PAIrq[3] rc1,0,sys rc1,0,sys IrqEnHig[7:0] rw,0000000,sys IrqEnMid[7:0] rw,0000000,sys IrqEnLow[7:0] rw,0000000,sys IrqPriority[7:0] r,11111111,sys VldIrq rc1,0,sys PAIrq[2] rc1,0,sys UartIrqTx rc1,0,sys PAIrq[1] rc1,0,sys UartIrqRx rc1,0,sys PAIrq[0] rc1,0,sys
IrqAC h0040 rc1,0,sys RegIrqMid UsrtCond1 h0041 rc1,0,sys RegIrqLow PAIrq[7] h0042 rc1,0,sys RegIrqEnHig h0043 RegIrqEnMid h0044 RegIrqEnLow h0045 RegIrqPriority h0046 RegIrqIrq h0047 RegIrqHig
IrqHig r,0,sys
IrqMid r,0,sys
IrqLow r,0,sys
Table 4-4-10. Interrupt handler registers origin different interrupts summarised table below. Event CntIrqA CntIrqB CntIrqC CntIrqD 128Hz PAIrq[7:0] UartIrqRx UartIrqTx UrstCond1 UsrtCond2 VldIrq IrqAC Event source Counter/Timer (counter block) Counter/Timer (counter block) Counter/Timer (counter block) Counter/Timer (counter block) prescaler (clock block) prescaler (clock block) Port UART reception UART transmission USRT condition USRT condition Voltage level detector Acquisition chain conversion interrupt
Table 4-4-11. Interrupt source description
D0304-60
Datasheet XE88LC01/01A
4.2.9
USRT (h0048-h004F)
UsrtWaitS0 r,0,sys
UsrtEnWaitCond1
Name Address RegUsrtS1 h0048 RegUsrtS0 h0049 RegUsrtCond1 h004A RegUsrtCond2 h004B RegUsrtCtrl h004C RegUsrtBufferS1 h004D RegUsrtEdgeS0 h004E
rw,0,sys
UsrtS1 s,1,sys UsrtS0 s,1,sys UsrtCond1 rc,0,sys UsrtCond2 rc,0,sys UsrtEnWaitS0 UsrtEnable rw,0,sys rw,0,sys UsrtBufferS1 r,0,sys UsrtEdgeS0 r,0,sys
Table 4-4-12. USRT register description 4.2.10 UART (h0050-h0057)
UartEcho rw,0,sys SelXtal rw,0,sys UartEnRx1 rw,0,sys UartEnRx2 rw,0,sys UartEnTx rw,0,sys UartXRx UartXTx rw,0,sys rw,0,sys UartRcSel[2:0] rw,000,sys UartTx[7:0] rw,0000000,sys UartPM rw,0,sys UartBR[2:0] rw,101,sys UartPE rw,0,sys UartWL rw,1,sys
Name Address RegUartCtrl h0050 RegUartCmd h0051 RegUartTx h0052 RegUartTxSta h0053 RegUartRx h0054 RegUartRxSta h0055
UartTxBusy UartTxFull r,0,sys r,0,sys UartRx[7:0] r,00000000,sys UartRxSErr UartRxPErr UartRxFErr UartRxOerr UartRxBusy UartRxFull r,0,sys r,0,sys r,0,sys rc,0,sys r,0,sys r,0,sys
Table 4-13. UART register description
4.2.11
Address
Counter/Timer/PWM registers (h0058-h005F)
Name RegCntA CounterA[7:0] s,xxxxxxxx,CounterB[7:0] s,xxxxxxxx,CounterC[7:0] s,xxxxxxxx,CounterD[7:0] s,xxxxxxxx,CntDCkSel[1:0] CntCCkSel[1:0] CntBCkSel[1:0] CntACkSel[1:0] CntCDownUp CntBDownUp CntADownUp CascadeCD CascadeAB CntPWM1 CntPWM0 rw,x,rw,x,rw,0,sys rw,0,sys rw,x,rw,x,rw,x,rw,x,CapSel[1:0] CapFunc[1:0] Pwm1Size[1:0] Pwm0Size[1:0] rw,00,sys rw,00,sys rw,xx,rw,xx,CntDEnable CntCEnable CntBEnable CntAEnable rw,0,sys rw,0,sys rw,0,sys rw,0,sys
h0058 RegCntB h0059 RegCntC h005A RegCntD h005B RegCntCtrlCk h005C RegCntConfig1 h005D RegCntConfig2 h005E RegCntOn h005F
Table 4-14. Counter/timer/PWM register description.
D0304-60
Datasheet XE88LC01/01A
4.2.12
Acquisition chain registers (h0060-h0067)
Name Address RegAcOutLsb OUT[7:0] h0060 r,0,sys RegAcOutMsb OUT[15:8] h0061 r,0,sys RegAcCfg0 START SET_NELCONV[1:0] SET_OSR[2:0] CONT rw,010,sys h0062 r0,0,sys rw,01,sys rw,0,sys RegAcCfg1 IB_AMP_ADC[1:0] IB_AMP_PGA[1:0] ENABLE[3:0] h0063 rw,11,sys rw,11,sys rw,0000,sys RegAcCfg2 PGA2_GAIN[1:0] PGA2_OFFSET[3:0] h0064 rw,00,sys rw,00,sys rw,0000,sys RegAcCfg3 PGA1_GAIN PGA3_GAIN[6:0] h0065 rw,0000000,sys Rw,0,sys PGA3_OFFSET RegAcCfg4 rw,0000000,sys h0066 RegAcCfg5 BUSY AMUX[4:0] h0067 r,0,sys rw,00000,sys
VMUX rw,0,sys
Table 4-15. Acquisition chain register description. 4.2.13 Voltage multiplier (h007C)
Enable rw,0,sys Fin[1:0] rw,00,sys
Name Address RegVmultCfg0 h007C
Table 4-16. VMULT register. 4.2.14
Address RegVldCtrl h007E RegVldStat h007F
Voltage Level Detector registers (h007E-h007F)
Name VldRange rw,0,sys VldTune[2:0] rw,000,sys VldResult VldValid r,0,sys r,0,sys VldEn rw,0,sys
Table 4-17. Voltage level detector register description 4.2.15 (h0080-h027F)
bytes accessed read write operations. reset function. Variables stored should initialised before since they have value circuit start
D0304-60
Datasheet XE88LC01/01A
System Block
Overview Operating mode
system_ff september 2002
D0304-60
Datasheet XE88LC01/01A
Overview
XE8000 chips have three operating modes. There are; normal, current very current modes (see Figure 5-1). different modes controlled reset clock blocks (see documentation respective blocks).
Operating mode
Start-up bits reset design when (power-on-reset) active. enabled, Xtal disabled reset (pmaddr 0000). port used return from sleep mode, bits with resetcold don't change (see sleep mode) Reset bits with resetsystem resetpconf enabled) reset. Clock configuration doesn't change except cpuck. reset Active mode This mode where peripherals work execute embedded software. Standby mode Executing HALT instruction moves XE8000 into Standby mode. stopped, clocks remain active. Therefor, enabled peripherals remain active e.g. time keeping. reset interrupt/event request enabled) cancels standby mode. Sleep mode This very low-power mode because circuit clocks peripherals stopped. Only some service blocks remain active. time-keeping possible. instructions necessary move into sleep mode. First, SleepEn (sleep enable) RegSysCtrl sleep mode then activated setting Sleep RegSysReset There three possibe ways wake-up from sleep mode: (power-on-reset caused power-down followed power-on). information lost. padreset Port reset combination Port present product). Port documentation more details. Note: Port used return from sleep mode, bits with resetcold don't change (RegSysCtrl, RegSysReset (except sleep), EnExtClock BiasRc RegSysClock, RegSysRcTrim1 RegSysRcTrim2). SleepFlag RegSysReset, reads back circuit sleep mode since flag last cleared (see reset block more details). lower power consumption, disable BiasRc RegSysClock before going sleep mode. start-up time oscillator will then longer however. recommended insert instruction after instruction that sets circuit sleep mode because this instruction executed when sleep mode left using resetfromportA.
Note: Note:
D0304-60
Datasheet XE88LC01/01A
START-UP
without condition
RESET
without condition padreset portA reset watchdog reset buserror reset padreset portA reset watchdog reset padreset portA reset
Halt instruction
ACTIVE
Interrupt/event
STAND-BY
SLEEP
sleep
normal mode
current
very current
Figure 5-1. XE88LC01 operating modes.
D0304-60
Datasheet XE88LC01/01A
Reset Block
6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6
Features Overview Register Reset handling capabilities Reset source description Power Reset RESET Programmable Port input combination Watchdog reset BusError reset Sleep mode Control register description operation Watchdog Start-up watchdog specifications
reset_ff April 2003
D0304-60
Datasheet XE88LC01/01A
Features
Power Reset (POR) External reset from RESET Programmable Watchdog timer reset Programmable BusError reset Sleep mode management Programmable Port input combination reset
Overview
reset block reset manager. handles different reset sources distributes them through system. also controls sleep mode circuit.
Pos.
Register
RegSysCtrl SleepEn EnResPConf Reset resetcold resetcold Function enables Sleep mode sleep mode disabled sleep mode enabled enables resetpconf signal when resetglobal active resetpconf disabled resetpconf enabled enables reset from BusError BusError reset source disabled BusError reset source enabled enables reset from Watchdog Watchdog reset source disabled Watchdog reset source enabled this unused
EnBusError EnResWD
resetcold resetcold
0000
Table 6-1. RegSysCtrl register.
Pos.
RegSysReset Sleep ResetBusError ResetWD ResetfromportA ResPad ResPadSleep
Reset resetsystem resetcold resetcold resetcold resetcold resetcold
Function Sleep mode control (reads always unused reset source BusError reset source Watchdog reset source Port combination reset source reset reset source reset sleep mode unused
Table 6-2. RegSysReset register
D0304-60
Datasheet XE88LC01/01A
Pos.
RegSysWD WDKey[3] WDCounter[3] WDKey[2] WDCounter[2] WDKey[1] WDCounter[1] WDKey[0] WDCounter[0]
Reset 0000 resetcold resetcold resetcold resetcold
Function unused
Watchdog Watchdog counter Watchdog Watchdog counter Watchdog Watchdog counter Watchdog Watchdog counter
Table 6-3. RegSysWD register
Reset handling capabilities
There reset sources: Power Reset (POR) External reset from RESET Programmable Port input combination Programmable watchdog timer reset Programmable BusError reset processor access outside allocated memory Another reset source Sleep RegSysReset register. This source fully controlled software only used during sleep mode. Four internal reset signals generated from these sources distributed through system: resetcold: asserted resetsystem: asserted when resetcold other enabled reset source active resetpconf: asserted when resetsystem active EnResPConf RegSysCtrl register set. This reset generally used different ports. allows maintain port configuration unchanged while rest circuit reset. resetsleep: asserted when circuit sleep mode circuits XE88LC01A XE88LC05A circuits XE88LC01 XE88LC05 Table shows summary dependency internal reset signals various reset sources. tables describing different registers, reset source indicated. Internal reset signals Asserted reset source RESET RESET PortA input Watchdog BusError Sleep resetsystem Asserted Asserted Asserted Asserted Asserted Asserted resetpconf when when EnResPConf=0 EnResPConf=1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted resetsleep Asserted Asserted Asserted resetcold Asserted Asserted
circuits XE88LC01A XE88LC05A circuits XE88LC01 XE88LC05
Table Internal reset assertion function reset source.
D0304-60
Datasheet XE88LC01/01A
6.5.1
Reset source description
Power Reset
power reset (POR) monitors external supply voltage. activates reset rising edge this supply voltage. reset inactivated only internal voltage regulator started precise voltage level detection performed block. 6.5.2 RESET
reset activated applying high input state RESET pin. 6.5.3 Programmable Port input combination
reset signal generated Port description Port further information. 6.5.4 Watchdog reset
Watchdog will generate reset EnResetWD RegSysCtrl register been watchdog cleared time processor. chapter describing watchdog further information. 6.5.5 BusError reset
address space assigned shown register product. EnBusError RegSysCtrl register non-existant address accessed software, reset generated. 6.5.6 Sleep mode
Entering sleep mode will reset part circuit. reset used configure circuit correct wake-up after sleep mode. SleepEn RegSysCtrl register been set, sleep mode entered setting Sleep RegSysReset. During sleep mode, resetsleep signal active. detailed information sleep mode, system documentation.
Control register description operation
registers dedicated reset status control, RegSysReset RegSysCtrl. bits Sleep, SleepEn also located those registers described chapter dedicated different operating modes circuit (system block). RegSysReset register gives information source which generated last reset. read beginning application program detect circuit recovering from error exception condition, circuit starting normally. when ResBusError forbidden address access generated reset. when ResWD watchdog generated reset. when ResPortA PortA combination generated reset. when ResPad reset generated reset. when ResPadSleep reset sleep mode generated reset. Note: reset source internal POR. Note: Several bits might not, register cleared between reset occurrences. Write value RegSysReset clear Note: When reset wakes chip from sleep mode, ResPad ResPadSleep bits equal D0304-60
Datasheet XE88LC01/01A
last concerns sleep mode control (see system documentation sleep mode description). when Sleep SleepEn sleep mode entered. always reads back RegSysCtrl register enables different available reset sources sleep mode. EnResWD enables reset watchdog (can disabled once enabled). EnBusError enables reset error condition. EnResPConf enables reset port configurations when reset Port Error watchdog. SleepEn unlocks Sleep bit. long SleepEn Sleep effect.
Watchdog
watchdog timer which cleared least every seconds software prevent reset being generated timeout condition. watchdog enabled software setting EnResWD RegSysCtrl register then only disabled power reset. watchdog timer cleared writing consecutively values Hx0A Hx03 RegSysWD register. sequence must strictly respected clear watchdog. assembler code, sequence clear watchdog move AddrRegSysWD, #0x0A move AddrRegSysWD, #0x03 Only writing Hx0A followed Hx03 resets some other write instruction done RegSysWD between writing Hx0A Hx03 values, watchdog timer will cleared. possible read status watchdog RegSysWD register. watchdog counter with count range between system reset generated when counter reaching value
Start-up watchdog specifications
start-up circuit, (power-on-reset) block generates reset signal during tPOR. circuit starts software execution after this period (see system chapter). intended force circuit correct state start-up. precise monitoring supply voltage, voltage level detector (VLD) used.
D0304-60
Datasheet XE88LC01/01A
Symbol TPOR TRESET TRESET Vbat_sl_M Vbat_sl_R WDtime
Parameter reset duration RESET reset duration RESET reset duration Supply ramp version Supply ramp version Watchdog timeout period
0.25
Unit V/ms V/ms
Comments
Table 6-5. Electrical timing specifications Note: Vbat_sl defines minimum slope required VBAT. Correct start-up circuit guaranteed this slope slow. such case, delay built using RESET pin. Note: minimal watchdog timeout period guaranteed when internal oscillators used. watchdog takes clock from prescaler. case external clock source used, oscillator must enabled also (EnRC=1 RegSysClock). Otherwise, watchdog stopped (see clock block documentation). Note: circuit versions XE88LC01 XE88LC05. Gives time reset active after falling edge RESET pin. Note: circuit versions XE88LC01A XE88LC05A. Gives time reset active after falling edge RESET pin.
D0304-60
Datasheet XE88LC01/01A
Clock Generator
7.5.1 7.5.2 7.5.3
Features Overview Register Interrupts events Clock sources oscillator Xtal oscillator External clock Clock source selection RegSysMisc Description Prescalers frequency selector
clock_gen_ff august 2002
D0304-60
Datasheet XE88LC01/01A
Features
available clock sources oscillator, quartz oscillator external clock). divider chains: high-prescaler bits) low-prescaler bits). clock disabling halt mode.
Overview
XE88LC01 chips work different clock sources oscillator, quartz oscillator external clock). clock generator block charge distributing necessary clock frequencies circuit. Figure represents functionality clock block. internal oscillator drives high prescaler. This prescaler generates frequency divisions down 1/256 input frequency. 32kHz clock generated enabling quartz oscillator present product) selecting appropriate high prescaler. prescaler generates clock signals from 32kHz down 1Hz. clock source selected from oscillator, external clock 32kHz clock.
Register
RegSysClock CpuSel Extclk EnExtClock BiasRc ColdXtal ColdRC EnableXtal EnableRc Reset resetsleep resetcold resetcold resetcold resetsleep resetsleep resetsleep resetsleep function Select speed cpuck, 0=RC, 1=xtal external clock External clock detected, 1=available Enable external clock, 1=enabled Enable Rcbias (reduces start-up time RC). Xtal start phase start phase Enable Xtal oscillator, 0=disabled, 1=enabled Enable oscillator, 0=disabled, 1=enabled
pos.
Table 7-1: RegSysClock register pos. RegSysMisc -RCOnPA0 DebFast OutputCkXtal OutputCpuCk Reset 0000 resetsleep resetsleep resetsleep resetsleep Function Unused Start PA[0], 0=disabled, 1=enabled Debouncer clock speed, 0=256Hz, 1=8kHz Output Xtal Clock PB[3], 0=disabled, 1=enabled EnXtal=1 else PB[3]=0 Output clock PB[2], 0=disabled, 1=enabled
Table 7-2: RegSysMisc register pos. RegSysPre0 -ResPre reset 0000000 Function Unused Write reset prescaler, always reads
Table 7-3: RegSysPre0 register
D0304-60
Datasheet XE88LC01/01A
pos.
RegSysRcTrim1 -Reserved RcFreqRange RcFreqCoarse[3] RcFreqCoarse[2] RcFreqCoarse[1] RcFreqCoarse[0]
reset resetcold resetcold resetcold resetcold resetcold resetcold
Function Unused Reserved Low/high freq. range (low=0) coarse trim coarse trim coarse trim coarse trim
Table 7-4: RegSysRCTrim1 register pos. RegSysRcTrim2 -RcFreqFine[5] RcFreqFine[4] RcFreqFine[3] RcFreqFine[2] RcFreqFine[1] RcFreqFine[0] reset resetcold resetcold resetcold resetcold resetcold resetcold function Unused fine trim fine trim fine trim fine trim fine trim fine trim
Table 7-5: RegSysRCTrim2 register
RegSysRcTrim1 RegSysRcTrim2
CkRc
High prescaler
CkRc CkRc/256
External Clock CkXtal
CpuSel prescaler 32kHz
OSCIN
Xtal
EnXtal not(ExtClk EnExtClk) CpuCk
Figure 7-1. Clock block structure
D0304-60
Datasheet XE88LC01/01A
Interrupts events
Interrupt source Ck128Hz Ck1Hz Mapping interrupt manager RegIrqHig(6) RegIrqMid(3) Table 7-6: Interrupts events Mapping event manager RegEvn(5) RegEvn(1)
Interrupt IrqPre1 IrqPre2
7.5.1
Clock sources
oscillator Configuration
7.5.1.1
oscillator always turned selected system operation power-on reset when exiting sleep mode. turned after Xtal (quartz oscillator) been started, after selection external clock entering sleep mode. oscillator frequency ranges: sub-MHz (100 MHz) above-MHz MHz). Inside range, frequency tuned software coarse fine adjustment. registers RegSysRcTrim1 RegSysRcTrim2. EnableRC register RegSysClock controls propagation clock signal operation oscillator. user stop oscillator resetting EnableRC. Entering sleep mode disables oscillator. Note: Before turning oscillator, cpusel RegSysClock must one. Note: oscillator bias maintained while oscillator switched setting BiasRc RegSysClock. This allows faster restart oscillator cost increased power consumption when oscillator disabled (see section 7.5.1.3). 7.5.1.2 oscillator frequency tuning
oscillator frequency using bits RegSysRcTrim1 RegSysRcTrim2 registers. Figure shows nominal frequency oscillator function these bits. absolute value frequency given register content change ±50% from chip chip tolerances integrated capacitors resistors. However, modification frequency function modification register content fairly precise frequencies below 2MHz. This means that curves Figure shift down that slope remains unchanged. RcFreqRange modifies oscillator frequency factor upper curve figure corresponds RcFreqRange=1. RcFreqCoarse modifies frequency oscillator factor (RcFreqCoarse+1). figure represents frequency different values bits RcFreqCoarse: each value frequency multiplied Incrementing RcFreqFine code increases frequency about 1.4%. frequency oscillator therefor given
D0304-60
Datasheet XE88LC01/01A with fRcmin oscillator frequency registers higher frequencies, frequency deviate from value predicted equation.
1E+08
RcFreqRange='1' RcFreqRange='0'
Nominal oscillator frequency [Hz]
1E+07
RcFreqFine(5:0)
1E+06
RcFreqFine(5:0)
1E+05
1E+04 0000 0001 0011 0111 1111
RcFreqCoarse(3:0)
Figure 7-2. oscillator nominal frequency tuning. 7.5.1.3 oscillator specifications description Lowest frequency fine tuning step startup time Supply voltage dependence Temperature dependence unit %/°C Comments Note BiasRc=0 BiasRc=1 Note Note
symbol fRCmin RcFreqFine RC_su PSRR
Table 7-7. oscillator specifications Note this frequency tolerance when trimming codes Note frequency shift function VBAT with normal regulator function. Note frequency shift function VBAT while regulator short-circuited VBAT.
D0304-60
Datasheet XE88LC01/01A tolerances minimal frequency drift with supply temperature cancelled using software DFLL (digital frequency locked loop) which uses crystal oscillator reference frequency. 7.5.2 7.5.2.1 Xtal oscillator Xtal configuration
Xtal operates with external crystal 32'768 During Xtal oscillator start-up, first 32768 cycles masked. bits EnableXtal ColdXtal register RegSysClock control oscillator. power-on reset during sleep mode, EnableXtal reset ColdXtal (Xtal oscillator selected start-up). user start Xtal oscillator setting EnableXtal. When Xtal oscillator starts, ColdXtal reset after 32768 cycles. Before ColdXtal reset system, Xtal frequency precision guaranteed. Xtal oscillator stopped user resetting EnableXtal. When user enters into sleep mode, Xtal stopped. When external clock detected (ExtClk EnExtClock EnableXtal 7.5.2.2 Xtal oscillator specifications
crystal oscillator been designed crystal with specifications given Table 7-8. oscillator precision only guaranteed this crystal. Symbol Description Resonance frequency nominal frequency Motional resistance Motional capacitance Shunt capacitance Motional resistance overtone (parasitic) Quality factor 32768 400k Unit Comments
Table 7-8. Crystal specifications. safe operation, power consumption meet specified precision, careful board layout required: Keep lines OSCIN OSCOUT short insert line between them. Connect crystal package VSS. noisy digital lines near OSCIN OSCOUT. Insert guards where needed. Respect board specifications Table 7-9.
D0304-60
Datasheet XE88LC01/01A
Symbol Rh_oscin Rh_oscout Rh_oscin_oscout Cp_oscin Cp_oscout Cp_oscin_oscout
Description
Resistance OSCIN-VSS Resistance OSCOUT-VSS
Resistance OSCIN-OSCOUT
Capacitance OSCIN-VSS Capacitance OSCOUT-VSS
Capacitance OSCIN-OSCOUT
Unit
Comments
Table 7-9. Board layout specifications. oscillator characteristics given Table 7-10. characteristics valid only crystal board layout meet specifications above. Symbol fXtal St_xtal Fstab Description Nominal frequency Start-up time Frequency deviation 32768 Unit Comments
-100
Note
Table 7-10. Crystal oscillator characteristics. Note This gives relative frequency deviation from nominal crystal with CL=8.2pF within temperature range -40°C 85°C. crystal tolerance, crystal aging crystal temperature drift included this figure. 7.5.3 7.5.3.1 External clock External clock configuration
user provide external clock instead internal oscillators. Only external clock. external clock input OSCIN. system configured external clock EnExtClock register RegSysClock. When EnExtClock external clock detected after pulses OSCIN. ExtClk shows when external clock available. Note: when using external clock, Xtal available. 7.5.3.2 External clock specification
external clock satisfy specifications table below. Correct behavior circuit guaranteed external clock signal does respect specifications below. Symbol FEXT PW_1 PW_0 Description External frequency Pulse width Pulse width clock Table 7-11. External clock specifications. Unit Comments
D0304-60
Datasheet XE88LC01/01A
Clock source selection
There three possible clock sources available clock. clock always selected after power-up after Sleep mode. clock selection done with CpuSel RegSysClock clock, from Xtal EnableXtal ExtClk EnExtClk else external clock). Switching from clock source another glitch free. next table summarizes different clock configurations circuit: Clock Sources EnableXtal EnableRc EnExtClk Mode name Cpuck
Note
Clock targets High Prescaler Clock input Prescaler Clock input Xtal High presc. Xtal High presc.
CpuSel=0
CpuSel=1 Xtal Xtal External External
Sleep Xtal Xtal External External
Table 7-12: Table clocking modes. Note clock divided using freq instruction (see coolrisc instruction set) Switching from clock source another stopping unused clock source must performed using MOVE instructions RegSysClock. First select clock source, secondly change CpuSel finally stop unused one.
RegSysMisc Description
RCOnPA0 RegSysMisc used enable oscillator event external circuit. RCOnPA0 oscillator enabled (EnableRC soon value port PA[0] equal Port debounced (see Port documentation). DebFast RegSysMisc register allows chose debouncer clock between 256Hz 8kHz (DebFast DebFast respectively). Debouncer clock used debounce inputs (see Port documentation). OutputCkXtal allows show Xtal clock PB[3]. EnableXtal must else PB[3] equals (see port documentation Port OutputCpuCk allows show CpuClock PB[2] (see Port documentation).
D0304-60
Datasheet XE88LC01/01A
Prescalers
clock generator block embeds divider chains: high prescaler prescaler. high prescaler made stage dividing chain prescaler stage dividing chain. Features: High prescaler only driven with clock (bit EnableRc have set, Table 7-12). prescaler driven from high prescaler directly with Xtal clock when EnableXtal EnExtClock ExtClk equal ResPre RegSysPre0 register allows reset synchronously prescaler, prescaler also automatically cleared when EnableXtal set. Both dividing chains reset asynchronously resetsleep signal. ColdXtal=1 indicates Xtal start phase. active 37268 Xtal cycles after setting EnableXtal.
frequency selector
decoder used select from high prescaler frequency that closest operate prescaler when Xtal running. this case, oscillator frequency ±50% will also valid prescaler frequency outputs.
D0304-60
Datasheet XE88LC01/01A
Interrupt handler
Features Overview Register
irq_ff august 2002
D0304-60
Datasheet XE88LC01/01A
Features
XE8000 chips support interrupt sources, divided into levels priority.
Overview
interruption generated memorized when interrupt becomes active. interrupt sources divided into levels priority: High interrupt sources), interrupt sources), interrupt sources). Those levels priority directly mapped those supported CoolRisc (IN0, IN2; CoolRisc documentation more information). RegIrqHig, RegIrqMid, RegIrqLow 8-bit registers containing flags interrupt sources. Those flags when interrupt enabled (i.e. corresponding registers RegIrqEnHig, RegIrqEnMid RegIrqEnLow set) rising edge detected corresponding interrupt source. Once memorized, interrupt flag cleared writing corresponding RegIrqHig, RegIrqMid RegIrqLow. Writing does modify flag. definitively clear interrupt, clear CoolRisc interrupt CoolRisc status register. interrupts automatically cleared after reset. registers provided facilitate writing interrupt service software. RegIrqPriority contains number highest priority interrupt (its value 0xFF when interrupt set). RegIrqIrq indicates priority level current interrupts. RegIrqIrq RegIrqPriority values dependent upon memorized state interrupts reflected flags RegIrqHig, RegIrqMid RegIrqLow).
Register
pos. RegIrqHig RegIrqHig[7] RegIrqHig[6] RegIrqHig[5] RegIrqHig[4] RegIrqHig[3] RegIrqHig[2] RegIrqHig[1] RegIrqHig[0] reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem function interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written interrupt (high priority) clear interrupt when written
Table 8-1: RegIrqHig
D0304-60
Datasheet XE88LC01/01A
pos.
RegIrqMid RegIrqMid[7] RegIrqMid[6] RegIrqMid[5] RegIrqMid[4] RegIrqMid[3] RegIrqMid[2] RegIrqMid[1] RegIrqMid[0]
reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem
function interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written interrupt (mid priority) clear interrupt when written
Table 8-2: RegIrqMid pos. RegIrqLow RegIrqLow[7] RegIrqLow[6] RegIrqLow[5] RegIrqLow[4] RegIrqLow[3] RegIrqLow[2] RegIrqLow[1] RegIrqLow[0] reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem function interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written interrupt (low priority) clear interrupt when written
Table 8-3: RegIrqLow pos. RegIrqEnHig RegIrqEnHig[7] RegIrqEnHig[6] RegIrqEnHig[5] RegIrqEnHig[4] RegIrqEnHig[3] RegIrqEnHig[2] RegIrqEnHig[1] RegIrqEnHig[0] reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem function enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt
Table 8-4: RegIrqEnHig
D0304-60
Datasheet XE88LC01/01A
pos.
RegIrqEnMid RegIrqEnMid[7] RegIrqEnMid[6] RegIrqEnMid[5] RegIrqEnMid[4] RegIrqEnMid[3] RegIrqEnMid[2] RegIrqEnMid[1] RegIrqEnMid[0]
reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem
function enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt
Table 8-5: RegIrqEnMid pos. RegIrqEnLow RegIrqEnLow[7] RegIrqEnLow[6] RegIrqEnLow[5] RegIrqEnLow[4] RegIrqEnLow[3] RegIrqEnLow[2] RegIrqEnLow[1] RegIrqEnLow[0] reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem function enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt enable interrupt
Table 8-6: RegIrqEnLow pos. RegIrqPriority RegIrqPriority reset 11111111 resetsystem function code highest priority
Table 8-7: RegIrqPriority pos. RegIrqIrq IrqHig IrqMid IrqLow Reset 00000 resetsystem resetsystem resetsystem function unused more high priority interrupt more priority interrupt more priority interrupt
Table 8-8: RegIrqIrq
D0304-60
Datasheet XE88LC01/01A
Event handler
Features Overview Register
evn_ff august 2002
D0304-60
Datasheet XE88LC01/01A
Features
XE88LC01 chips support event sources, divided into levels priority.
Overview
event generated memorized when event source becomes active. event sources divided into levels priority: High event sources) event sources). Those levels priority directly mapped those supported CoolRisc (EV0 EV1; CoolRisc documentation more information). RegEvn 8-bit register containing flags event sources. Those flags when event enabled (i.e. corresponding registers RegEvnEn set) rising edge detected corresponding event source. Once memorized, writing corresponding RegEvn clears event flag. Writing does modify flag. interrupts automatically cleared after reset. registers provided facilitate writing event service software. RegEvnPriority contains number highest priority event (its value 0xFF when event set). RegEvnEvn indicates priority level current interrupts. RegEvnEvn RegEvnPriority values dependent upon memorized state events reflected flags RegEvn).
Register
pos. RegEvn RegEvn[7] RegEvn[6] RegEvn[5] RegEvn[4] RegEvn[3] RegEvn[2] RegEvn[1] RegEvn[0] reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem function event (high priority) clear event when written event (high priority) clear event when written event (high priority) clear event when written event (high priority) clear event when written event (low priority) clear event when written event (low priority) clear event when written event (low priority) clear event when written event (low priority) clear event when written
Table 9-1: RegEvn
D0304-60
Datasheet XE88LC01/01A
pos.
RegEvnEn RegEvnEn[7] RegEvnEn[6] RegEvnEn[5] RegEvnEn[4] RegEvnEn[3] RegEvnEn[2] RegEvnEn[1] RegEvnEn[0]
reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem
function enable event enable event enable event enable event enable event enable event enable event enable event
Table 9-2: RegEvnEn pos. RegEvnPriority RegEvnPriority reset 11111111 resetsystem function code highest event
Table 9-3: RegEvnPriority pos. RegEvnEvn EvnHig EvnLow reset 00000 resetsystem resetsystem function unused more high priority event more priority event
Table 9-4: RegEvnEvn
D0304-60
Datasheet XE88LC01/01A
power
10.1 10.2 10.3
Features Overview Register
10-2 10-2 10-2
10-1
reg_ff august 2002
D0304-60
Datasheet XE88LC01/01A
10.1 Features
power locations.
10.2 Overview
order save power consumption, 8-bit registers provided page These memory locations should reserved often-updated variables. Accessing these register locations requires much less power than other general purpose locations.
10.3 Register
pos. Reg00 Reg00 reset XXXXXXXX function low-power data memory
Table 10-1: Reg00 pos. Reg01 Reg01 reset XXXXXXXX function low-power data memory
Table 10-2: Reg01 pos. Reg02 Reg02 reset XXXXXXXX function low-power data memory
Table 10-3: Reg02 pos. Reg03 Reg03 reset XXXXXXXX function low-power data memory
Table 10-4: Reg03 pos. Reg04 Reg04 reset XXXXXXXX function low-power data memory
Table 10-5: Reg04 pos. Reg05 Reg05 reset XXXXXXXX function low-power data memory
Table 10-6: Reg05 pos. Reg06 Reg06 XXXXXXXX function low-power data memory
Table 10-7: Reg06 pos. Reg07 Reg07 reset XXXXXXXX function low-power data memory
Table 10-8: Reg07
10-2
D0304-60
Datasheet XE88LC01/01A
Port
11.1 11.2 11.3 11.4 11.5 11.6
Features Overview Register Interrupts events Port (PA) Operation Port electrical specification
11-2 11-2 11-3 11-4 11-4 11-5
11-1
pa_ff 2002
D0304-60
Datasheet XE88LC01/01A
11.1 Features
Input port, bits wide Each individually debounced direct input Each individually pull-up Each interrupt request source rising falling edge system reset generated input pattern PA[0] PA[1] generate events CPU, individually maskable PA[0] PA[3] used clock inputs counters/timers/PWM (product dependent) PA[0] used enable oscillator
11.2 Overview
Port general purpose wide digital input port, with interrupt capability. Figure 11-1 shows structure.
VBat
Port
debounce RegPAPullup RegPADebounce DebFast (RegSysMisc(2)) RegPACtrl RegPAIn RegPAEdge interrupts events cntclocks resetfromporta PAReset[x] RegPARes1 RegPARes0
Figure 11-1:structure Port
11-2
D0304-60
Datasheet XE88LC01/01A
11.3 Register
There registers Port (PA), namely RegPAIn, RegPADebounce, RegPAEdge, RegPAPullup, RegPARes0 RegPARes1. Table 11-1 Table 11-6 show mapping control bits functionality.
pos. RegPAIn PAIn[7:0] reset description PA[7] PA[0] input value
Table 11-1: RegPAIn
pos. RegPADebounce PADebounce[7:0] reset 00000000 resetpconf description PA[7] PA[0] debounce enabled debounce disabled
Table 11-2: RegPADebounce
pos. RegPAEdge PAEdge[7:0] reset 00000000 resetsystem description PA[7] PA[0] edge configuration positive edge negative edge
Table 11-3: RegPAEdge
pos. RegPAPullup PAPullup[7:0] reset 00000000 resetpconf description PA[7] PA[0] pullup enable pullup disabled pullup enabled
Table 11-4: RegPAPullup
pos. RegPARes0 PARes0[7:0] Reset 00000000 resetsystem description PA[7] PA[0] reset configuration
Table 11-5: RegPARes0
pos. RegPARes1 PARes1[7:0] reset 00000000 resetsystem Description PA[7] PA[0] reset configuration
Table 11-6: RegPARes
11-3
D0304-60
Datasheet XE88LC01/01A
11.4 Interrupts events
Interrupt source pa_irqbus[5] pa_irqbus[4] pa_irqbus[1] pa_irqbus[0] pa_irqbus[7] pa_irqbus[6] pa_irqbus[3] pa_irqbus[2] Default mapping interrupt manager RegIrqMid[5] RegIrqMid[4] RegIrqMid[1] RegIrqMid[0] RegIrqLow[7] RegIrqLow[6] RegIrqLow[3] RegIrqLow[2] Default mapping event manager
RegEvn[4] RegEvn[0]
11.5 Port (PA) Operation
Port input status (debounced not) read from RegPAin. Debounce mode: Each Port individually debounced setting corresponding RegPADebounce. After reset, debounce function disabled. After enabling debouncer, change input value accepted only input value identical consecutive sampling rising edge selected clock. Selection clock done DebFast Register RegSysMisc (see clock block documentation more precision frequency).
DebFast Clock filter
Table 11-7: debounce frequency selection
Input CkDebounce Debounced
Figure 11-2: digital debouncer Pull-ups: When corresponding RegPAPullup inputs floating (pull-up resistors disconnected). When corresponding RegPAPullup pull-up resistor connected input pin. Port starts with pull-up resistors disconnected. Port interrupt source: Each Port input interrupt request source rising falling edge with corresponding RegPAEdge. After reset, rising edge selected interrupt generation default. interrupt source debounced setting register RegPADebounce. Note: care must taken when modifying RegPAEdge because this register performs edge selection. change this register result transition which interpreted valid interruption.
11-4
D0304-60
Datasheet XE88LC01/01A
Port event source: interrupt signals pins PA[0] PA[1] also available events event controller. PortA clock source (product dependent): Images PA[0] PA[3] input ports (debounced not) available clock sources counter/timer/PWM peripheral (see counter block documentation more information). Port reset source: Port used generate system reset placing predetermined word Port externally. reset built using logical PARes[x] signals: resetfromportA PAReset[7] PAReset[6] PAReset[5] PAReset[0] PAReset[x] itself logical function corresponding PA[x]. four logical functions selected each writing into registers RegPARes0 RegPARes1 shown Table 11-8.
PARes1[x] PARes0[x] PAReset[x] PA[x] not(PA[x])
Table 11-8: Selection bits reset signal reset from Port inhibited placing both PARes1[x] PARes0[x] least pin. Setting both PARes1[x] PARes0[x] makes reset independent value corresponding pin. Setting both registers hFF, will reset circuit independent from Port input value. This makes possible reset software. Note: depending value PA[0] PA[7], change RegPARes0 RegPARes1 cause reset. Therefore safe have always (RegPARes0[x], RegPARes1[x]) equal `00' during setting operations. Port enable: PA[0] used enable oscillator. When RCOnPA0 RegSysMisc value PA[0] (debounced not) equal EnRc RegSysClock automatically
11.6 Port electrical specification
VINH VINL description Input high voltage Input voltage Pull-up resistance Input capacitance 0.7*VBAT VBAT 0.2*VBAT unit Comments VBAT2.4V VBAT2.4V Note
Note this value indicative only since depends package. Table 11-9. Port electrical specification.
11-5
D0304-60
Datasheet XE88LC01/01A
Port
12.1 12.2 12.3 12.4 12.5 12.5.1 12.5.2 12.6 12.7 12.7.1 12.7.2
Features Overview Register Port capabilities Port analog capability Port analog configuration Port analog function specification Port function capability Port digital capabilities Port digital configuration Port digital function specification
12-2 12-2 12-2 12-3 12-3 12-3 12-4 12-4 12-5 12-5 12-6
12-1
pb_ff september 2002
D0304-60
Datasheet XE88LC01/01A
12.1 Features
Input output analog port, bits wide Each individually input output Each individually open-drain push-pull Each individually pull-up (for input open-drain mode) open-drain mode, pull-up active when corresponding zero pads connected pairs four internal analog lines line analog bus) internal freq. (cpuck kHz) output PB[2] PB[3] Product dependant: signals outputted pads PB[0] PB[1] synchronous serial interface (USRT) uses pads PB[5], PB[4] UART interface uses pads PB[6] PB[7]
12.2 Overview
Port multi-purpose Input/output port. addition digital functions, pins used analog signals. port terminals selected pairs digital input output analog sharing four possible analog lines.
12.3 Register
Pos.
RegPBOut
PBOut[7-0]
reset
resetpconf
description digital mode
PB[7-0] output value
description analog mode
Analog selection PB[7-0]
Table 12-1: RegPBOut Pos.
RegPBIn
PBIn[7-0]
reset
description digital mode
PB[7-0] input status
description analog mode
Unused
Table 12-2: RegPBIn Pos.
RegPBDir
PBDir [7-0]
reset
resetpconf
description digital mode
PB[7-0] direction (0=input)
description analog mode
Analog selection PB[7-0]
Table 12-3: RegPBDir Pos.
RegPBOpen
PBOpen[7-0]
reset
resetpconf
description digital mode
PB[7-0] open drain open drain)
description analog mode
Unused
Table 12-4: RegPBOpen
Pos.
RegPBPullup
PBPullup[7]
reset
resetpconf
description digital mode
Pull-up PB[7-0] (1=active)
description analog mode
Connect PB[7-0] selected
Table 12-5: RegPBPullup Pos.
RegPBAna
-PBAna PBAna PBAna PBAna
reset
0000 resetpconf resetpconf resetpconf resetpconf
description digital mode
Unused PB[7:6] analog mode PB[5:4] analog mode PB[3:2] analog mode PB[1:0] analog mode
description analog mode
Unused PB[7:6] analog mode PB[5:4] analog mode PB[3:2] analog mode PB[1:0] analog mode
Table 12-6: RegPBAna
12-2
D0304-60
Datasheet XE88LC01/01A
Note: Depending status EnResPConf RegSysCtrl, reset conditions registers different. reset block documentation more details resetpconf signal.
12.4 Port capabilities
Port name PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] analog (high) analog analog analog analog usage (priority) functions (medium) uart uart usrt usrt clock PWM1 Counter (C+D) PWM0 Counter (A+B) Table 12-7: Different Port functionality Table 12-7 shows different usage that made Port with order priority. pair pins selected analog, overwrites function digital set-up. selected analog, function enabled, overwrites digital set-up. neither analog function selected pin, used ordinary digital I/O. This default configuration start-up. digital (low) (default)
12.5 Port analog capability
12.5.1 Port analog configuration
Port terminals attached line analog setting PBAna[x] bits RegPBAna register. other registers then define connection these analog lines different pads Port This used implement simple driver converter. Analog switching available only when circuit powered with sufficient voltage (see specification below). Below specified supply voltage, only voltages that close VBAT switched. When PBAna[x] pair Port terminals switched from digital mode analog mode. usage registers RegPBPullup, RegPBOut RegPBDir define analog configuration (see Table 12-8). When PBAna[x] then PBPullup[x] connects analog bus. PBDir[x] PBPOut[x] select which analog lines used. values selection bits register RegPBOut (see Table 12-8). even values selection bits register RegPBDir (see Table 12-9). odd, PBOut[x, x-1] PBPullup[x] PB[x] selection analog line analog line analog line analog line High impedance
Table 12-8: Selection analog lines PB[x] when PBAna[x]
12-3
D0304-60
Datasheet XE88LC01/01A
even, PBDir[x+1,
PBPullup[x]
PB[x] selection analog line analog line analog line analog line High impedance
Table 12-9: Selection analog lines PB[x] when even PBAna[x] Example: pads PB[2] PB[3] analog line (the values depend configuration others pads) apply high impedance analog mode (move RegPBPullup,#0bXXXX00XX) analog mode (move RegPBAna,#0bXXXXXX1X) select analog line3 (move RegPBDir,#0bXXXX11XX move RegPBOut,#0bXXXX11XX) connect analog line pins (move RegPBPullup,#0bXXXX11XX) 12.5.2 Port analog function specification
table below defines on-resistance switches between analog different conditions. series resistance between pins Port connected same analog line twice resistance given table. description switch resistance switch resistance input capacitance (off) input capacitance (on) unit Comments Note Note Note Note
Table 12-10. Analog input specifications. Note This series resistance between analog line cases VBAT 2.4V VMULT peripheral present circuit enabled. VBAT 3.0V VMULT peripheral present circuit. Note This series resistance case VBAT 2.8V peripheral VMULT present circuit. Note This input capacitance seen when connected analog line. This value indicative only since product package dependent. Note This input capacitance seen when connected analog line other connected same analog line. This value indicative only since product package dependent.
12.6 Port function capability
Port used different functions implemented other peripherals. description below applicable only circuit contains these peripherals. When counters used implement function (see documentation counters), PB[0] PB[1] terminals used outputs (PB[0] used CntPWM0 RegCntConfig1 PB[1] used CntPWM1 RegCntConfig1 generated values overwrite values written RegPBout. However, PBDir(0) PBDir(1) automatically overwritten have
12-4
D0304-60
Datasheet XE88LC01/01A OutputCkXtal RegSysMisc, Xtal clock output PB[3] (EnableXtal RegSysClock must This overrides value contained PBOut(3). However, PBDir(3) must duty cycle clock signal about 50%. Similarly, OutputCkCpu RegSysMisc, frequency output PB[2]. This overrides value contained PBOut(2). However, PBDir(2) must frequency clock depends selection CpuSel RegSysClock register (see clock_gen_ff). Pins PB[5] PB[4] used USRT (see USRT documentation) when UsrtEnable RegUsrtCtrl. PB[5] PB[4] then become open-drain. This overrides values contained PBOpen(5:4), PBOut(5:4) PBDir(5:4). there external pull-up resistor these pins, internal pull-ups should selected setting PBPullup(5:4). When output, PB[4] takes value UsrtS0 RegUrstS0. When output, PB[5] takes value UsrtS1 RegUrstS1. Pins PB[6] PB[7] used UART (see UART documentation). When UartEnTx RegUartCtrl PB[6] used output signal When UartEnRx RegUartCtrl PB[7] used input signal This overrides values contained PBOut(7:6) PBDir(7:6).
12.7 Port digital capabilities
12.7.1 Port digital configuration
direction each within Port (input only input/output) individually using RegPBDir register. PBDir[x] both input output buffer active corresponding Port PBDir[x] corresponding Port input only output buffer high impedance. After reset (resetpconf) Port input only mode (PBDir[x] reset input values Port available RegPBIn (read only). Reading always direct there debounce function Port case possible noise input signals, software debouncer with polling external hardware filter have realized. input buffer also active when port defined output allows read back effective value pin. Data stored RegPBOut output Port PBDir[x] default value after reset (0). When output mode (PBDir[x] output conventional CMOS (PushPull) N-channel Open-drain, driving output only low. default, after reset (resetpconf) PBOpen[x] RegPBOpen cleared (push-pull). PBOpen[x] RegPBOpen then internal transistor output buffer electrically removed output only driven (PBOut[x]=0). When PBOut[x]=1, high Impedance. internal pull-up external pull-up resistor used drive high. Note: Because transistor actually exists (this real Open-drain output) pull-up range limited 0.2V (avoid forward bias transistor diode). Each individually pull-up using register RegPBPullup. Input pulled when corresponding this register Default status after (resetpconf) which means without pull limit power consumption, pull-up resistors only enabled when associated either digital input N-channel open-drain output with other cases (push-pull output open-drain output driven low), pull resistors disabled independent value RegPBPullup. After power-on reset, Port configured input port without pull-up.
12-5
D0304-60
Datasheet XE88LC01/01A input buffer always active, except analog mode. This means that Port input should valid digital value times unless analog mode. Violating this rule lead high power consumption. 12.7.2 VINH VINL Port digital function specification description Input high voltage Input voltage Output high voltage Output voltage 0.7*VBAT VBAT-0.4 VBAT 0.2*VBAT VBAT VSS+0.4 unit Comments VBAT2.4V VBAT2.4V VBAT=1.2V, =0.3mA VBAT=2.4V, =5.0mA VBAT=4.5V, =8.0mA VBAT=1.2V, =0.3mA VBAT=2.4V, =12.0mA VBAT=4.5V, =15.0mA Note
Pull-up resistance Input capacitance
Note this value indicative only since depends package.
12-6
D0304-60
Datasheet XE88LC01/01A
Port
13.1 13.2 13.3 13.4 13.5
Features Overview Port (PC) Operation Register Port electrical specification
13-2 13-2 13-2 13-2 13-3
13-1
pc_ff august 2002
D0304-60
Datasheet XE88LC01/01A
13.1 Features
Input output port, bits wide Each individually input output
13.2 Overview
Port (PC) general purpose input/output digital port. Figure 13-1 shows structure.
Port
RegPCOut
RegPCDir
RegPCIn
Figure 13-1 structure Port
13.3 Port (PC) Operation
direction each within Port (input output) individually using RegPCDir register. PCDir[x] corresponding Port becomes output. After reset, Port input mode (PCDir[x] reset Output mode: Data stored RegPCOut prior output Port Input mode: status Port available RegPCIn (read only). Reading always direct there digital debounce function associated with Port case possible noise input signals, software debouncer external filter must realized. default after reset, Port configured input port.
13.4 Register
There three registers Port (PC), namely RegPCIn, RegPCOut RegPCDir. Table 13-1 Table 13-3 show mapping control bits functionality these registers.
Pos. RegPCIn PCIn Reset Description input value
Table 13-1 RegPCIn
13-2
D0304-60
Datasheet XE88LC01/01A
Pos.
RegPCOut PCOut
Reset resetpconf
Description output value
Table 13-2 RegPCOut
Pos.
RegPCDir PCDir
Reset resetpconf
Description direction (0=input)
Table 13-3 RegPCDir
13.5 Port electrical specification
VINH VINL description Input high voltage Input voltage Output high voltage Output voltage 0.7*VBAT VBAT-0.4 VBAT 0.2*VBAT VBAT VSS+0.4 unit Comments VBAT2.4V VBAT2.4V VBAT=1.2V, =0.3mA VBAT=2.4V, =5.0mA VBAT=4.5V, =8.0mA VBAT=1.2V, =0.3mA VBAT=2.4V, =12.0mA VBAT=4.5V, =15.0mA Note
Input capacitance
Note this value indicative only since depends package. Table 13-4. Port electrical specification
13-3
D0304-60
Datasheet XE88LC01/01A
UART
14.1 14.2 14.3 14.4 14.5 14.5.1 14.5.2 14.6 14.6.1 14.6.2 14.6.3 14.7 14.8
Features Overview Registers Interrupts Uart baud rate selection Uart oscillator Uart crystal oscillator Function description Configuration bits Transmission Reception Interrupt polling Software hints
14-2 14-2 14-2 14-3 14-3 14-3 14-4 14-4 14-4 14-5 14-6 14-6 14-7
14-1
uart_ff september 2002
D0304-60
Datasheet XE88LC01/01A
14.1 Features Full duplex operation with buffered receiver transmitter. Internal baud rate generator with programmable baud rates (300 115200). bits word length. Even, odd, no-parity generation detection stop Error receive detection: Start, Parity, Frame Overrun Receiver echo mode interrupts (receive full transmit empty) Enable receive and/or transmit Invert and/or 14.2 Overview UART pins PB[7], which used receive PB[6] transmit. 14.3 Registers pos. RegUartCmd SelXtal UartEnRx2 UartRcSel(2:0) UartPM UartPE UartWL Reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem Description Select input clock: RC/external, xtal Enable Uart Reception prescaler selection Select parity mode: odd, even Enable parity: with parity, parity Select word length: bits, bits
Table 14-1: RegUartCmd Pos. RegUartCtrl UartEcho UartEnRx1 UartEnTx UartXRx UartXTx UartBR(2:0) reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem Table 14-2: RegUartCtrl pos. RegUartTx UartTx reset 00000000 resetsystem Table 14-3: RegUartTx Description Data sent Description Enable echo mode: echo Rx->Tx, echo Enable uart reception Enable uart transmission Invert Invert Select baud rate
14-2
D0304-60
Datasheet XE88LC01/01A
pos.
RegUartTxSta UartTxBusy UartTxFull
reset 000000 resetsystem resetsystem
description Unused Uart busy transmitting RegUartTx full writing RegUartTx Cleared when transferring RegUartTx into internal shift register
Table 14-4: RegUartTxSta pos. RegUartRx UartRx reset 00000000 resetsystem Table 14-5: RegUartRx pos. RegUartRxSta UartRxSErr UartRxPErr UartRxFErr UartRxOErr UartRxBusy UartRxFull Reset resetsystem resetsystem resetsystem resetsystem resetsystem resetsystem description Unused Start error Parity error Frame error Overrun error Cleared writing RegUartRxSta Uart busy receiving RegUartRx full Cleared reading RegUartRx description Received data
Table 14-6: RegUartRxSta 14.4 Interrupts interrupt source Irq_uart_Tx Irq_uart_Rx default mapping interrupt manager IrqHig(1) IrqHig(0) Table 14-7: Interrupts
14.5 Uart baud rate selection
order have correct baud rates, Uart interface with stable trimmed clock source. clock source oscillator crystal oscillator. precision baud rate will depend precision selected clock source. 14.5.1 Uart oscillator
select oscillator Uart, SelXtal RegUartCmd order obtain correct baud rate, oscillator frequency frequencies given table below. precision obtained baud rate directly proportional frequency deviation with respect values table.
14-3
D0304-60
Datasheet XE88LC01/01A
Frequency selection correct Uart baud rate with oscillator (Hz) 2'457'600 1'843'200 1'228'800 614'400 each these frequencies, baud rate selected with bits UartBR(2:0) RegUartCtrl UartRcSel(2:0) RegUartCmd shown Table 14-8 frequency (Hz) UartRcSel UartBR 2'457'600 1'228'800 38400 19200 9600 4800 614'400 1'843'200 115200 57600 28800 14400
possible
Table 14-8: Uart baud rate with clock Note: precision baud rate directly proportional frequency deviation used clock from ideal frequency given table. order increase precision stability oscillator, DFLL (digital frequency locked loop) used with crystal oscillator reference. 14.5.2 Uart crystal oscillator
order crystal oscillator clock source Uart, SelXtal RegUartCmd set. crystal oscillator enabled setting EnableXtal RegSysClock. baud rate selection done using UartBR UartRcSel bits shown Table 14-9. Xtal freq. (Hz) 32768 UartRcSel UartBR Baud rate 2400 1200
Table 14-9: Uart baud rate with Xtal clock ratio between crystal oscillator frequency baud rate, generated baud rate systematic error -2.48%. 14.6 Function description 14.6.1 Configuration bits
configuration bits Uart serial interface found registers RegUartCmd RegUartCtrl. SelXtal used select clock source (see chapter 14.5). bits UartSelRc UartBR select baud rate (see chapter 14.5). UartEnTx used enable disable transmission.
14-4
D0304-60
Datasheet XE88LC01/01A bits UartEnRx1 UartEnRx2 used enable disable reception. When reception enabled. word length data bits) chosen with UartWL. parity added during transmission checked during reception UartPE set. parity mode (odd even) chosen with UartPM. Setting bits UartXRx UartXTx inverts respectively signals. UartEcho used send received data automatically back. transmission function becomes then: UartXTx. 14.6.2 Transmission
order send data, transmitter enabled setting UartEnTx. Data sent written register RegUartTx. UartTxFull RegUartTxSta then goes indicating transmitter that word available. soon transmitter finished sending previous word, then loads contents register RegUartTx internal shift register clears UartTxFull bit. interrupt generated Irq_uart_Tx falling edge UartTxFull bit. UartTxBusy RegUartTxSta shows that transmitter busy transmitting word. timing diagram shown Figure 14-1. Data sent first. data should written register RegUartTx only while UartTxFull otherwise data will lost.
Asynchronous Transmission
write RegUartTx RegUartTx reguarttx_shift shift clock UartTxBusy UartTxFull Irq_uart_Tx start b6/7 parity stop word word
Asynchronous Transmission (back back)
word write RegUartTx RegUartTx reguarttx_shift shift clock UartTxBusy UartTxFull Irq_uart_Tx start b6/7 stop start word word word word word
Figure 14-1. Uart transmission timing diagram.
14-5
D0304-60
Datasheet XE88LC01/01A 14.6.3 Reception
detection start bit, UartRxBusy set. detection stop bit, received data transferred from internal shift register register RegUartRx. same time, UartRxFull interrupt generated Irq_uart_Rx. This indicates that data available RegUartRx. timing diagram shown Figure 14-2. UartRxFull cleared when RegUartRx read. register read before receiver transfers word UartRxOErr (overflow error) previous contents register lost. UartRxOErr cleared writing data RegUartRxSta. UartRxSErr start error been detected. updated data transfer RegUartRx. UartRxPErr parity error been detected, i.e. received parity equal calculated parity received data. updated data transfer RegUartRx. UartRxFErr RegUartRxSta shows that frame error been detected. stop been detected.
Asynchronous Reception
read RegUartRx (software) reguartrx_shift RegUartRx shift clock UartRxBusy UartRxFull Irq_uart_Rx start b6/7 parity stop word word
Figure 14-2. Uart reception timing diagram. 14.7 Interrupt polling transmission reception software driven interruption polling status bits. Interrupt driven reception: each time Irq_uart_Rx interrupt generated, word available RegUartRx. register read before word received. Interrupt driven transmission: each time contents RegUartTx transferred transmission shift register, Irq_uart_Tx interrupt generated. word then written RegUartTx. Reception driven polling: UartRxFull read checked. When RegUartRx register contains data read before word received. Transmission driven polling: UartTxFull read checked. When RegUartTx register empty word written
14-6
D0304-60
Datasheet XE88LC01/01A
14.8 Software hints Example program transmission with polling: RegUartCmd register RegUartCtrl register initialized (for example: word length, parity, 9600 baud, enable Uart transmission). Write byte RegUartTx. Wait until UartTxFull RegUartTxSta register equals Jump write next byte message finished. transmission. Example program transmission with interrupt: RegUartCmd register RegUartCtrl register initialized (for example: word length, parity, 9600 baud, enable Uart transmission). Write byte RegUartTx. After interrupt message finished, jump transmission. Example program reception with polling: RegUartCmd register RegUartCtrl register initialized (for example: word length, parity, 9600 baud, enable Uart reception). Wait until UartRxFull RegUartRxSta register equals Read RegUartRxSta check there error. Read data RegUartRx. data equal End-Of-Line, then jump reception. Example program reception with interrupt: RegUartCmd register RegUartCtrl register initialized (for example: word length, parity, 9600 baud, enable Uart reception). When there interrupt, jump Read RegUartRxSta check there error. Read data RegUartRx. data equal End-Of-Line, then jump reception.
14-7
D0304-60
Datasheet XE88LC01/01A
USRT
15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8
Features Overview Register Interrupts Conditional edge detection Conditional edge detection Interrupts polling Function description
15-2 15-2 15-2 15-3 15-4 15-4 15-4 15-4
15-1
usrt_ff september 2002
D0304-60
Datasheet XE88LC01/01A
15.1 Features
USRT implements hardware support software implemented serial protocols: Control external lines (read/write). Conditional edge detection generates interrupts. rising edge detection. value stored rising edge. signal forced after falling edge clock stretching state. signal stretched state after falling edge after conditional detection.
15.2 Overview
USRT block supports software universal synchronous receiver transmitter mode interfaces. External lines respectively correspond clock line data line. mapped PB[4] PB[5] when USRT block enabled. independent from RegPBdir (Port input output). When USRT enabled, configurations port PB[4] PB[5] overwritten USRT configuration. Internal pull-ups used setting PBPullup[5:4] bits. Conditional edge detections provided. RegUsrtS1 used read data line from PB[5] receive mode drive output line PB[5] writing when transmit mode. advised read data when receive mode from RegUsrtBufferS1 register, which value sampled rising edge
15.3 Register
Block configuration registers: pos. RegUsrtS1 UsrtS1 reset 0000000 resetsystem function Unused Write: data written PB[5]), Read: value PB[5] (not UsrtS1 value).
Table 15-1: RegUsrtS1 pos. RegUsrtS0 UsrtS0 Reset 0000000 resetsystem function Unused Write: clock written PB[4], Read: value PB[4] (not UsrtS0 value).
Table 15-2: RegUsrtS0 values that read registers RegUsrtS1 RegUsrtS0 necessarily same values that were written register. read value read back circuit pins, registers. Since outputs open drain, value different from register value forced external circuit circuit pins.
15-2
D0304-60
Datasheet XE88LC01/01A
pos.
RegUsrtCtrl UsrtWaitS0 UsrtEnWaitCond1 UsrtEnWaitS0 UsrtEnable
reset "0000" resetsystem resetsystem resetsystem resetsystem
function Unused Clock stretching flag (0=no stretching), cleared writing RegUsrtBufferS1 Enable stretching UsrtCond1 detection (0=disable) Enable stretching operation (0=disable) Enable USRT operation (0=disable)
Table 15-3: RegUsrtCtrl pos. RegUsrtCond1 UsrtCond1 reset 0000000 resetsystem
function
Unused State condition detection =detected), cleared when written.
Table 15-4: RegUsrtCond1 pos. RegUsrtCond2 UsrtCond2 reset 0000000 resetsystem function Unused State condition detection =detected), cleared when written.
Table 15-5: RegUsrtCond2 pos. RegUsrtBufferS1 UsrtBufferS1 reset 0000000 function Unused Value last rising edge. Clear RegUsrtEdgeS0 RegUsrtEdgeS0 Clear UsrtWaitS0 RegUsrtCtrl with value
Table 15-6: RegUsrtBufferS1 pos. RegUsrtEdgeS0 UsrtEdgeS0 reset 0000000 resetsystem function Unused State rising edge detection (1=detected). Cleared RegUsrtBufferS1
reading
Table 15-7: RegUsrtEdgeS0
15.4 Interrupts interrupt source
Irq_cond1 Irq_cond2 default mapping interrupt manager RegIrqMid(7) RegIrqMid(6) Table 15-8: Interrupts
15-3
D0304-60
Datasheet XE88LC01/01A
15.5 Conditional edge detection
Figure 15-1: Condition Condition satisfied when S0=1 falling edge UsrtCond1 RegUsrtCond1 when condition detected USRT interface enabled (UsrtEnable=1). Condition asserted both modes (receiver transmitter). UsrtCond1 read only cleared reset conditions writing data address. Condition occurrence also generates interrupt Irq_cond1.
15.6 Conditional edge detection
Figure 15-2: Condition Condition satisfied when S0=1 rising edge UsrtCond2 RegUsrtCond2 when condition detected USRT interface enabled. Condition asserted both modes (receiver transmitter). UsrtCond2 read only cleared reset conditions writing data address. Condition occurrence also generates interrupt Irq_cond2.
15.7 Interrupts polling
receive mode, there possibilities detect condition detection condition generate interrupt registers polled (reading checking RegUsrtCond1 RegUsrtCond2 registers status USRT communication).
15.8 Function description
UsrtEnable RegUsrtCtrl used enable USRT interface controls PB[4] PB[5] pins. This puts these port lines open drain configuration requested USRT interface.
15-4
D0304-60
Datasheet XE88LC01/01A
external pull-ups added PB[4] PB[5], user activate internal pull-ups setting PBPullup[4] PBPullup[5] RegPBPullup. bits UsrtEnWaitS0, UsrtEnWaitCond1, transmitter/receiver control USRT interface. UsrtWaitS0 RegUsrtCtrl used
Figure 15-3 shows unconditional clock stretching function which enabled setting UsrtEnWaitS0.
UsrtWaitS0
write UsrtBufferS1
Figure 15-3: Stretching (UsrtEnWaitS0=1) When UsrtEnWaitS0 line will maintained after falling edge (clock stretching). UsrtWaitS0 then indicating that line forced low. release writing RegUsrtBufferS1 register. same done combination with condition detection setting UsrtEnWaitCond1 bit. Figure 15-4 shows conditional clock stretching function which enabled setting UsrtEnWaitCond1.
UsrtWaitS0
write UsrtBufferS1
Figure 15-4: Conditional stretching (UsrtEnWaitCond1=1)
15-5
D0304-60
Datasheet XE88LC01/01A When UsrtEnWaitCond1 signal will stretched state after falling edge condition been detected before (UsrtCond1=1). UsrtWaitS0 then indicating that line forced low. release writing RegUsrtBufferS1 register. Figure 15-5 shows sampling function implemented UsrtBufferS1 bit. UsrtBufferS1 RegUsrtBufferS1 value sampled PB[4] last rising edge UsrtEdgeS0 RegUsrtEdgeS0 same rising edge cleared read operation RegUsrtBufferS1 register. therefor indicates that value present RegUsrtBufferS1 which read.
UsrtBufferS1
read UsrtBufferS1
UsrtEdgeS0
Figure 15-5: sampling
15-6
D0304-60
Datasheet XE88LC01/01A
16.1 16.2 16.3
Acquisition chain
ZoomingADC Features 16-2 Overview 16-2 Register 16-3 ZoomingADC Description 16-4 Acquisition Chain 16-4 Peripheral Registers 16-6 Continuous-Time On-Request 16-7 Input Multiplexers 16-9 Programmable Gain Amplifiers 16-10 Enabling 16-11 PGA1 16-12 PGA2 16-12 PGA3 16-12 Characteristics 16-13 Conversion Sequence 16-13 Sampling Frequency. 16-14 Over-Sampling Ratio 16-14 Elementary Conversions. 16-14 Resolution 16-15 Conversion Time Throughput. 16-16 Output Code Format 16-16 Power Saving Modes. 16-18 Specifications Measured Curves 16-18 Default Settings 16-18 Specifications. 16-19 Linearity 16-21 Integral non-linearity 16-21 Differential non-linearity 16-24 Noise. 16-25 Gain Error Offset Error. 16-26 Power Consumption 16-27 Power Supply Rejection Ratio 16-29 Application Hints 16-30 Input Impedance 16-30 Settling Input Channel Modifications 16-30 Gain Offset, Linearity Noise. 16-30 Frequency Response. 16-31 Power Reduction 16-32
16.4 16.4.1 16.4.2 16.4.3 16.5 16.6 16.6.1 16.6.2 16.6.3 16.6.4 16.7 16.7.1 16.7.2 16.7.3 16.7.4 16.7.5 16.7.6 16.7.7 16.7.8 16.8 16.8.1 16.8.2 16.8.3 16.8.3.1 16.8.3.2 16.8.4 16.8.5 16.8.6 16.8.7 16.9 16.9.1 16.9.2 16.9.3 16.9.4 16.9.5
16-1
D0304-60
Datasheet XE88LC01/01A
16.1 ZoomingADC Features
ZoomingADC complete versatile low-power analog front-end interface typically intended sensing applications. features ZoomingADC are: Programmable 16-bit dynamic range oversampled Flexible gain programming between 1000 Flexible large range offset compensation 4-channel differential 8-channel single-ended input multiplexer 2-channel differential reference inputs Power saving modes Direct interfacing CoolRisc microcontroller
16.2 Overview
PGA1 PGA2
PGA3
Analog Inputs
VIN,ADC
Input Selection
OFF2
OFF3
Reference Inputs
VREF
Offset2 Offset3 Gain3
Reference Selection
Gain1 Gain2
ZOOM
Figure 16-1. ZoomingADC general functional block diagram total acquisition chain consists input multiplexer, programmable gain amplifier stages oversampled converter. reference voltage selected different channels. offset compensation amplifiers allow wide offset compensation range. programmable gain offset allow zoom small portion reference voltage defined input range.
16-2
D0304-60
Datasheet XE88LC01/01A
16.3 Register
There eight registers acquisition chain (AC), namely RegAcOutLsb, RegAcOutMsb, RegAcCfg0, RegAcCfg1, RegAcCfg2, RegAcCfg3, RegAcCfg4 RegAcCfg5. Table 16-2 Table 16-9 show mapping control bits functionality these registers while Table 16-1 gives overview these eight. register only gives short description different configuration bits. More detailed information found subsequent sections. register name RegAcOutLsb RegAcOutMsb RegAcCfg0 RegAcCfg1 RegAcCfg2 RegAcCfg3 RegAcCfg4 RegAcCfg5 Table 16-1: registers
pos. RegAcOutLsb Out[7:0] reset 00000000 resetsystem description output code
Table 16-2: RegAcOutLsb
pos. RegAcOutMsb Out[15:8] reset 00000000 resetsystem description output code
Table 16-3: RegAcOutMsb
pos. RegAcCfg0 Start SET_NELCONV[1:0] SET_OSR[2:0] CONT reserved reset resetsystem resetsystem resetsystem resetsystem resetsystem description starts conversion sets number elementary conversions sets oversampling rate elementary conversion continuous conversion mode
Table 16-4: RegAcCfg0
pos. RegAcCfg1 IB_AMP_ADC[1:0] IB_AMP_PGA[1:0] ENABLE[3:0] reset resetsystem resetsystem 0000 resetsystem description Bias current selection converter Bias current selection stages Enables different stages
Table 16-5: RegAcCfg1
16-3
D0304-60
Datasheet XE88LC01/01A
pos.
RegAcCfg2 FIN[1:0] PGA2_GAIN[1:0] PGA2_OFFSET[3:0]
reset resetsystem resetsystem 0000 resetsystem
description Sampling frequency selection PGA2 stage gain selection PGA2 stage offset selection
Table 16-6: RegAcCfg2
pos. RegAcCfg3 PGA1_GAIN PGA3_GAIN[6:0] reset resetsystem 0000000 resetsystem description PGA1 stage gain selection PGA3 stage gain selection
Table 16-7: RegAcCfg3
pos. RegAcCfg4 reserved PGA3_OFFSET[6:0] reset 0000000 resetsystem description Unused PGA3 stage offset selection
Table 16-8: RegAcCfg4
pos. RegAcCfg5 BUSY AMUX[4:0] VMUX reset resetsystem 00000 resetsystem resetsystem description Activity flag Selects default configuration Input channel configuration selector Reference channel selector
Table 16-9: RegAcCfg5
16.4 ZoomingADC Description
Figure 16-2 gives more detailed description acquisition chain. 16.4.1 Acquisition Chain
Figure 16-1 shows general block diagram acquisition chain (AC). control block (not shown Figure 16-1) manages communications with CoolRisc microcontroller. Analog inputs selected among eight input channels, while reference input selected between differential channels. core zooming section made three differential programmable amplifiers (PGA). After selection combination input reference signals VREF, input voltage modulated amplified through stages Fine gain programming 1'000V/V possible. addition, last stages provide programmable offset. Each amplifier bypassed needed. output stages directly analog-to-digital converter (ADC), which converts signal VIN,ADC into digital.
16-4
D0304-60
Datasheet XE88LC01/01A
Like most ADCs intended instrumentation sensing applications, ZoomingADC oversampled converter (See Note1). so-called incremental converter, with bipolar operation (the accepts both positive negative input voltages). first approximation, output result relative full-scale (FS) delivers quantity:
(Eq.
two's complement (see Sections 16.4 16.7 details). output code OUTADC -FS/2 +FS/2 VIN,ADC -VREF/2 +VREF/2 respectively. will shown section 16.6, VIN,ADC related input voltage relationship:
GDTOT GDoff
(Eq.
where GDTOT total gain, GDoffTOT total offset.
Inputs
AC_A
PGA1
PGA2 PGA3 VIN,ADC
OFF2
OFF3
AC_R
VREF
Acquisition Chain Register Bank
RegACCfg5 RegACCfg4 RegACCfg3 RegACCfg2 RegACCfg1 RegACCfg0
Power Saving Modes Enabling Conversion Start Elementary Cycles Over-Sampling Ratio Continuous On-Request
RegACOutLSB RegACOutMSB
Busy Flag Default Settings
Sampling Frequency
Figure 16-2. ZoomingADC detailed functional block diagram
Note: Over-sampled converters operated with sampling frequency much higher than input signal's Nyquist rate (typically 20-1'000 times input signal bandwidth). sampling frequency throughput ratio large (typically 10-500). These converters include digital decimation filtering. They mainly used high resolution, and/or low-to-medium speed applications.
16-5
D0304-60
Datasheet XE88LC01/01A
16.4.2
Peripheral Registers
Figure 16-2 shows detailed functional diagram ZoomingADC. Table 16-10 configuration peripheral registers detailed. system bank eight 8bit registers: registers used configure acquisition chain (RegAcCfg0 registers used store output code analog-to-digital conversion (RegAcOutMsb Lsb). register coding parameters performance characteristics detailed Section 16.7. Table 16-10. Peripheral registers configure acquisition chain (AC) store analog-to-digital conversion (ADC) result Register Name RegAcOutLsb RegAcOutMsb RegAcCfg0 Default values: RegAcCfg1 Default values: RegAcCfg2 Default values: RegAcCfg3 Default values: RegAcCfg4 Default values: RegAcCfg5 Default values:
With:
Position OUT[7:0] OUT[15:8] STAR SET_NELC[1:0] SET_OSR[2:0] CONT IB_AMP_ADC[ IB_AMP_PGA[1: ENABLE[3:0] 1:0] 0001 FIN[1:0] PGA1 BUSY PGA2_GAIN[1:0] PGA2_OFFSET[3:0] 0000
TEST
PGA3_GAIN[6:0] 0000000 PGA3_OFFSET[6:0] 0000000 AMUX[4:0] 00000 VMUX
OUT: digital output code analog-to-digital converter. (MSB OUT[15]) START: setting this triggers single conversion (after current finished). This always reads back SET_NELC: (rw) sets number elementary conversions 2SET_NELC[1:0] compensate offsets, input signal chopped between elementary conversions (1,2,4,8). SET_OSR: (rw) sets over-sampling rate (OSR) elementary conversion 2(3+SET_OSR[2:0]) 512, 1024. CONT: (rw) setting this starts conversion. conversion will automatically begin long remains TEST: only used test purposes. normal mode, this forced cannot overwritten. IB_AMP_ADC: (rw) sets bias current 0.25*(1+ IB_AMP_ADC[1:0]) normal operation current (25, 100% nominal current). used low-power, lowspeed operation. IB_AMP_PGA: (rw) sets bias current PGAs 0.25*(1+IB_AMP_PGA[1:0]) normal operation current (25, 100% nominal current). used low-power, lowspeed operation.
16-6
D0304-60
Datasheet XE88LC01/01A
ENABLE: (rw) enables modulator (bit different stages PGAs (PGAi i=1,2,3). stages that disabled bypassed. FIN: (rw) These bits sampling frequency acquisition chain. Expressed fraction oscillator frequency, sampling frequency given fRC, fRC, 1/32 fRC, ~8kHz. PGA1_GAIN: (rw) sets gain first stage: PGA2_GAIN: (rw) sets gain second stage: PGA3_GAIN: (rw) sets gain third stage PGA3_GAIN[6:0]1/12. PGA2_OFFSET: (rw) sets offset second stage between with increments 0.2. gives sign positive, negative); amplitude coded with bits PGA2_OFFSET[5:0]. PGA3_OFFSET: (rw) sets offset third stage between -5.25 +5.25, with increments 1/12. gives sign positive, negative); amplitude coded with bits PGA3_OFFSET[5:0]. BUSY: conversion running. Note that flag effective start conversion. Since generally synchronized lower frequency clock than CPU, there might small delay (max. cycle sampling frequency) between writing START CONT bits appearance BUSY flag. DEF: sets values their defaults (PGA disabled, speed, nominal modulator bias current, elementary conversions, over-sampling rate starts conversion without waiting preceding one. AMUX(4:0): (rw) AMUX[4] sets mode differential inputs, inputs with A(0) common reference) AMUX(3) sets sign straight, cross) AMUX[2:0] sets channel. VMUX: (rw) sets differential reference channel R(1) R(0), R(3) R(2)). read; write; read write)
16.4.3
Continuous-Time On-Request
operated distinct modes: "continuous-time" "on-request" modes (selected using CONT). "continuous-time" mode, input signal repeatedly converted into digital. After conversion finished, automatically initiated. value then written result register, corresponding internal trigger pulse generated. This operation sketched Figure 16-3. conversion time this case defined TCONV.
TCONV Internal Trig Ouput Code RegACOut[15:0] BUSY
Figure 16-3. "continuous-time" operation
CONV Internal Trig Request START Ouput Code RegACOut[15:0] BUSY
Figure 16-4. "on-request" operation
16-7
D0304-60
Datasheet XE88LC01/01A
"on-request" mode, internal behaviour converter same "continuoustime" mode, conversion initiated user request (with START bit). shown Figure 16-4, conv
Other recent searches
SUM110N08-07 - SUM110N08-07 SUM110N08-07 Datasheet
STR-S6525 - STR-S6525 STR-S6525 Datasheet
MA00774 - MA00774 MA00774 Datasheet
HMC247 - HMC247 HMC247 Datasheet
gs2100 - gs2100 gs2100 Datasheet
FW60 - FW60 FW60 Datasheet
API2HR21-000 - API2HR21-000 API2HR21-000 Datasheet
API1FS07-001 - API1FS07-001 API1FS07-001 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
