VSSD VSSA VSSA VREF VREG11 VREG16 Microphone Bias XE3006

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VSSD VSSA VSSA VREF VREG11 VREG16 Microphone Bias XE3006

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Datasheet XE3005/XE3006
VSSD VSSA VSSA VREF VREG11 VREG16
Microphone Bias
XE3006
Power supply management
RESET VDDPA
Amp.
modulator
Decimator
Power amplifier
AOUTP AOUTN VSSPA
Sandman Functions
Serial Audio Interface
Clock
MISO MOSI SMAD SMDA BCLK FSYNC MCLK
XE3005 XE3006
Low-Power Audio CODEC
General Description
XE3005 ultra low-power CODEC (Analog Digital Digital Analog Converter) voice audio applications. includes microphone supply, preamplifier, 16-bit ADC, 16-bit DAC, serial audio interface, power management clock management DAC. sampling frequency adjusted from kHz. XE3006 also includes Sandmanfunction, which signals whether relevant voice audio signal present DAC.
Features
Ultra low-power consumption, below Low-voltage operation down Sandmanfunction reduce system power consumption (XE3006) Single supply voltage Adjustable sampling frequency: Digital format: complement Requires minimum number external components Easy interfacing various DSPs Direct connection microphone speaker Various programming options
Applications
Wireless Headsets Bluetoothheadset Hands-free telephony Digital hearing instruments Consumer multimedia applications battery-operated portable audio devices
Quick Reference Data
supply voltage current (@20 sampling) sampling frequency Typical dynamic range Typical dynamic range
Ordering Information
Part XE3005 XE3005 XE3006 Package TSSOP pins uCSP® balls TSSOP pins Ext. part XE3005I033 XE3005I064LF XE3006I019 Temperature range
Cool Solutions Wireless Connectivity
XEMICS e-mail: info@xemics.com web: www.xemics.com
Datasheet XE3005/XE3006
Table contents
Device Description. Terminals Description XE3005/6 Functional Description Device Functions Power-Down Functions. Serial Communications Serial Audio Interface. Register Programming Serial Peripheral Interface SandmanFunction (XE3006). Specifications. Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Application Information. Application Schematics XE3006. Register Description. Register Functional Summary Register Definitions. Mechanical Information. XE3005 package size (TSSOP20) XE3005 package size (5x4 uCSP®) XE3006 Package size (TSSOP24) XE3005 Land pattern recommendations (5x4 uCSP®)
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Datasheet XE3005/XE3006
Device Description
MCLK SMAD SMDA MOSI MISO MCLK MOSI
XE3005
NRESET VREG16 VREF VSSA VSSD VREG11
BCLK FSYNC AOUTP VDDPA AOUTN VSSPA
XE3006
NRESET VSSA VREG16 VREF VSSA
BCLK FSYNC AOUTP VDDPA AOUTN VSSPA
VSSD VREG11
Figure layout XE3006 XE3005 TSSOP
BCLK
AOUTP
AOUTN
XEMICS XE3005
MOSI
FSYNC
VDDPA
VSSPA
MCLK
VREG16
VSSD
VREG11
NRESET
VREF
VSSA
VIEW
BOTTOM VIEW
Figure layout XE3005 uCSP®
XE3006 available TSSOP24 package. XE3005 available TSSOP20 uCSP® package. Detailed information found chapter Mechanical Information.
D0311-116
Datasheet XE3005/XE3006
Terminals Description XE3005/6
Terminals Description Name Type Master Clock. MCLK derives internal clocks Sandman output Sandman output Digital power supply Reset signal generated CODEC. required, reset signal applied externally initialize internal CODEC registers Analog ground Regulator voltage used supply microphone Reference voltage Analog ground Digital ground Regulated microphone output supply voltage Analog input signal Power Amplifier Ground Analog Output negative Power Amplifier Supply Analog Output positive Serial audio interface Frame Synchronization Serial audio interface Clock Serial audio interface Data Output Serial audio interface Data Input Master Slave Serial Clock Slave Select Master Slave
XE3006
TSSOP24
XE3005
TSSOP20 uCSP®
Note:
MCLK SMAD SMDA NRESET VSSA VREG16 VREF VSSA VSSD VREG11 VSSPA AOUTN VDDPA AOUTP FSYNC BCLK MISO MOSI
ZI/O DI/O DI/O
Analog Input Analog Output Digital Input Digital Output DI/O Digital Impedance Output internal Pull internal Pull Down ZI/O impedance
D0311-116
Datasheet XE3005/XE3006
Functional Description
CODEC typically used voice audio applications interface between Digital Signal processor (DSP) microcontroller analogue interfaces like microphone loudspeaker.
MIC-Amplifier
Power Amplifier
Serial Audio Interface CODEC
Microcontroller
Digital wireless transmission BluetoothVoice recognition speech synthesis
Figure typical usage CODEC This chapter provides brief description CODEC features relating CODEC configuration. configuration CODEC defined programming registers through serial interface. detailed description registers defining details CODEC setup found chapter Digital voice audio samples passed through Serial Audio Interface.
2.1.1
Device Functions
Signal Channel
channel chain programmable amplifier, band-pass filter, sigma-delta modulator decimation filter. amplifier gain programmable (default) 20x. band-pass filter cut-off frequencies proportional sampling rate. sigma-delta modulator operates frequency times sampling rate. analog modulator followed digital decimation filter. digital output data bits, complement format) made available through Serial Audio Interface. format Serial Audio interface selected through register With default register settings sampling frequency kHz. When used with sampling frequency higher than kHz, then register changed. whole chain powered-down through register
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Datasheet XE3005/XE3006
2.1.2
Input
programmable pre-amplifier microphone bias sources VREG11 VREG16 optimized operate with electret microphones. VREG11 provides reference voltage. VREG11 deliver VREG11 enabled through control register VREG16 regulated voltage typically 1.6V deliver mA.VREG16 always enabled.
NRESET VSSA VREG16 VREF VSSA VSSD VREG11
0.1µF
390k
(gain (gain
Figure typical microphone interface (1.1 bias through VREG11)
NRESET VSSA VREG16 VREF VSSA VSSD VREG11
0.1µF
(gain (gain
depends microphone type
390k
Figure typical microphone interface (1.6 bias through VREG16)
XE3006
XE3006
D0311-116
Datasheet XE3005/XE3006
2.1.3
Signal Channel
based multi sigma-delta modulator, which operates frequency times sampling rate. outputs modulator complement words bit. pulse-width modulator (PWM) converts words into single streams times sampling frequency. Finally streams supplied power amplifier. Power Amplifier Class amplifier, which offers higher efficiency than traditional Class topologies. uses three-state unbalanced PWM. This means that both channels (AOUTP AOUTN) will switch same time, therefore outputs purely differential (see figure
XE3005/6
VDDPA
From Serial Audio Interface
Interpolator Modulator
Pulse Width Modulator
pwm_in(5:0) 8xFsync
Power Amplifier
AOUTP
streams 256xFsync
dac_in(15:0) Fsync
AOUTN
VSSPA
Figure block diagram Figure shows relation input output samples (The timing diagram scale time-axis).
VDDPA VSSPA -VDDPA
pwm_in(5:0)
pwm_in(5:0)
pwm_in(5:0)
pwm_in(5:0)
1/(256 Fsync) OUTP-OUTN
1/(256 Fsync)
1/(8 Fsync)
2/(256 Fsync)
Figure examples (not scale) receives 16-bit wide complement format through Serial Audio Interface. protocol selected through register complete amplifier chain powered-down through register
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Datasheet XE3005/XE3006
2.1.4
Digital Loop Back
digital loop back mode, output routed directly input. This allows in-circuit system level tests. digital loop back mode selected through register 2.1.5 Operating Frequency
master clock (MCLK) applied XE3005/3006. clock frequency signal applied MCLK vary between 1.024 minimum 33.9 maximum. maximum internal clock signal frequency (MCLK/div_factor) should exceed 12.288 MHz. div_factor user register default value div_factor `1'. 2.1.6 Serial Audio Interface
Serial Audio Interface 4-wire interface bi-directional communication audio data. operates serial clock BCLK frame synchronization signal FSYNC. sampling frequency CODEC corresponds rate which Audio Serial Interface will succeeding frames. frame always corresponds sample. frame always contains channels. Synchronizing Serial Audio Interface MCLK recommended. FSYNC MCLK must have fixed ratio defined following relation: FSYNC Sampling frequency frame rate MCLK/(256 div_factor). BCLK defines time when data must presented serial audio interface shifted into (pin SDI) (pin SDO) CODEC. number BCLK periods FSYNC period user select first clock cycles (channel second clock cycles (channel BLCK shift data samples. table below shows some examples relationships between MCLK, BCLK FSYNC MCLK 2048 8192 5120 22579.2 Div_factor BCLK 1411.2 FSYNC 44.1
table below shows possible functional configurations serial audio interface CODEC master slave supported protocol (Long Frame Sync) LFS, Optimization (Short Frame Sync)
default Serial Audio Interface operates slave, mode. slave mode user needs generate signals BLCK, FSYNC supply CODEC. master mode CODEC generates BLCK FSYNC signals. that case BLCK operates times frequency FSYNC. CODEC master mode used with protocol only. register used different setups serial audio interface.
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Datasheet XE3005/XE3006
2.1.7
Serial Peripheral Interface
interface used control register values. serial communications interface that independent rest CODEC. allows device communicate synchronously with microprocessor DSP. CODEC interface only implements slave controller. detailed description found chapter 3.3.
2.1.8
SandmanADC Function
Sandmanfunction monitors signals, which processed signal channel signal channel. logic output signal SMAD indicates whether signal channel processed audio signal only noise, long. reference signal amplitude selected through register time window parameters time time (registers
Amp.
modulator
Serial Audio Interface Decimator Sandman Interface
FSYNC BCLK
SMAD
Figure Implementation Sandman function (SMAD)
logic output SMAD used power-down reduce clock speed other devices application, such microcontroller, wireless link. Also, SMAD used phone pick-up indicator. Sandmanfunction illustrated Figure valid both SMAD (related signal) SMDA (related signal). Initially, SMAD inactive (low), which means that "noise" processed ADC, i.e. audio signal amplitude above Reference. SandmanInterface compares every output sample signal channel Reference value. signal lower than Reference value, SMAD remains inactive (low). soon signal passes reference (time on-time counter started. (for moment defined time='x' Figure However, signal returns below reference (time before on-time counter reached time, on-time counter reset SMAD signal remains inactive (low). next time signal gets higher than Reference (time on-time counter started again when reaches time, SMAD signal becomes active (high), indicating that audio signal present (time long signal remains above Reference, nothing happens SMAD signal remains active (high). When signal falls below Reference (time off-time counter started, does reach time before signal passes again Reference (time SMAD remains active (high). Also during period from time time time counter does reach time. When signal falls below Reference (time remains below Reference until off-time counter reached off-time, SMAD signal changed into inactive (low) state (time 10).
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Datasheet XE3005/XE3006 2.1.9 SandmanDAC Function
Sandmanfunction monitors signals, which processed signal, channel signal channel. logic output signal SMDA indicates whether signal channel processes audio signal only noise, this certain duration. reference signal amplitude selected through register time window parameters time time (registers
Sandman Interface SMDA VDDPA FSYNC BCLK Serial Audio Interface Power amplifier AOUTP AOUTN VSSPA
Figure Implementation Sandman function (SMDA) logic output SMDA employed power-down other devices application, such external audio power amplifier. setting register on-chip signal channel powered-down through SMDA too. Sandmanfunction illustrated Figure valid both SMAD (related signal) SMDA (related signal).
AIN/SDO (AOUT/SDI) reference
reference
On-time counter
Time step 1/fs 1/FSYNC Off-time counter
on-time SMAD (SMDA)
off-time
time
Figure Illustration Sandmanfunction. above illustration valid either SMAD output result AIN/SDO SMDA output function AOUT/SDI.
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Datasheet XE3005/XE3006 2.1.10 Start-up Initialization CODEC generates power reset signal after power supply connected pin. reset signal made available user NRESET. rising edge NRESET indicates that startup sequence CODEC finished. most applications NRESET left open. NRESET signal generated CODEC used initialize various blocks device guarantees correct start-up circuit. start-up sequence that automatically carried upon power-up device listed below illustrated Figure NRESET (0V) when device powered remains short time when (upper curve Figure applied. state sustains while VDD, VREG16, VREF stabilizing. soon MCLK signal present, counter activated that counts periods MCLK. After this moment NRESET high state (VDD).
1.8.3.3V VREG16 1.6V
VREF 1.2V
time
MCLK
(MCLK=2.048KHz) NRESET main reset
Figure Startup sequence NRESET signal after power-on. user NRESET different ways combinations: Leave NRESET connected. this case CODEC will startup described figure NRESET output indicate, e.g. microcontroller, that CODEC finished power sequence that CODEC ready operate. NRESET force re-initialization registers their default values. this case user force NRESET least periods MCLK. circuit which forces NRESET should able sink least
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Datasheet XE3005/XE3006 Figure shows block diagram CODEC reset.
reset analog digital circuitry codec
Power Reset
delay delay counter MCLK XE3005/6 drive buffer
NRESET
Figure Codec reset circuitry
2.2.1
Power-Down Functions
Software Power-Down
Register allows selective power down signal channel signal channel through control. wake-up time, after powering down device typically 200µs. maximum standby current 96µA, depending highly upon Master clock (MCLK), 5.3.5.2 Power Modes. 2.2.2 Hardware Power-Down
device power-down pin. However, holding down NRESET (resetting device) well pins MCLK, BCLK FSYNC, power consumption will reach standby current typically 16µA. standard procedure power (see start-up initialization procedure) after hardware power down apply your registers setup procedure.
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Datasheet XE3005/XE3006
Serial Communications
Serial Audio Interface
Serial Audio Interface 4-wire interface bi-directional communication audio data. terminals listed below: BCLK: FSYNC: SDI: SDO: serial clock, clock cycle corresponds data transmitted received. Frame Synchronization. This signal indicates start data word. frequency FSYNC corresponds sample frequency CODEC. Serial Data data received from external device sent DAC. Serial Data Out, data received from sent external device.
same clock (BCLK) synchronization (FSYNC) signals used both sending receiving. synchronization signal FSYNC must have fixed ratio with master clock signal MCLK. Serial Audio Interface supports formats that commonly used audio/voice CODECs that referred (Short Frame Synchronization) (Long Frame Synchronization). Data transmitted received channels. Which channel selected depends programmed values registers. interface protocols shown below.
FSYNC BCLK
channel sample
channel data
channel sample
n+115 n+115
Figure Audio interface timing mode, channel
FSYNC BCLK
channel sample
channel sample
channel sample
n+115 n+115
Figure Audio interface timing mode, channel
Data should changed rising edge BCLK. data will read CODEC falling edge BLCK. data will change rising edge BCLK. data should read falling edge BLCK. Each rising edge FSYNC indicates start sample.
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Datasheet XE3005/XE3006 3.1.1 Optimization
transmitting receiving, clock cycles frame always required (figure 13). This even case when only bits have sent received. most cases this handled easily with microcontroller. user wants send minimum BLCK cycles, possible shorten channel (channel shortened). mode possibility exists shorten number BLCK cycles instead this case data transmitted received channel Channel shortened BLCK cycle only. Note! This optimization possible slave mode only. figure shows this special mode.
channel data
channel data channel sample channel sample
FSYNC BCLK
Figure Audio interface timing mode, BLCK cycles, channel
Register Programming
control registers define configuration CODEC define various modes operation. During power-up, registers will configured with default values. control register consists registers. detailed description provided chapter control registers changed following ways: Logic values pins during power-up There bits inside registers which configured depending logic values pins MOSI during power startup sequence described section 2.1.10
Value power MOSI MOSI
Influenced bits registers Register I(0)=0 Register I(0)=1 Register J(0)=1 Register J(0)=0 Register E(2) Register E(2)
comments MCLKDIV division MCLKDIV division protocol protocol preamplifier gain preamplifier gain
Using pins startup user able configure CODEC corresponding setups without reprogramming through interface protocol. best case interface then completely omitted pins fixed `1'. D0311-116
Datasheet XE3005/XE3006
Programming through interface after power-up Once device been powered configuration registers modified times (also when device active) through interface. following section describes protocol which required change control registers from their default values.
Serial Peripheral Interface
serial peripheral interface (SPI) allows device communicate synchronously with other devices such microprocessor DSP. CODEC interface only implements slave controller. This section describes communication from master (e.g. DSP) slave (CODEC MOSI) from slave (CODEC MISO) master (e.g. DSP). Four lines used transmit data between slave master: MOSI (Master Out, Slave data from master slave, synchronous with clock (SCK). MISO (Master Slave Out) data from slave master, synchronous with clock (SCK). (Serial Clock) synchronizes data bits MOSI MISO. (Slave Select) Slave devices selected activating
3.3.1
Protocol
During communication, data simultaneously transmitted received.
trecovery
MOSI MISO
1/Fsck
tdisable
Figure signal timing master puts data MOSI line falling edge SCK; slave reads data rising edge SCK. slave puts data MISO line falling edge SCK; master reads data rising edge SCK. Transmission either direction bytes with first. should kept during whole transfer data. There three timing constraints: Recovery time recovery) between falling edge falling edge SCK. Disable time disable) between last rising edge rising edge frequency (FSCK)
Delay recover disable
Tmaster
Fmaster
Unit
Comments Tmaster clock period master clock MCLK Fmaster frequency master clock MCLK D0311-116
Datasheet XE3005/XE3006
3.3.2
Interface Modes
There modes: read write. 3.3.2.1 Read Mode
Read communication always takes place pairs bytes. read request bytes sent MOSI line. content addressed register, byte, dumped MISO line during transmission second byte MOSI. formats byte following: mosi miso D(7:0) (4:0)
mosi
request (read <address A(4:0)>)
miso
read data D(7:0) address A(4:0)
Figure signal timing read mode 3.3.2.2 Write Mode
Write communication always takes place pairs bytes. format bytes
mosi mosi
D(7:0)
A(4:0)
mosi
request (write address A(4:0))
write data D(7:0) address A(4:0)
Figure signal timing write mode
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Datasheet XE3005/XE3006
SandmanFunction (XE3006)
Sandmanfunction analyzes audio signals DAC. output signals indicate whether audio signal present processed signal just noise. threshold reference value between noise audio signal well minimum duration audio signal user-programmable through interface. XE3006 CODEC used system that includes microcontroller, link, outputs SandmanInterface used bring these devices into standby sleep mode whenever audio signal being processed. this way, Sandmanfunction contributes significant additional power savings system level outside XE3006 chip. SandmanInterface consists digital outputs: SMAD detects whether processes audio signal. calculation made with digital data leaving ADC. SMDA detects whether audio signal processed DAC. calculation made with digital data entering through Audio Interface. SandmanInterface implemented identical way. works with user-defined parameters: time, on-time, ADC-reference DAC-reference. time time same DAC. However, reference values adjusted separately, indicated table below.
Input parameters Off-time1(7:0) Off-time2(15:8) On-time(7:0) ADC_reference(7:0) DAC_reference(7:0)
Register
Sandman
Sandman
SandmanInterface (for well DAC) configured with three parameters: Reference (7:0): Absolute value under which signal considered noise above which signal considered audio signal. Sandmanfunction disabled (SMAD SMDA logic this parameter zero. have separate Reference values. Off-time (15:0): Time until power down. number sequential samples that have lower than Reference power down signal become active. Sandmanfunction disabled (SMAD SMDA logic this parameter zero. have common Off-time value. On-time (7:0): Time until wakeup. number sequential samples that have higher than Reference power down signal become inactive. Sandmanfunction disabled (SMAD SMDA logic this parameter zero. have common On-time value. these parameters registers Reference(7:0) don't care don't care 1.-.255 corresponds 128.-.32640 On-time(7:0) don't care don't care 1.-.255 corresponds Off-time(15:0) don't care don't care 65535 corresponds Sandman (SMAD SMDA) logic (disable function) logic (disable function) logic (disable function) logic (signal higher than ref) logic (signal lower than ref) Comments Sandman disable Sandman disable Sandman disable registers zero time FSYNC 20kHz
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Datasheet XE3005/XE3006 reference (7:0) value related absolute value bits input signal. following format used comparison: inputs data (2's-complement) 0111'1111'1111'1111 0x7FFF reference (unsigned) 0111'1111'1000'0000 0xFF00/2 positive value reference
reference compared most significant bits absolute value input signal: reference(7:0) Absolute reference 32640 (mV) gain 0.00 1.10 2.20 (mV) gain 0.00 0.27 0.55
values this table amplitude values, values derived dividing numbers working mechanism Sandmanfunction following: incoming data compared reference after each time step (1/FSYNC 50µs FSYNC 20kHz). During On-time phase input data higher than reference, counter will incremented otherwise counter reset. When counter reaches On-time value, then SMAD SMDA signal activated (high level). During Off-time phase input data lower than reference, counter will incremented otherwise counter reset. When counter reaches Off-time value, then SMAD SMDA signal deactivated (low level). first approximation, following points recommended: On-time least 1ms. On-time shorter than Sandmanfunction becomes sensitive spikes audio input signal AIN. Off-time least 10ms, Off-time should longer than 1/fmin 10ms, (code 200). fmin minimum audio frequency 100Hz FSYNC 20kHz. value fmin scales proportionally with sampling frequency FSYNC. high-pass filter filters signals below 100Hz. Reference should adjusted just above noise level. CODEC bandwidth around nominal system frequency settings (MCLK MHz, CKDIV FSYNC kHz). digital loop back mode, data entering into Audio Interface transferred DAC. However, Sandmanfunction activated) continues output SMDA signal based data entered into Audio Interface (input terminal SDI).
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Datasheet XE3005/XE3006
Specifications
Absolute Maximum Ratings
Stresses above those listed following table cause permanent failure. Exposure absolute ratings extended periods affect device reliability. values accordance with Absolute Maximum Rating System (IEC 134). voltages referenced ground (VSSA VSSD). Analog digital grounds equal (VSSA VSSD). Symbol Parameter Conditions Unit Supply voltage -0.3 3.65 Tstg Storage temperature Operating free-air temperature, Electrostatic discharge protection Ilus Static latchup current Vlud Dynamic latchup voltage Tested according MIL883C Method 3015.6, class JEDEC (Standardized Human Body Model: 1500 pulses, protection related substrate). Static dynamic latchup values valid
Recommended Operating Conditions
voltages referenced ground (VSSA VSSD). Supply voltage, Analog signal peak input voltage, (gain 20x) Analog signal peak input voltage, (gain Differential output load resistance Master clock frequency conversion rate Operating free-air temperature, 1.024 Unit
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Datasheet XE3005/XE3006
Electrical Characteristics
operating conditions this section are: 25°C. 5.3.1 Digital Inputs Outputs, FSYNC kHz, output loaded Test Conditions -360uA
Parameter High-level output voltage, DOUT Low-level output voltage, DOUT 5.3.2 High-level input current, digital input Low-level input current, digital input Input capacitance Output capacitance Dynamic Performance, FSYNC Parameter Signal-to-noise ratio Total harmonic distortion cut-off frequency dB), Note High cut-off frequency dB), Note Group delay
VSSD-0.5
VDD+0.5
Unit
Test Conditions
Pre-amp gain Vin=250mV (full scale)
Unit
full scale FSYNC FSYNC FSYNC
Note proportional FSYNC Note equals FSYNC/2 5.3.3 Channel Characteristics, FSYNC Parameter Peak input voltage (single ended) Test Conditions Pre-amp gain Pre-amp gain
A-weighted, Hz-10 pre-amp gain A-weighted, Hz-10 pre-amp gain Pre-amp gain Vin=250mV (full scale)
Unit
Vneq Equivalent input noise Dynamic range PSRR Power supply rejection ratio, input referred Input capacitor Input resistance VSSA gain error offset error input noise Integral linearity
MOhm
Preamp-gain Preamp gain 1.8-3.3V 1.8-3.3V 1.8-3.3V 1.8-3.3V 1.8-3.3V
Differential linearity
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Datasheet XE3005/XE3006
5.3.4
Dynamic Performance, load filter
FSYNC kHz, MCLK MHz, info filter chapter Application Information. Parameter Signal-to-noise ratio Total harmonic distortion Dynamic range Group delay Test Conditions Bandwidth full scale Bandwidth FSYNC Unit
5.3.5 5.3.5.1
Power Supply Regulated supply characteristics 25°C Test Conditions capacitor resistor
Parameter VREF VREG11 I_vreg11 R_vreg11 VREG16 I_vreg16 VREF PSRR reference Voltage regulated Voltage 1.1V available current output impedance regulated Voltage 1.6V available output current power supply rejection ratio, input referred
Unit
kOhm
capacitor
VREG11 PSRR power supply rejection ratio, input referred VREG16 PSRR power supply rejection ratio, input referred 5.3.5.2 power mode
Stand-by mode 3.0V, 25°C Parameter Istb1 Istb2 Istb3 Supply current standby mode Supply current standby mode Supply current standby mode Test Conditions
off, MCLK MHz, off, MCLK 12.2880 NRESET mode MCLK
Unit
Stand-by mode 1.8V, 25°C Parameter Istb1 Istb2 Istb3 Supply current standby mode Supply current standby mode Supply current standby mode Test Conditions
off, MCLK MHz, off, MCLK 12.2880 NRESET mode MCLK
Unit
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Datasheet XE3005/XE3006
5.3.5.3
Normal operation, output load consumption included.
Normal operations 3.0V, FSYNC kHz, 25°C, Register C(7:0) 0xF0 Parameter IADC IDAC Supply current CODEC Supply current Supply current Test Conditions
FSYNC kHz, load FSYNC kHz, load off, FSYNC kHz, load
Unit
Normal operations 3.0V, FSYNC kHz, 25°C, Register C(7:0) 0xC4 Parameter IADC IDAC Supply current CODEC Supply current Supply current Test Conditions
FSYNC kHz, load FSYNC kHz, load off, FSYNC kHz, load
1720 1200
Unit
Normal operations 1.8V, FSYNC kHz, 25°C, Register C(7:0) 0xF0 Parameter IADC IDAC Supply current CODEC Supply current Supply current Test Conditions
FSYNC kHz, load FSYNC kHz, load off, FSYNC kHz, load
Unit
Normal operations 1.8V, FSYNC kHz, 25°C, Register C(7:0) 0xC4 Parameter IADC IDAC Supply current CODEC Supply current Supply current Test Conditions
FSYNC kHz, load FSYNC kHz, load off, FSYNC kHz, load
1250 1010
Unit
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Datasheet XE3005/XE3006
5.3.6
Timing Requirements serial audio interface
Ref.
Characteristics Master Clock Frequency MCLK
MCLK Duty Cycle Rise Time Digital Signals Fall Time Digital Signals Hold time BCLK FSYNC high after MCLK Setup time BCLK FSYNC high MCLK Hold time BCLK FSYNC after MCLK Setup time BCLK FSYNC MCLK
Test Conditions
1024
5.12
Unit
CLoad 10pF 32xFSYNC TBCLK/4 TBCLK/4 TBCLK/4 TBCLK/4 TBCLK/4
MCLK/2
Clock Frequency BCLK TBCLK
Setup time data input BCLK Hold time data input after BCLK Delay time valid after BCLK high Setup time data input FSYNC BCLK Hold time data input FSYNC after BCLK
*see figure 18,19
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Datasheet XE3005/XE3006 5.3.6.1 Timing diagram serial audio interface mode
MCLK BCLK FSYNC
Figure LFS, timing diagram
MCLK BCLK FSYNC
Figure LFS, zoom timing diagram
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Datasheet XE3005/XE3006 5.3.6.2 Timing diagram serial audio interface mode
MCLK BCLK FSYNC
Figure SFS, timing diagram
MCLK BCLK FSYNC
Figure zoom timing diagram
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Datasheet XE3005/XE3006
5.3.7
Timing Requirements Serial Peripheral Interface
Ref. No.*
MCLK Duty Cycle Recovery Time Disable Time Setup time MISO valid high Hold time MISO valid after high Delay time MOSI valid after figure
Characteristics Serial Clock Frequency TSCK
Test Conditions
TSCK/4 TSCK/4 TSCK/4
MCLK/2
CLoad 10pF
Unit
MISO MOSI
Figure Serial Peripheral Interface timing
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Datasheet XE3005/XE3006
Application Information
6.1.1
Application Schematics XE3006
Typical Application schematic
Sandman output Master Clock
MCLK SMAD SMDA MOSI MISO
XE3006
0.1µF
NRESET VSSA VREG16 VREF VSSA VSSD VREG11
BCLK FSYNC AOUTP VDDPA AOUTN VSSPA
Serial Audio Interface L=680µH 2µ2F 4µ7F R=56
390k
lowpass filter, Bluetoothvoice application MCLK 2.048 MHz, div_factor
Figure Typical Application with order output Filter
6.1.2
External components required optimal performances
following minimum set-up external components required: Capacitor Vref: Resistor Vref: Capacitor VREG16:
pass filter between output speaker depends CODEC settings speaker type.
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Datasheet XE3005/XE3006
Register Description
Register Functional Summary
following registers programmed configure operation modes. also section Register Programming. Name Register Description current setting. data this register following functions: Adjust current FSYNC 20kHz 0xF0 FSYNC<= kHz, 0xC4 FSYNC kHz. Analog Input. data this register following functions: Enable/disable microphone bias source Gain setting pre-amplifier. Function enable clock division. data this register following functions: Enable/disable Sandman function Enable/disable channel (DAC, power amplifier) Enable/disable channel (pre-amplifier, ADC, decimation filter) Division master clock Audio Interface Configuration. data this register following functions: Enable/disable digital loopback Channel select receive Select master slave mode Output impedance Channel select transmit Select short long frame sync Sandmanfunction, Off-time, byte. data this register following function: Define Off-time (low byte) Sandmanfunction Sandmanfunction, Off-time, high byte. data this register following function: Define Off-time (high byte) Sandmanfunction Sandmanfunction, On-time. data this register following function: Define On-time Sandmanfunction Sandmanfunction, reference ADC. data this register following function: Define reference amplitude Sandmanfunction Sandmanfunction, reference DAC. data this register following function: Define reference amplitude Sandmanfunction
Register
Register
Register
Register
Register
Register
Register
Register
D0311-116
Datasheet XE3005/XE3006
Register Definitions
complete register setup consists registers bits each, shown table below. registers preconfigured with default values have programmed user changes setup required. registers used configure XE3005 XE3006 differently than default setup. registers related Sandmanfunction available XE3006.
Register
Address (hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
Name Reserved Reserved current Reserved Analog input Reserved Reserved Reserved Block on/off clock division Audio interface configuration Reserved Sandmanfunction, off-time byte Sandmanfunction, off-time byte Sandmanfunction, on-time Sandmanfunction, reference Sandmanfunction, reference
Default value (hex) 0x48 0x8F 0xF0 0x00 0x08/0x0C 0x82 0x00 0x00 0x00/0x01 0x25/0x24 0x00 0x00 0x00 0x00 0x00 0x00
Register (7:0) address 0x02
current current
Default value: 0xF0 0xF0
Description 0xF0 FSYNC<= kHz, 0xC4 FSYNC kHz.
Register (7:0) address 0x04
input VMIC_EN reserved PREAMP_ GAIN
Default value 0x08/0x0C 0001
Description Generation microphone supply VREG11: enables VREG11 disables VREG11 reserved Gain preamplifier: (270 peak) peak)
default depending logic value MOSI during startup (see section 3.2) MOSI=0, default will MOSI=1, default will
reserved
reserved
D0311-116
Datasheet XE3005/XE3006
Register (7:0) address 0x08
block on/off clock division EN_DAC EN_ADC MCLKDIV
Default value 0x00/0x01 0000
Description reserved enable disable converter (DAC enable disable converter (Preamp decimator) Division factor master clock: reserved
default depending logic value during startup (see Section 3.2) SS=0, default will SS=1, default will
Register (7:0) address 0x09
Audio interface configuration LOOPBACK RX_FIRST_ SECOND reserved MASTER SDO_HI_EN
Default value 0x25/ 0x24
Description
TX_FIRST TX_SECOND PROTOCOL
disable loopback, normal mode enable loopback CODEC connects internally output input Receive audio data first 16-bit channel after frame synchronization. Receive audio data second 16-bit channel after frame synchronization. reserved enable audio interface master mode (only LFS) enable audio interface slave mode (LFS, Optimization SFS) continuously output mode both data channels. output mode when transmitting channel with data (J(2) J(1)=1). switched automatically into high-impedance state when channel with data transmitted (J(2) J(1)=0). transmit audio data first 16-bit channel after frame synchronization. transmit data first channel. transmit audio data second 16-bit channel after frame synchronization. transmit data second channel. Short Frame Synchronization mode (slave mode). Long Frame Synchronization mode (master slave mode).
default depending logic value during startup (see Section 3.2) SCK=0, default will SCK=1, default will
D0311-116
Datasheet XE3005/XE3006
Register (7:0) address 0x0B
Sandmanfunction, off-time, least significant byte SM_OFF_LSB
Default value 0x00 00000000
Description Least significant byte off-time Sandmanfunction
Register (7:0) address 0x0C
Sandmanfunction, off-time, most significant byte SM_OFF_MSB
Default value 0x00 00000000
Description Most significant byte off-time Sandmanfunction
Register (7:0) address 0x0D
Sandmanfunction, on-time SM_ON
Default value 0x00 00000000
Description On-time Sandmanfunction
Register (7:0) address 0x0E
Sandmanfunction, reference SMAD_REF
Default value 0x00 00000000
Description Reference amplitude Sandmanfunction
Register (7:0) address 0x0F
Sandmanfunction, reference SMDA _REF
Default value 0x00 00000000
Description Reference amplitude Sandmanfunction
D0311-116
Datasheet XE3005/XE3006
Mechanical Information
XE3005 package size (TSSOP20)
index
detail
DIMENSIONS original ensions) UNIT max. 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50
0.13
Figure TSSOP20 Plastic Thin Shrink Small Outline Package, leads, body width:
D0311-116
Datasheet XE3005/XE3006
XE3005 package size (5x4 uCSP®)
SIDE VIEW
PACKAGE OUTLINE XE300 uCSP XE3005
XEMICS XE3005
VIEW Nominal dimensions sion
BOTTOM VIEW
0.31
0.46
0.37
2.745 0.075
1.95
3.225 0.125
2.40
0.65
0.60
0.325 0.075 0.125
Figure uCSP® Ultra Chip Scale Package, balls array.
D0311-116
Datasheet XE3005/XE3006
XE3006 Package size (TSSOP24)
index
detail
DIMENSIONS originadimensions) UNIT max. 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50 0.13
Figure TSSOP24 Plastic Thin Shrink Small Outline Package with leads body width
D0311-116
Datasheet XE3005/XE3006
XE3005 Land pattern recommendations (5x4 uCSP®)
0.25 0.25 PASTE_MASK SOLDER_MASK 0.35
LAND PATTERN RECOMMENDATION PATT XE3005 uCSP
PLACEMENT OUTLINE
Nominal dimensions sion
2.82
3.35
0.65
0.60
0.325
Figure Land pattern recommendations (5x4 uCSP®)
©XEMICS, 2003 rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent other industrial intellectual property rights. XEMICS PRODUCTS DESIGNED, INTENDED, AUTHORIZED WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION XEMICS PRODUCTS SUCH APPLICATIONS UNDERSTOOD UNDERTAKEN SOLELY CUSTOMER'S RISK. Should customer purchase XEMICS products such unauthorized application, customer shall indemnify hold XEMICS officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs damages attorney fees which could arise.
D0311-116

VSSD VSSA VSSA VREF VREG11 VREG16 Microphone Bias XE3006

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