VSSD VSSA VSSA Power supply management RESET VDDPA XE30
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Data Sheet XE3004
VSSD VSSA VSSA
Power supply management
RESET VDDPA
XE3004
Power amplifier
AOUTP AOUTN VSSPA
Serial Audio Interface
Clock
MOSI BCLK FSYNC
MCLK
XE3004
Low-Power
General Description
XE3004 ultra low-power Digital Analog Converter voice audio applications. includes 16-bit DAC, serial audio interface, power management clock management. sampling frequency adjusted from kHz.
Features
Ultra low-power consumption, below Low-voltage operation down Single supply voltage Adjustable sampling frequency: Digital format: complement Easy interfacing various DSPs Direct connection speaker Various programming options
Quick Reference Data Applications
Wireless speakers Digital audio playback Consumer electronics Multimedia applications Battery-operated portable audio devices Supply voltage Typ. current (@1.8V, fs=20 kHz) Sampling frequency Typical dynamic range
Ordering Information
Part XE3004 Package TSSOP pins Temperature range
Cool Solutions Wireless Connectivity
XEMICS e-mail: info@xemics.com web: www.xemics.com
Data Sheet XE3004
Table contents
Device Description Terminal Description XE3004.3
Functional Description.4 Device Functions Power-Down Functions.8
Serial Communications.9 Serial Audio Interface.9 Register Programming Serial Peripheral Interface
Specifications Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics
Application Information Application Schematics XE3004.19
Register Description Register Functional Summary Register Definitions.20
Mechanical Information
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Data Sheet XE3004
Device Description
MCLK NRESET MOSI
BCLK FSYNC AOUTP VDDPA AOUTN
VSSA VSSA VSSD VSSPA
Figure layout XE3004 XE3004 available TSSOP16 package. Detailed information found chapter Mechanical Information.
Terminal Description XE3004
Terminals XE3004 Type Name MCLK NRESET VSSA VSSA VSSD VSSPA AOUTN VDDPA AOUTP FSYNC BCLK MOSI ZI/O DI/O DI/O Description Master Clock. MCLK derives internal clock Slave Select Digital power supply Reset signal generated DAC. required, reset signal applied externally initialize internal registers Analog ground Analog ground Digital ground Power Amplifier Ground Analog Output negative Power Amplifier Supply Analog Output positive Serial audio interface Frame Synchronization Serial audio interface Clock Serial audio interface Data Input Serial Clock Master Slave
Note:
Analog Input Analog Output Digital Input Digital Output DI/O Digital Impedance Output internal Pull internal Pull Down ZI/O impedance
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Data Sheet XE3004
Functional Description
XE3004 typically used digital audio converter voice audio applications interface between Digital Signal Processor (DSP) microcontroller analogue interface.
Power Amplifier Serial Audio Interface
Microcontroller
Digital wireless transmission Digital audio playback
Figure Typical usage This chapter provides brief description features. configuration defined programming registers through serial interface. detailed description registers found chapter digital voice audio samples passed through Serial Audio Interface.
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Data Sheet XE3004
2.1.1
Device Functions
Signal Channel
based multi sigma-delta modulator, which operates frequency times sampling rate. outputs modulator complement words bit. pulse-width modulator (PWM) converts words into single streams times sampling frequency. Finally streams supplied power amplifier. Power Amplifier Class amplifier, which offers higher efficiency than traditional Class topologies. uses three-state unbalanced PWM. This means that both channels (AOUTP AOUTN) will switch same time, therefore outputs purely differential (see figure
XE3004
VDDPA
From Serial Audio Interface
Interpolator Modulator
Pulse Width Modulator
pwm_in(5:0) 8xFsync
Power Amplifier
AOUTP
streams 256xFsync
dac_in(15:0) Fsync
AOUTN
VSSPA
Figure block diagram Figure shows relation input output samples (The timing diagram scale time-axis).
VDDPA VSSPA -VDDPA
pwm_in(5:0)
pwm_in(5:0)
pwm_in(5:0)
pwm_in(5:0)
1/(256 Fsync) OUTP-OUTN
1/(256 Fsync)
1/(8 Fsync)
2/(256 Fsync)
Figure examples (not scale) receives 16-bit wide complement format through Serial Audio Interface. protocol selected through register complete amplifier chain powered-down through register
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Data Sheet XE3004 2.1.2 Operating Frequency
master clock (MCLK) applied DAC. clock frequency signal applied MCLK vary between 1.024 minimum 33.9 maximum. maximum internal clock signal frequency (MCLK/div_factor) should exceed 12.288 MHz. div_factor user register default value div_factor `1'. 2.1.3 Serial Audio Interface
Serial Audio Interface 3-wire interface. operates serial clock BCLK frame synchronization signal FSYNC. sampling frequency corresponds rate which Audio Serial Interface will succeeding frames. frame always corresponds sample. frame always contains channels. Synchronizing Serial Audio Interface MCLK recommended. FSYNC MCLK must have fixed ratio defined following relation: FSYNC Sampling frequency frame rate MCLK/(256 div_factor).
BCLK defines time when data must presented serial audio interface shifted into (pin SDI) DAC. number BCLK periods FSYNC period user select first clock cycles (channel second clock cycles (channel BLCK shift data samples. table below shows some examples relationships between MCLK, BCLK FSYNC MCLK 2048 8192 5120 22579.2 Div_factor BCLK 1411.2 FSYNC 44.1
table below shows possible functional configurations serial audio interface master slave supported protocol (Long Frame Sync) LFS, Optimization (Short Frame Sync)
default Serial Audio Interface operates slave, mode. slave mode user needs generate signals BLCK, FSYNC supply DAC. master mode generates BLCK FSYNC signals. that case BLCK operates times frequency FSYNC. master mode used with protocol only. register used different setups serial audio interface.
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Data Sheet XE3004
2.1.4
Serial Peripheral Interface
interface used control register values. serial communications interface that independent rest DAC. allows device communicate synchronously with microprocessor DSP. interface only implements slave controller. detailed description found chapter Serial Communication.
2.1.5
Start-up Initialization
generates power reset signal after power supply connected pin. reset signal made available user NRESET. rising edge NRESET indicates that startup sequence finished. most applications NRESET left open. NRESET signal generated used initialize various blocks device guarantees correct start-up circuit. start-up sequence that automatically carried upon power-up device listed below illustrated Figure NRESET (0V) when device powered remains short time when (upper curve Figure applied. state sustains while VDD, VREF stabilizing. VERF internal signal only. soon MCLK signal present, counter activated that counts periods MCLK. After this moment NRESET high state (VDD).
1.8.3.3V
VREF* 1.2V
time internal signal only
MCLK
1024 (MCLK=2.048 kHz)
NRESET
main reset
Figure Startup sequence NRESET signal after power-on.
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Data Sheet XE3004
user NRESET different ways combinations: Leave NRESET connected. this case will startup described figure NRESET output indicate, e.g. microcontroller, that finished power NRESET force re-initialization registers their default values. this case user force NRESET least periods MCLK. circuit which forces NRESET should able sink least Figure shows block diagram reset.
reset analog digital circuitry codec
Power Reset XE3004
delay delay counter MCLK drive buffer
NRESET
Figure reset circuitry
2.2.1
Power-Down Functions
Software Power-Down
Register allows power down through control. wake-up time, after powering down device typically 200µs. maximum standby current 96µA, depending highly upon Master clock (MCLK), 4.3.3 Power Consumption. 2.2.2 Hardware Power-Down
device power-down pin. However, holding down NRESET (resetting device) well pins MCLK, BCLK FSYNC, power consumption will reach standby current typically 16µA. standard procedure power (see start-up initialization procedure) after hardware power down apply your registers setup procedure.
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Data Sheet XE3004
Serial Communications
Serial Audio Interface
Serial Audio Interface 3-wire interface communication audio data. terminals listed below: BCLK: FSYNC: SDI: serial clock, clock cycle corresponds data transmitted received. Frame Synchronization. This signal indicates start data word. frequency FSYNC corresponds sample frequency DAC. Serial Data data received from external device sent DAC.
clock (BCLK) synchronization (FSYNC) signals used receiving audio data. synchronization signal FSYNC must have fixed ratio with master clock signal MCLK. Serial Audio Interface supports formats that commonly used that referred (Short Frame Synchronization) (Long Frame Synchronization). Data received channels. Which channel selected depends programmed values registers. interface protocols shown below.
FSYNC BCLK
channel sample
channel data
channel sample
n+115
Figure Audio interface timing mode, channel
FSYNC BCLK
channel sample
channel sample
channel sample
n+115
Figure Audio interface timing mode, channel
Data should changed rising edge BCLK. data will read falling edge BLCK. Each rising edge FSYNC indicates start sample.
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Data Sheet XE3004
3.1.1
optimization
receiving, clock cycles frame always required (figure This even case when only bits have received. most cases this easily handled with microcontroller. user wants send minimum BLCK cycles, possible shorten channel (channel shortened). mode, possibility exists shorten number BLCK cycles instead this case data received channel Channel shortened BLCK cycle only. Note! This optimization possible slave mode only. figure below shows this special mode.
channel data channel data channel sample channel sample
FSYNC BCLK
Figure Audio interface timing mode,17 BLCK cycles, channel
Register Programming
control registers define configuration define various modes operation. During power-up, registers will configured with default values. control register consists registers. detailed description provided chapter Register Description. control registers changed following ways: Logic values pins during power-up There bits inside registers which configured depending logic values pins MOSI during power startup sequence described chapter 2.1.5
Value power MOSI
Influenced bits registers Register I(0)=0 Register I(0)=1 Register J(0)=1 Register J(0)=0
comments MCLKDIV division MCLKDIV division protocol protocol
Using pins startup user able configure corresponding setups without reprogramming through interface protocol. best case interface then completely omitted pins fixed `1'.
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Data Sheet XE3004
Programming through interface after power-up Once device been powered configuration registers modified times (also when device active) through interface. following section describes protocol which required change control registers from their default values.
Serial Peripheral Interface
serial peripheral interface (SPI) allows device communicate synchronously with other devices such microprocessor DSP. interface only implements slave controller. This section describes communication from master (e.g. DSP) slave (DAC MOSI). Three lines used transmit data between slave master: MOSI (Master Out, Slave data from master slave, synchronous with clock (SCK). (Serial Clock) synchronizes data bits MOSI MISO. (Slave Select) Slave devices selected activating
3.3.1
Protocol
master puts data MOSI line falling edge SCK; slave reads data rising edge SCK. Transmission bytes with first. should kept during whole transfer data.
trecovery
MOSI
1/Fsck
tdisable
Figure signal timing
There three timing constraints: Recovery time recovery) between falling edge falling edge SCK. Disable time disable) between last rising edge rising edge frequency (FSCK)
Delay recover disable
Tmaster
Fmaster
Unit
Comments Tmaster clock period master clock MCLK Fmaster frequency master clock MCLK
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Data Sheet XE3004
3.3.2
Interface Modes
There only mode: write. 3.3.2.1 Write Mode
Write communication always takes place pairs bytes. format bytes
mosi mosi
D(7:0)
A(4:0)
mosi
request (write address A(4:0))
write data D(7:0) address A(4:0)
Figure signal timing write mode
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Data Sheet XE3004
Specifications
Absolute Maximum Ratings
Stresses above those listed following table cause permanent failure. Exposure absolute ratings extended periods affect device reliability. values accordance with Absolute Maximum Rating System (IEC 134). voltages referenced ground (VSSA VSSD). Analog digital grounds equal (VSSA VSSD). Symbol Parameter Conditions Unit Supply voltage -0.3 3.65 Tstg Storage temperature Operating free-air temperature, Electrostatic discharge protection Ilus Static latchup current Vlud Dynamic latchup voltage Tested according MIL883C Method 3015.6, class JEDEC (Standardized Human Body Model: 1500 pulses, protection related substrate). Static dynamic latchup values valid
Recommended Operating Conditions
voltages referenced ground (VSSA VSSD). 1.024 Unit
Supply voltage, Differential output load resistance Master clock frequency conversion rate Operating free-air temperature,
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Data Sheet XE3004
Electrical Characteristics
operating conditions this section are: 25°C. 4.3.1 Digital Inputs Outputs, FSYNC kHz, output loaded Parameter High-level output voltage, DOUT Low-level output voltage, DOUT High-level input current, digital input Low-level input current, digital input Input capacitance Output capacitance Test Conditions -360µA VSSD-0.5 VDD+0.5 Unit
4.3.2
Dynamic Performance, load filter
FSYNC kHz, MCLK MHz. Parameter Signal-to-noise ratio Total harmonic distortion Dynamic range Group delay Test Conditions Bandwidth full scale Bandwidth FSYNC Unit
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Data Sheet XE3004
4.3.3 4.3.3.1
Power Consumption power mode
Stand-by mode 3.0V, 25°C Parameter Istb1 Istb2 Istb3 Supply current standby mode Supply current standby mode Supply current standby mode Test Conditions
MCLK MHz, MCLK 12.2880 NRESET mode MCLK
Unit
Stand-by mode 1.8V, 25°C Parameter Istb1 Istb2 Istb3 Supply current standby mode Supply current standby mode Supply current standby mode Test Conditions
MCLK MHz, MCLK 12.2880 NRESET mode MCLK
Unit
4.3.3.2
Normal operation, output load consumption included.
Normal operations 3.0V, FSYNC kHz, 25°C, Register C(7:0) 0xF0 Parameter IDAC Supply current Test Conditions
FSYNC kHz, load
Unit
Normal operations 3.0V, FSYNC kHz, 25°C, Register C(7:0) 0xC4 Parameter IDAC Supply current Test Conditions
FSYNC kHz, load
Unit
Normal operations 1.8V, FSYNC kHz, 25°C, Register C(7:0) 0xF0 Parameter IDAC Supply current Test Conditions
FSYNC kHz, load
Unit
Normal operations 1.8V, FSYNC kHz, 25°C, Register C(7:0) 0xC4 Parameter IDAC Supply current Test Conditions
FSYNC kHz, load
Unit
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Data Sheet XE3004
4.3.4
Ref.
Timing Requirements serial audio interface
Test Conditions
Characteristics Master Clock Frequency MCLK
MCLK Duty Cycle Rise Time Digital Signals Fall Time Digital Signals Hold time BCLK FSYNC high after MCLK Setup time BCLK FSYNC high MCLK Hold time BCLK FSYNC after MCLK Setup time BCLK FSYNC MCLK
1024
5.12
Unit
CLoad 10pF
32xFSYNC TBCLK/4 TBCLK/4 applicable TBCLK/4 TBCLK/4
MCLK/2
Clock Frequency BCLK TBCLK
Setup time data input BCLK Hold time data input after BCLK Delay time valid after BCLK high Setup time data input FSYNC BCLK Hold time data input FSYNC after BCLK
*see figure
4.3.4.1
Timing diagram serial audio interface mode
MCLK BCLK FSYNC
Figure mode, timing diagram
MCLK BCLK FSYNC
Figure Timing diagram serial audio interface mode
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Data Sheet XE3004 4.3.4.2 Timing diagram serial audio interface mode
MCLK BCLK FSYNC
Figure mode, timing diagram
MCLK BCLK FSYNC
Figure mode, zoom timing diagram
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Data Sheet XE3004
4.3.5
Timing Requirements Serial Peripheral Interface
Ref.
Characteristics Serial Clock Frequency TSCK
MCLK Duty Cycle Recovery Time Disable Time Setup time MISO valid high Hold time MISO valid after high Delay time MOSI valid after
Test Conditions
MCLK/2
CLoad 10pF
applicable applicable TSCK/4
Unit
figure
Figure Serial Peripheral Interface timing
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Data Sheet XE3004
Application Information
Application Schematics XE3004
Master Clock
MCLK NRESET
MOSI
BCLK FSYNC AOUTP VDDPA AOUTN
0.1µF
Serial Audio Interface 2µ2F 4µ7F R=56
VSSA VSSA VSSD VSSPA
0.1µF
L=680µH
lowpass filter, Bluetoothvoice application MCLK 2.048 MHz, div_factor
Figure Typical Application with order output Filter
pass filter between output speaker depends settings speaker type.
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Data Sheet XE3004
Register Description
Register Functional Summary
following registers programmed configure operation modes. also chapter Register Programming. Name Register Description Function enable clock division. data this register following functions: Division master clock Enable/disable channel (DAC, power amplifier) Audio Interface Configuration. data this register following functions: Channel select receive Select master slave mode Output impedance Channel select transmit Select short long frame sync
Register
Register Definitions
complete register setup consists registers bits each, shown table below. registers preconfigured with default values have programmed user changes setup required. registers used configure XE3004 differently than default setup.
Register
Address (hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Block on/off clock division Audio interface configuration Reserved
Default value (hex) 0x48 0x8F 0xF0 0x00 0x0x 0x82 0x00 0x00 0x00/0x01 0x25/0x24 0x00
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Data Sheet XE3004
Register (7:0) address 0x08
block on/off clock division EN_DAC
Default value 0x00/0x01 0000
Description reserved enable disable converter (DAC reserved Division factor master clock: reserved
default depending logic value during startup (see Section 3.2) SS=0, default will SS=1, default will
MCLKDIV
Register (7:0) address 0x09
Audio interface configuration
RX_FIRST_ SECOND
Default value 0x25/ 0x24
Description
reserved MASTER
PROTOCOL
reserved Receive audio data first 16-bit channel after frame synchronization. Receive audio data second 16-bit channel after frame synchronization. reserved enable audio interface master mode (only LFS) enable audio interface slave mode (LFS, Optimization SFS) reserved reserved reserved Short Frame Synchronization mode (slave mode). Long Frame Synchronization mode (master slave mode).
default depending logic value during startup (see Section 3.2) SCK=0, default will SCK=1, default will
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Data Sheet XE3004
Mechanical Information
index
detail
DIMENSIONS original ensions UNIT max. 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50 0.13 0.40 0.06
Figure TSSOP16: Plastic Thin Shrink Small Outline Package, leads, body width:
©XEMICS, 2003 rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent other industrial intellectual property rights. XEMICS PRODUCTS DESIGNED, INTENDED, AUTHORIZED WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION XEMICS PRODUCTS SUCH APPLICATIONS UNDERSTOOD UNDERTAKEN SOLELY CUSTOMER'S RISK. Should customer purchase XEMICS products such unauthorized application, customer shall indemnify hold XEMICS officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs damages attorney fees which could arise.
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