VSSD VSSA VREG11 VREG16 VREF Microphone Bias Power supp

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VSSD VSSA VREG11 VREG16 VREF Microphone Bias Power supp

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Data Sheet XE3003
VSSD VSSA VREG11 VREG16
VREF
Microphone Bias
Power supply management
RESET
Amp.
modulator
Decimator
XE3003
Serial Audio Interface
Clock
MISO MOSI
BCLK FSYNC MCLK
XE3003
Low-Power Audio
General Description
XE3003 ultra low-power (Analog Digital Converter) voice audio applications. includes microphone supply, programmable preamplifier, 16-bit ADC, Serial Peripheral Interface (SPI), serial audio interface (PCM) well power clock management ADC. sampling frequency adjusted from kHz.
Features
Ultra low-power consumption, below Low-voltage operation down Single supply voltage Adjustable sampling frequency: Digital format: complement Only minimum external components Easy interfacing various DSPs Direct connection microphone Various programming options
Applications
Wireless Microphones Bluetoothheadset Hands-free telephony Digital hearing instruments Consumer multimedia applications battery-operated portable audio devices
Quick Reference Data
Supply voltage range 1.8- Typ. current (@3V kHz) 0.24 Sampling frequency range Typical dynamic range Typ. power supply rejection
Ordering Information
Part XE3003 Package TSSOP pins Temperature range
Cool Solutions Wireless Connectivity
XEMICS e-mail: info@xemics.com web: www.xemics.com
Data Sheet XE3003
Table contents
Device Description.3 Terminal Descriptions XE3003 Functional Description Device Functions Power-Down Functions.8 Serial Communications Serial Audio Interface.9 Register Programming Serial Peripheral Interface Specifications.13 Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Application Information.20 Application Schematics XE3003.20 Register Description.21 Register Functional Summary Register Definitions.22 Mechanical Information.24 XE3003 package size (TSSOP16)
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Data Sheet XE3003
Device Description
MCLK NRESET VREG16 VREF VSSA VSSD VREG11 MOSI MISO BCLK FSYNC
Figure layout XE3003 XE3003 available TSSOP16 package. Detailed information found section Mechanical Information.
Terminal Descriptions XE3003
Terminals
XE3006 Name
Type MCLK NRESET VREG16 VREF VSSA VSSD VREG11 FSYNC BCLK MISO MOSI ZI/O DI/O DI/O
Description Master Clock. MCLK derives internal clock ADC. Digital power supply Reset signal generated ADC. required, reset signal applied externally initialize internal registers. Regulator voltage used supply microphone. Reference voltage Analog ground Digital ground Regulated microphone output supply voltage Analog input signal Serial audio interface Frame Synchronization Serial audio interface Clock Serial audio interface Data Output Master Slave Serial Clock Slave Select Master Slave
Note:
Analog Input Analog Output Digital Input Digital Output DI/O Digital Impedance Output internal Pull internal Pull Down ZI/O impedance
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Data Sheet XE3003
Functional Description
XE3003 typically used audio converter voice audio applications between Digital Signal Processor (DSP) analogue interface microphone.
MIC-Amplifier
Serial Audio Interface
Microcontroller
Digital wireless transmission Voice recognition speech synthesis
Figure Typical usage XE3003 This chapter provides brief description audio features. configuration defined programming registers through serial interface. detailed description registers defining details setup found sections Digital audio samples passed through Serial Audio Interface further processing DSP.
2.1.1
Device Functions
Signal Channel
channel chain programmable amplifier, band-pass filter, sigma-delta modulator decimation filter. amplifier gain programmable (default) 20x. band-pass filter cut-off frequencies proportional sampling rate. sigma-delta modulator operates frequency times sampling rate. analog modulator followed digital decimation filter. digital output data bits, complement format) made available through Serial Audio Interface. format Serial Audio interface selected through register With default register settings, sampling frequency kHz. When used with sampling frequency higher than kHz, then register changed. whole chain powered-down through register further details about configuring section Register Description.
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Data Sheet XE3003
2.1.2
Input
programmable pre-amplifier microphone bias sources VREG11 VREG16 optimized operate with electret microphones. VREG11 provides reference voltage. VREG11 deliver VREG11 enabled through control register VREG16 regulated voltage typically deliver mA.VREG16 always enabled.
MCLK
0.1µF
NRESET VREG16 VREF VSSA VSSD VREG11
390k
(gain (gain
Figure Typical microphone interface (1.1 50µA bias through VREG11)
MCLK
0.1µF
NRESET VREG16 VREF VSSA VSSD VREG11
390k
(gain (gain
depends microphone type
Figure Typical microphone interface (1.6 max. bias through VREG16)
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Data Sheet XE3003
2.1.3
Operating Frequency
master clock (MCLK) applied XE3003. clock frequency signal applied MCLK vary between 1.024 minimum 33.9 maximum. maximum internal clock signal frequency (MCLK/div_factor) should exceed 12.288 MHz. div_factor user register default value div_factor `1'. 2.1.4 Serial Audio Interface
Serial Audio Interface 3-wire interface communication audio data. operates serial clock BCLK frame synchronization signal FSYNC. sampling frequency corresponds rate which Audio Serial Interface will succeeding frames. frame always corresponds sample. frame always contains channels. Synchronizing Serial Audio Interface MCLK recommended. FSYNC MCLK must have fixed ratio defined following relation: FSYNC Sampling frequency frame rate MCLK/(256 div_factor). BCLK defines time when data must shifted (pin SDO) ADC. number BCLK periods FSYNC period user select first clock cycles (channel second clock cycles (channel BLCK shift data samples. table below shows some examples relationships between MCLK, BCLK FSYNC MCLK 2048 8192 5120 22579.2 Div_factor BCLK 1411.2 FSYNC 44.1
table below shows possible functional configurations serial audio interface master slave supported protocol (Long Frame Sync) LFS, Optimization (Short Frame Sync)
default Serial Audio Interface operates slave, mode. slave mode user needs generate signals BLCK, FSYNC supply ADC. master mode generates BLCK FSYNC signals. that case BLCK operates times frequency FSYNC. master mode used with protocol only. register used different setups serial audio interface.
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Data Sheet XE3003
2.1.5
Serial Peripheral Interface
interface used control register values. serial communications interface that independent rest ADC. allows device communicate synchronously with microprocessor DSP. interface only implements slave controller. detailed description found section 3.3.
2.1.6
Start-up Initialization
generates power reset signal after power supply connected pin. reset signal made available user NRESET. rising edge NRESET indicates that startup sequence finished. most applications NRESET left open. NRESET signal generated used initialize various blocks device guarantees correct start-up circuit. start-up sequence that automatically carried upon power-up device listed below illustrated Figure NRESET (0V) when device powered remains short time when (upper curve Figure applied. state sustains while VDD, VREG16, VREF stabilizing. soon MCLK signal present, counter activated that counts periods MCLK. After this moment NRESET high state (VDD).
1.8.3.3V VREG16 1.6V
VREF 1.2V
time
MCLK
1024 (MCLK=2.048KHz) NRESET main reset
Figure Startup sequence NRESET signal after power-on.
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Data Sheet XE3003
user NRESET different ways combinations: Leave NRESET connected. this case will startup described figure NRESET output indicate, e.g. microcontroller, that finished power sequence that ready operate. NRESET force re-initialization registers their default values. this case user force NRESET least periods MCLK. circuit which forces NRESET should able sink least Figure shows block diagram CODEC reset.
reset analog digital circuitry
Power Reset
delay delay counter MCLK XE3003 drive buffer
NRESET
Figure reset circuitry
2.2.1
Power-Down Functions
Software Power-Down
Register allows selective power down signal channel. wake-up time, after powering down device typically 200µs. maximum standby current 96µA, depending highly upon Master clock (MCLK), 4.3.4.2 Power Modes. 2.2.2 Hardware Power-Down
device power-down pin. However, holding down NRESET (resetting device) well pins MCLK, BCLK FSYNC, power consumption will reach standby current typically 16µA. standard procedure power (see start-up initialization procedure) after hardware power down registers setup procedure must applied.
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Data Sheet XE3003
Serial Communications
Serial Audio Interface
Serial Audio Interface 3-wire interface communication audio data. terminals listed below: BCLK: FSYNC: SDO: serial clock, clock cycle corresponds data transmitted received. Frame Synchronization. This signal indicates start data word. frequency FSYNC corresponds sample frequency ADC. Serial Data Out, data received from sent external device.
clock (BCLK) synchronization (FSYNC) signals used sending audio data. synchronization signal FSYNC must have fixed ratio with master clock signal MCLK. Serial Audio Interface supports formats that commonly used audio/voice ADCs that referred (Short Frame Synchronization) (Long Frame Synchronization). Data transmitted channels. Which channel selected depends programmed values registers. interface protocols shown below.
FSYNC BCLK
channel sample
channel data
channel sample
n+115
Figure Audio interface timing mode, channel
FSYNC BCLK
channel sample
channel sample
channel sample
n+115
Figure Audio interface timing mode, channel
data will change rising edge BCLK. data should read falling edge BLCK. Each rising edge FSYNC indicates start sample.
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Data Sheet XE3003
3.1.1
optimization
receiving, clock cycles frame always required (figure This even case when only bits have received. most cases this easily handled with microcontroller. user wants send minimum BLCK cycles, possible shorten channel (channel shortened). mode possibility exists shorten number BLCK cycles instead this case data received channel Channel shortened BLCK cycle only. Note! This optimization possible slave mode only. figure shows this special mode.
channel data channel data channel sample channel sample
FSYNC BCLK
Figure Audio interface timing mode, BLCK cycles, channel
Register Programming
control registers define configuration define various modes operation. During powerup, registers will configured with default values. control register consists registers. detailed description provided section control registers changed following ways: Logic values pins during power-up There bits inside registers which configured depending logic values pins MOSI during power startup sequence described section 2.1.6.
Value power MOSI MOSI
Influenced bits registers Register I(0)=0 Register I(0)=1 Register J(0)=1 Register J(0)=0 Register E(2) Register E(2)
comments MCLKDIV division MCLKDIV division protocol protocol preamplifier gain preamplifier gain
Using pins startup, user able configure corresponding setups without reprogramming through interface protocol. best case interface then completely omitted pins fixed `1'.
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Data Sheet XE3003
Programming through interface after power-up Once device been powered configuration registers modified times (also when device active) through interface. following section describes protocol which required change control registers from their default values.
Serial Peripheral Interface
Serial Peripheral Interface (SPI) allows device communicate synchronously with other devices such microprocessor DSP. interface only implements slave controller. This section describes communication from master (e.g. DSP) slave (ADC MOSI) from slave (ADC MISO) master (e.g. DSP). Four lines used transmit data between slave master: MOSI (Master Out, Slave data from master slave, synchronous with clock (SCK). MISO (Master Slave Out) data from slave master, synchronous with clock (SCK). (Serial Clock) synchronizes data bits MOSI MISO. (Slave Select) Slave devices selected activating
3.3.1
Protocol
During communication, data simultaneously transmitted received.
trecovery
MOSI MISO
1/Fsck
tdisable
Figure signal timing master puts data MOSI line falling edge SCK; slave reads data rising edge SCK. slave puts data MISO line falling edge SCK; master reads data rising edge SCK. Transmission either direction bytes with first. should kept during whole transfer data. There three timing constraints: Recovery time recovery) between falling edge falling edge SCK. Disable time disable) between last rising edge rising edge frequency (FSCK)
Delay recover disable
Tmaster
Fmaster
Unit
Comments Tmaster clock period master clock MCLK Fmaster frequency master clock MCLK
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Data Sheet XE3003
3.3.2
Interface Modes
There modes: read write. 3.3.2.1 Read Mode
Read communication always takes place pairs bytes. read request bytes sent MOSI line. content addressed register, byte, dumped MISO line during transmission second byte MOSI. formats byte following: mosi miso D(7:0) (4:0)
mosi
request (read <address A(4:0)>)
miso
read data D(7:0) address A(4:0)
Figure signal timing read mode 3.3.2.2 Write Mode
Write communication always takes place pairs bytes. format bytes
mosi mosi
D(7:0)
A(4:0)
mosi
request (write address A(4:0))
write data D(7:0) address A(4:0)
Figure signal timing write mode
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Data Sheet XE3003
Specifications
Absolute Maximum Ratings
Stresses above those listed following table cause permanent failure. Exposure absolute ratings extended periods affect device reliability. values accordance with Absolute Maximum Rating System (IEC 134). voltages referenced ground (VSSA VSSD). Analog digital grounds equal (VSSA VSSD). Symbol Parameter Conditions Unit Supply voltage -0.3 3.65 Tstg Storage temperature Operating free-air temperature, Electrostatic discharge protection Ilus Static latchup current Vlud Dynamic latchup voltage Tested according MIL883C Method 3015.6, class JEDEC (Standardized Human Body Model: 1500 pulses, protection related substrate). Static dynamic latchup values valid
Recommended Operating Conditions
voltages referenced ground (VSSA VSSD). 1.024 Unit
Supply voltage, Analog signal peak input voltage, (gain 20x) Analog signal peak input voltage, (gain Differential output load resistance Master clock frequency conversion rate Operating free-air temperature,
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Data Sheet XE3003
Electrical Characteristics
operating conditions this section are: 25°C. 4.3.1 Digital Inputs Outputs, FSYNC kHz, output loaded Parameter High-level output voltage, DOUT Low-level output voltage, DOUT High-level input current, digital input Low-level input current, digital input Input capacitance Output capacitance Test Conditions -360uA VSSD-0.5 VDD+0.5 Unit
4.3.2
Dynamic Performance, FSYNC Parameter Test Conditions
Pre-amp gain Vin=250mV (full scale)
Unit
Signal-to-noise ratio Total harmonic distortion cut-off frequency dB), Note High cut-off frequency dB), Note Group delay
full scale FSYNC FSYNC FSYNC
Note proportional FSYNC Note equals FSYNC/2 4.3.3 Channel Characteristics, FSYNC Parameter Peak input voltage (single ended) Test Conditions Pre-amp gain Pre-amp gain
A-weighted, Hz-10 pre-amp gain A-weighted, Hz-10 pre-amp gain Pre-amp gain Vin=250mV (full scale)
Unit
Vneq
Equivalent input noise Dynamic range
MOhm
PSRR Power supply rejection ratio, input referred Input capacitor Input resistance VSSA gain error offset error input noise Integral linearity Differential linearity
Preamp-gain Preamp gain 1.8-3.3V 1.8-3.3V 1.8-3.3V 1.8-3.3V 1.8-3.3V
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Data Sheet XE3003
4.3.4 4.3.4.1
Power Supply Regulated supply characteristics 25°C Parameter VREF reference Voltage regulated Voltage 1.1V available current output impedance regulated Voltage 1.6V available output current power supply rejection ratio, input referred power supply rejection ratio, input referred power supply rejection ratio, input referred capacitor Test Conditions capacitor 390k resistor Unit kOhm
VREG11 I_vreg11 R_vreg11 VREG16 I_vreg16 VREF PSRR VREG11 PSRR VREG16 PSRR 4.3.4.2
power mode
Stand-by mode 3.0V, 25°C Parameter Istb1 Istb2 Istb3 Supply current standby mode Supply current standby mode Supply current standby mode Test Conditions
off, MCLK MHz, off, MCLK 12.2880 NRESET mode MCLK
Unit
Stand-by mode 1.8V, 25°C Parameter Istb1 Istb2 Istb3 Supply current standby mode Supply current standby mode Supply current standby mode Test Conditions
off, MCLK MHz, off, MCLK 12.2880 NRESET mode MCLK
Unit
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Data Sheet XE3003
4.3.4.3
Normal operation
Normal operations 3.0V, FSYNC kHz, 25°C, Register C(7:0) 0xF0 Parameter IADC Supply current Test Conditions
FSYNC
Unit
Normal operations 3.0V, FSYNC kHz, 25°C, Register C(7:0) 0xC4 Parameter IADC Supply current Test Conditions
FSYNC
1200
Unit
Normal operations 1.8V, FSYNC kHz, 25°C, Register C(7:0) 0xF0 Parameter IADC Supply current Test Conditions
FSYNC
Unit
Normal operations 1.8V, FSYNC kHz, 25°C, Register C(7:0) 0xC4 Parameter IADC Supply current Test Conditions
FSYNC
1010
Unit
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Data Sheet XE3003
4.3.5
Ref.
Timing Requirements serial audio interface
Test Conditions
Characteristics Master Clock Frequency MCLK
MCLK Duty Cycle Rise Time Digital Signals Fall Time Digital Signals Hold time BCLK FSYNC high after MCLK Setup time BCLK FSYNC high MCLK Hold time BCLK FSYNC after MCLK Setup time BCLK FSYNC MCLK
1024
5.12
Unit
CLoad 10pF
32xFSYNC MCLK/2 applicable applicable TBCLK/4 TBCLK/4 TBCLK/4
Clock Frequency BCLK TBCLK
Setup time data input BCLK Hold time data input after BCLK Delay time valid after BCLK high Setup time data input FSYNC BCLK Hold time data input FSYNC after BCLK
*see figure 13,14 mode
4.3.5.1
Timing diagram serial audio interface mode
MCLK BCLK FSYNC
Figure mode, timing diagram
Figure mode, zoom timing diagram
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Data Sheet XE3003
4.3.5.2
Timing diagram serial audio interface mode
MCLK BCLK FSYNC
Figure mode, timing diagram
Figure mode, zoom timing diagram
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Data Sheet XE3003
4.3.6
Timing Requirements Serial Peripheral Interface
Ref.
Characteristics Serial Clock Frequency TSCK
MCLK Duty Cycle Recovery Time Disable Time Setup time MISO valid high Hold time MISO valid after high Delay time MOSI valid after
Test Conditions
TSCK/4 TSCK/4 TSCK/4
MCLK/2
CLoad 10pF
Unit
figure
MISO MOSI
Figure Serial Peripheral Interface timing
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Data Sheet XE3003
Application Information
5.1.1
Application Schematics XE3003
Typical Application schematic microphone bias through VREG11 (1.1
MCLK NRESET VREG16 VREF VSSA VSSD VREG11 MOSI MISO BCLK FSYNC
Master Clock
0.1µF
Serial Audio Interface
390k
Figure Typical Application with microphone bias through VREG11 (1.1V 50µA)
5.1.2
Typical Application schematic microphone bias through VREG16 (1.6
MCLK NRESET VREG16 VREF VSSA VSSD VREG11 MOSI MISO BCLK FSYNC
Master Clock
0.1µF
Serial Audio Interface
390k
depends microphone type
Figure Typical Application with microphone bias through VREG16 (1.6V max. 1mA)
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Data Sheet XE3003
Register Description
Register Functional Summary
following registers programmed configure operation modes. also section Register Programming. Name Register Description current setting. data this register following functions: Adjust current FSYNC 20kHz 0xF0 FSYNC<= kHz, 0xC4 FSYNC kHz. Analog Input. data this register following functions: Enable/disable microphone bias source Gain setting pre-amplifier. Function enable clock division. data this register following functions: Enable/disable channel (pre-amplifier, ADC, decimation filter) Division master clock Audio Interface Configuration. data this register following functions: Channel select receive Select master slave mode Output impedance Channel select transmit Select short long frame sync
Register
Register
Register
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Data Sheet XE3003
Register Definitions
complete register setup consists registers bits each, shown table below. registers preconfigured with default values have programmed user changes setup required. registers used configure XE3003 differently than default setup.
Register
Address (hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A
Name Reserved Reserved current Reserved Analog input Reserved Reserved Reserved Block on/off clock division Audio interface configuration Reserved
Default value (hex) 0x48 0x8F 0xF0 0x00 0x08/0x0C 0x82 0x00 0x00 0x00/0x01 0x25/0x24 0x00
Register (7:0) address 0x02
current current
Default value: 0xF0 0xF0
Description 0xF0 FSYNC<= kHz, 0xC4 FSYNC kHz.
Register (7:0) address 0x04
input VMIC_EN reserved PREAMP_ GAIN
Default value 0x08/0x0C 0001
Description Generation microphone supply VREG11: enables VREG11 disables VREG11 reserved Gain preamplifier: (280 peak) peak)
default depending logic value MOSI during startup (see section 3.2) MOSI=0, default will MOSI=1, default will
reserved
reserved
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Data Sheet XE3003
Register (7:0) address 0x08
block on/off clock division reserved EN_ADC MCLKDIV
Default value 0x00/0x01 0000
Description reserved reserved enable disable converter (Preamp decimator) Division factor master clock: reserved
default depending logic value during startup (see section Register Programming) SS=0, default will SS=1, default will
Register (7:0) address 0x09
Audio interface configuration reserved RX_FIRST_ SECOND reserved MASTER SDO_HI_EN
Default value 0x25/ 0x24
Description
TX_FIRST TX_SECOND PROTOCOL
reserved Receive audio data first 16-bit channel after frame synchronization. Receive audio data second 16-bit channel after frame synchronization. reserved enable audio interface master mode (only LFS) enable audio interface slave mode (LFS, Optimization SFS) continuously output mode both data channels. output mode when transmitting channel with data (J(2) J(1)=1). switched automatically into high-impedance state when channel with data transmitted (J(2) J(1)=0). transmit audio data first 16-bit channel after frame synchronization. transmit data first channel. transmit audio data second 16-bit channel after frame synchronization. transmit data second channel. Short Frame Synchronization mode (slave mode). Long Frame Synchronization mode (master slave mode).
default depending logic value during startup (see section Register Programming) SCK=0, default will SCK=1, default will
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Data Sheet XE3003
Mechanical Information
XE3003 package size (TSSOP16)
index
detail
DIMENSIONS original ensions UNIT max. 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50 0.13 0.40 0.06
Figure TSSOP16 Plastic Thin Shrink Small Outline Package; leads; body width
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Data Sheet XE3003
©XEMICS, 2003 rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent other industrial intellectual property rights. XEMICS PRODUCTS DESIGNED, INTENDED, AUTHORIZED WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION XEMICS PRODUCTS SUCH APPLICATIONS UNDERSTOOD UNDERTAKEN SOLELY CUSTOMER'S RISK. Should customer purchase XEMICS products such unauthorized application, customer shall indemnify hold XEMICS officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs damages attorney fees which could arise.
D0311-142

VSSD VSSA VREG11 VREG16 VREF Microphone Bias Power supp

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