WT65F4 with Flash Memory 12-bit Converter Data Sheet
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WT65F4 with Flash memory 12bit
WT65F4
with Flash Memory
12-bit Converter
Data Sheet
REV.1.00 Nov.18, 2001
information this document subject change without notice.
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WT65F4 with Flash memory 12bit
Table Content
5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 GENERAL DESCRIPTION FEATURES.1 PACKAGE INFORMATION.2 ASSIGNMENT DESCRIPTION.3 CONFIGURATION.5 FUNCTION DESCRIPTION WT65F4 MODULE MICROCONTROLLER ANALOG DIGITAL CONVERTER ).11 PULSE WIDTH MODULATION( ADPCM PUSH-PULL WT65F4 ADDRESS SPACE MAPPING.14 WT65F4 SPECIAL FUNCTION REGISTER ADDRESS SPACE EXTERNAL FUNCTION REGISTER ADDRESS SPACE.16 CLOCK UNIT RESET POWERDOWN MODE IDLE MODE.19 INTERRUPT.20 FUNCTION ENDPOINT TRANSMIT FIFOS TRANSMIT FIFOS FEATURES TRANSMIT DATA MANAGEMENT.23 TRANSMIT FIFO REGISTERS RECEIVE FIFOS.24 RECEIVE FIFO FEATURES RECEIVE DATA MANAGEMENT RECEIVE FIFO REGISTERS.26 SETUP TOKEN RECEIVE FIFO HANDLING SUSPEND RESUME MODE MODE NORMAL DOWNLOAD MODE EXTERRNAL FUNCTION REGISTERS TRAGERT SPECIFICATION.66
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Index Figures
Figure WT65F4 40-pin 28-pin package.5 Figure WT65F4 48-pin package Figure WT65F4 4General Block Diagram Figure Interface Block Diagram Figure Memory mapping Flash ROM, boot ROM, Figure Interface Diagram Figure Timing Diagram.12 Figure Output Waveform Diagram Figure ADPCM block diagram Figure Clock circuit when function used Figure Clock divided-by-2 circuit Figure Reset Signals Figure Block Diagram INT0 Figure WT65F4 interrupt circuit Figure Transmit FIFO outline.22 Figure Receive FIFO Outline Figure Suspend Resume State Diagram Figure Port circuit diagram.47 Figure External Clock Drive Waveform.67
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Index Tables
Table WT65F4 Package Types Table Descriptions.3 Table Interface Description.12 Table Addressing mapping Table WT65F4 Special Function Register layout.15 Table External Function Register layout.16 Table Internal clock generation Table Writing Byte Count Register Table Truth table transmit FIFO management.24 Table Status receive FIFO data set.26 Table Truth table receive FIFO management.26 Table Function Address Register FADDR, ).30 Table Interrupt Register USBI, Table board Interrupt Enable Register USBKAIIE, Table Interface Register SIE1, Table Endpoint Index Register EPINDEX, Table Endpoint Control Register EPCON, Table Speaker Watch-dog Timer Control Register SPWDCTL, Table Transmit FIFO Data Register TXDAT, Table Transmit FIFO Control Register TXCON, Table Transmit FIFO Flag Register TXFLG, Table Transmit FIFO Byte Count Register (TXCNT, Table Endpoint Transmit Status Register TXSTAT, ).43 Table PWM0 Duty Control Register PWM0, Table PWM1 Duty Control Register PWM1, ).46 Table Port2 Current Control Register P2ODCTL, Table program control Register ISP_CTL, Table Address byte Register ISPADDL, Table Address high byte Register ISPADDH, Table program data Register ISPDATA, Table function control Register ADPWM_C, Table Clock Control Register ADCLK, Table borad Interrupt Register KYADI, Table Receive FIFO Data Register RXDAT, Table Receive FIFO Control Register RXCON, ).56
Table Receive FIFO Flag Register RXFLG, ).57
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Table Receive FIFO Byte Count Register RXCNT, ).59 Table Endpoint Receive Status Register RXSTAT, ).60 Table Lower Byte Data Register ADL, Table Higer Byte Data Register ADH, ).64 Table Push-pull speaker output envelope SPKENV0, Table Push-pull speaker output envelope SPKENV1, Table Electrical Characteristics.66 Table Absolute Maximum Rating Table Electrical Characteristics.6
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General Description
WT65F4 single chip Micro-controller with speed Universal Serial (USB) functions. includes 8-bit 8051 core, bytes SRAM, Bytes Flash memories, boot/ICE ROM, Programmable I/O. Build-in function suitable UPS, touch pad, joystick digital board application.
Features
8051 core Internal Oscillator circuit crystal from 0.5MHz, 1MHz, 2MHz, 4MHz, 6MHz, 8MHz 12MHz bytes SRAM byte Internal software function bytes Flash Memory flash programming modes: parallel, 2-wire ISP, ICE, normal mode (USB download RS232 download). programmable pins 8-pin wake function Full duplex serial synchronous asynchronous Embedded function with three endpoints (one control Enpoint0, Interrupt endpoint) Watchdog timer (222 clock cycles time) 16-bit programmable timers Two-channel 8-bit programmable ADPCM push-pull Seven-channel 12-bits rail-to-rail converters reset 3.5V 3.7V Power reset Support power down/idle power management Integrated 3.3V power regulator CMOS technology power consumption Total ports with 25mA Source Current ports with 25mA Sink Current DIP-40, LQFP-48, SDIP-28 SOP-28 package
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3.Package information
Table 1.WT65F4 Package Types Package Type LQFP Part Number WT65F4-Q48 WT65F4-N28 WT65F4-N40 WT65F4-S28
4.Pin Assignment Description
Table Descriptions Name P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET P30/RXD P31/TXD P32/INT0 P33/INT1 P34/T0 P35/T1 P36/PWM0 Description General purpose with pull-up resister General purpose with pull-up resister General purpose with pull-up resister General purpose with pull-up resister General purpose with pull-up resister General purpose with pull-up resister General purpose with pull-up resister General purpose with pull-up resister Active High external Reset input General purpose with pull-up resister/serial receive port General purpose with pull-up resister/serial transmit port General purpose with pull-up resister/external interrupt General purpose with pull-up resister/external interrupt General purpose with pull-up resister/Timer external input General purpose with pull-up resister/Timer external input General purpose with pull-up resister/PWM0 output
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P37/PWM1 DAOUT0 DAOUT1 XTAL2 XTAL1
General purpose with pull-up resister/PWM1 output Power Ground output output Power Source Oscillator output Oscillator input Power ground
P20/AD0 P21/AD1 P22/AD2 P23/AD3 P24/AD4 P25/AD5 P26/AD6 P27/Advref P07/K17 P06/K16 PO5/K15 P04/K14 ICE_N ICESTOP_N P03/K13 P02/K12
General Purpose with pull-up resistor/ADC channel (25mA Source/Sink current) General Purpose with pull-up resistor/ADC channel (25mA Source/Sink current) General Purpose with pull-up resistor/ADC channel (25mA Source/Sink current) General Purpose with pull-up resistor/ADC channel (25mA Source/Sink current) General Purpose with pull-up resistor/ADC channel (25mA Source/Sink current) General Purpose with pull-up resistor/ADC channel (25mA Source/Sink current) General Purpose with pull-up resistor/ADC channel (25mA Source/Sink current) General Purpose with pull-up resistor/ADC reference voltage (25mA Source/Sink current) D-signal signal 3.3V power regulation output General Purpose with pull-up resistor/key interrupt General Purpose with pull-up resistor/key interrupt General Purpose with pull-up resistor/key interrupt General Purpose with pull-up resistor/key interrupt mode input with internal pull-up. Active low. interrupt mode with pull-up resistor. Active General Purpose with pull-up resistor. General Purpose with pull-up resistor. General Purpose with pull-up resistor/key interrupt General Purpose with pull-up resistor/key interrupt
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P01/K11 P00/K10
General Purpose with pull-up resistor/key interrupt General Purpose with pull-up resistor/key interrupt power supply.
Configuration
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Figure WT65F4 40-pin 28-pin SOP/DIP package
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Figure WT65F4 48-pin package
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5.Function Description
WT65F4 highly integrated Micro controller with Universal interface. contains 8051 based core, bytes Flash memory, bytes RAM,4K bytes boot 2-wire software function transceiver Serial Interface Engine System Interface Logic transmit receive FIFOs. function supports low-speed data rate 1.5M suspend resume mode, control interrupt bulk transfer fully compliant with specification version 1.1. Operations interface special function controlled through external function registers XFRs special function registers SFRs SIE, SIL, FIFOs 8051 microcontroller that described following sections. Figure shows main functional blocks WT65F4 module they interface with 8051 CPU.
Figure 3.WT65F4 General Block Diagram
WT65F4 Module
function interface manages communications between Host function. WT65F4 interface consists low-speed transceiver, serial engine system interface logic transmit receive FIFOs. low-speed transceiver provides WT65F4 physical interface lines, handles communication protocol USB, handles data transfers provides interface among SIE, 8051 CPU, function FIFOs
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matrix keyboard. shown Figure main blocks module are:
Speed Transceiver: This block on-chip transceiver having differential
driver transmit data onto single ended receivers lines well differential receiver receive data signal bus.
Full Serial Interface Engine (SIE): does front functions protocol such clock/data separation, syncfield identification, NRZI-NRZ conversion, token packet decoding, stripping, stuffing, NRZ-NRZI conversion, CRC5 checking CRC16 generation checking. Besides, manages detecting reset, suspend resume signals upstream port WT65F4 wakeup system from suspend state. also provides serial-to-parallel conversion serial packet from Speed Transceiver parallel data System Interface Logic parallel data from System Interface Logic serial packet Speed Transceiver.
System Interface Logic (SlL): operates conjunction with 8051 provide
capabilities controlling operation FIFOs, monitoring status data transactions, transferring event control 8051 through interrupt requests appropriate moment, initiating resume signaling while WT65F4 powerdown mode. Operation controlled through external function registers.
Function FIFOs: WT65F4 function interface three endpoints support serveral types data transfer: control, interrupt bulk. Endpoint contains FIFO transmit receive, endpoint endpoint have only transmit FIFO. Transmit FIFOs written 8051 CPU, then read transmission. Receive FIFO written following reception, then read 8051 CPU. Endpoint supports control transfer configuration command status type communication flows between client software function. Endpoint endpoint supports interrupt transfer.
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Figure Interface Block Diagram
Microcontroller
8051 high performance on-chip microcontroller running firmware associated with operation function. features 8K-byte FLASH memory, 256-byte RAM, 4K-byte boot/ICE ROM, 16-bit timers. addition, 8051 power saving modes enabling further power reduction. 8051 CPU's operation speed same external clock frequency. main blocks 8051 are:
Port Port 8-bit bi-directional port with internal pull-up. Port assigned input
after reset (i.e., POOE 00H). input output control depend value POOE. When Port assigned output, internal pull-up resistor must disabled automatically. other
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hand, when Port assigned input, internal pull-up resistor disabled setting register PUPCTL. Port also multiplexed interrupt wake-up function during input status.
Port Port 8-bit bi-directional port with internal pull-up. Port assigned input
after reset (i.e., P1OE 00H). input output control depend value P1OE. When Port assigned output, internal pull-up resister must disabled automatically. other hand, when Port assigned input, internal pull-up resistor disabled setting register PUPCTL.
Port Port 8-bit bi-directional port with internal pull-up. Port assigned input
after reset (i.e., P2OE 00H). input output control depend value P2OE. When Port assigned output purpose, internal pull-up resister must disabled automatically. other hand, when Port assigned input, internal pull-up resistor disabled setting register PUPCTL. Port also multiplexed analog digital converter (ADC) function during high-impedance inputs. port, enhanced internal circuits directly drive outside components such LED, buzzer, etc. ports offer source sink currents about 25mA.
Port Port 8-bit bi-directional port with internal pull-up. Port assigned input
after reset (i.e., P3OE 00H). input output control depend value P3OE. When Port assigned output, internal pull-up resister must disabled automatically. other hand, when Port assigned input, internal pull-up resistor disabled setting register PUPCTL. Port also serves functions various special features listed below:
Port
Alternate Function RXD(serial input port)
TXD(serial output port) INT0(external interrupt INT1(external interrupt (timer external input (timer external input PWM0 (PWM output port) PWM1 (PWM output port)
Port Port 2-bit bi-directional port with internal pull-up. Port assigned input
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after reset (i.e., P4OE 00H). input output control depend value P4OE. When Port assigned output, internal pull-up resister must disabled automatically. other hand, when Port assigned input, internal pull-up resistor disabled setting register PUPCTL.
16-bit Timer: WT65F4 bits timers that clocked Oscillator.
programmed applications such periodically generating interrupt serving firmware watchdog timer etc.
8051 On-Chip Memory: 8051 provides on-chip program memory beginning location
4000H normal mode, testing mode, parallel programming mode. where, following chip reset, first instruction fetched executed Flash memory. 8051 also provides on-chip data beginning location 00H. Locations 00H-7FH accessed with direct, indirect addressing while locations 80H-FFH only accessed with indirect addressing. 2-wire programming mode mode, program memory begins location 4000H. mode, address continuesly compared with both BRK0 BRK1 registers. match occurs, breakpoint interrupt (i.e., NMI)is issured address jumped $8010h.
Type
Flash Byte Boot boot/ICE Byte
Memory Location
000h-1FFFh 8000h-8FFFh
Figure Memory mapping Flash ROM, boot ROM, following flash addresses reserved special purpose: $0000h program-reset vector. $0003h external interrupt scan input interrupt vector. $000Bh timer interrupt. $0013h external interrupt interrupt vector. $001Bh timer interrupt. $0023h serial interrupts. $8010h breakpoint interrupt mode
Analog Digital Converter (ADC)
seven channels 12-bits converter turned ADON (Table 31). ADSEL0, channel selected bits control which channels' signal will converted. input analog signal will converted digital stored register ADL. ADINT_IE Table being
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after converted interrupt occurs ADINT Table "1",AD block show Figure
Figure 6.ADC Interface Diagram
Figure Timing Diagram
Table Interface Description
Signals
DAON ADEN AD0~6 ADVRF CLKIN 1DH,1EH ADRDY
Description
0:Power-down mode;1:ADC turned Conversion start. Rising edge trigger analog inputs reference voltage.1uF capacitor must connected between ADVRF clock input digital output bus. available from ADRDY rising edge ADEN becoming low. output ready. Rising edge triggered
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Pulse Width Modulation (PWM)
corresponding register (Table Table controls duty cycle. Duty cycle ranges from 0/32 31/32. 3-bit register determines frame extended Tosc (Tosc 1/external clock frequency). extended pulse. extended Tosc frame extended Tosc frame extended Tosc frame extended Tosc frame extended Tosc frame extended Tosc frame 1,2, extended Tosc frame 5-bit register determines 0/32 31/32 duty cycle each frame. However, both PWM0 PWM1 duty cycles extended depending value ADPWMCLK register. This done dividing external clock desired frequency (new Tosc), then generate pulse width according 5-bit register. Figure shows three examples pulses extended.
Figure Output Waveform Diagram
ADPCM push-pull
voice envelope register buffers, SPKENV0 SPKENV1, added XFR. ADPCM enabled (i.e., setting SPKON high), P36/PWM0 P37/PWM1 outputs value from ADPCM push-pull Otherwise, output selected. DUALT indicates whether envolope datas needs combined together order generate dual tone.
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Figure ADPCM block diagram
WT65F4 Address Space Mapping
WT65F4 five address spaces: program memory space, internal data memory space, special function register space, external function register space, register file. Table shows addressing mapping WT65F4. Table Addressing mapping Memory Type Flash Code External Function Register Internal Data SFRs Register File
Note Direct Indirect:
Size bytes bytes bytes bytes bytes bytes
Location 0000H1FFFH 00H-1FH 00H-7FH 80H-FFH 80H-FFH R0-R7
Data Addressing Indirect using MOVC instruction Indirect using MOVX instruction Direct, Indirect Indirect Direct Register
Direct Byte Addressing Indirect Byte Addressing Please refer 8051 data sheet definition each SFR.
WT65F4 Special Function Register Address Space
special function registers SFRs) reside this optimized 8051 microcontroller Core. Table
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lists location WT65F4 SFRs. Please refer 8051 Data sheet definition each SFR.
Table WT65F4 Special Function Register (SFR) layout initi
0x01 0000
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0xx0 0000
xxxx
WT65F4 with Flash memory 12bit
xx00 xxxx xx00 xxxx xx00
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Read only addressable
External Function Register Address Space
external function registers (XFRs) reside inside module. 8051 connected these registers when register addressed contents registers internal data memory. instructions, MOVX @Rr, MOVX used data movement between XFRs accumulator 8051. Table lists location XFRs. When instruction, MOVX @Rr, MOVX @Rr, executed, address contained registers latched signal then direction data movement between XFRs 8051 controlled signals subsequently generated 8051.
Table External Function Register (XFR) layout
Init
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WT65F4 with Flash memory 12bit
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WT65F4 with Flash memory 12bit
Note
Read clear (2)Write clear Initial value only Endpoint
Clock Unit
Several different external clock frequencies applied WT65F4, they 0.5MHz, 1MHz, 2MHz, 4MHz, 6MHz, 8MHz, 12MHz. feedback resistor built turned during power-down mode waked interrupt, external interrupt, resume signal from host. When function used, only 6MHz 12MHz external clock used. core only accepts 6MHz, when 12MHz clock applied, SIEI register that divided-by-2 circuit activated. There different internal clock speed applied WT65F4 functions, 1.5MHz 6MHz. implementation internal clocks shown below: Table Internal clock generation speed speed External 6MHz 12MHz Spec clock Disable 6MHz Disable DPLL 1.5MHz 1.5MHz Disable
Note: means divided-by-2 circuit DPLL means divided-by-4 digital PLL.
shown Figure clock control section stopped where (IDL) power control register (PCON) firmware, thereby operation halted idle mode. Idle mode freezes clocks known states while peripherals continue clocked. status before entering idle mode preserved. contents SFRs, XFRs also retained. Idle mode used while device unenumerated state following chip reset. Activation enabled interrupt logic high chip reset ways exit idle mode.
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clock where controlled section peripherals that including some portions function stopped where (PD) power control register (PCON) firmware. Therefore both Oscillator operation halted powerdown mode. status before entering powerdown mode preserved. addition, contents SFRs, XFRs also retained. suspend, firmware must WT65F4 into powerdown mode meet limitation Activation enabled interrupt logic high chip reset ways exit powerdown mode. clock source usb_clock used sampling clock function (6MHz 1.5MHz) speed Transactions. Besides clock generated core logic 8051 CPU, WT65F4 also needs generate clock source Convertor (ad_clk). speed ad_clk depends ADSEL bits ADPWM_C register. Please Table detail.
Figure Clock circuit when function used
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Figure Clock divided-by-2 circuit
5.10
Reset
Chip reset initiated watch-dog timer reset, voltage reset, USB-initiated reset, power-on reset (POR), external high level reset. external reset must applied RESET least 80ms while Oscillator runningin order reset entire chip. voltage (VCC VLvR) causes reset condition entire chip prevent chip Flash memory being placed unknown state. 8051 reset extended states order synchronize PSEN.
Figure Reset Signals
5.11 Powerdown Mode IdIe Mode
instruction that sets PCON.0 last instruction executed before idle mode activated. Once idle mode status preserved entirety. Activation enabled interrupt will cause PCON.0 cleared hardware then idle mode terminated.
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instruction that sets PCON.1 last executed prior entering powerdown mode. Once powerdown mode, Oscillator stopped. contents on-chip RAM, Special Function Registers External Function Registers saved. Hardware reset activation enabled interrupt ways exiting powerdown mode. Powerdown mode should used suspend operation. PCON.1 interrupt caused active SUSPEND signal. Please section 5.12 details. WT65F4 initiate resume signaling host through remote wakeup function while powerdown mode. While powerdown mode, remote wakeup initiated through assertion enabled external interrupt. powerdown mode controlled ADPWR ADPWM_C register.
5.12 Interrupt
shown Figure there interrupt sources share interrupt inputs 8051 (interrupt interrupt Interrupt This interrupt connected external hardware interrupt input P32/INT0 WT65F4. interrupts, interrupt (ADINT) keyboard interrupt (KEYINT), also interrupt operate. normal operation, both interrupt keyboard interrupt disabled. powerdown mode, interrupt would disable keyboard interrupt enable terminate powerdown mode (suspend state) support remote wakeup. interrupt vector 03H. external interrupt P32/INT0 only used when both ADINT KEYINT interrupt functions disabled. Figure shows control block diagram P32/INT0, ADINT, KEYINT.
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Figure Block Diagram INT0 Interrupt This interrupt used function interrupt connected external hardware interrupt input (P33/INT1) WT65F4. This interrupt used control transfer interrupt transfer interrupt vector 13H. This interrupt also initiated assertion suspend interrupt signal resume interrupt signal. Similar interrupt external interrupt P33/INT1 used when anyone interrupt functions enabled.
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Figure Wt65F4 interrupt circuit
5.13 Function Endpoint
WT65F4 supports three function endpoints. Endpoint contains FIFO transmit receive while endpoint endpoint transmitted only. Endpoint endpoint handles interrupt data transfer. EPINDE register (Table selects endpoint given data transaction.
5.14 Transmit FIFOs
WT65F4 transmit FIFO each function endpoint (See Figure
5.15 Transmit FIFOs Features
transmit FIFOs data buffers with following features (See Figure 15): support data greater than bytes byte count register store number bytes data protection against overwriting data full FIFO capability retransmit current data
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Figure Transmit FIFO outline
8051 writes FIFO location specified write pointer also used bytecounter indicate many bytes have been written read SIL. write pointer automatically increments after write decrements after read. read pointer points next FIFO location read SIL. read pointer automatically increments after read. transmit FIFO inhibited read when empty before data been successfully written into
5.16 Transmit Data Management
TXFULL TXFLG register (Table 21), indicates data been written into FIFO ready transmission. Following reset, TXFULL TXEMP signifying empty FIFO. Only first eight bytes data which size greater than eight written into FIFO. this case, TXFULL until write TXCNT (Table 22). case TXFULL farther writing TXDAT (Table TXCNT ignored. Please note that content TXCNT determines number bytes transmitted over lines. Discrepancy between byte number written TXCNT number bytes actually written FIFO will cause unexpected result. Read FIFO prohibited when FIFO empty TXFULL events cause TXFULL updated: data written FIFO: writes bytes FIFO TXDAT writes number bytes TXCNT. TXFULL only after write TXCNT. TXCNT-0 indicates zero length transmission. this case, TXFULL TXEMP remains unchanged indicate FIFO still empty. This process illustrated Table data FIFO successfully transmitted: reads data Flashmemory FIFO transmission. When good transmission acknowledged, TXFULL cleared TXEMP set. Table Writing Byte Count Register
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Zero Length Transmi ssion
Write bytes TXDATx Write byte count TXCNTx
Data Written Write lgnored
When good transmission completed, both read pointer write pointer advanced start point FIFO transmitting next data set. When transmission encountered, read pointer reversed start point FIFO enable re-read last data retransmission. pointer reversal advance accomplished automatically hardware. Table summarizes actions following transmission depend TXERR TXACK. Table Truth table transmit FIFO management
Action Transfer Cycle Transfer Cycle Read Pointer Write Pointer both start point FIFO Read Pointer start point FIFO
5.17 Transmit FIFO Registers
TXDAT, transmit FIFO data register (see Table Section TXCNT, transmit FIFO byte count register (see Table Section TXCON, transmit FIFO control register (see Table Section TXFLG, transmit FIFO flag register (see Table Section These registers endpoint indexed. They used control operation transmit
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FIFO, associated with current endpoint specified EPINDEX register (see Table Section
5.18 Receive FIFOs
WT65F4 receive FIFO endpoint (See Figure This FIFO shared with transmit FIFO. Detail operating described section.
5.19 Receive FIFO Features
receive FIFO data buffer with following features (see Figure 16):
support data greater than eight bytes byte count register accesses number bytes data flag signal full FIFO empty FIFO capability re-receive last data
Figure Receive FIFO Outline writes FIFO location specified write pointer also used byte-counter
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indicate many bytes have been written read 8051 CPU. write pointer automatically increments after write decrements after read. read pointer points next FIFO location read 8051 CPU. read pointer automatically increments after read. receive FIFO inhibited read 8051 when empty before data been successfully written into When SETUP token detected SIL, flushes FIFO even FIFO being read 8051 CPU.
5.20 Receive Data Management
RXFULL RXFLG register (Table 36), indicates data been written into FIFO ready reception. Following reset, RXFULL RXEMP signifying empty FIFO. Only first eight bytes data which size greater than eight written into FIFO. RXFULL however until reception done successfully acknowledged. RXFULL cleared setting FFRC RXCON (Table firmware indicate data
successfully read CPU. case RXFULL farther writes FIFO ignored. Please note that content RXCNT (Table should read 8051 determine numbers bytes need read Flashmemory FIFO 8051 CPU. Further reading Flashmemory empty FIFO ignored. Table Status receive FIFO data RXEM Status Data being written FIFO Empty Data already written FIFO Zero length packet received
When good reception completed data been successfully read 8051, firmware must FFRC RXCON advance write pointer read pointer start point FIFO receiving next data set. When reception completed, write pointer reversed position start point FIFO enable re-write last data re-reception. pointer advance reversal accomplished automatically hardware. Table summarizes actions following reception depend RXERR RXACK. Table Truth table receive FIFO management
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Action Transfer Cycle operation Read Pointer Write Pointer start point FIFO when firmware sets FFRC RXCON Write Pointer start point FIFO
5.21 Receive FIFO Registers
RXDAT, receive FIFO data register (see Table Section RXCNT, receive FIFO byte count register (see Table Section RXCON, receive FIFO control register (see Table Section RXFLG, receive FIFO flag register (see Table Section These registers endpoint indexed. They used control operation receive FIFO associated with current endpoint specified EPINDEX register (see Table Section
5.22 Setup Token Receive FIFO Handling
SETUP tokens received endpoint zero must acknowledged, even receive FIFO empty. described section 5.19, when SETUP token detected SIL, flushes FIFO sets STOVW RXSTAT (Table reset locking read pointer. These prevent RXURF RXFLG read pointer Flashmemory being receive FIFO flush occurs middle 8051 data read cycle. STOVW cleared EDOVW when SETUP packet been successfully acknowledged. read pointer will remain locked until both STOVW EDOVW bits cleared. SETUP packets only, firmware must clear EDOVW before reading data Flashmemory FIFO. this done, data read Flashmemory FIFO will invalid. After processing SETUP packet, firmware should always check STOVW EDOVW flags before setting RXFFRC bit. When SETUP packet either been being received, setting RXFFRC effect either STOVW EDOVW set.
5.23 Suspend Resume
order reduce power consumption, WT65F4 automatically enters suspend state when
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observed traffic When suspend, 8051 peripherals powerdown mode. Keyboard interrupt enabled support remote wakeup. entire chip consumes less than suspended state. WT65F4 exits suspend mode when there activity. device also request host exits Flashmemory suspend selective suspend using electrical signaling indicate remote wakeup. ability device signal remote wakeup optional. WT65F4 allows host enable disable this capability. Device states described Figure
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Figure Suspend Resume State Diagram
5.24 Mode
Five pins released performing mode, they VDD, GND, RESET, P30/RXD, P31/TXD. applying special pattern through RESET, P30/RXD, P31/TXD, device forced enter mode. detection this special pattern done firmware. Once mode detected, flag (ISPM) written PCON. other hand, mode detected after then normal mode considered. While mode, data external clock applied P30/RXD P31/TXD, respectively. Furthermore, flash rerouted from normal interface corresponding registers. order accommodate system clock variation, necessary build-in "delay loop" into program ROM. length delay depends system's clock information notified P31.
5.25 Mode
WT65F4 support easy function. Program download, free running sets breakpoint function supported. During mode, commands into device P4.0 P4.1. controls will done Weltrend Soft_ICE.
5.26 Normal Download Mode
User control Flash-ROM programming Normal Download mode. When BKEN2 firmware, Flash routed from normal interface four external function registers: ISPCTL, ISPADDL, ISPADDH, ISPDATA.
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External Function Register FADDR
Address: Reset State:
0000 0000B Function Address Register. This holds address function. During enumeration, written with unique value assigned host. Table Function Address Register (FADDR,00H) -ADR6:0
Number
Mnemoni
-ADR6:0
Function
Reserved: Write zero this 7-bit Programmable Function Address: This register programmed through commands Received endpoint configuration, which should only time firmware should change value this Register. This register hardware read-only
USBI
Address: Reset State:
(Read clear)
xx00 0000B Table Interrupt Register (USBI,01H)
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SUSP
USBRx0
USBTx 2INT
USBTx 1INT
USBTx 0INT
Mnemo RESUM SUSPE USBRx 0INT USBTx 2INT USBTx 1INT USBTx 0INT
Function detected RESUME signaling lines. This interrupt used terminate powerdown mode. detected SUSPEND signaling lines. corresponding should whole chip into powerdown mode. Function Receive Done Flag endpoint Function Transmit Done Flag endpoint Function Transmit Done Flag endpoint Function Transmit Done Flag endpoint
USBKAIE
Address: Reset State:
0000 0000B USB/Keyboard/AD Interrupt Enable Register.
Table USB/Keyboard/AD Interrupt Enable Register (USBKAIIE, 02H) RESU ME_I SUSPE ND_IE Rx0I NT_I Tx2I NT_I Tx1I NT_I Tx0I NT_I
Mnemoni
Function
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WT65F4 with Flash memory 12bit
KINT_IE ADINT_I RESUME SUSPEN D_IE Rx0INT_I Tx2INT_I Tx1INT_I Tx0INT_I
Keyboard Interrupt Enable: Enable Keyboard Interrupt (KEYINT). Firmware this before entering powerdown idle mode enable remote wakeup. operation. External2 Interrrupt Enable: Enable External2 Interrupt EXT2INT RESUME Interrupt Enable. SUSPEND Interrupt Enable. Function Transmit Done Interrupt Enable Enable receive done interrupt endpoint (USBTx0INT). Function Transmit Done Interrupt Enable2: Enable receive done interrupt endpoint (USBTx0INT). Function Transmit Done Interrupt Enable Enable receive done interrupt endpoint (USBTx0INT). Function Transmit Done Interrupt Enable Enable receive done interrupt endpoint (USBTx0INT).
bits, means interrupt enabled will cause interrupt Signaled microcontroller. means associated interrupt source Disabled cannot cause interrupt.
SIEI
Address: Reset State:
Xx00 0000B Interface Register. Table Interface Register (SIEI,03H) LVRE CLK1 2MEN V33E USBS TREN
WAKE
V1.0
WT65F4 with Flash memory 12bit
Mnemoni -LVREN CLK12M V33EN USBRST DMEN WAKEUP
Function Reserved: Values read Flashmemory these bits indeterminate. Write zeros these bits. disabled enabled clock source comes from 6MHz X'tal. clock source comes from 12MHz X'tal. 3.3V regulator circuits turned voltage reset circuit disabled. 3.3V Regulator circuits turned voltage reset circuit enabled. Reset enable. Firmware this enable /disable Reset. 1.5k-ohm resisters turn off. 1.5k-ohm resisters turn This used initiate remote wakeup. firmware drive resume signaling lines host upstream hub. Cleared hardware when resume signaling done.
EPINDEX
Address: Reset State:
xxxx xx00B
Endpoint Index Register. This Register identifies endpoint pair. contents select transmit receive FIFO pair serve index endpoint-specific XFRs. Table Endpoint Index Register (EPINDEX,05H) -EPI
Function
V1.0
WT65F4 with Flash memory 12bit
Mnemoni -Reserved Values read Flashmemory these bits indeterminate. Write zeros these bits. Endpoint Index: Function Endpoint Function Endpoint Function Endpoint Function Endpoint
EPINX1:0
value this register selects associated bank endpoint-indexed XFRs Including TXDAT, TXCON, TXFLG, TXCNT, TXSTAT, RXDAT, RXCON, RXFLG, RXCNT, RXSTAT EPCON.
EPCON
(Endpoint-indexed) 001x0101B Reset State: Endpoint
Address:
Endpoint 1,2:
x0xx xx00B Endpoint Control Register. This configures operation endpoint specified EPINDEX. Table Endpoint Control Register (EPCON,06H) -RXI
Mnemoni RXSTL
Function Stall Receive Endpoint: this stall receive endpoint Clear this
V1.0
WT65F4 with Flash memory 12bit
TXSTL
CTLEP
only when host intervened through commands sent down endpoint When this bits RXSETUP clear, receive endpoint will respond with STALL handshake valid token. When this RXSETUP set, receive endpoint will NAK. This does affect reception SETUP token control endpoint. Stall Transmit Endpoint: this stall transmit endpoint. This should cleared only when host intervened through commands sent down endpoint When this RXSETUP clear, receive endpoint will respond with STALL handshake valid token. When this RXSETUP set, receive endpoint will NAK. Control Endpoint: this configure endpoint control endpoint. Only control endpoint capable receiving SETUP tokens. Reserved: Value read Flashmemory this indeterminate. Write zero this bit.
V1.0
WT65F4 with Flash memory 12bit
Mnemoni
Function Receive Input Enable: this enable data Flashmemory written into receive FIFO. cleared, endpoint will write receive data into receive FIFO reception, will return handshake valid token RXSTL set. This does affect valid SETUP token. valid SETUP token packet overrides this cleared, place receive data FIFO. Receive Endpoint Enable: this enable receive endpoint. When disabled, endpoint does respond valid SETUP token. This hardware read-only highest priority among RXIE RXSTL. Note that endpoint enabled reception upon reset. Transmit Output Enable: This used enable data TXDAT transmitted. cleared, endpoint returns handshake valid token TXSTL set. Transmit Endpoint Enable: This used enable transmit endpoint. When disabled, endpoint does response valid Token. This hardware read only. Note that endpoint enabled transmission upon reset.
RXIE
RXEPEN
TXOE
TXEPEN
V1.0
WT65F4 with Flash memory 12bit
SPWDCTL
Address:
0000 0010B
Reset State:
Enable Disable Watch-dog timer function. Watch-dog timer will generate reset pulse does write data CLRWDT register more than clock cycles (CPU clock). This function could disabled clearing EN_WDT bit.
Table Speaker/Watch-dog Timer Control Register (SPWDCTL,07H) Mnemoni SPKON DUALT -EN_WDT WDTRST
Function ADPCM push-pull function enable. disabled function enabled. ADPCM push-pull disabled Dual-tone. Combine SPKENV0 SPKENV1 Mono-tone. Select only spkenv0 Reserved: Values read Flashmemory these bits indeterminate. Write zeros these bits. Enable Watch-dog timer Disable Watch-dog timer Watch-dog timer reset Generate pulse clear Watch-dog timer
V1.0
WT65F4 with Flash memory 12bit
TXDAT
Address: Reset State: xxxx
(Endpoint-indexed)
xxxxB
Transmit FIFO Data Register. Data transmitted FIFO specified EPINDEX first written this register.
Table 19.Transmit FIFO Data Register (TXDAT, 08H) TXDAT7:0
Mnemonic TXDAT7:
Function Transmit Data Bytes (write-only) write data transmit FIFO, write this register. write pointer incremented automatically after write.
V1.0
WT65F4 with Flash memory 12bit
TXCON
Address: Reset State: 0xxx
(Endpoint-indexed)
xxxxB
Transmit FIFO Control Register. Controls transmit FIFO specified EPINDEX.
Table 20.Transmit FIFO Control Register (TXCIN, 09H)
Mnemoni
Function Transmit Clear: Setting this flushes transmit FIFO, resets read/write pointers, sets EMPTY TXFLG, clears other bits TXFLG. After flush, hardware clears this bit. Reserved: Values read Flashmemory these bits indeterminate. write zeros these bits.
TXCLR
V1.0
WT65F4 with Flash memory 12bit
TXFLG
Address: Reset State: xxxx
RW(Write clear)(Endpoint-indexed)
1000B
Transmit FIFO Flag Register. These flags indicate status data packets transmit FIFO specified EPINDEX. Table Transmit FIFO Flag Register (TXFLG,0AH) Mnemoni
Function Reserved: Values read Flashmemory these bits Indeterminate. Write zeros these bits. Transmit FIFO Empty Flag (read-only): Hardware sets this when data been read transmit FIFO SIL. Hardware clears this when empty condition longer exists. This always tracks current transmit FIFO status. This flag also when zero-length data packet transmitted. Transmit FIFO Full Flag (read-only): This flag indicates data present transmit FIFO. This after write TXCNT reflect condition data set. Hardware clears this when data been successfully transmitted. Transmit FIFO Underrun Flag (read-, clear-only)*: Hardware sets this flag when addition byte read Flashmemory empty transmit FIFO. This sticky that must cleared through firmware writing this .When transmit FIFO underruns, read
V1.0
TXEMP
TXFULL
TXURF
WT65F4 with Flash memory 12bit
TXOVF
pointer will advance-it remains locked empty position. Transmit FIFO Overrun Flag (read-, clear-only)*: This when additional byte written FIFO with TXFULL This sticky that must
cleared through firmware writing this When transmit FIFO overruns, write pointer will advance remains locked full position. Note When set, transmission NAKed.
V1.0
WT65F4 with Flash memory 12bit
TXCNT
Address: Reset State: 0000
(Endpoint-indexed)
0000B
Transmit FIFO Byte Count Register. This register stores number bytes data packet transmit FIFO specified EPINDEX.
Table Transmit FIFO Bytes Count Register (TXCNT, 0BH) -Bit -Bit Mnemoni -TXCNT -TXCNT
Function Reserved: Write zeros these bits. Transmit Byte Count (write-only): number bytes data being written transmit FIFO. When this register written, TXFULL set. Write byte count this register after writing data TXDAT.
send status stage after control write data control command null packed, write TXCNT.
V1.0
WT65F4 with Flash memory 12bit
TXSTAT
Address: Reset State: 0000
RW(Write clear)(Endpoint-indexed)
0000B Endpoint Transmit Status Register. Contains current endpoint status transmit FIFO specified EPINDEX. Table Endpoint Transmit Status Register (TXSTAT, 0CH)
Mnemoni
Function Transmit Current Sequence (read-only): This will transmitted next toggled valid handshake. This toggled hardware valid SETUP token. Reserved: Write zeros these bits. Transmit Void (read-only): void condition occurred response valid token. Transmit void closely associated with NAK/STALL handshake returned function after valid token, conditions that cause Transmit FIFO unable ready transmit. this check NAK/STALL handshake returned function. This does affect USBTxxINT, TXERR TXACK bit. This updated hardware non-isochronous transaction response valid token. Transmit Error (read-only): error condition occurred with transmission. Complete partial data been transmitted. error following: Data transmitted successfully handshake received.
V1.0
TXSEQ
TXVOID
TXERR
WT65F4 with Flash memory 12bit
Transmit FIFO goes into underrun condition while transmitting. corresponding transmit done when active. This updated hardware along with TXACK data transmission (this mutually exclusive with TXACK).
Mnemoni
Function Transmit Acknowledge (read-only): Data transmission completed acknowledged successfully. corresponding transmit done when active. This updated hardware along with TXERR data transmission (this mutually exclusive with TXERR)
TXACK
V1.0
WT65F4 with Flash memory 12bit
PWM0
Address: Reset State: 0000
0000B PWM0 Duty Control Register Table Pwm0 Duty Control Register (PWM, 0DH) Mnemoni PWM07 PWM06 PWM05 PWM04 PWM03
Function Select 0/32 31/32 duty cycle extended pulse 00000: duty cycle 00001: duty cycle 1/32 00010: duty cycle 2/32 11110: duty cycle 30/32 11111: duty cycle 31/32 corresponding register controls duty cycle. Duty cycle range from 0/32 31/32. 3-bit register determines which frame will extended Tosc. extended pulse. extend Tosc frame extended Tosc frame extended Tosc frame 4and extended Tosc frame 5and extended Tosc frame 5and extended Tosc frame 6and extended Tosc frame
PWM02 PWM01 PWM00
V1.0
WT65F4 with Flash memory 12bit
PWM1
Address: Reset State: 0000
0000B PWM1 Duty Control Register
Table PWM1 Duty Control Register (PWM1, 0EH) Mnemoni PWM17 PWM16 PWM15 PWM14 PWM13
Function Select 0/32 31/32 duty cycle extended pulse 00000: duty cycle 00001: duty cycle 1/32 00010: duty cycle =2/32 11110: duty cycle 30/32 11111: duty cycle 31/32 corresponding register controls duty cycle. Duty cycle range from 0/32 31/32. 3-bit register determines which frame will extended Tosc. extended pulse. extend Tosc frame extended Tosc frame extended Tosc frame 4and extended Tosc frame 5and extended Tosc frame 5and extended Tosc frame 6and extended Tosc frame
PWM12 PWM11 PWM10
V1.0
WT65F4 with Flash memory 12bit
P2ODCTL
Address: Reset State: 0000
0000B Strong Current Source Control Port 20~27.
Table Port2 Current Control Register (P2ODCTL, 0FH) -P25 -P21
Mnemoni -P25SN P24SN -P21SN P20SN
Function
Default value `00000000' (strong current source turned off). When written bits, corresponding strong current source turned
shown Figure strong source current PMOS turned (open drain circuit). Open drain circuit selected when P2xSN high order turn corresponding PMOS.
Figure Port circuit diagram
ISP_CTL
Address:
V1.0
WT65F4 with Flash memory 12bit
xxxxB Program Data Flash function.
Reset State: xxxx
Table program control Register (ISP_CTL, 11H)
Mnemoni NVSTR PROG MAS1 ERASE
Function Defines non-volatile store cycle. Defines program cycle. Defines mass erase cycle, erase whole block. Defines erase cycle. Output enable, tri-state DOUT when OE=0. Sense amplifier enable. address enable, YMUX disabled when YE=0. address enable, rows disabled when XE=0.
V1.0
WT65F4 with Flash memory 12bit
ISPADDL
Address: Reset State: xxxx
xxxxB Address byte Flash function.
Table Address byte Register (ISPADDL, 12H)
Mnemoni YADR[7:0 A[4:0]
Function
Address (which indicates YADR
V1.0
WT65F4 with Flash memory 12bit
ISPADDH
Address: Reset State: xxxx
xxxxB Address high byte Flash function.
Table Address high byte Register (ISPADDH, 13H) Mnemoni YADR[7:0 A[12:5]
Function
Address (which indicates XADR
V1.0
WT65F4 with Flash memory 12bit
ISPDATA
Address: Reset State: xxxx
xxxxH Program Data Flash function.
Table program data Register (ISPDATA, 14H) Mnemoni
Function Program data flash during function
V1.0
WT65F4 with Flash memory 12bit
ADPWM_C
Address: Reset State: 0000
0000B AD/PWM function control.
Table AD/PWM function control Register (ADPWM_C, 15H)
Mnemoni PWMEN0 PWMEN1 ADref
Function Disable channel function Enable channel function Disable channel function Enable channel function Select reference voltage circuit Select ADvref (P07) reference input voltage circuit 000: Selected input 001: Selected input 010: Selected input 011: Selected input 100: Selected input 101: Selected input 110: Selected input 111: Selected input Disable function Enable function Disable power-down mode Enable power-down mode
ADSEL[2:
ADEN ADON
V1.0
WT65F4 with Flash memory 12bit
ADCLK
Address: Reset State: x000
0000B Sample clock control register.
Table Transmit FIFO Flag Register (TXFLG,0AH) -Bit -ADC
Mnemoni
Function Reserved Reserved Reserved 000: clock=Fosc/2 (used 8051 clock=0.5MHz) 001: clock=Fosc/4 (used 8051 clock=1MHz) 010: clock=Fosc/8 (used 8051 clock=2MHz) 011: clock=Fosc/16 (used 8051 clock=4MHz) 100: clock=Fosc/32 (used 8051 clock=6, 8MHz) 101: clock=Fosc/48 (used 8051 clock=10~12MHz)
ADCLK
V1.0
WT65F4 with Flash memory 12bit
KYADI
Address: Reset State: 00xx
RW(Read clear)
xxxxB
Kayboard/AD Interrupt Register. Contains Keyboard interrupt flags. Indicates that interrupt actively pending. bits cleared after read.
Table Kayborad/AD Interrupt Register (KYADI, 17H) Mnemoni
Function Keyboard Interrupt Flag. This when Keyboard Input (K10~K17) low. This interrupt used wake-up from powerdown mode idle mode. Normal operation, this interrupt also from External interrupt pins. converter interrupt flag. This when data converted. Reserved: Values read Flashmemory these bits indeterminate. Write zeros these bits.
KEYINT
ADINT
KYADI register read even KINT_IE ADINT_IE bits USBKAIE (02h) enabled.
V1.0
WT65F4 with Flash memory 12bit
RXDAT
Address: Reset State: xxxx
xxxxB
Receive FIFO Data Register. Receive FIFO data specified EPINDEX stored read Flashmemory this register.
Table Receive FIFO Data Register (RXDAT, 18H) RXDAT7:0 Mnemoni
Function Receive Data Byte (read-only): write data receive FIFO, writes this register. read data Flashmemory receive FIFO, 8051 reads Flashmemory this register. write pointer read pointer incremented automatically after write read, respectively.
RXDAT7:
V1.0
WT65F4 with Flash memory 12bit
RXCON
Address: Reset State: 0xx0
xxxxB Receive FIFO Control Register. Controls receive FIFO.
Table Receive FIFO Control Register (RXCON, 19H) -RXF
Mnemoni
Function Clear Receive FIFO: this flush entire receive FIFO. flags RXFLG revert their reset states (RXEMP set; other flags clear). Hardware clears this when flush operation complete. Reserved: Values read Flashmemory these bits indeterminate. Write zeros these bits. FIFO Read Complete: this release receive FIFO when data read complete. Setting this clears RXFULL RXFLG register) corresponding data that just read. Hardware clears this after RXFULL cleared. data Flashmemory this data must have been read. Note that FIFO Read Complete only works STOVW EDOVW cleared. Reserved: Values read Flashmemory these bits indeterminate. Write zeros these bits.
RXCLR
RXFFRC
V1.0
WT65F4 with Flash memory 12bit
RXFLG
Address: Reset State: xxxx
RW(Write clear)
1000B
Receive FIFO Flag register. These flags indicate status data packets Receive FIFO.
Table receive FIFO Flag Register (RXFLG, 1AH) -RXE
Mnemoni
Function Reserved: Values read Flashmemory these bits indeterminate. Write zeros these bits. Receive FIFO Empty Flag (read-only): Hardware sets this when data been read receive FIFO. Hardware clears this when empty condition longer exists. This sticky always tracks current status. This flag also when zero-length packet received. Receive FIFO Full Flag (read-only): This flag indicates data present receive FIFO. Hardware sets this when data been successfully received. This cleared after write RXCNT reflect condition data set. Likewise, this cleared after setting RXFFRC bit. Receive FIFO Underrun Flag (read-, clear-only)*: Hardware sets this when additional byte read Flashmemory empty receive FIFO. This cleared through firmware writing this When receive FIFO underruns, read pointer will advance remains locked empty position.
V1.0
RXEMP
RXFULL
RXURF
WT65F4 with Flash memory 12bit
RXOVF
Receive FIFO Overrun Flag (read-, clear-only)*: This when writes additional byte
receive FIFO with RXFULL This sticky that must cleared through firmware writing this bit, although cleared hardware SETUP packed received after RXOVF error already occurred. When receive FIFO overruns, write pointer will advance remains locked full position.
When set, transmission NAKed.
V1.0
WT65F4 with Flash memory 12bit
RXCNT
Address: Reset State: 0000
0000B
Receive FIFO Byte Count Register. This register used store number byte data packed received receive FIFO specified EPINDEX.
Table Receive FIFo Byte Count Register (RXCNT, 1BH) -Bit -Bit Mnemoni -RXCNT3:0
Function Reserved: Always zeros. Byte Count (read-only): number bytes data being written receive FIFO. When this register written, RXFULL until reception successfully acknowledged. After writes data RXFIFO, writes byte count this register. 8051 reads byte count Flashmemory this register determine many bytes read Flashmemory RXFIFO.
RXCNT3:
V1.0
WT65F4 with Flash memory 12bit
RXSTAT
Address: Reset State: 0000
RW(Write clear)
0000B
Endpoint Receive Status Register. Contains current endpoint status receive FIFO specified EPINDEX. Table Endpoint Receive Status Register (RXSTAT, 1CH) RXSE
Mnemoni
Function Receive Endpoint Sequence (read-only): This will toggled completion handshake response token. This will created) hardware after reception SETUP token. Receive Setup Token (read-, clear-only): This hardware when valid SETUP token been received. When set, this causes received token NAKED until cleared allow control transaction. token NAKed even endpoint stalled (RXSTL TXSTL) allow control transaction clear stalled endpoint. Clear this upon detection SETUP token after firmware ready complete setup stage control transaction. Start Overwrite Flag (read-only); hardware upon receipt SETUP token control endpoint indicate that receive FIFO being overwritten with SETUP data. When set, FIFO state (RXFULL read pointer) resets locked this endpoint until EDOVW set. This prevents prior, ongoing firmware read Flashmemory corrupting read pointer receive FIFO being cleared data being written into This cleared hardware handshake phase transmission setup stage. This used only control endpoint.
V1.0
RXSEQ
RXSETU
STOVW
WT65F4 with Flash memory 12bit
EDOVM
RXVOID
RXERR
RXACK
Overwrite Flag (read-, clear-only): This flag hardware during handshake phase SETUP stage. after every SETUP packet received must cleared prior reading contents FIFO. When set, FIFO state (RXFULL read pointer) remains locked this endpoint until this cleared. This prevents prior, ongoing firmware read Flashmemory corrupting read pointer after data been written into receive FIFO. This only used control endpoint. Note: Make sure EDOVW cleared prior reading contents receive FIFO. Reserved: write zero this bit. Receive Void Condition (read-only): This when valid data received response SETUP token following conditions: receive FIFO still locked. EPCON register RXSTL set. This cleared hardware. This updated hardware transaction response valid token. Receive Error (read-only): when error condition occurred with reception. Complete partial data been written into receive FIFO. handshake returned. error following conditions: Data failed check. stuffing error. receive FIFO goes into overrun underrun condition while receiving. This updated hardware valid SETUP token transaction. corresponding receive done when active. This updated with RXACK data reception mutually exclusive with RXACK. Receive Acknowledged (read-only): This when data received completely into receive FIFO handshake sent. This readonly updated hardware valid SETUP token transaction. corresponding
V1.0
WT65F4 with Flash memory 12bit
receive done when active. This updated with RXERR data reception mutually exclusive with RXERR.
V1.0
WT65F4 with Flash memory 12bit
Address: Reset State: 0000
0000B Lower Byte Data.
Table Lower Byte Data Register (ADL, 1DH) Mnemoni
Function Data lower byte
Address:
V1.0
WT65F4 with Flash memory 12bit
0000B Higher Byte Data Register.
Reset State: 0000
Table Higer Byte Data Register (ADH, 1EH)
Mnemoni
Function Data higher byte [11:8]
SPKENV0
Address: Reset State:
V1.0
WT65F4 with Flash memory 12bit
0000 0000B Push-pull speaker output envelope Register.
Table Push-pull speaker output envelope (spkenv0, 10H) SPKENV0 Mnemoni SPKENV
Function Push-pull speaker output envelope
SPKENV1
Address: Reset State: 0000
0000B Push-pull speaker output envelope Register.
Table Push-pull speaker output envelope (SPKENV1, 1FH) SPKENV1 Mnemoni
Function
V1.0
WT65F4 with Flash memory 12bit
SPKENV
Push-pull speaker output envelope
Electrical Characteristics
Table Electrical Characteristics (VCC=5V± GND=0V, TA=0~70, FOSC=6MHz, unless otherwise noted) Parameter Condition
Supply Voltage
Input High Voltage
Input Voltage
D0.1
Output High Voltage (Port Output High Voltage (Port 1~3) Output Voltage (Port Output Voltage (port 1~3) Input Leakage Current
IOH= -25mA IOH= -80uA IOL=25mA
IOL= 1.6mA 0V<VIN<VDD
V1.0
WT65F4 with Flash memory 12bit
Pull High Resistance Operating Current Idle Mode Current Power Down Mode Current regulator output Reset Voltagenote FOSC= 6MHz, load FOSC= 6MHz, load V3.3 regulator 1.5K register turn Oscillator disabled. Load, V3.3 regulator 1.5K register turn
IDD,
IDD,
IDD,
Note: Reset voltage only valid when function used.
V1.0
WT65F4 with Flash memory 12bit
Table Absolute Maximum Rating supply voltage Input Output voltage Operating ambient temperature Storage temperature Operating voltage (VCC) -0.3V +7.0V 0.3V 0.3V +2.7V 5.5V
Figure External Clock Drive Waveform
V1.0
WT65F4 with Flash memory 12bit
Table Electrical Characteristics
Symbol
1/TCLCL TCHCX TCLCX TCLCH TCHCL
Parameter
Oscillator frequency High time time
Min.
5.94 0.35T 0.35T
CLCL CLCL
Max.
6.06 0.65TC 0.65TC
Unit
Rise time Fall time Power reset internal TPOR High time Note pullup resistor, 50pF
V1.0
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