Device Controller with WT6561F Embedded Controller with

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WT6561F
Device Controller with
WT6561F
Embedded Controller with
(Flash Type)
Preliminary Specification v.099h
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V0.99h
WT6561F
Device Controller with
Table Contents
FEATURES. GENERAL DESCRIPTION. FEATURES ORDERING INFORMATION ASSIGNMENT PACKAGE TYPES
Description Configuration.13
FUNCTIONAL DESCRIPTION.
WT6561F Module.16 Micro-controller.18 WT6561F Address Space Mapping
3.3.1 3.3.2 WT6561F Special Function Register Address Space External Function Register Address Space
Clock Unit.21 Reset.22 Power-down Mode Idle Mode Interrupt Function Endpoint.24 Transmit FIFOs
3.9.1 3.12.3 Transmit FIFOs Features Transmit FIFO Registers 3.12.2 Transmit Data Management.
3.13
Receive FIFOs
3.13.1 Receive FIFO Features 3.13.2 Receive Data Management. 3.13.3 Receive FIFO Registers
3.14 Setup Token Receive FIFO Handling 3.15 Suspend Resume
EXTERNAL FUNCTION REGISTERS
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WT6561F
Device Controller with
TARGET SPECIFICATION.
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WT6561F
Device Controller with
Figure List
Figure WT6561F 48-Pin Package. Figure WT6561F 48-Pin Package. Figure WT6561F Core Pads Figure Clock Circuit. Figure Transmit FIFO Outline (example bytes FIFO). Figure Receive FIFO Outline(example bytes FIFO). Figure Suspend Resume State Diagram. Figure External Clock Drive Waveform
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WT6561F
Device Controller with
Table List
Table WT6561F Signals Arranged Number Table WT6561F Signal Description. Table Addressing Mapping. Table WT6561F Special Function Register Layout Table Writing Byte Count Register Table Truth Table Transmit FIFO Management. Table Status Receive FIFO Data Table Truth Table Receive FIFO Management. Table External Function Register Layout Table Function Address Register Table Function Interrupt Register Table Function Interrupt Enable Register Table Interface Register. Table Endpoint Index Register Table Endpoint Control Register Table Watchdog Timer Reset Register Table Transmit FIFO Data Register Table Transmit FIFO Control Register Table Transmit FIFO Flag Register. Table Transmit FIFO Byte Count Register Table Endpoint Transmit Status Register. Table Port Status Register Table Port Status Change Register Table Notebook Register Table Address Register Table Interrupt Register. Table Interrupt Enable Register Table Status Configuration Register Table Endpoint Status Change Register. Table Port Index Register Jess Technology
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V0.99h
WT6561F
Device Controller with Table Port Control Register Table Port Status Register. Table Receive FIFO Data Register Table Receive FIFO Control Register Table Receive FIFO Flag Register. Table Receive FIFO Byte Count Register Table Endpoint Receive Status Register. Table Register Table Register. Table Register Table External Interrupt Direction Register Table External Interrupt Enable Register Table Watch-Dog Timer Extension Register Table Port Remote Wakeup Enable Register. Table PWM0 Duty Control Register Table Enable Register Table Lower Byte Register Table Upper Byte Register Table Lower Byte Register Table Enable/Disable pull-up PUPCTRLA Register Table Enable/Disable pull-up PUPCTRLB Register Table Enable/Disable byte channel Register Table Enable/Disable high byte channel Register. Table Enable/Disable Power Switch Pins Register Table PA,PD,PE output enable Register. Table Control Register. Table Interface Status Register Table Interface Control Register. Table Transmit/Receive Buffer Register Table Interface Address Register Table Electrical Characteristics. Table Absolute Maximum Rating Table Electrical Characteristics
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WT6561F
Device Controller with
Features
GENERAL DESCRIPTION
WT6561F embedded flash memory type micro-controller based Full Speed device with down stream Hub. contains 8051 CPU, bytes Flash, bytes SRAM, channels bits converter, PWMs, Interface. suitable combination peripheral functions with Hub, such X-Box game pad/joystick, game controller, keyboard etc.
FEATURES
8-bit 8051 compatible with operating frequency bytes Flash, bytes SRAM 6MHz crystal oscillator Universal Serial (USB) with upstream port, external downstream ports, internal downstream port embedded function. Complete Universal Serial specification compatible Connectivity behavior Power management, including suspend resume Device connect disconnect detection fault detection recovery Full speed device support Gang mode downstream port power enable Gang mode over-current detection Embedded function: Support USB1.1 Full Speed Functions Compliant Human Interface Devices (HID) specification specification. control endpoint, IN/OUT each with Bytes (8/16/32/64 bytes programmable) FIFO Interrupt endpoint, with Bytes(8/16/32/64 bytes programmable) FIFO Generic endpoints (IN/OUT programmable) each with Bytes(8/16/32/64 V0.99h
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WT6561F
Device Controller with bytes programmable) FIFO
channels 12-bit converter channels bits GPIO(minimum), (Maximum programmable pin) reset Fast mode master/slave interface (support 50/100/200 400KHz) Watch-dog timer (programmable ranged from 10ms 640ms) 16bit programmable timer
ORDERING INFORMATION
Package Type 48-pin LQFP 48-pin Part Number WT6561F-LQ48 WT6561F-N48 WT6561F-Die
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WT6561F
Device Controller with
Assignment Package Types
Name
VDDA VSSA PB0/AD0 PB1/AD1 PB2/AD2 PB3/AD3 PB4/AD4 PB5/AD5 PB6/AD6
Name
PB7/AD7 PD0/AD8 PD1/AD9 PD2/AD10 PD3/AD11/ADvref PD4/PWM0 PD5/PWM1 PD6/PWM2 PD7/PWM3 PA0/EXINT0 PA1/EXINT1 PA2/EXINT2 PA3/EXINT3 PA4/EXINT4 PA5/EXINT5 PA6/EXINT6
Name
PA7/EXINT7 PC4/SCL PC5/SDA XTAL1 XTAL2 RESET PE0/NUPE PE1/NOVI
Table WT6561F Signals Arranged Number
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WT6561F
Device Controller with
Description
Description PDIP LQFP Package)
LQFP Signal Name 3.3Volts output, Must connected capacitor larger) ensure proper operation differential line drivers. other lead capacitor must connected GND. plus data line upstream port. internal 1.5K pull-up resistor connected between this lead select full-speed operation. internal resistor controlled DPEN. minus data line upstream port. plus data lines downstream ports. external pull-down resistor must connected each these leads. minus data lines downstream ports. external pull-down resistor must connected each these leads. plus data lines downstream ports. external pull-down resistor must connected each these leads. minus data lines downstream ports. external pull-down resistor must connected each these leads. supply voltage, analog circuit Ground analog circuit Option GPIO Port, With Schmitt-trigger programmable pull-up resistor input mode. Option Input converter. Type Description
VDDA VSSA PB1/AD0 PB1/AD1 PB2/AD2 PB3/AD3 PB4/AD4 PB5/AD5 PB6/AD6 PB7/AD7
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WT6561F
Device Controller with
PD0/AD8 PD1/AD9 PD2/AD10 PD3/AD11/ ADVref /PWM0 PD5/PWM1 PD6/PWM2 PD7/PWM3 PA0/EXINT0 Option GPIO Port, With Schmitt-trigger programmable pull-up resistor input mode. Option 8-bit PWM. Option GPIO Port, With Schmitt-trigger pull-up resistor input mode. Option External interrupt. PA1/EXINT1 PA2/EXINT2 PA3/EXINT3 PA4/EXINT4 PA5/EXINT5 PA6/EXINT6 PA7/EXINT7 PC4/SCL PC5/SDA XTAL1 XTAL2 GPIO Port, With Schmitt-trigger pull-up resistor input mode. Option GPIO Port, With Schmitt-trigger pull-up resistor input mode. Option Hardware interface GPIO Port, With Schmitt-trigger pull-up resistor input mode. power supply voltage. Crystal oscillator input Crystal oscillator output. Note: (PD3/AD11/ADVref). programmed reference voltage (ADVref), then only channels used (i.e. AD[10:0]). otherwise, when channels will used, reference voltage VDDA.
Ground
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WT6561F
Device Controller with
RESET PE0/NUPE Reset input. Active high. This internal pull-down resister connected.
Option GPIO Port, With Schmitt-trigger pull-up resistor input mode. Option Downstream port power enable, active internal pull-up.
PE1/NOVI
Option GPIO Port, With Schmitt-trigger pull-up resistor input mode. Option Downstream port over-current detection, active internal pull-up. High Voltage used test mode operating 0~15V (not bonded) Analog pins used test mode operating 0~VDD. (not bonded)
TM[1:0]
Note: flash programming purpose, total pins used. They PB[7:0], PC[2:0], PD[7], PE[1:0], XTAL1, RESET, VDD, VSS. PE[7:2] shown core simply GPIO ports with Schmitt-trigger
pull-up resistor input mode.
Table WT6561F Signal Description
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WT6561F
Device Controller with
Configuration
SCL/PC4 SDA/PC5 XTAL1 XTAL2 RESET NUPE/PE0 NOVI/PE1 PA7/EXINT7 PA6/EXINT6 PA5/EXINT5 PA4/EXINT4 PA3/EXINT3 PA2/EXINT2 PA1/EXINT1 PA0/EXINT0 PD7/PWM4
PB0/AD0 PB1/AD1 PB2/AD2
WT6561F
Figure WT6561F 48-Pin Package
PD6/PWM2 PD5/PWM1 PD4/PWM0 PD3/AD11 PD2/AD10 PD1/AD9 PD0/AD8 PB7/AD7 PB6/AD6 PB5/AD5 PB4/AD4 PB3/AD3 Jess Technology
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WT6561F
Device Controller with
XTAL1 XTAL2 RESET PE0/NUPE PE1/NOVI PB0/AD0 PB1/AD1 PB2/AD2 PB3/AD3 PB4/AD4 PB5/AD5 PB6/AD6 PB7/AD7 PD0/AD8
WT6561F View Component mount board
PC5/SDA PC4/SCL PA7/EXINT7 PA6/EXINT6 PA5/EXINT5 PA4/EXINT4 PA3/EXINT3 PA2/EXINT2 PA1/EXINT1 PA0/EXINT0 PD7/PWM3 PD6/PWM2 PD5/PWM1 PD4/PWM0 PD3/AD11 PD2/AD10 PD1/AD9
Figure WT6561F 48-Pin Package
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WT6561F
Device Controller with
SCL/PC4 SDA/PC5 XTAL1 XTAL2 RESET NUPE/PE0 NOVI/PE1 PB0/AD0 PB1/AD1 PB2/AD2
WT6561F CORE
PA7/EXINT7 PA6/EXINT6 PA5/EXINT5 PA4/EXINT4 PA3/EXINT3 PA2/EXINT2 PA1/EXINT1 PA0/EXINT0 PD7/PWM3
Note: Three pads, TM[0], TM[1] foundry usage, shown figure.
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PD6/PWM2 PD5/PWM1 PD4/PWM0 PD3/AD11 PD2/AD10 PD1/AD9 PD0/AD8 PB7/AD7 PB6/AD6 PB5/AD5 PB4/AD4 PB3/AD3 Figure WT6561F Core Pads
V0.99h
WT6561F
Device Controller with
Functional Description
WT6561F physical entity that conjoins device downstream interface compound device with interface. functions device with 2-port hub. Operations interface device function controlled through external function registers (XFRs) special function registers (SFRs) SIE, HIU, SIL, FIFOs 8051 micro-controller that described following sections.
WT6561F Module
function interface manages communications between Host function. WT6561F interface consists full speed transceiver, serial engine (SIE), interface unit (HIU), system interface logic (SIL), transmit receive FIFOs. transceiver WT6561F provides physical interface lines. handles communication protocol USB. manages data transmission between upstream downstream ports. handles data transfers provides interface among SIE, 8051 function FIFOs. main blocks module are: Full Speed Transceiver: This on-chip transceiver having differential driver transmit data onto single ended receivers lines well differential receiver receive data signal bus. Serial Interface Engine (SIE): does front-end functions protocol such clock/data separation, sync-field identification, NRZI-NRZ conversion, token packet decoding, stripping, stuffing, NRZ-NRZI conversion, CRC5 checking CRC16 generation checking. Besides, manages detecting reset, suspend resume signals upstream port WT6561F wakeup system from suspend state. also provides serial-to-parallel conversion serial packet from full speed transceiver parallel data system interface logic V0.99h
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WT6561F
Device Controller with parallel data from system interface logic serial packet full speed transceiver. Interface Unit (HIU): processes packets transmission, detects each packet enable disable data line send packets both direction. System Interface Logic (SIL): operates conjunction with 8051 provide capabilities controlling operation FIFOs. also monitors status data transactions, transfers event control 8051 through interrupt requests appropriate moment, initiate resume signaling while WT6561F power-down mode. Operation controlled through external function registers. Device Function Hub-Function FIFOs: WT6561F device function interface four endpoints that support three types data transfer: control, interrupt bulk transfer. Transmit FIFOs written 8051 CPU, then read transmission. Receive FIFO written following reception, then read 8051 CPU. Endpoint supports control transfer configuration command status type communication flows between client software function. Endpoint 1/2/3 supports interrupt/bulk transfer. function endpoints supporting types data transfer: control interrupt. Endpoint contains FIFO transmit receive while endpoint used status-change notification only byte register used.
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WT6561F
Device Controller with
Micro-controller
8051 high performance 8-bit on-chip micro-controller running firmware associated with operation function. shown Figure -(TBD), features 16Kbyte Flash, 512-byte timers. addition, 8051 power saving modes enabling further power reduction. 16-bit Timer: WT6561F timers that clocked oscillator. programmed applications such periodically generating interrupt requests serving firmware watchdog timer. 8051 On-Chip Memory: 8051 provides on-chip program memory beginning location 0000H where, following chip reset, first instruction fetched executed from. 8051 also provides on-chip data beginning location 00H. Locations 00H-7FH accessed with direct, indirect addressing while locations 80H-FFH only accessed with indirect addressing. Locations 20H-2FH addressable.
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WT6561F
Device Controller with
WT6561F Address Space Mapping
WT6561F five address spaces program memory space, internal data memory space, special function register space, external function register space, register file. Table shows addressing mapping WT6561F. Memory Type Code External Function Register Embedded External Internal Data Size bytes bytes 192bytes bytes bytes bytes bytes Location 0000H-1FFFH 00H-3FH 40H-FFH 00H-7FH 80H-FFH 80H-FFH R0-R7 Data Addressing Indirect using MOVC instruction Indirect using MOVX instruction Indirect using MOVX instruction Direct, Indirect Indirect Direct Register
SFRs Register File Note: Direct: Direct Byte Addressing Indirect: Indirect Byte Addressing
Table Addressing Mapping
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WT6561F
Device Controller with
3.3.1 WT6561F Special Function Register Address Space
special function registers (SFRs) reside this optimized 8051 micro-controller core. Table lists location WT6561F SFRs. Please refer 8051 data sheet definition each SFR. Data Address Register Name PCON TCON TMOD Description Port Stack Point Data Point Data Point High Power Control Register Timer Control Register Timer Mode Register Timer Order Timer High Order Port Port Interrupt Enable Register Port Interrupt Priority Register Program Status Word Accumulator Register
Table WT6561F Special Function Register Layout
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WT6561F
Device Controller with
3.3.2 External Function Register Address Space
external function registers (XFRs) reside inside module. 8051 connected these registers when register addressed contents registers internal data memory. instructions, MOVX @Rr, MOVX used data movement between XFRs accumulator 8051.Table lists location XFRs. When instruction, MOVX @Rr, MOVX @Rr, executed, address contained registers latched signal then direction data movement between XFRs 8051 controlled signals subsequently generated 8051.
Clock Unit
WT6561F external clock on-chip oscillator with crystal ceramic resonator clock source. timing waveform XTAL1 provided on-chip oscillator employing external crystal resonator connected across XTAL1 XTAL2 external clock source connected XTAL1 frequency clock 6MHz normal operation, used internal input, then output 48MHz clock times full-speed bit-rate internal clock). shown Figure clock control section stopped where (IDL) power control register (PCON) firmware, thereby operation halted idle mode. Idle mode freezes clocks known states while peripherals continue clocked. status before entering idle mode preserved. contents SFRs, XFRs also retained. Idle mode used while device un-enumerated state following chip reset. Activation enabled interrupt logic high chip reset ways exit idle mode. Jess Technology
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WT6561F
Device Controller with
clock where controlled section peripherals that including some portions function stopped where (PD) power control register (PCON) firmware. Therefore both oscillator operation halted power-down mode. status before entering power-down mode preserved. addition, contents SFRs, XFRs also retained. suspend, firmware must WT6561F into power-down mode meet limitation Activation enabled interrupt logic high chip reset ways exit power-down mode.
Chip Peripherals XTAL1
Freq.=6 XTAL2 PCON[1] (Power Down Mode) USB_CLOCK 8051 Micro-controller PCON[0] (Idle Mode)
Figure Clock Circuit
Reset
Chip reset initiated built-in power reset (low voltage reset) USBinitiated reset, high level signal RESET least 100us while oscillator running. Built-in power reset circuit generate pulse reset entire chip. "low" voltage (VCC VLVR) causes reset condition entire chip prevent chip from being placed unknown state. Jess Technology
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WT6561F
Device Controller with
Power-down Mode Idle Mode
instruction that sets PCON.0 last instruction executed before idle mode activated. Once idle mode status preserved entirety. Activation enabled interrupt will cause PCON.0 cleared hardware then idle mode terminated. instruction that sets PCON.1 last executed prior entering power-down mode. Once power-down mode, oscillator stopped. contents on-chip RAM, Special Function Registers External Function Registers saved. Hardware reset activation enabled interrupt ways exiting power-down mode. Power-down mode should used suspend operation. PCON.1 interrupt caused active SUSPEND signal. WT6561F initiate resume signaling host through remote wakeup function while power-down mode. While power-down mode, remote wakeup initiated through assertion enabled interrupt. interrupt activated active SUSPEND signal, interrupt should enabled firmware prior entering power-down mode which terminated activation enabled interrupt signal enabled resume interrupt signal (RESUME). ISR, interrupt signal should disable before escaping from power-down mode. Upon completion ISR, program execution continues with instruction immediately following instruction that activated power-down. Note: "NOP" instructions after power-down instruction avoid code execution error.
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WT6561F
Device Controller with
Interrupt
There interrupt sources share external interrupt inputs 8051: Interrupt This interrupt connected external hardware interrupt input 8051. WT6561F, this interrupt used function interrupts (include suspend resume processing), interrupt vector 03H. Interrupt This interrupt connected external hardware interrupt input 8051. WT6561F, device function interrupts port-3 interrupts operate. normal operation, interrupt disabled. power-down mode support remote wakeup, interrupt enabled terminate power-down mode (suspend state). interrupt vector 13H.
Function Endpoint
WT6561F supports four device function endpoints. Endpoint contains FIFO each transmit receive. Endpoint endpoint programmed transmit receive. Endpoint handles control data transfer. Endpoint endpoint interrupt bulk transfer. EPINDEX register selects endpoint given data transaction. WT6561F supports function endpoints. Endpoint contains FIFO each transmit receive control data while endpoint used status-change only byte register available.
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WT6561F
Device Controller with
Transmit FIFOs
3.9.1 Transmit FIFOs Features
transmit FIFOs data buffers with following features (See Figure support data greater than 8/16/32/64 bytes (programmable counter setting) byte count register store number bytes data protection against overwriting data full FIFO capable retransmit current data
Write Pointer Read Pointer
Figure Transmit FIFO Outline (example bytes FIFO)
8051 writes FIFO location specified write pointer also used byte-counter indicate many bytes have been written read SIL. write pointer automatically increments after write decrements after read. read pointer points next FIFO location read SIL. read pointer automatically increments after read. transmit FIFO inhibited read when empty before data been successfully written into
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WT6561F
Device Controller with
3.12.2 Transmit Data Management
TXFULL TXFLG register, indicates data been written into FIFO ready transmission. Following reset, TXFULL TXEMP signifying empty FIFO. Only first eight bytes data which size greater than eight written into FIFO. this case, TXFULL until write TXCNT. case TXFULL farther writing TXDAT TXCNT ignored. Please note that content TXCNT determines number bytes transmitted over lines. Discrepancy between byte number written TXCNT number bytes actually written FIFO will cause unexpected result. Read FIFO prohibited when FIFO empty TXFULL events cause TXFULL updated: data written FIFO: writes bytes FIFO TXDAT writes number bytes TXCNT. TXFULL only after write TXCNT. TXCNT=0 indicates zero length transmission. this case, TXFULL TXEMP remains unchanged indicate FIFO still empty. This process illustrated Table data FIFO successfully transmitted: reads data from FIFO transmission. When good transmission acknowledged, TXFULL cleared TXEMP set. FULL Zero Length Transmission Write bytes TXDATx Data Written Write Ignored FULL
Write byte count TXCNTx
Table Writing Byte Count Register When good transmission completed, both read pointer write pointer advanced Jess Technology
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WT6561F
Device Controller with start point FIFO transmitting next data set. When transmission encountered, read pointer reversed start point FIFO enable re-read last data retransmission. pointer reversal advance accomplished automatically hardware. Table summarizes actions following transmission depend TXERR TXACK. TXERR TXACK Action Transfer Cycle operation Read Pointer Write Pointer both start point FIFO Read Pointer start point FIFO
Table Truth Table Transmit FIFO Management
3.12.3 Transmit FIFO Registers
TXDAT, transmit FIFO data register (see Table TXCNT, transmit FIFO byte count register (see Table TXCON, transmit FIFO control register (see Table TXFLG, transmit FIFO flag register (see Table These registers endpoint indexed. They used control operation transmit FIFO, associated with current endpoint specified EPINDEX register
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WT6561F
Device Controller with
3.13 Receive FIFOs
WT6561F receive FIFO Device endpoint This FIFO shared with transmit FIFO. Detail operating described section 5.15
3.13.1 Receive FIFO Features
receive FIFO data buffer with following features (see Figure support data greater than eight bytes byte count register accesses number bytes data flag signal full FIFO empty FIFO capability re-receive last data
Read Pointer
Write Pointer
Figure Receive FIFO Outline(example bytes FIFO) writes FIFO location specified write pointer also used bytecounter indicate many bytes have been written read 8051 CPU. write pointer automatically increments after write decrements after read. read pointer points next FIFO location read 8051 CPU. read pointer automatically increments after read. receive FIFO inhibited read 8051 when empty before data been successfully written into Jess Technology
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WT6561F
Device Controller with When SETUP token detected SIL, flushes FIFO even FIFO being read 8051 CPU.
3.13.2 Receive Data Management
RXFULL RXFLG register, indicates data been written into FIFO ready reception. Following reset, RXFULL RXEMP signifying empty FIFO. Only first eight bytes data which size greater than eight written into FIFO. RXFULL however until reception done successfully acknowledged. RXFULL cleared setting FFRC RXCON firmware indicate data successfully read CPU. case RXFULL farther writes FIFO ignored. Please note that content RXCNT should read 8051 determine numbers bytes need read from FIFO 8051 CPU. Further reading from empty FIFO ignored. RXFULL RXEMP Status Data being written FIFO Empty Data already written FIFO Zero length packet received
Table Status Receive FIFO Data When good reception completed data been successfully read 8051, firmware must FFRC RXCON advance write pointer read pointer start point FIFO receiving next data set. When reception completed, write pointer reversed position start point FIFO enable re-write last data re-reception. pointer advance reversal accomplished automatically hardware. Table summarizes actions following reception depend RXERR RXACK. RXERR RXACK Action Transfer Cycle operation Read Pointer Write Pointer start point FIFO when firmware sets FFRC RXCON V0.99h
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WT6561F
Device Controller with Write Pointer start point FIFO
Table Truth Table Receive FIFO Management
3.13.3 Receive FIFO Registers
RXDAT, receive FIFO data register (see Table RXCNT, receive FIFO byte count register (see Table RXCON, receive FIFO control register (see Table RXFLG, receive FIFO flag register (see Table These registers endpoint indexed. They used control operation receive FIFO associated with current endpoint specified EPINDEX register.
3.14 Setup Token Receive FIFO Handling
SETUP tokens received endpoint zero must acknowledged, even receive FIFO empty. described section 5.14, when SETUP token detected SIL, flushes FIFO sets STOVW RXSTAT reset locking read pointer. These prevent RXURF RXFLG read pointer from being receive FIFO flush occurs middle 8051 data read cycle. STOVW cleared EDOVW when SETUP packet been successfully acknowledged. read pointer will remain locked until both STOVW EDOVW bits cleared. SETUP packets only, firmware must clear EDOVW before reading data from FIFO. this done, data read from FIFO will invalid. After processing SETUP packet, firmware should always check STOVW EDOVW flags before setting RXFFRC bit. When SETUP packet either been being received, setting RXFFRC effect either STOVW EDOVW set.
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WT6561F
Device Controller with
3.15 Suspend Resume
order reduce power consumption, WT6561F automatically enters suspend state when observed traffic When suspend, 8051 peripherals power down mode, interrupt enabled support remote wakeup. entire chip consumes less than suspended state. WT6561F exits suspend mode when there activity. device also request host exits from suspend selective suspend using electrical signaling indicate remote wakeup. ability device signal remote wakeup optional. WT6561F allows host enable disable this capability. Device states described Figure
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WT6561F
Device Controller with
Reset
Un-enumerated
Device Configured
Interrupt
Idle/Application code Device function
Interrupt
Transmit Interrupt Interrupt
Transmit
Interrupt
Receive Interrupt Resume
Device interrupt disabled. Power-down mode terminated
Setup, Receive
Suspend Interrupt
Suspend
Resume Interrupt Device Remote Wake disabled. remote wake-up detected mode terminated
interrupts enabled power-down mode
Device Interrupt (remote wake-up)
Figure Suspend Resume State Diagram Jess Technology
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V0.99h
WT6561F
Device Controller with
External Function Registers
Data Address Register Name FADDR USBFI USBFIE SIEI (TEST) EPINDEX EPCON WDTRST TXDAT TXCON TXFLG TXCNT TXSTAT HPBSTAT HPSC NOTEBOOK HADDR USBHI USBHIE HSTAT HEPSC HPINDEX HPCON HPSTAT RXDAT RXCON RXFLG RXCNT RXSTAT Description Function Address Register Function Interrupt Register Function Interrupt Enable Register Interface Register Reserved Testing Endpoint Index Register Endpoint Data-flow Control Register Watchdog Timer Reset Register Transmit FIFO Data Register Transmit FIFO Control Register Transmit FIFO Flag Register Transmit FIFO Byte Count Register Endpoint Transmit Status Register Port Status Register Port Status Change Register Notebook Register Address Register Interrupt Register Interrupt Enable Register Status Configuration Register Endpoint Status Change Register Port Index Register Port Control Register Port Status Register Receive FIFO Data Register Receive FIFO Control Register Receive FIFO Flag Register Receive FIFO Byte Count Register Endpoint Receive Status Register Port (corresponding data Port (corresponding data Port (corresponding data
Jess Technology
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V0.99h
WT6561F
Device Controller with
Data Address
Register Name EXINTD EXINTEN WDTEXT RMPEN PWM0 PWM1 PWM2 PWM3 PWMEN AD_C PUCTRLB PUCTRLD ADCHENL ADCHENH PSWEN PAOE PDOE PEOE I2CCON I2CSTA I2CCON2 I2CTX I2CRX I2CADR
Description Rising/Falling Trigger Control External Intr. Enable/Disable Control External Interrupts Extension watch-dog timer Enable/Disable port Remote wakeup data data data data Enable PWMs data lower bits data upper bits control bits programmable pull-up programmable pull-up Channel enable select, Channel enable select, 11:8 Power Switch Control Output Enable Output Enable Output Enable Function Control (For Firmware only) Interface Status Register Interface Control Register Interface Transmit Buffer Register Interface Receive Buffer Register Interface Address Register
Table External Function Register Layout
Jess Technology
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V0.99h
WT6561F
Device Controller with
FADDR
Address: Reset State:
0000 0000B
Function Address Register. This holds address function. During enumeration, written with unique value assigned host. -Bit Number Mnemonic -FA6:0 FA6:0 Function Reserved: Write zero this bit. 7-bit Programmable Function Address: This register programmed through commands received endpoint configuration, which should only time firmware should change value this register. This register hardware read-only.
Table Function Address Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
USBFI
Address: Reset State:
x000 0000B
Function Interrupt Register. indicates that interrupt actively pending. bits cleared after read. RMPINT ADINT EXINT USBx 3INT USBx 2INT USBx 1INT Function (Remote wake interrupt enable) During suspend, enabled port (see RMPEN) detects "low", then RMPINT remote-wakeup processed Converter Interrupt flag. This when data converted External Interrupt Interrupt detected (Only occurs when EXINTEN interrupt Function Transmit/Receive Dong Flag endpoint Function Transmit/Receive Dong Flag endpoint Function Transmit/Receive Dong Flag endpoint Function Receive Dong Flag endpoint Function Transmit Done Flag endpoint USBRx 0INT USBTx 0INT
Number
Mnemonic RMPINT ADINT EXINT USBx3INT USBx2INT USBx1INT USBRx0INT USBTx0INT
Table Function Interrupt Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
USBFIE
Address: Reset State:
x000 0000B
Function Interrupt Enable Register. -ADINT_IE -USBx 3INT_IE USBx 2INT_IE USBx 1INT_IE Function ADINT Interrupt Enable Function Transmit/Receive Dong Interrupt Enable Enable USBx3INT Function Transmit/Receive Done Interrupt Enable Enable function transmit/receive done interrupt endpoint (USBx2INT). Function Transmit/Receive Done Interrupt Enable Enable function transmit/receive done interrupt endpoint (USBx1INT). Function Transmit Receive Done Interrupt Enable Enable function transmit receive done interrupt endpoint (USBRx0INT). Function Transmit Done Interrupt Enable Enable function transmit done interrupt endpoint (USBTx0INT). USBRx 0INT_IE USBTx 0INT_IE
Number
Mnemonic Reserved ADINT_IE Reserved USBx3INT_IE USBx2INT_IE USBx1INT_IE USBRx0INT_IE USBTx0INT_IE
Table Function Interrupt Enable Register
bits, means interrupt enabled will cause interrupt signaled micro-controller. means associated interrupt source disabled cannot cause interrupt.
Jess Technology
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V0.99h
WT6561F
Device Controller with
SIEI
Address: Reset State:
xxxx x000B
Interface Register. -Bit Number -Bit Mnemonic -USBRSTEN DPEN -USBRSTEN Function Reserved: Values read from these bits indeterminate. Write zeros these bits. Reset Enable: this enable reset. This should least 500µs after DPEN set. This reset reset. Enable: When this cleared, CEXT does provide 3.3V output high impedance state. this case, 1.5K resistor does connect line upstream port device disconnected. this normal operation. This reset reset. Wakeup: This used function initiate remote wakeup. firmware drive resume signaling lines host upstream hub. Cleared hardware when resume signaling done. DPEN WAKEUP
WAKEUP
Table Interface Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
EPINDEX
Address: Reset State:
1xxx xx00B
Endpoint Index Register. This Register identifies endpoint pair. contents select transmit receive FIFO pair serve index endpoint-specific XFRs. HORF Number -Bit Mnemonic HORF -EPINX1:0 -Function Hub/function Bit: Hub. Selects FIFOs XFRs. Function. Selects function FIFOs XFRs. Reserved: Values read from these bits indeterminate. Write zeros these bits. Endpoint Index: Endpoint Endpoint Endpoint Endpoint EPINX1 EPINX0
Table Endpoint Index Register
value this register selects associated bank endpoint-indexed XFRs including TXDAT, TXCON, TXFLG, TXCNT, TXSTAT, RXDAT, RXCON, RXFLG, RXCNT, RXSTAT EPCON.
Jess Technology
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V0.99h
WT6561F
Device Controller with
Address: Endpoint 001x 0101B Endpoint x0xx xx00B Function Endpoint 1,2,3 x0xx xx00B Endpoint Control Register. This configures operation endpoint specified EPINDEX. RXSTL TXSTL CTLEP -RXIE RXEPEN TXOE TXEPEN EPCON (Endpoint-indexed) Reset State: Number Mnemonic RXSTL Function Stall Receive Endpoint: this stall receive endpoint. Clear this only when host intervened through commands sent down endpoint When this RXSETUP clear, receive endpoint will respond with STALL handshake valid token. When this RXSETUP set, receive endpoint will NAK. This does affect reception SETUP token control endpoint. Stall Transmit Endpoint: this stall transmit endpoint. This should cleared only when host intervened through commands sent down endpoint When this RXSETUP clear, receive endpoint will respond with STALL handshake valid token. When this RXSETUP set, receive endpoint will NAK. Control Endpoint: this configure endpoint control endpoint. Only control endpoint capable receiving SETUP tokens. Reserved: Value read from this indeterminate. Write zero this bit. Receive Input Enable: this enable data from written into receive FIFO. cleared, endpoint will write received data into receive FIFO reception, will return handshake valid token RXSTL set. This does affect valid SETUP token. valid SETUP token packet overrides this cleared, place receive data FIFO. Receive Endpoint Enable: this enable receive endpoint. When disabled, endpoint does respond valid SETUP token. This hardware readonly highest priority among RXIE RXSTL. Note that endpoint enabled reception upon reset. Transmit Output Enable: This used enable data TXDAT transmitted. cleared, endpoint returns handshake valid token TXSTL set. Transmit Endpoint Enable: This used enable transmit endpoint. When disabled, endpoint does response valid token. This hardware readonly. Note that endpoint enabled transmission upon reset.
TXSTL
CTLEP -RXIE
RXEPEN
TXOE
TXEPEN
Table Endpoint Control Register Jess Technology
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V0.99h
WT6561F
Device Controller with
WDTRST
Address: Reset State:
xxxx xxxxB
Watchdog Timer Reset Register. After device reset, hardware watchdog cleared disabled. Write WDTRST register clear enable watchdog timer. watchdog timer overflows 10.9 overflows, initiates device reset. Firmware should write WDTRST clear before overflows. WDTRST7:0 Number Mnemonic WDTRST7:0 Function Watchdog Timer Reset (write-only): Write clear enable WDT.
Table Watchdog Timer Reset Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
TXDAT (Endpoint-indexed)
Address: Reset State:
xxxx xxxx
Transmit FIFO Data Register. Data transmitted FIFO specified EPINDEX first written this register. TXDAT7:0 Number Mnemonic TXDAT7:0 Function Transmit Data Byte (write-only): write data transmit FIFO, write this register. write pointer incremented automatically after write.
Table Transmit FIFO Data Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
TXCON (Endpoint-indexed)
Address: Reset State:
0xxx xxxxB
Transmit FIFO Control Register. Controls transmit FIFO specified EPINDEX. TXCLR Number -Bit Mnemonic TXCLR -Function Transmit Clear: Setting this flushes transmit FIFO, resets read/write pointers, sets EMPTY TXFLG, clears other bits TXFLG. After flush, hardware clears this bit. Reserved: Values read from these bits indeterminate. Write zeros these bits.
Table Transmit FIFO Control Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
TXFLG (Endpoint-indexed)
Address: Reset State:
xxxx 1000B
Transmit FIFO Flag Register. These flags indicate status data packets transmit FIFO specified EPINDEX. -Bit Number -Bit Mnemonic -TXEMP -TXEMP TXFULL Function Reserved: Values read from these bits indeterminate. Write zeros these bits. Transmit FIFO Empty Flag (read-only): Hardware sets this when data been read transmit FIFO SIL. Hardware clears this when empty condition longer exists. This always tracks current transmit FIFO status. This flag also when zero-length data packet transmitted. Transmit FIFO Full Flag (read-only): This flag indicates data present transmit FIFO. This after write TXCNT reflect condition data set. Hardware clears this when data been successfully transmitted. Transmit FIFO Under-run Flag (read-, clear-only)*: Hardware sets this flag when addition byte read from empty transmit FIFO. This sticky that must cleared through firmware writing this bit. When transmit FIFO under-runs, read pointer will advance remains locked empty position. Transmit FIFO Overrun Flag (read-, clear-only)*: This when additional byte written FIFO with TXFULL This sticky that must cleared through firmware writing this bit. When transmit FIFO overruns, write pointer will advance remains locked full position. TXURF TXOVF
TXFULL
TXURF
TXOVF
Table Transmit FIFO Flag Register
When set, transmission NAKed.
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V0.99h
WT6561F
Device Controller with
TXCNT (Endpoint-indexed)
Address: Reset State:
0000 0000B
Transmit FIFO Byte Count Register. This register stores number bytes data packet transmit FIFO specified EPINDEX. -Bit Number -Bit Mnemonic -TXCNT[5:0] TXCNT5 TXCNT4 Function Reserved: Write zeros these bits. Transmit Byte Count (write-only): number bytes data written transmit FIFO. When this register written, TXFULL set. Write byte count this register after writing data TXDAT. TXCNT3:0
Table Transmit FIFO Byte Count Register
send status stage after control write data control command null packet, write TXCNT.
Jess Technology
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V0.99h
WT6561F
Device Controller with
TXSTAT (Endpoint-indexed)
Address: Reset State:
0000 0000B
Endpoint Transmit Status Register. Contains current endpoint status transmit FIFO specified EPINDEX. TXSEQ Number -Bit Mnemonic TXSEQ -TXVOID Function Transmit Current Sequence (read, clear-only): This will transmitted next toggled valid handshake. This toggled hardware valid SETUP token. will handle sequence tracking. This should only used when initializing configuration interface. Reserved: Write zeros these bits. Transmit Void (read-only): void condition occurred response valid token. Transmit void closely associated with NAK/STALL handshake returned function after valid token, conditions that cause transmit FIFO unable ready transmit. this check NAK/STALL handshake returned function. This does affect USBTxxINT, TXERR TXACK bit. This updated hardware non-isochronous transaction response valid token. Transmit Error (read-only): error condition occurred with transmission. Complete partial data been transmitted. error following: Data transmitted successfully handshake received. Transmit FIFO goes into underrun condition while transmitting. corresponding transmit done when active. This updated hardware along with TXACK data transmission (this mutually exclusive with TXACK). Transmit Acknowledge (read-only): Data transmission completed acknowledged successfully. corresponding transmit done when active. This updated hardware along with TXERR data transmission (this mutually exclusive with TXERR). TXERR TXACK
-TXVOID
TXERR
TXACK
Table Endpoint Transmit Status Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
HPBSTAT (Port-indexed)
Address: Reset State:
xxxx xxxxB
port status register. This register indicates current status port DP/DM status. -Bit Number -Bit Mnemonic -DPSTAT DMSTAT -Function Reserved: Values read from these bits indeterminate. Status (read-only): Value port last frame. cleared hardware EOF2 point near frame Status (read-only): Value port last frame. cleared hardware EOF2 point near frame DPSTAT DMSTAT
Table Port Status Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
HPSC (Port-indexed)
Address: Reset State:
xxx0 0000B
Port Status Change Register. This register indicates change status port, including reset, overcurrent, suspend, enable connect status -Bit Number -Bit Mnemonic -RSTSC -RSTSC OVISC PSSC Function Reserved: Write zeros these bits. Reset Status Change (read-, clear-only): indicates reset port complete. indicates change. This hardware approximately msec after receipt port reset enable commend. Over-Current Indicator Status Change (read-, clear-only): This will hardware change detected overcurrent status, even condition goes away before detected firmware. Always when selecting ganged over-current report mode. Port Suspend Status Change (read-, clear-only): indicates resume process complete. indicates change. This hardware upon completion firmware-initiated resume process. Port Enable/Disable Status Change (read-, clear-only): indicates port enabled/disabled status change. indicates change. This hardware hardware events only. This indicates port disabled port error condition. Port Connect Status Change (read-, clear-only): indicates connect status change. indicates change. This hardware hardware connects disconnects. PESC PCSC
POVISC
PSSC
PESC
PCSC
Table Port Status Change Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
NOTEBOOK
Address: Reset State:
0000 0000B
Notebook Register. firmware test purposes. NOTEBOOK Number Mnemonic NOTEBOOK Function Notebook Register: This register write read time. reset reset.
Table Notebook Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
HADDR
Address: Reset State:
0000 0000B
Address Register. This holds address hub. During enumeration, written with unique value assigned host. -Bit Number Mnemonic -HA6:0 HA6:0 Function Reserved: Write zero this bit. 7-bit Programmable Address: This register programmed through commands received endpoint configuration, which should only time firmware should change value this register. This register hardware read-only.
Table Address Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
USBHI
Address: Reset State:
0000 0000B
Interrupt Register. Contains start frame, suspend, resume, Transmit Receive Done interrupt flags. indicates that interrupt actively pending. bits cleared after read. -SOF RESUME SUSPEND -HUBRx 0INT HUBTx 0INT
Number
Mnemonic -SOF RESUME SUSPEND -HUBRx0INT HUBTx0INT
Function Reserved: Write zero this bit. This hardware indicate that reception actual packet from internally generated from frame timer. detected RESUME signaling lines. This interrupt used terminate power-down mode. detected SUSPEND signaling lines. corresponding should whole chip into power-down mode. Reserved. Reserved: Write zeros these bits. Receive Done Flag endpoint Transmit Done Flag endpoint
Table Interrupt Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
USBHIE
Address: Reset State:
0000 xx00B
Interrupt Enable Register. NAKINT Number HTx0INT
SOF_IE
RESUME
SUSPEND
HRx0INT
Mnemonic NAKINT_IE
Function Interrupt Enable: this enable interrupt keyboard function even STALL handshake returned. Interrupt Enable. RESUME Interrupt Enable. SUSPEND Interrupt Enable. Reserved. Reserved: Values read from these bits indeterminate. Write zeros these bits. Receive Done Interrupt Enable Enable receive done interrupt endpoint (HUBRx0INT). Transmit Done Interrupt Enable Enable transmit done interrupt endpoint (HUBTx0INT).
SOF_IE RESUME_IE SUSPEND -HRx0INT_IE HTx0INT_IE
Table Interrupt Enable Register
bits, means interrupt enabled will cause interrupt signaled micro-controller. means associated interrupt source disabled cannot cause interrupt.
Jess Technology
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V0.99h
WT6561F
Device Controller with
HSTAT
Address: Reset State:
0011 0x0xB
Status Configuration Register. This contains bits configuration, remote wakeup, status status change indicators over-current. HCONFIG Number HRWUPE Mnemonic HCONFIG GANGP GANGI OVISC -Function Configuration: This indicates whether value configuration zero. While zero, will drive downstream ports. this when receives SetConfiguration() request with configuration value other than zero. Remote Wakeup Enable: suspended enabled request remote wakeup connect/disconnect event resume event when HEPSC. When `0', suspended blocks resume signaling connect disconnect detected downstream ports. Individual Gang power control mode selection. this ganged power control mode, clear this individual power control mode. Write this bit. Individual Gang over-current report mode selection. this ganged over-current report mode, clear this individual overcurrent report mode. Write this bit. Over-current Indicator Status Change (read-, clear-only): change detected over-current status, even condition goes away before detected firmware. Reserved: Value read from this indeterminate. Write zero this bit. Over-current Indicator (read-only): Hardware sets clears this OVI# input pin. indicates over-current condition. indicates normal power operation. Reserved: Value read from this indeterminate. Write zero this bit.
HRWUPE
GANGP GANGI OVISC -OVI
Table Status Configuration Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
HEPSC
Address: Reset State:
0000 0000B
Endpoint Status Change Register. -Bit Number -Bit Mnemonic -HEPSC3:0 -HEPSC3 HEPSC2 Function Reserved: Always zeros. Endpoint Status Change (read-only): Hardware communicates status changes host setting appropriate bit: HEPSC0: status change HEPSC1: port status change HEPSC2: port status change HEPSC3: port status change indicates status change indicates status change. When endpoint addressed token, entire byte sent least `1'. bits zeros, handshake returned. HEPSC1 HEPSC0
Table Endpoint Status Change Register
Setting port HPSC results hardware setting corresponding HEPSC. Bits cleared indirectly firmware clearing condition that caused status change.
Jess Technology
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V0.99h
WT6561F
Device Controller with
HPINDEX
Address: Reset State:
xxxx xx00B
Port Index Register. This register contains binary value port whose HPSC, HPSTAT HPCON registers accessed. -Bit Number -Bit Mnemonic -HPIDX1:0 -Function Reserved: Values read from these bits indeterminate. Write zeros these bits. Port Index Select: Port (internal port) Port Port HPIDX1 HPIDX0
Table Port Index Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
HPCON (Port-indexed)
Address: Reset State:
xxxx x000B
Port Control Register. Firmware writes this register power-off, power-on, disable, reset, suspend resume port. -Bit Number -Bit Mnemonic -HPCON2:0 -HPCON2 Function Reserved: Write zeros these bits. Encoded Port Control Commands: Power-off port Power-on port Disable port Reset enable port Suspend port Resume port HPCON1 HPCON0
Table Port Control Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
HPSTAT (Port-indexed)
Address: Reset State:
x000 0000B
Port Status Register. This register indicates current status port, including power, reset, suspend, low-speed device, enable, connect, over-current (valid when select individual power mode). -Bit Number LSSTAT Mnemonic -LSSTAT PPSTAT PRSTAT POSTAT PSSTAT Function Reserved: Values read from these bits indeterminate. Low-speed Device Attach Status (read-only): cleared hardware upon detection presence absence low-speed device. low-speed device attached. full-speed device attached. Port Power Status (read-only): cleared hardware based present power status port, controlled either firmware using HPCON register, overcurrent condition hardware. port powered port powered off. Port Reset Status (read-only): cleared hardware result initiating port reset writing HPCON. reset signaling currently asserted. reset signaling asserted. Port Over-Current Status (read-only): Hardware sets clears this OVI(1/2) input pin. indicates over-current condition. indicates normal power operation. Always when select ganged over-current report mode. Port Suspend Status (read-only): cleared hardware controlled firmware HPCON. port currently suspended. suspended. Port Enable/Disable Status (read-only): cleared hardware controlled firmware HPCON. port currently enabled. port disabled. Port Connect Status (read-only): cleared hardware reflect connect state port. device present port. device present. PESTAT PCSTAT
PPSTAT
PRSTAT
POSTAT
PSSTAT PESTAT PCSTAT
Table Port Status Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
RXDAT (Endpoint-indexed)
Address: Reset State:
xxxx xxxxB
Receive FIFO Data Register. Receive FIFO data specified EPINDEX stored read from this register. RXDAT7:0 Number Mnemonic RXDAT7:0 Function Receive Data Byte (read-only): write data receive FIFO, writes this register. read data from receive FIFO, 8051 reads from this register. write pointer read pointer incremented automatically after write read, respectively.
Table Receive FIFO Data Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
RXCON (Endpoint-indexed)
Address: Reset State:
0xx0 xxxxB
Receive FIFO Control Register. Controls receive FIFO specified EPINDEX. RXCLR Number -Bit Mnemonic RXCLR -RXFFRC -Function Clear Receive FIFO: this flush entire receive FIFO. flags RXFLG revert their reset states (RXEMP set; other flags clear). Hardware clears this when flush operation complete. Reserved: Values read from these bits indeterminate. Write zeros these bits. FIFO Read Complete: this release receive FIFO when data read complete. Setting this clears RXFULL RXFLG register) corresponding data that just read. Hardware clears this after RXFULL cleared. data from this data must have been read. Note that FIFO Read Complete only works STOVW EDOVW cleared. Reserved: Values read from these bits indeterminate. Write zeros these bits.
-RXFFRC
Table Receive FIFO Control Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
RXFLG (Endpoint-indexed)
Address: Reset State:
xxxx 1000B
Receive FIFO Flag Register. These flags indicate status data packets Receive FIFO specified EPINDEX. -Bit Number -Bit Mnemonic -RXEMP -RXEMP RXFULL Function Reserved: Values read from these bits indeterminate. Write zeros these bits. Receive FIFO Empty Flag (read-only): Hardware sets this when data been read receive FIFO. Hardware clears this when empty condition longer exists. This sticky always tracks current status. This flag also when zero-length packet received. Receive FIFO Full Flag (read-only): This flag indicates data present receive FIFO. Hardware sets this when data been successfully received. This cleared after write RXCNT reflect condition data set. Likewise, this cleared after setting RXFFRC bit. Receive FIFO Under-run Flag (read-, clear-only)*: Hardware sets this when additional byte read from empty receive FIFO. This cleared through firmware writing this bit. When receive FIFO under-runs, read pointer will advance remains locked empty position. Receive FIFO Overrun Flag (read-, clear-only)*: This when writes additional byte receive FIFO with RXFULL This sticky that must cleared through firmware writing this bit, although cleared hardware SETUP packet received after RXOVF error already occurred. When receive FIFO overruns, write pointer will advance remains locked full position. RXURF RXOVF
RXFULL
RXURF
RXOVF
Table Receive FIFO Flag Register
When set, transmissions NAKed.
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V0.99h
WT6561F
Device Controller with
RXCNT (Endpoint-indexed)
Address: Reset State:
0000 0000B
Receive FIFO Byte Count Register. This register used store number byte data packed received receive FIFO specified EPINDEX. -Bit Number -Bit Mnemonic -RXCNT[5:0] RXCNT5 RXCNT4 Function Reserved: Always zeros. Byte Count (read-only): number bytes data written receive FIFO. When this register written, RXFULL until reception successfully acknowledged. After writes data RXFIFO, writes byte count this register. 8051 reads byte count from this register determine many bytes read from RXFIFO. RXCNT3:0
Table Receive FIFO Byte Count Register
Jess Technology
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V0.99h
WT6561F
Device Controller with
RXSTAT (Endpoint-indexed)
Address: Reset State:
0000 0000B
Endpoint Receive Status Register. Contains current endpoint status receive FIFO specified EPINDEX. RXSEQ Number RXSETUP Mnemonic RXSEQ STOVW EDOVW -RXVOID Function Receive Endpoint Sequence (read, clear-only): This will toggled completion handshake response token. This will created) hardware after reception SETUP token. will handle sequence tracking. This should only used when initializing configuration interface. don't want change sequence bit, this when write this register. Receive Setup Token (read-, clear-only): This hardware when valid SETUP token been received. When set, this causes received token NAKed until cleared allow control transaction. token NAKed even endpoint stalled (RXSTL TXSTL) allow control transaction clear stalled endpoint. Clear this upon detection SETUP token after firmware ready complete setup stage control transaction. Start Overwrite Flag (read-only): hardware upon receipt SETUP token control endpoint indicate that receive FIFO being overwritten with SETUP data. When set, FIFO state (RXFULL read pointer) resets locked this endpoint until EDOVW set. This prevents prior, ongoing firmware read from corrupting read pointer receive FIFO being cleared data being written into This cleared hardware wazzu handshake phase transmission setup stage. This used only control endpoint. RXERR RXACK
RXSETUP
STOVW
Jess Technology
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V0.99h
WT6561F
Device Controller with
Number
Mnemonic EDOVW
Function Overwrite Flag (read-, clear-only): This flag hardware during handshake phase SETUP stage. after every SETUP packet received must cleared prior reading contents FIFO. When set, FIFO state (RXFULL read pointer) remains locked this endpoint until this cleared. This prevents prior, ongoing firmware read from corrupting read pointer after data been written into receive FIFO. This only used control endpoint. Note: Make sure EDOVW cleared prior reading contents receive FIFO. Reserved: Write zero this bit. Receive Void Condition (read-only): This when valid data received response SETUP token following conditions: receive FIFO still locked. EPCON register's RXSTL set. This cleared hardware. This updated hardware transaction response valid token. Receive Error (read-only): when error condition occurred with reception. Complete partial data been written into receive FIFO. handshake returned. error following conditions: Data failed check. stuffing error. receive FIFO goes into overrun underrun condition while receiving. This updated hardware valid SETUP token transaction. corresponding receive done when active. This updated with RXACK data reception mutually exclusive with RXACK. Receive Acknowledged (read-only): This when data received completely into receive FIFO handshake sent. This read-only updated hardware valid SETUP token transaction. corresponding receive done when active. This updated with RXERR data reception mutually exclusive with RXERR.
-RXVOID
RXERR
RXACK
Table Endpoint Receive Status Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
Address: Reset State:
0000 0000B
(corresponding read/write data Number Mnemonic PA[7:0] Function data
Table Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
Address: Reset State:
0000 0000B
(corresponding read/write data Number Mnemonic PD[7:0] Function data
Table Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
Address: Reset State:
0000 0000B
(corresponding read/write data Number Mnemonic PE[1:0] Function data
Table Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
EXINTD
Address: Reset State:
0000 0000B
External Interrupt Rising/Falling Trigger direction EXINTD7 Number EXINTD0
EXINTD6
EXINTD5
EXINTD4
EXINTD3
EXINTD2
EXINTD1
Mnemonic EXINTD[7:0]
Function Rising edge trigger Falling edge trigger
Table External Interrupt Direction Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
EXINTEN
Address: Reset State:
0000 0000B
External Interrupt Enable/Disable direction EXINTEN Number EXINTEN
EXINTEN
EXINTEN
EXINTEN
EXINTEN
EXINTEN
EXINTEN
Mnemonic EXINTEN[7:0]
Function Enable corresponding external interrupt EXINT Disable corresponding external interrupt EXINT
Table External Interrupt Enable Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
WDTEXT
Address: Reset State:
xx00 0000B
Extension Watch-Dog Timer -WDTEXT WDTEXT WDTEXT WDTEXT WDTEXT WDTEXT
Number
Mnemonic -WDTEXT[5:0]
Function Reserved 111111:Extend watchdog timer times 111110:Extend watchdog timer times 000011:Extend watchdog timer times 000010:Extend watchdog timer times 000001:Extend watchdog timer times 000000: watchdog timer extension.
Table Watch-Dog Timer Extension Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
RMPEN
Address: Reset State:
xxx0 0000B
Port Remote wakeup Enable Control -RMPEN4 RMPEN3 RMPEN2 RMPEN2 Function Reserved Port Remote-wakeup Enable Enable Disable Port Remote-wakeup Enable Enable Disable Port High nibble Remote-wakeup Enable Enable Disable Port nibble Remote-wakeup Enable Enable Disable Port Remote-wakeup Enable Enable Disable Port Remote-wakeup Enable Enable Disable RMPEN1 RMPEN0
Number
Mnemonic -RMPEN4 RMPEN3 RMPEN2H RMPEN2L RMPEN1 RMPEN0
Table Port Remote Wakeup Enable Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
PWM0
Address: Reset State:
0000 0000B
PWM0 Duty Control PWM0.7 Number PWM0.0
PWM0.6 Mnemonic PWM0[7:0]
PWM0.5
PWM0.4
PWM0.3
PWM0.2 Function
PWM0.1
Select 0/256 255/256 duty cycles extended pulse. Each cycle 1/12MHz width. 00000000: Duty cycle 00000001: Duty cycle 1/256 00000010: Duty cycle 2/256 00000011: Duty cycle 3/256 11111110: Duty cycle 254/256 11111111: Duty cycle 255/256
Table PWM0 Duty Control Register
PWM1 PWM2 PWM3 Address: Reset State: Address: Reset State: Address: Reset State: 0000 0000B 0000 0000B 0000 0000B
Function PWM1, PWM2, PWM3 same PWM0.
cycles 83.3ns
00000001: 00000010: 00000011: 00000100: 00000101: 00000110: 11111111: Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
PWMEN
Address: Reset State:
xxxx 0000B
Port Remote wakeup Enable Control -Bit Number -Bit Mnemonic -PWMEN3 PWMEN2 PWMEN1 PWMEN0 -PWMEN3 PWMEN2 PWMEN1 PWMEN0
Function Reserved PWM3 Enable Enable Disable PWM2 Enable Enable Disable PWM1 Enable Enable Disable PWM0 Enable Enable Disable
When PWMEN set, corresponding from PDOE(7:4) ignored corresponding from PD(7:4) output always.
Table Enable Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
Address: Reset State:
0000 0000B
Lower Byte Data ADB7 Number ADB6 Mnemonic ADB[7:0] ADB5 ADB4 ADB3 ADB2 Function Lower Data Byte ADB1 ADB0
Table Lower Byte Register
Address: Reset State:
0000 0000B
Lower Byte Data -Bit Number -Bit Mnemonic ADB[11:8] -ADB11 ADB10 Function Upper Data ADB9 ADB8
Table Upper Byte Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
AD_C
Address: Reset State:
0000 0000B
Lower Byte Data ADON Number ADEN Mnemonic ADON ADEN ADSEL[3:0] ADSEL3 ADSEL2 ADSEL1 ADSEL0 Function Disable power-down mode Turn Disable function Enable function 0000: Select input 0001: Select input 0010: Select input 0011: Select input 0100: Select input 0101: Select input 0110: Select input 0111: Select input 1000: Select input 1001: Select input 1010: Select AD10 input 1011: Select AD11 input Others: Invalid Select reference voltage circuit Select ADREF (AD11) reference input voltage circuit Reserved ADVREF_C
Note:
ADVREF_C
ADVref_C set, then only channels used. conversion time channel 125KHz clock cycles. conversion range from 50mV (VDD 50mV).
Table Lower Byte Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
PUPCTRLB
Address: Reset State:
1111 1111B
Enable/Disable Pull-up resisters Disable Enable PUAD7 Number PUAD6 Mnemonic PUAD7 PUAD6 PUAD5 PUAD4 PUAD3 PUAD2 PUAD1 PUAD0 PUAD5 PUAD4 PUAD3 PUAD2 Function Enable/Disable corresponding pull-up resisters PB7/AD7 Enable/Disable corresponding pull-up resisters PB6/AD6 Enable/Disable corresponding pull-up resisters PB5/AD5 Enable/Disable corresponding pull-up resisters PB4/AD4 Enable/Disable corresponding pull-up resisters PB3/AD3 Enable/Disable corresponding pull-up resisters PB2/AD2 Enable/Disable corresponding pull-up resisters PB1/AD1 Enable/Disable corresponding pull-up resisters PB0/AD0 PUAD1 PUAD0
Table Enable/Disable pull-up PUPCTRLA Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
PUPCTRLD
Address: Reset State:
1111 1111B
Enable/Disable Pull-up resisters Disable Enable PUPD7 Number PUPD6 Mnemonic PUPD7 PUPD6 PUPD5 PUPD4 PUAD11 PUAD10 PUAD9 PUAD8 PUPD5 PUPD4 PUAD11 PUAD10 Function Enable/Disable corresponding pull-up resisters PD7/PWM3 Enable/Disable corresponding pull-up resisters PD6/PWM2 Enable/Disable corresponding pull-up resisters PD5/PWM1 Enable/Disable corresponding pull-up resisters PD4/PWM0 Enable/Disable corresponding pull-up resisters PD3/AD11/ADVref Enable/Disable corresponding pull-up resisters PD2/AD10 Enable/Disable corresponding pull-up resisters PD1/AD9 Enable/Disable corresponding pull-up resisters PD0/AD8 PUAD9 PUAD8
Table Enable/Disable pull-up PUPCTRLB Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
ADCHENL
Address: Reset State:
0000 0000B
channel Enable/Disable Disable Enable ADCHEN Number ADCHEN
ADCHEN Mnemonic ADCHEN7 ADCHEN6 ADCHEN5 ADCHEN4 ADCHEN3 ADCHEN2 ADCHEN1 ADCHEN0
ADCHEN
ADCHEN
ADCHEN
ADCHEN
ADCHEN
Function Enable/Disable channel Enable/Disable channel Enable/Disable channel Enable/Disable channel Enable/Disable channel Enable/Disable channel Enable/Disable channel Enable/Disable channel
Table Enable/Disable byte channel Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
ADCHENH
Address: Reset State:
0000 0000B
channel Enable/Disable Disable Enable -ADCHEN ADCHEN Function Reserved Reserved Reserved Reserved Enable/Disable channel Enable/Disable channel Enable/Disable channel Enable/Disable channel ADCHEN ADCHEN
Number
Mnemonic -ADCHEN11 ADCHEN10 ADCHEN9 ADCHEN8
When ADCHENH enabled, corresponding from PDOE(3:0) ignored corresponding from PD(3:0) input mode always.
Table Enable/Disable high byte channel Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
PSWEN
Address: Reset State:
0000 0000B
Power-Switch Pins Enable/Disable Disable Enable -Bit Number -Bit Mnemonic -OVIEN -Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Enable/Disable Pin. Disable function, configured GPIO Enable function, input mode only PSWEN
When PSWEN set, corresponding from PEOE(1:0) ignored. result that PE(0) PE(1) output input mode, respectively.
Table Enable/Disable Power Switch Pins Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
PAOE
Address: Reset State:
0000 0000B
output enable PA7OE Number PA6OE Mnemonic PAxOE PA5OE PA4OE PA3OE PA2OE Function output enable Corresponding GPIO input Corresponding GPIO output Address: Reset State: Address: Reset State: 0000 0000B 0000 0000B PA1OE PA0OE
PDOE PEOE
Function PDOE PEOE same PAOE. Table PA,PD,PE output enable Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
I2CCON
Address: Reset State:
0000 0000B
Power-Switch Pins Enable/Disable Disable Enable -Bit Number -Bit Mnemonic -I2CINTEN I2CINT -Function Reserved Reserved Reserved Reserved Reserved Reserved Enable/Disable Interrupt Disable Enable Interrupt Interrupt Interrupt I2CINTEN I2CINT
Table Control Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
I2CSTA Read Only Interface Status Register -Bit Number -Bit Mnemonic SFIRST SSTOP RXNAK2 I2CRDY SFIRST SSTOP
Address: Reset State:
0010 0010B
Function
RXNAK2
I2CRDY
Reserved Reserved busy idle. Both pins keep high level after STOP condition This when received START first byte slave mode This when received STOP condition slave mode Received slave mode Read command received Write command received NACK received received This when byte received, transmitted STOP condition detected
Table Interface Status Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
I2CCON2 Write Only Interface Status Register ENI2C Number MCLK1 Mnemonic ENI2C MCLK1 MCLK0 MCLK0 MSTR MSTOP
Address: Reset State:
0000 0010B
I2CRW Function
TXNAK2
SLAVE
MSTR MSTOP I2CRW
TXNAK2 SLAVE
Enable/Disable Enable function Disable function, Pins configured GPIO Select clock master mode 400KHz 100KHz 50KHz 200KHz Output START condition master mode when this Output STOP condition master mode when this Master mode: Transmitter Receiver Slave Mode Receiver Transmitter Output NACK Output ACK. will pull SDA2 acknowledge Slave Mode Master Mode
Table Interface Control Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
I2CTX (Write Only) I2CRX (Read Only)
Address: Address: Reset State:
xxxx xxxx
Interface Transmit/Receive Buffer Register MTX7 MRX7 Number MTX6 MRX6 Mnemonic MTX[7:0] MRX[7:0] MTX5 MRX5 MTX4 MRX4 MTX3 MRX3 MTX2 MRX2 Function Master Transmit/Receive Data MTX1 MRX1 MTX0 MRX0
Table Transmit/Receive Buffer Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
I2CADR Write Only Interface Address Register SAR7 Number SAR6 Mnemonic SAR[7:0] SAR5 SAR4 SAR3
Address: Reset State:
xxxx xxxx
SAR2 Function Slave Address SAR1 SAR0
Table Interface Address Register
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
Target Specification
(VCC=5V, GND=0V, TA=25°C, Fosc=6MHz, unless otherwise noted)
Parameter Active current Power-down current Input high voltage (except XTAL1, RESET) Input high voltage (XTAL1, RESET) Input voltage (except RESET) Input voltage (RESET) Output high voltage VCC-0.3 VCC-0.7 VCC-1.5 Output voltage voltage reset Input high leakage current RESET pull-down resistor Input pull-up resistor capacitor (except XTAL1, XTAL2, RESET) VLVR RRST 0.45 VIL=0V VIH=5V IOH=-25µA (Note) IOH=-65µA (Note) IOH=-100µA (Note) IOL=4mA (Note) VIL1 -0.5 VIH1 0.7VCC VCC+0.5 Symbol 0.2VCC+0.9 Min. Typ. Max. VCC+0.5 Unit Condition
Note Needs external pull-up resistor Table Electrical Characteristics
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h
WT6561F
Device Controller with
supply voltage Input Output voltage Operating ambient temperature Storage temperature Operating voltage (VCC)
-0.3V +7.0V GND-0.2V +0.2V -0°C +70°C -55°C +125°C +4.0V 5.25V
Table Absolute Maximum Rating
TCLCH VCC+0.5 0.7VCC
0.45V
TCHCX
TCLCX
TCLCL 0.2VCC-0.1 TCHCL
Figure External Clock Drive Waveform Parameter Oscillator frequency High time time Rise time Fall time Power reset internal high time Note pull-up resistor, C=50pF Symbol 1/TCLCL TCHCX TCLCX TCLCH TCHCL TPOR Min. 5.94 0.35 TCLCL 0.35 TCLCL Max. 6.06 0.65 TCLCL 0.65 TCLCL Units
Table Electrical Characteristics
Jess Technology
Suites 2202-7, 22/F Tower6, Gateway, Tsimshatsui, Kowloon, Hong Kong TEL:852-2123 3289 FAX:852- 2123 3393 Page
V0.99h

Device Controller with WT6561F Embedded Controller with

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