V0.97 DESCRIPTION WT5082 high-performance, low-cost, CMOS 8-bit s
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WT5082
V0.97 DESCRIPTION
WT5082 high-performance, low-cost, CMOS 8-bit single-chip micro-controller with POCSAG decoder12KB SRAM 296KB 56x32 56x33 dot-matrix driver embedded, which suitable information paging applications, especially when large number dots large SRAM space needed, such Chinese character display pagers.
This chip 8-bit CPU, RAM, ROM, I/Os, timers/counters, interrupt controller, driver watchdog timer. suitable portable battery-powered applications, power saving function included.
FEATURES POCSAG pager code decoder Single crystal support 512, 1200 2400 baud rates 76.8kHz crystal Support RICs addresses independent frame numbers Support partial address match facility address 260k addresses provided control lines PLL, quick charge enable Build data filter 16-times over-sampling data clock recovery Interrupt 6502 when there status change interrupt mode send received message data 8-bit single chip Microcontroller with 56x32 56x33 driver 12Kbytes SRAM bits display SRAM Kbytes character pattern 32Kbytes program 8Kbytes test program Wide voltage operating range from Built-in Ring Oscillator with maximum frequency port pins) Input port pins Input/output port pins Watchdog Timer Operating current 0.5mA 1MHz providing standby mode wake-up mode Ring 76.8KHz X'tal current consumption
WT5082
V0.97 Both 1Mhz 76.8KHz X'tal OFF: current consumption Dual timer counters 7-bit external port interrupt wake-up interrupt l-bit external port interrupt 6502 battery remove detect flex decoder 32bit UART( bits signal function 2.2V threshold automatic power reset 2.0V power reset Package: Chip form 128-pin LQFP 14mm 14mm 1.4mm
PACKAGE OUTLINE
WT5082
V0.97 BLOCK DIAGRAM
WT5082
V0.97 FUNCTION 128-pin LQFP
WT5082
BIAS BIAS EPI4 EPI5 RFDI EPI0 EPI3 RESETB XOUT ROSC Ptimer0 Ptimer1 768KO TEST COM0
Output Output Output Output Input Output Output Output Input Input Output Output Input Input Input Input Output Input Output Input Output
Power Source segment output common output common output ICON bias voltage output voltage supply RO*2 pumping capacitor pumping capacitor EPI4 Battery detect EPI5 Battery detect General Lamp output General output Serial UART serial output General General EEPROM General EEPROM General EEPROM DATA General EEPROM control signal output enable MISO input Serial General input Serial EPI6 UART Serial Input control signal output enable MISO input Serial control signal output output signal data input General port Input port EPI7 signal output 4-bit input port External interrupt general input System reset signal input active Ground Crystal input Crystal output Power source Resistor ring oscillator General port output from ptimer0 General port output from ptimer1 76.8KHz clock output FLEX decoder Enable control signal Test pin. High active common output
V0.97 APPLICATION DIAGRAM
WT5082
V0.97
WT5082
SECTION MEMORY CONFIGRATION MEMORY INTERNAL MEMORY CONFIGRUATION
MEMORY ADDRESS $0000 $004F $0050 $00FF $0100 $01FF $0200 $2EFF $2F19 $3F18 $3F19 $3FF8 $3FF9 $3FFF $4000 $5FFF $6000 $7FFF $8000 $FFF1 $FFFA $FFFF
FUNCTION PORT REGISTERS INTERNAL SRAM 6502STACK SRAM Reserved Display SRAM Buffer Icon SRAM Buffer Font Window1 Font Window2 PROGRAM INTERRUPT ECTOR
ADDRESS SPACE bytes
Vector address $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF
Vector type vector Reset vector vector
V.0.97
WT5082
ADDR
NAME Port P0DIR Port P0CFG Port Data P0DAT Port P1CFG Port Data P1DAT Port Direction P2DIR Port configuration P2CFG Port Data P2DAT Whtchdog Timer Control WDTCTL Port Timer0 Control PT0CTL Port Timer0 Preload Data PTIME0 Port Timer0 Count value TIMER0 Port Timer1Control PT1CTL Port Timer1 Preload Data PTIME1 Port Timer1 Count value TIMER1 Halt register HALT
Read Write
number P07D P07C P27D P27C EPT0 PT07 EPT1 PT17 P06D P06C P26D P26C PT06 PT16 P15C P25D P25C PT0S PT05 PT1S PT15 P04C P14C P24D P24C OPT0 PT04 OPT1 PT14 P03D P03C P13C P23D P23C PT03 PT13 PT02 PT12 P02D P02C P12C P22D P22C P01C P11C P21D P21C WCK1 PTS01 PT01 PTS11 PT11 P00C P10C P20D P20C WCK0 PTS00 PT00 PTS10 PT10
WT5082
V.0.97
ADDR
NAME Time Base Timer Control BTCTL Time Base Timer Preload data BTIME Time Base Counter Value TIMERB timer control RTCCTL Hour register Hour Minute register Minute Minute register Second Interrupt Mask IRQMK Interrupt Status IRQSR Interrupt Mask EPIMK Interrupt Status EPISR Inverse signal IEP1 P_decoder Interrupt Mask PDIMK P_decoder Interrupt Status PDISR Expand Window0 Address ROMWinADR0 Expand Window1 Address ROMWinADR1
Read Write
number FEP1 MRTC FRTC EEP16 EP16 IEP16 EPD16 PD16 RT11 MSIO FSIO EEP15 EP15 IEP15 EPD15 PD15 RT10 MRT1 FRT1 EEP14 EP14 IEP14 EPD14 PD14 W0A4 W1A4 MRT0 FRT0 EEP13 EP13 IEP13 EPD13 PD13 W0A3 W1A3 EEP12 EP12 IEP12 EPD12 PD12 W0A2 W1A2 BTS1 RT01 MPT1 FPT1 EEP11 EP11 IEP11 EPD11 PD11 W0A1 W1A1 BTS0 RT00 MPT0 FPT0 EEP10 EP10 IEP10 EPD10 PD10 W0A0 W1A0
EEP17 EP17 IEP17
EPD17 PD17
WT5082
V.0.97
ADDR
NAME P_decoder Control PDCTL P_decoder Receive Data PDDR P_decoder mode Address pointer byte PDDRpH
Read Write
number
LostSync
ErrorFlag
PDD4 PDA4
EPDMA PDD3 PDA3
REON PDD2 PDA2
PDEOM PDD1 PDA1
PDON PDD0 PDA0
OverRange PDD7 PDA7
PDD6 PDA6
PDD5 PDA5
PDDR mode Address pointer high byte Base Address MPDDRp PDDRp pointer mask MPDDRp P_decoder mark PDEOM Dis[play Control LCDCTL Serial Control SIOCTL Data Buffer SIOB0 Data Buffer SIOB1 Data Buffer SIOB2 Data Buffer SIOB3 UART Control UARTCTL Control PWMCTL Data Buffer PWMB System Clock Control CKCTL
PDBA3
PDBA2
PDBA1
PDBA0
PDA9
PDA8
EOM7 SIOE
ADCL EOM6
LCDPMP
EOM5 LCDDC SIOB05 SIOB13 SIOB21 SIOB29
EOM4 LCDI SIOB04 SIOB12 SIOB20 SIOB28
MPDA9 MPDA8 MPDA7 MPDA6 EOM3 FRQS3 SIOB03 SIOB11 SIOB19 SIOB27 Plndex3 EOM2 FRQS2 EOM1 FRQS1 EOM0 FRQS0 SCKO SIOB00 SIOB8 SIOB16 SIOB24
UART_TX
SIOB06 SIOB14 SIOB22 SIOB30
SIOB07 SIOB15 SIOB23 SIOB31 EUART EPWM
SIOB02 SIOB01 SIOB10 SIOB9
SIOB18 SIOB17 SIOB26 SIOB25 Plndex2 Plndex1
RX_FULL TX_Empty PWM_TX
ClrPadr
Plndex0
PWMB7 PWMB6 PWMB5 PWMB4 PWMB3 PWMB2 PWMB1 PWMB0 PLL4 PLL3 PLL2 PLL1 PLL0
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WT5082
ADDR
NAME P_DECODER CONFIGURATION PDCONF0 P_DECODER CONFIGURATION PDCONF1 P_DECODER CONFIGURATION PDCONF2 P_DECODER CONFIGURATION PDCONF3 P_DECODER CONFIGURATION PDCONF4 P_DECODER CONFIGURATION PDCONF5 P_DECODER CONFIGURATION PDCONF6 P_DECODER CONFIGURATION PDCONF7 P_DECODER CONFIGURATION PDCONF8 P_DECODER CONFIGURATION PDCONF9 P_DECODER CONFIGURATION PDCONF10 P_DECODER CONFIGURATION PDCONF11 P_DECODER CONFIGURATION PDCONF12 P_DECODER CONFIGURATION PDCONF13 P_DECODER CONFIGURATION PDCONF14 P_DECODER CONFIGURATION PDCONF15
Read Write
number FCA1 FCB1 FCC1 FCD1 FCE1 FCA0 FCB0 FCC0 FCD0 FCE0
V0.97
WT5082
ADDR
NAME P_DECODER CONFIGURATION PDCONF16 P_DECODER CONFIGURATION PDCONF17 P_DECODER CONFIGURATION PDCONF18 P_DECODER CONFIGURATION PDCONF19 P_DECODER CONFIGURATION PDCONF20 P_DECODER CONFIGURATION PDCONF21 P_DECODER CONFIGURATION PDCONF22 P_DECODER CONFIGURATION PDCONF23 P_DECODER CONFIGURATION PDCONF24 P_DECODER CONFIGURATION PDCONF25 P_DECODER CONFIGURATION PDCONF26 Reserved P_Decoder Status Test PSTAT
Read Write
number MF16 MF17 MF10 MF11 MF12 FCF1 MF13 FCF0 MF14 MF15
Test only
WT5082
V.0.97 SECTION INPUT OUTPUT PORTS
WT5082 consists three parallel ports, namely And, these entire ports served multiple purposes depend port configuration. port reset input mode.
SECTION PORT
Port bits input output port. functions listed below controlled individual register. function enabled when input. Port Ptimer0 Ptimer1 RFDI Output Output Input Function control signal output output serial control signal output quick charge MOSI output serial General output port output from ptimer0 General output port output from ptimer1 signal data input General EPI6 General EPI7
P0DIR Port Direction Register reset value 0xFF Address P07D P06D P03D P02D
P0CFG Port Configuration Register reset value 0x00 Address P07C P06C
P04C P03C P02C P01C P00C
WT5082
V.0.97 P0DAT Port Data Register reset value 0x00 Address
used output only with control signal Serial I/O. User SIOE enable works with Serial function. SIOE P00C P01C Function Port control output with Push-pull control output with open drain Serial output with Push-pull Serial output with open drain
used input output with general output Ptimer output. User EPT0 EPT1 enable works with Ptimer output. P02D P03D OPT0 OPT1 P02C P03C
Function Port General output with Push-pull General output with open drain Ptimer output with Push-pull Ptimer output with open drain General input without pull-up General input with pull-up
input only signal Input. P04C
Function Port Input without pull-up Input with pull-up
WT5082
V.0.97 used multi-function with general input. EPI6 EPI7 make works with interrupt. Disable EPI6 EPI7 works with general port. P06D P07D P06C P07C
EPI6 EPI7
Function Port General output with Push-pull General output with open drain General input without pull-up General input with pull-up input without pull-up input with pull-up
WT5082
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SECTION 3.2.1 PORT External interrupt input port
served External Port Interrupt Function, configuration programmed P1CFG.
P1CFG Port configuration Register reset value 0x00 Address P15C P14C P13C P12C P11C P10C
P10C P15C
Function Port P10C P15C Input without pull-up Input with pull-up
P1DAT Port data Register reset value 0x00 Address
also connect interrupt input when EPDI7 enable EPI5 disable. used Battery detect. User connect with borad signal, will automatically detect when active.
WT5082
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SECTION PORT general input output port
Port.P2 used general I/O. User program communicate with EEPROM Flex Decoder. direction P2DIR. with without open-drain setting PWCFG. Input with without pull-up same way. P2DAT Port Data Register reset value 0x00 Address
P2DIR Port direction Register reset value 0xFF Address P27D P26D P25D P24D P23D P22D P21D P20D
P2CFG Port configuration Register reset value 0xFF Address P27C P2Xd P26C P2xC P25C P24C P23C P22C P21C P20C
Function Port Output with Push-pull Output with open drain Input without pull-up Input with pull-up
WT5082
V.0.97 SECTION RELATIVE MODULES
WT5082 includes 6502 module this section describes some 6502 functions that relative WT5082 application.
SECTION HALT CONTROL
HALT HALT Control register reset value 0x00 Address
write operation except interrupt routine this address will stop clock source module interrupt call will restart clock source.
SECTION CLOCK SOURCE
CKCTL System Clock Control register reset value 0x00
WT5082
Address PLL4 PLL3 PLL2
PLL1 PLL0
Where CKCTL register defines clock source 6502 module
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clock sources selection clock source 76.8K 38.4K 153.6K 307.2K
Before switch Clock source must PLL0 first. select output frequency following table. User choose Ring select PLL4 PLL0 equal other value PLL4 PLL0 will work with PLL. output clock table PLL4 PLL3 PLL2 PLL1
PLL0
RingOSC
WT5082
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SECTON CHIP RESET
module reset from four sources, namely external RESETB pin, automatic voltage power reset module, watchdog timer reset 2.0V power reset.
RESETB only external reset source, connected with Schmidt trigger input gate improve noise figure Schmidt trigger. Whenever RESETB pulled low, reset operation active until this changed high.
automatic power reset module internal 2.2V voltage detector module, generates power reset pulse when power under voltage threshold value. watchdog timer reset generated when watchdog time threshold value reached. programming function watchdog timer introduced next section. lowpower reset will automatically detect VDD. When under 2.0V, will generate reset signal chip reset. normally works with
CHIP RESET SOURCE DIAGRAM
WT5082
V.0.97
SECTION WATCHDOG TIMER
watchdog timer controlled WEN-bit WDTCTL register, clock source from fWTCK watchdog timer clock Frequencies this clock defined WCK1 WCK0 WDTCTL register. Whenever accesses WDTCTL register, watchdog timer counter will reset zero.
WDTCTL Watchdog Timer Control register reset value 0x00
Address
WCK1 WCK0
WCK1
WCK0
Watchdog timer active cycle second second second
WT5082
second
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SECTON TIMER MODULE PTIMER TIME BASE
There timer modules WT5082M, namely ptimer ptimer1, time base timer real time clock PTIMER generate interrupt when timer reloaded after counting value reaches zero. User programming preload timer values into PTIME0 PTIME1 registers, then enable these timer modules. clock source these timers selected from PTS11, PTS10, PTS01 PTS00 PT0CTL PT1CTL register. Both timers also serve counter function, counter value obtained from TIMER0 TIMER1 registers.
PT0CTL PORT TIMER CONTROL register reset value 0x00
Address EPT0 PT0S
OPT0 PTS01 PTS00
WT5082
PTIME0 PORT TIMER PRELOAD DATA reset value 0x00
Address PT07 PT06 PT05
PT03 PT02 PT01 PT00 PT04
TIMER0 PORT TIMER COUNTER VALUE reset value 0x00
Address
TIMER0 PORT TIMER COUNTER VALUE reset value 0x00
Address EPT1 PT1S
OPT1 PTS11 PTS10 V.0.97
PTIME1 PORT TIMER PRELOAD DATA reset value 0x00
Address PT17 PT16 PT15
PT13 PT12 PT11 PT10 PT14
TIMER1 PORT TIMER COUNTER VALUE reset value 0x00
Address
WT5082
PTOCTL PT1CTL registers control port timer timer enabling not. PTS11, PTS10, PTS01, PTS00 data bits PT0CTL PT1CTL registers define clock source PTIME0 PTIME1 clock counter. PT0S, PT1S registers define output waveform normal inverse.
EPT1
EPT0
Function Enable Port Timer PTIME Disable Port Timer PTIME Enable Port Timer PTIME Disable Port Timer PTIME
When Disable Ptimer.0 Ptimer.1, will output High
PT1S
PT0S
Function Inverse Output Waveform PTIME1 Normal Output Waveform PTIME1 Inverse Output Waveform PTIME0 Normal Output Waveform PTIME0 v.0.97
OPT1
OPT0
Function Enable output with Ptimer1 Disable output with Ptimer1 Enable output with Ptimer0 Disable output with Ptimer0
PTS01
PTS00
PTIME0 clock source when 32.768khz 76.8khz 76.8k 153.6k fPTIME1 clock from PTIME1
WT5082
256hz
PTS11
PTS10
PTIME1 clock source when 32.768khz 76.8khz 76.8k 307.2k 512hz 256hz
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WT5082
v.0.97 Time base timer timer timer controlled BTCTL RTCCTL registers. BTCTL enables Time base timer BTS1 BTS0 bits define clock source time base timer. While reload timer value given TIMERB register, counter value time base timer obtained from BTIME register. RT11 RT10 bits RTCCTL register define RTC1 interrupt clock source, RT01 RT00 bits define RTC0 interrupt source. convenience sake, also provide Hour, Minute, Second register display time. User program Hour, Minute, Second. suggest that user write Hour register before programming. time counting unless there interrupt minute order refresh Date, Month, Year system application. more detail Section4.6.
WT5082
BTCTL Time base timer control register reset value 0x00
Address
BTS1 BTS0
BTIME Time base timer preload data reset value 0x00
Address
TIMERB Time base counter value reset value 0x00
Address
RTCCTL timer control reset value 0x00
Address RT11
RT10 RT01 RT00 v.0.97
BTS1
BTS0
Function Clock source Time base timer disable Time base timer enable 1024hz 256hz 64hz
WT5082
16hz
RT11 RT01
RT10 RT00
Clock source 32hz
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Hour Hour register reset value 0x00
Address
WT5082
Minute Minute register reset value 0x00
Address
Second Second register reset value 0x00
Address
SECTION INTERRUPT SOURCE
interrupt source connected with P_DECODER module, interrupt source connected with other timer external interrupt input.
SOURCE DIAGRAM
POSCAG DECODER PDI, EPI5 interrupt EPI5 EPI0 EPI5 EPI6 EPI7 PTIMER TIME BASE TIMER PDI, EPI5 interrupt
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Interrupt vector address
Vector Address
Interrupt Source interrupt
FFFAH FFFBH
WT5082
FFFCH FFFDH FFFEH FFFFH
Reset
Interrupt mask registers
IRQMK interrupt mask register reset value 0x00
Address MRTC MSIO
MRT1 MRT0 MPT1 MPT0
EPIMK interrupt mask register reset value 0x00
Address EEPI7 EEPI6 EEPI5
EEPI4 EEPI3 EEPI2 EEPI1 EEPI0
PDIMK P-decoder Interrupt Mask register reset value 0x00
Address EPDI7 EPDI6 EPDI5
EPDI4 EPDI3 EPDI2 EPDI1 EPDI0
NOTE PDECODER interrupt connect with interrupt
v.0.97 Interrupt status registers
IRQSR interrupt status register reset value 0x00, reset after read
Address
WT5082
FEPI
FRTC
FSIO
FRT1
FRT0
FPT1
FPT0
NOTE
read operation IRQSR will clear IRQSR data bits except FEPI FEPI will reset when EPISR cleared zero.
EPISR interrupt status register reset value 0x00, reset after read
Address EPI7
NOTE
EPI6 EPI5 EPI4 EPI3 EPI2 EPI1 EPI0
read operation EPISR will clear EPISR data bits. EPI5 also connect when EPDI7 enable EEPI5 disable
PDISR P-Decoder interrupt status register reset value 0x00, reset after read
Address PDI7
NOTE
PDI6 PDI5 PDI4 PDI3 PDI2 PDI1 PDI0
read operation PDISR will clear PDI0 PDI7
INTERRUPT DEFINITION Interrupt PTIMER 0/1, Time Base timer, EPI, 0/1, Minute interrupt generated input (External Port Interrupt, used wakeup interrupt), time base timer, port timer 0/1, clock interrupt. P10-PI7 pins service basic functions: External Port Interrupt input pins general-purpose input pins. EPI.4 default used will automatically detect battery voltage when active EPI.5 also connect .0.97 interrupt input when EEPI5 diable EPDI7 enable. other function enabled falling edge detected enabled input, EPIx-bit EPISR register
WT5082
EEPIx-bit EPIMK register enabled, interrupt generated 6502. Each input enabled disabled corresponding EEPIx-bit EPIMK register, usage function does affect input function port user status from EPISR data register.
IRQSR interrupt status register clear after read
FEPI FRTC FSIIO FRT1 FRT0 FPT1 FPT0 Interrupt status Ptimer interrupt Ptime interrupt Time base timer interrupt interrupt interrupt There interrupt Minute interrupt There interrupt
note when FEPI EPISR status
IRQMK interrupt mask register status
MRTC MSIO MRT1 MRT0 MPT1 MPT0 Interrupt status Enable Ptimer interrupt Enable Ptimer interrupt Enable Time base timer interrupt Enable interrupt Enable interrupt Enable interrupt Enable interrupt
note interrupt mask defined EPIMK register
v.0.97 External Port Interrupt Interrupt
WT5082
EPIMK register controls external port interrupt function acted not. EPIEx EPIMK register disables function. IEPI register invert input EPIx signal value, when IEPIx rising edge EPIx will generates interrupt. other case, IEPIx interrupt generated when there falling edge change EPIx input. Becarefully EPI.5 also connect with interrupt input when EEPI5 disable EPDI7 enable. EPIMK interrupt Mask register reset value 0x00 Address EEPI7 EEPI6 EEPI5 EEPI4 EEPI3 EEPI2 EEPI1 EEPI0
EEPI7 EEPI0 EEPIx
External Port Interrupt Enable
External Port Interrupt Disable Enable
WT5082
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IEPI Interrupt signal register reset value 0x00 Address IEPI7 IEPI6 IEPI5 IEEPI4 IEPI3 IEPI2 IEPI1 IEPI0
IEPI7 IEPI0 IEPIx
Invert input, only Port active function clock edge Normal rising edge active Invert falling edge active
EPISR status register reset value 0x00, reset after read Address EPI7 EPI6 EPI5 EEPI4 EPI3 EPI2 EPI1 EPI0
IEPI7 IEPI0 IEPIx
Invert input, only Port active function clock edge Normal rising edge active Invert falling edge active
Note EPI5 connect with interrupt when EEPI5 disable EPDI7 enable. EPI4 work with batter detect, will automatically detect when active
WT5082
v.0.97 P-DECODER Interrupt interrupt exclusively used service POCSAG code decoder module interrupt PDECODER Interrupt interrupt generated when there status change POCSAG code decoder such receiver address, message range indicator buffer overflow. interrupt status obtained from PDISR register, P-DECODER based internal status decoder updates this register then interrupts module when there status changed. This PDISR register read only data register, when there change PDISR register, PDIMK register enables disables interrupt operation module. EPDMA-bit PDCTL register enables P-decoder with interface mode into mode, more details information please refer POCSAG CODE DECODER section.
PDISR P-DECODER Interrupt status
PDI7 PDI6 PDI5 PDI4 PDI3 PDI2 PDI1 PDI0 Interrupt status P-DECODER Address matched message codeword receive Over Range Synchronize with POSCAG code Send message codeword data Incoming POCSAG frame Buffer Overflow External interrupt form Port15
WT5082
PDIMK P-DECODER Interrupt Mask register
EPDI7 EPDI6 EPDI5 EPDI4 EPDI3 EPDI2 EPDI1 EPDI0 Interrupt status P-DECODER Enable PDI0 interrupt Enable PDI1 interrupt Enable PDI2 interrupt Enable PDI3 interrupt Enable PDI4 interrupt Enable PDI5 interrupt Enable PDI6 interrupt Enable PDI7 interrupt
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SECTION POCSAG CODE DECODER
POCSAG code decoder P-DECODER module fully compatible with CCIR Radio Paging Code Number support bps, 1200bps 2400bps data speed base single crystal. WT5082 architecture allows numeric, alphanumeric, tone only pager application.
SECTION DECODER FEATURE
Fully compatible with CCIR Radio-paging Code POCSAG standard Single crystal support 512, 1200 2400 baud rate 76.SkHz crystal Support addresses independent frame numbers. Support partial address match facility address 260k addresses provided power saving control lines PLL, quick charge, enable Support alphanumeric, numeric tone only pages application. Build data filter 16-times over-sampling data clock recovery. Interrupt 6502 when there status change Communicate with 6502 base memory method. Provide 2-bit random error correction bits random error detection code words. Synchronize over range indication. interrupt mode send received message data 6502 CPU.
WT5082
v.0.97 PDCONFx P-DECODER configuration registers reset value 0x00
WT5082
ADDR 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 0040H 0041H 0042H 0043H 0044H 0045H 0046H 0047H 0048H 0049H 004AH
NAME PDCONF0 PDCONF1 PDCONF2 PDCONF3 PDCONF4 PDCONF5 PDCONF6 PDCONF7 PDCONF8 PDCONF9 PDCONF10 PDCONF11 PDCONF12 PDCONF13 PDCONF14 PDCONF15 PDCONF16 PDCONF17 PDCONF18 PDCONF19 PDCONF20 PDCONF21 PDCONF22 PDCONF23 PDCONF24 PDCONF25 PDCONF26
Read Write
number MF16 MF17 MF10 MF11 MF12 FCA1 FCB1 FCC1 FCD1 FCE1 FCF1 MF13 FCA0 FCB0 FCC0 FCD0 FCE0 FCF0 MF14 MF15
v.0.97 SECTION RELATIVE REGISTERS PDCTL P-DECODER control register reset value 0x00
WT5082
Address OverRan
REON
LostSyn ErrorFla
PDEOM
EPDMA
REON
PDEOM
PDON
EPDMA
PDON
Ennable function Enable P-Decoder Enable P-Decoder mode Force Enable P-Decoder mode
following bits read only will reset when address match Function status Lost sync with POCSAG Ever Sync with S.C. have error OverRange POCSAG sync status LostSync Never Sync with S.C. OverRange ErrorFlag error LostSync will reset after reading PDIMK P-DECODER interrupt mask register reset value 0x00 Address
PDIMK
EPDI7 EPDI6 EPDI5 EPDI4 EPDI3 EPDI2 EPDI1 EPDI0
PDISR P-DECODER interrupt status register reset value 0x00, reset after read Address
PDISR
PDI7 PDI6 PDI5 PDI4 PDI3 PDI2 PDI1 PDI0 v.0.97
PDDR P-DECODER receive data register reset value 0x00
WT5082
Address
PDDR
PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0
PDDRp PDDR mode address pointer byte reset value 0x00 Address
PDDRp
PDA7 PDA6 PDA5 PDA4 PDA3 PDA2 PDA1 PDA0
PDDRpH PDDR mode address pointer high byte Base address reset value 0x00 Address
PDDRpH
PDBA3 PDBA2 PDBA1 PDBA0 PDA9 PDA8
Note PDA8, PDA9 read only others R/W. MPDDRp PDDRp mask register reset value 0x00 Address
MPDDRp
ADCL MPDA9 MPDA8 MPDA7 MPDA6
PDEOM P-DECODER Address
PDEOM
Message
mark register reset value 0x00 EOM4 EOM3 EOM2 EOM1 EOM0
EOM7
EOM6
EOM5
v.0.97
WT5082
ABSOLUTE MAXIMUM RATINGS SYMBO PARAMETER RATING Supply Voltage -0.5 +3.6 Input Voltage -0.5 Range Operating Temperature Storage Tstg +150 Temperature
UNIT
V0.97
POCSAG DECODER MODULE P-DECODER
WT5082
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SECTION INTERFACE module configures P-DECODER PDCONF0 PDCONF26 registers, enables turn P-DECODER PDON PDCTL register. When there status changed P-DECODER, P-DECODER interrupts module sets interrupt flag bits PDISR register. received POCSAG codeword data obtained from PDDR registers. After P-DECODER turned pins acted power saving control output ports P-DEOCDER waits incoming POCSAG code signal from RFDI input pin.
P-DECODER interrupts
When P-DECODER turned enabled, P-DECODER starts receive incoming POCSAG codeword data. there status changed, P-DECODER PDIx bits PDISR register, then interrupts module. Whenever addresses, that PDCONFx registers, matched with incoming POCSAG address codeword, PDECODER interrupts module starts send received codeword data PDDR registers. PDIMK register used control P-decoder interrupt operation, either enable disable.
PDISR P-DECODER status
WT5082
PDI7
PDI6
PDI5
PDI4
PDI3
PDI2
PDI1
PDI0
Interrupt status P-DECODER Address matched message codeword receive Over Range Synchronize with POSCAG code Send message codeword data Incoming POCSAG frame Buffer Overflow Battery removed
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PDIMK P-DECODER Interrupt Mask register)
EPDI7 EPDI6 EPDI5 EPDI4 EPDI3 EPDI2 EPDI1 EPDI0
Enable function Enable PDI0 interrupt Enable PDI1 interrupt Enable PDI2 interrupt Enable PDI3 interrupt Enable PDI4 interrupt Enable PDI5 interrupt Enable PDI6 interrupt Enable PDI7 interrupt
Data mode P-DECODER
P-DECODER receives incoming message codeword data matched address, transfers them module either interrupt mode mode. interrupt mode,
WT5082
enables PDDR active interrupt setting EPDI4 PDISR register. While receives this interrupt, obtain incoming message codeword data PDDR register. EPDMA PDCTL register enables P-DECODER data mode. this mode, P-DECODER automatically transfers incoming message codeword data into data module that addressed PDDR address pointer, which read only defined PDDRp PDDRpH register. PDDR address pointer register automatically increases after each PDDR data write operation. 6502 module last data address pointer accessing this register PDBAx PDDRp PDDRpH MPDDRp descide page size. PDBAx PDDRpH indicate which page used. Before using mode, PDBAx available memory address. strongly suggest that PDBAx "0000 zero page Page PDBAx 0000, Page PDBAx 0001, Page15 PDBAx 1111, PDDR address pointer PDBAx, PDA9, PDA8, PDA1, PDA0 v.0.97
P-DECODER data mode
WT5082
v.0.97
DECODER data mode, memory address defined PDDRp PDDRpH register, define 14-bit memory address. MPDDRp register mask address output PDDRp PDDRpH register, using MPDDRp register updated memory area limited sub-area memory. PDDRpH being mask, PDA9 PDA6 written change different address. example, when MPPDRp equals 0x0FH, then PDA9 PDA6 witten. PDDRpH register 0x04H, PDDRp register 0x80H then memory address will limited 0480H 04BFH area. PDDRp register 0x40H then memory address will limited 0440H 047FH area. MPPDRp equals 0x0CH, then only PDA9 PDA8 written, PDA7 PDA6 read only. PDDRpH register 0x04H, PDDRp register can't then memory address will limited 0400H 04FFH area. User MPDDRp clear PDDRp PDDRpH after each reading, ADCL MDDRp clear automatically PDDRp PDDRpH when P_decoder address matched.
WT5082
MPDAx
Data memory address
PDAx read write Enable PDAx PDAx read only (note: between
MPDDRp 0x0F 0x0E 0x0C 0x08 0x00
Data memory address
1024
v.0.97 RECEIVED MESSAGE DATA FORMAT PDDR REGISTER When incoming POCSAG address codeword matches internal RICs, P-DECODER interrupts module stores incoming codeword data into PDDR register. There different formats PDDR register data words, start word, message word (end message) mark byte. start word contains matched address address codeword data code. message word contains received message codeword data error flag. data format message word package data format direct shift format. package data format bits byte, which X07, PDCONFx register. mark byte sent while message codeword. mark byte defined
WT5082
PDEOM register enabled when PDEOM PDCTL register enabled.
Start Word bytes
Message Word bytes
Mark Byte note
(note: mark byte enabled when PDEOM PDCTL register
POCSAG Address codeword Format:
Bit2 bit19
Bit20
Bit21
Bit22 bit31 Code
Bit32 Parity
Start word Format Total PDDR data byte
PDDR PDDR PDDR
v.0.97 Address Code Bits ID0, ID1,
Address Match
WT5082
Message word format: Direct shift mode FCx0/FCxl PDCONFx register defines message word whether acted "direct shift" format "data package" format. While direct shift format, i.e., FCx0/FCxl equal message word shifts message codeword data P-DECODER received corrected them, hasn't data package.
POCSAG message codeword format
Bit2 bit21
Bit22 bit31
Bit32 Parity
MA00 MA19
Message word PDDR data bytes
PDDR PDDR PDDR MA04 MA12 Error MA05 MA13 MA06 MA14 MA07 MA15 MA00 MA08 MA16 MA01 MA09 MA17 MA02 MA10 MA18 MA03 MA11 MA19
v.0.97
Message word format Data packaging mode Each POCSAG message codeword contain bits message code, P-DECODER divides each bits into some message bytes shift microprocessor. User define different package methods using different code code given POCSAG address codeword
WT5082
each different address also define different message codeword format.
Message codeword format selection different address Data Package mode Data package mode Depend bits data package method bits data package method Direct shift Mode
Note: Please comfirm FCx0 equal FC0, FCxl equal Message Codeword data packaging method (define X07, While FCx0 FCxl equal with different address have different data package format, depends table.
bits bits Data Package Method
Address Address
v.0.97
Example Data Packaging Method: bits packaging method POCSAG message codeword Format
WT5082
Bit2 bit21
Bit22 bit31
Bit32 Parity Parity
MA00 MA19 MB00 MB19
Bits Packaging Method Output
Message word PDDR data bytes
PDDR PDDR MA00 MA07 MA01 MA08 MA02 MA09 MA03 MA10 MA04 MA11 MA05 MA12 MA06 MA13 Error Error
Message word PDDR data bytes
PDDR PDDR PDDR MA14 MB01 MB08 MA15 MB02 MB09 MA16 MB03 MB10 MA17 MB04 MB11 MA18 MB05 MB12 MA19 MB06 MB13 MB00 MB07 MB14 Error Error Error
v.0.97 Bits Packaging Method Output
Message word PDDR data bytes
WT5082
PDDR PDDR PDDR PDDR PDDR
MA00 MA04 MA08 MA12 MA16
MA01 MA05 MA09 MA13 MA17
MA02 MA06 MA10 MA14 MA18
MA03 MA07 MA11 MA15 MA19
Error Error Error Error Error
Message word PDDR data bytes
PDDR PDDR PDDR PDDR PDDR MB00 MB04 MB08 MB12 MB16 MB01 MB05 MB09 MB13 MB17 MB02 MB06 MB10 MB14 MB18 MB03 MB07 MB11 MB15 MB19 Error Error Error Error Error
mark byte Format
Total PDDR data byte
EOM7 EOM6 EOM5 EOM4 EOM3 EOM2 EOM1 EOM0
Message mark data format defined PDEOM register, this byte sent only when PDEOM PDCTL register v.0.97
WT5082
v.0.97
WT5082
SECTION CONFIGURATION REGISTERS There total configuration registers POCSAG code decoder, data bits consist addresses, address frame, disable address flag, address mask bits, special function bits. module uses memory method program this registers, after PDON PDCTL register turned that P-DECODER depends these data bits start operation. NOTE P_DECODER c0nfigurati0n registers carl accessed ONLY when P_DECODER module off. (PDON=0
Address Bits Definition P-DECODER supply POCSAG addresses user frames. Each frame number independently programmed, that addresses same frame location not. User disable addresses setting Disable address bits. Address Bits Address Bits Address Bits Address Bits Address Bits Address Bits Address Bits
Frame Number Bits Frame number Address Frame number Address Frame number Address Frame number Address
WT5082
Frame number Address Frame number Address v.0.97
Address Definition POCSAG Code POCSAG Address codeword Format:
Bit2 bit19
Bit20
Bit21
Bit22 bit31 Code
Bit32 Parity
AddressCode
Relation between POCSAG Address-Code EEPROM Address-Code POCSAG Code number PDCONFx address name
Frame Number definition
Frame Number
WT5082
v.0.97
Disable Address Bits User defines following disable address code. Disable Address Bits
Disable Address Code Enable Disable Address Code Enable Disable Address Code Enable Disable Address Code Enable Disable Address Code Enable Disable Address Code Enable
Address Mask Bits Mask Address Pattern Match (MF0 MF10 MF11 MF12 MF13 MF14 MF15
Normal each pattern contains bits, while P-DECODER match sub-set address specific application.
Mask Bits Mask Mask Mask Mask
Address Code Mask Mask Mask Mask
WT5082
MF15 MF16 MF17
Mask Mask Mask Mask
Mask Mask Mask Mask v.0.97
Output Data Format Function selection FCx1 FCx0 X00-07 X38-53 Message codeword format selection different address
FCA1 FCB1 FCC1 FCA0 FCB0 FCC0
FCD1 FCE1 FCF1
FCD0 FCE0 FCF0
Data Package mode Data package mode Depend bits data package method bits data package method Direct shift Mode
Message Codeword data packaging method define While FCx0 FCx1 equal with different address have different address have different data package format, depends table
Address Address bits bits Data Package Method
WT5082
Message Error Flag Type Select User uses this data force P-DECODER sends message codeword data with can't recover this codeword Algorithm ever correct this codeword Message codeword Data Selection Algorithm can't recover this codeword Algorithm ever correct this codeword v.0.97 Disable Frame Number Match Turn frame number match address. When frame number match function disabled, P-DECODER always turns board after synchronizes with POCSAG. only matches addresses doesn't care frame number that defined PDCONFx registers. Frame Number Match Normal Disable Frame Number Match
Error Correction Mode Selection P-DECODER correct bits random error bits burst error codeword, user select these, application need. Codeword error correction mode selection Random Error Correction Mode Burst Error Correction Mode
active state
Active State
WT5082
High
Select message codeword error correct method address Error Correction Method random bits burst mode error correct bits error detection v.0.97 active width (X15
active width baud rate Preactive Width Active every sync. Codeword Cycle
Reverse RFDI input
data input Normal Reverse Data Input
Random error bits accept rate preamble pattern Define many random bits error accepted preamble pattern recognition within bits.
Accept error bits each bits ormal
WT5082
Baud rate selection option bits
Connected Crystal 76.8k 76.8k 76.8k
Baud Rate 1200 2400
v.0.97 Message codeword stop receive condition Stop Message Receive Condition Continue Receive Message, don't care error condition message codeword address codeword Stop Receive Message when Continue Message Codeword error Address Codeword error
pre-active width Pre-active width Baud Rate
Preactive width Pre-active time output
WT5082
Bits don't
v.0.97
Data Output Form Data Output Form operation with PDDR Operation PDDR with follow description
When data package bits, output data will become Original 0x00 0x01 0x02 0x03 0x04 0x05 0x06
After transfer 0x30 0x31 0x32 0x33 0x34 0x35 0x36
WT5082
0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
0x37 0x38 0x39 0x41 0x42 0x43 0x44 0x45 0x20
matter data package bits bits Register PDDR equals error flag. v.0.97
SECTION DRIVER
driver module supports with icon line maximum 1848 dots. bias driver duty 1/32 1/33. obtain good quality display, internal charge pump voltage generator included.
LCDCTL display control register reset value 0x00
Address
LCDPM FRQS1 LCDC LCDI FRQS3 FRQS2 FRQS1 FRQS0
FRQS3
FRQS2
FRQS0
Output 76.8khz 76.8khz 38.4khz 25.6khz 19.2khz 15.36khz 12.8khz 10.97khz 9.6khz 8.53khz
WT5082
7.68khz 6.98khz 6.4khz 5.9khz 5.485khz 5.12khz 4.8khz
Note actual frame frequency fLCD equals fo/4
v.0.97 LCDPMP LCDC
LCDI
Function Disable display Enable display without icon line Enable display with icon line voltage pumping voltage pumping
Display Memory Mapping
WT5082
Connecting Configurations Bias Voltage Doubler
v.0.97 v.0.97
SECTION Serial Interface
SOCTL Serial control register reset value 0x00 Address SIOE SCKO
When SlOE set, P00_RE, P01_RE1, P27_RE2 will become SCK, MOSI, MISO port function. also enables 768KO send 76.8KHz clock. User must P21_SS, P06_RDY recognize whether sending receiving mode when communicates with flex decoder. When ready, SCKO 76.8kHz clock 32bits will send out. data SIOB0-3 will send synchronized with MOSI pin. SIOB0-3 will also receive data from flex decoder same time MISO pin. wt5082 uses same address different register input output. When finished, generates interrupt FSIO IRQSR, user mask this interrupt MSIO IRQMK. SIOB0 Serial sending data Buffer register reset value 0x00 Address SIOB07 SIOB06 SIOB05 SIOB04 SIOB03 SIOB02 SIOB01 SIOB00
SIOB1 Serial sending data Buffer register reset value 0x00 Address
WT5082
SIOB15
SIOB14
SIOB13
SIOB12
SIOB11
SIOB10
SIOB09
SIOB08
SIOB2 Serial sending data Buffer register reset value 0x00 Address SIOB23 SIOB22 SIOB21 SIOB20 SIOB19 SIOB18 SIOB17 SIOB16
SIOB3 Serial sending data Buffer register reset value 0x00 Address SIOB31 SIOB30 SIOB29 SIOB28 SIOB27 SIOB26 SIOB25 SIOB24 v.0.97
SECTION Expanded
This chip embedded extra-large ROM, virtual memory bank access expanded ROM. virtual memory bank ROMW ADRx high byte 6502 address byte. ROMWinADR0 Data Memory from $4000 $5FFF, ROMWinADR1 uses Data Memory from $6000 $7FFF.
example, when ROMWinADR0 equal 6502 address equal $55AA, will access expand with address $D5AA
ROMWinADR0 Expand Window0 address register reset value 0x00 Address
WT5082
W0A4
W0A3
W0A2
W0A1
W0A0
ROMWinADR1 (Expand Windowl address register): reset value 0x00 Address W1A4 W1A3 W1A2 W1A1 W1A0
Configuration 256Kbytes Character 32Kbytes Program v.0.97
WT5082
v.0.97
Section UART
supply communication wt5082, UART function supplied. EUART enable UART function active, will switch data will switch data baud rate UART 9600 baud rate. UART Data Buffer UARTD active when EUART enabled. When ready sending data with UART, user must UART_TX start UART data out. EPI6 used interrupt after receiving data sending data, user check RX_Full TX_Empty verify Receive Buffer Full Transmit Buffer Empty.
UARTCTL (UART control register):reset value 0x00 Address EUART
RX_Full
TX_Empty
UART_TX
WT5082
RX_FULL
TX_EMPTY
Status TX_Buffer Empty Buffer Full
UARTD (Serial Buffer UART Data buffer register): reset value 0x00 Address SIOB07 UARTD SIOB06 UARTD
SIOB05 UARTD5
SIOB04 UARTD4
SIOB03 UARTD
SIOB02 UARTD
SIOB01 UARTD
SIOB00 UARTD0
UARTD active only when EUART equals High
v.0.97
Section
function control PWMCTL register, user EPWM enable function internal clock function, switch signal output, Port 768KO output enable control. EPI7 used transmission.
PWMCTL (PWM Control register): reset value 0x00 Address
EPWM
PWM_TX
ClrPAdr
PIndex3
PIndex2
PIndex1
PIndex0
WT5082
User EPWM enable circuit clock, function output baud rate signal. There bytes register store pattern. When writing PWMB register once, internal address PWMBx will increase automatically. User ClrPAdr reset internal address PWMBx initial address remember initial address 0x0F. Plndex descided many bytes will send Port P07. When PIndex equals 0x04, will shift data from PB4x PB0x first. User PWM_TX start sending signal, PWM_TX will reset automatically till signal. Port 768KO will preactive high bits delay bits till signal. Before send user program data from PWMBx, wt5082 will send Initial pattern about 4.587ms first.
signal timing pattern
Initial signal timing pattern v.0.97 PWMB Data Buffer register reset value 0x00 Address PWMBx PWMBx7
PWMBx5
PWMBx PWMBx4 PWMBx PWMBx
PWMBx0
WT5082
PAdr3 PAdr2 PAdr1 PAdr0 PWMB7 PWMB6 PWMB5 PWMB4 PWMB3 PWMB2 PWMB1 PWMB0 PB07 PB17 PB27 PB37 PB47 PB57 PB67 PB77 PB87 PB97 PBA7 PBB7 PBC7 PBD7 PBE7 PBF7 PB06 PB16 PB26 PB36 PB46 PB56 PB66 PB76 PB86 PB96 PBA6 PBB6 PBC6 PBD6 PBE6 PBF6 PB05 PB15 PB25 PB35 PB45 PB55 PB65 PB75 PB85 PB95 PBA5 PBB5 PBC5 PBD5 PBE5 PBF5 PB04 PB14 PB24 PB34 PB44 PB54 PB64 PB74 PB84 PB94 PBA4 PBB4 PBC4 PBD4 PBE4 PBF4 PB03 PB13 PB23 PB33 PB43 PB53 PB63 PB73 PB83 PB93 PBA3 PBB3 PBC3 PBD3 PBE3 PBF3 PB02 PB12 PB22 PB32 PB42 PB52 PB62 PB72 PB82 PB92 PBA2 PBB2 PBC2 PBD2 PBE2 PBF2 PB01 PB11 PB21 PB31 PB41 PB51 PB61 PB71 PB81 PB91 PBA1 PBB1 PBC1 PBD1 PBE1 PBF1 PB00 PB10 PB20 PB30 PB40 PB50 PB60 PB70 PB80 PB90 PBA0 PBB0 PBC0 PBD0 PBE0 PBF0
v.0.97 APPENDIX.A ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage
SYMBOL
RATING -0.5 +3.6 -0.5
UNIT
Input Voltage Range Operating
WT5082
Temperature Storage Temperature Tstg +150
ELECTRICAL CHARACTERISTICS Topr PARAMETER Operating Voltage Operating Current Standby Current Frequency Input High Level Input Level Output Current Output Current Clock SYMBO ISTB FOSC FCPU Typ. Unit 1MHz 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 2.7V 3.0V 0.5V 3.0V CONDITIONS
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APPENDIX.B DISPLAY SRAM MAPPING
Display $3F19 BYTE-ROW
WT5082
$3F19 $3F1A $3F1B $3F1C $3F1D $3F1E $3F1F $3F20 $3F21 $3F22 $3F23 $3F24 $3F25 $3F26 $3F27 $3F28 $3F29 $3F2A $3F2B $3F2C $3F2D $3F2E $3F2F $3F30 $3F31 $3F32 $3F33 $3F34 $3F35 $3F36 $3F37 $3F38 x0y7 x1y7 x2y7 x3y7 x4y7 x5y7 x6y7 x7y7 x8y7 x9y7 x10y7 x11y7 x12y7 x13y7 x14y7 x15y7 x16y7 x17y7 x18y7 x19y7 x20y7 x21y7 x22y7 x23y7 x24y7 x25y7 x26y7 x27y7 x28y7 x29y7 x30y7 x31y7
x0y6 x1y6 x2y6 x3y6 x4y6 x5y6 x6y6 x7y6 x8y6 x9y6 x10y6 x11y6 x12y6 x13y6 x14y6 x15y6 x16y6 x17y6 x18y6 x19y6 x20y6 x21y6 x22y6 x23y6 x24y6 x25y6 x26y6 x27y6 x28y6 x29y6 x30y6 x31y6
x0y5 x1y5 x2y5 x3y5 x4y5 x5y5 x6y5 x7y5 x8y5 x9y5 x10y5 x11y5 x12y5 x13y5 x14y5 x15y5 x16y5 x17y5 x18y5 x19y5 x20y5 x21y5 x22y5 x23y5 x24y5 x25y5 x26y5 x27y5 x28y5 x29y5 x30y5 x31y5
x0y4 x1y4 x2y4 x3y4 x4y4 x5y4 x6y4 x7y4 x8y4 x9y4 x10y4 x11y4 x12y4 x13y4 x14y4 x15y4 x16y4 x17y4 x18y4 x19y4 x20y4 x21y4 x22y4 x23y4 x24y4 x25y4 x26y4 x27y4 x28y4 x29y4 x30y4 x31y4
x0y3 x1y3 x2y3 x3y3 x4y3 x5y3 x6y3 x7y3 x8y3 x9y3 x10y3 x11y3 x12y3 x13y3 x14y3 x15y3 x16y3 x17y3 x18y3 x19y3 x20y3 x21y3 x22y3 x23y3 x24y3 x25y3 x26y3 x27y3 x28y3 x29y3 x30y3 x31y3
x0y2 x1y2 x2y2 x3y2 x4y2 x5y2 x6y2 x7y2 x8y2 x9y2 x10y2 x11y2 x12y2 x13y2 x14y2 x15y2 x16y2 x17y2 x18y2 x19y2 x20y2 x21y2 x22y2 x23y2 x24y2 x25y2 x26y2 x27y2 x28y2 x29y2 x30y2 x31y2
x0y1 x1y1 x2y1 x3y1 x4y1 x5y1 x6y1 x7y1 x8y1 x9y1 x10y1 x11y1 x12y1 x13y1 x14y1 x15y1 x16y1 x17y1 x18y1 x19y1 x20y1 x21y1 x22y1 x23y1 x24y1 x25y1 x26y1 x27y1 x28y1 x29y1 x30y1 x31y1
x0y0 x1y0 x2y0 x3y0 x4y0 x5y0 x6y0 x7y0 x8y0 x9y0 x10y0 x11y0 x12y0 x13y0 x14y0 x15y0 x16y0 x17y0 x18y0 x19y0 x20y0 x21y0 x22y0 x23y0 x24y0 x25y0 x26y0 x27y0 x28y0 x29y0 x30y0 x31y0
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WT5082
$3F39 $3F3A $3F3B $3F3C $3F3D $3F3E $3F3F $3F40 $3F41 $3F42 $3F43 $3F44 $3F45 $3F46 $3F47 $3F48 $3F49 $3F4A $3F4B $3F4C $3F4D $3F4E $3F4F $3F50
x32y7 x33y7 x34y7 x35y7 x36y7 x37y7 x38y7 x39y7 x40y7 x41y7 x42y7 x43y7 x44y7 x45y7 x46y7 x47y7 x48y7 x49y7 x50y7 x51y7 x52y7 x53y7 x54y7 x55y7
x32y6 x33y6 x34y6 x35y6 x36y6 x37y6 x38y6 x39y6 x40y6 x41y6 x42y6 x43y6 x44y6 x45y6 x46y6 x47y6 x48y6 x49y6 x50y6 x51y6 x52y6 x53y6 x54y6 x55y6
x32y5 x33y5 x34y5 x35y5 x36y5 x37y5 x38y5 x39y5 x40y5 x41y5 x42y5 x43y5 x44y5 x45y5 x46y5 x47y5 x48y5 x49y5 x50y5 x51y5 x52y5 x53y5 x54y5 x55y5
x32y4 x33y4 x34y4 x35y4 x36y4 x37y4 x38y4 x39y4 x40y4 x41y4 x42y4 x43y4 x44y4 x45y4 x46y4 x47y4 x48y4 x49y4 x50y4 x51y4 x52y4 x53y4 x54y4 x55y4
x32y3 x33y3 x34y3 x35y3 x36y3 x37y3 x38y3 x39y3 x40y3 x41y3 x42y3 x43y3 x44y3 x45y3 x46y3 x47y3 x48y3 x49y3 x50y3 x51y3 x52y3 x53y3 x54y3 x55y3
x32y2 x33y2 x34y2 x35y2 x36y2 x37y2 x38y2 x39y2 x40y2 x41y2 x42y2 x43y2 x44y2 x45y2 x46y2 x47y2 x48y2 x49y2 x50y2 x51y2 x52y2 x53y2 x54y2 x55y2
x32y1 x33y1 x34y1 x35y1 x36y1 x37y1 x38y1 x39y1 x40y1 x41y1 x42y1 x43y1 x44y1 x45y1 x46y1 x47y1 x48y1 x49y1 x50y1 x51y1 x52y1 x53y1 x54y1 x55y1
x32y0 x33y0 x34y0 x35y0 x36y0 x37y0 x38y0 x39y0 x40y0 x41y0 x42y0 x43y0 x44y0 x45y0 x46y0 x47y0 x48y0 x49y0 x50y0 x51y0 x52y0 x53y0 x54y0 x55y0
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WT5082
BYTE-ROW
$3F51 $3F52 $3F53 $3F54 $3F55 $3F56 $3F57 $3F58 $3F59 $3F5A $3F5B $3F5C $3F5D $3F5E $3F5F $3F60 $3F61 $3F62 $3F63 $3F64 $3F65 $3F66 $3F67 $3F68 x0y15 x1y15 x2y15 x3y15 x4y15 x5y15 x6y15 x7y15 x8y15 x9y15 x10y15 x11y15 x12y15 x13y15 x14y15 x15y15 x16y15 x17y15 x18y15 x19y15 x20y15 x21y15 x22y15 x23y15 x0y14 x1y14 x2y14 x3y14 x4y14 x5y14 x6y14 x7y14 x8y14 x9y14 x10y14 x11y14 x12y14 x13y14 x14y14 x15y14 x16y14 x17y14 x18y14 x19y14 x20y14 x21y14 x22y14 x23y14 x0y13 x1y13 x2y13 x3y13 x4y13 x5y13 x6y13 x7y13 x8y13 x9y13 x10y13 x11y13 x12y13 x13y13 x14y13 x15y13 x16y13 x17y13 x18y13 x19y13 x20y13 x21y13 x22y13 x23y13 x0y12 x1y12 x2y12 x3y12 x4y12 x5y12 x6y12 x7y12 x8y12 x9y12 x10y12 x11y12 x12y12 x13y12 x14y12 x15y12 x16y12 x17y12 x18y12 x19y12 x20y12 x21y12 x22y12 x23y12 x0y11 x1y11 x2y11 x3y11 x4y11 x5y11 x6y11 x7y11 x8y11 x9y11 x10y11 x11y11 x12y11 x13y11 x14y11 x15y11 x16y11 x17y11 x18y11 x19y11 x20y11 x21y11 x22y11 x23y11 x0y10 x1y10 x2y10 x3y10 x4y10 x5y10 x6y10 x7y10 x8y10 x9y10 x10y10 x11y10 x12y10 x13y10 x14y10 x15y10 x16y10 x17y10 x18y10 x19y10 x20y10 x21y10 x22y10 x23y10 x0y9 x1y9 x2y9 x3y9 x4y9 x5y9 x6y9 x7y9 x8y9 x9y9 x10y9 x11y9 x12y9 x13y9 x14y9 x15y9 x16y9 x17y9 x18y9 x19y9 x20y9 x21y9 x22y9 x23y9 x0y8 x1y8 x2y8 x3y8 x4y8 x5y8 x6y8 x7y8 x8y8 x9y8 x10y8 x11y8 x12y8 x13y8 x14y8 x15y8 x16y8 x17y8 x18y8 x19y8 x20y8 x21y8 x22y8 x23y8
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WT5082
$3F70 $3F71 $3F72 $3F73 $3F74 $3F75 $3F76 $3F77 $3F78 $3F79 $3F7A $3F7B $3F7C $3F7D $3F7E $3F7F $3F80 $3F81 $3F82 $3F83 $3F84 $3F85 $3F86 $3F87 $3F88
x31y15 x32y15 x33y15 x34y15 x35y15 x36y15 x37y15 x38y15 x39y15 x40y15 x41y15 x42y15 x43y15 x44y15 x45y15 x46y15 x47y15 x48y15 x49y15 x50y15 x51y15 x52y15 x53y15 x54y15 x55y15
x31y14 x32y14 x33y14 x34y14 x35y14 x36y14 x37y14 x38y14 x39y14 x40y14 x41y14 x42y14 x43y14 x44y14 x45y14 x46y14 x47y14 x48y14 x49y14 x50y14 x51y14 x52y14 x53y14 x54y14 x55y14
x31y13 x32y13 x33y13 x34y13 x35y13 x36y13 x37y13 x38y13 x39y13 x40y13 x41y13 x42y13 x43y13 x44y13 x45y13 x46y13 x47y13 x48y13 x49y13 x50y13 x51y13 x52y13 x53y13 x54y13 x55y13
x31y12 x32y12 x33y12 x34y12 x35y12 x36y12 x37y12 x38y12 x39y12 x40y12 x41y12 x42y12 x43y12 x44y12 x45y12 x46y12 x47y12 x48y12 x49y12 x50y12 x51y12 x52y12 x53y12 x54y12 x55y12
x31y11 x32y11 x33y11 x34y11 x35y11 x36y11 x37y11 x38y11 x39y11 x40y11 x41y11 x42y11 x43y11 x44y11 x45y11 x46y11 x47y11 x48y11 x49y11 x50y11 x51y11 x52y11 x53y11 x54y11 x55y11
x31y10 x32y10 x33y10 x34y10 x35y10 x36y10 x37y10 x38y10 x39y10 x40y10 x41y10 x42y10 x43y10 x44y10 x45y10 x46y10 x47y10 x48y10 x49y10 x50y10 x51y10 x52y10 x53y10 x54y10 x55y10
x31y9 x32y9 x33y9 x34y9 x35y9 x36y9 x37y9 x38y9 x39y9 x40y9 x41y9 x42y9 x43y9 x44y9 x45y9 x46y9 x47y9 x48y9 x49y9 x50y9 x51y9 x52y9 x53y9 x54y9 x55y9
x31y8 x32y8 x33y8 x34y8 x35y8 x36y8 x37y8 x38y8 x39y8 x40y8 x41y8 x42y8 x43y8 x44y8 x45y8 x46y8 x47y8 x48y8 x49y8 x50y8 x51y8 x52y8 x53y8 x54y8 x55y8
V0.97
WT5082
BYTE-ROW
$3F89 $3F8A $3F8B $3F8C $3F8D $3F8E $3F8F $3F90 $3F91 $3F92 x0y23 x1y23 x2y23 x3y23 x4y23 x5y23 x6y23 x7y23 x8y23 x9y23 x10y23 x11y23 x12y23 x13y23 x14y23 x15y23 x16y23 x17y23 x18y23 x19y23 x20y23 x21y23 x22y23 x23y23 x24y23 x25y23 x26y23 x27y23 x28y23 x29y23 x30y23 x31y23 x0y22 x1y22 x2y22 x3y22 x4y22 x5y22 x6y22 x7y22 x8y22 x9y22 x10y22 x11y22 x12y22 x13y22 x14y22 x15y22 x16y22 x17y22 x18y22 x19y22 x20y22 x21y22 x22y22 x23y22 x24y22 x25y22 x26y22 x27y22 x28y22 x29y22 x30y22 x31y22 x0y21 x1y21 x2y21 x3y21 x4y21 x5y21 x6y21 x7y21 x8y21 x9y21 x10y21 x11y21 x12y21 x13y21 x14y21 x15y21 x16y21 x17y21 x18y21 x19y21 x20y21 x21y21 x22y21 x23y21 x24y21 x25y21 x26y21 x27y21 x28y21 x29y21 x30y21 x31y21 x0y20 x1y20 x2y20 x3y20 x4y20 x5y20 x6y20 x7y20 x8y20 x9y20 x10y20 x11y20 x12y20 x13y20 x14y20 x15y20 x16y20 x17y20 x18y20 x19y20 x20y20 x21y20 x22y20 x23y20 x24y20 x25y20 x26y20 x27y20 x28y20 x29y20 x30y20 x31y20 x0y19 x1y19 x2y19 x3y19 x4y19 x5y19 x6y19 x7y19 x8y19 x9y19 x10y19 x11y19 x12y19 x13y19 x14y19 x15y19 x16y19 x17y19 x18y19 x19y19 x20y19 x21y19 x22y19 x23y19 x24y19 x25y19 x26y19 x27y19 x28y19 x29y19 x30y19 x31y19 x0y18 x1y18 x2y18 x3y18 x4y18 x5y18 x6y18 x7y18 x8y18 x9y18 x10y18 x11y18 x12y18 x13y18 x14y18 x15y18 x16y18 x17y18 x18y18 x19y18 x20y18 x21y18 x22y18 x23y18 x24y18 x25y18 x26y18 x27y18 x28y18 x29y18 x30y18 x31y18 x0y17 x1y17 x2y17 x3y17 x4y17 x5y17 x6y17 x7y17 x8y17 x9y17 x10y17 x11y17 x12y17 x13y17 x14y17 x15y17 x16y17 x17y17 x18y17 x19y17 x20y17 x21y17 x22y17 x23y17 x24y17 x25y17 x26y17 x27y17 x28y17 x29y17 x30y17 x31y17 x0y16 x1y16 x2y16 x3y16 x4y16 x5y16 x6y16 x7y16 x8y16 x9y16 x10y16 x11y16 x12y16 x13y16 x14y16 x15y16 x16y16 x17y16 x18y16 x19y16 x20y16 x21y16 x22y16 x23y16 x24y16 x25y16 x26y16 x27y16 x28y16 x29y16 x30y16 x31y16
$3F93 $3F94 $3F95 $3F96 $3F97 $3F98 $3F99 $3F9A $3F9B $3F9C $3F9D $3F9E $3F9F $3FA0 $3FA1 $3FA2
$3FA3 $3FA4 $3FA5 $3FA6 $3FA7 $3FA8
V0.97
WT5082
$3FA9 $3FAA $3FAB $3FAC $3FAD $3FAE $3FAF $3FB0 $3FB1 $3FB2
x32y23 x33y23 x34y23 x35y23 x36y23 x37y23 x38y23 x39y23 x40y23 x41y23 x42y23 x43y23 x44y23 x45y23 x46y23 x47y23 x48y23 x49y23 x50y23 x51y23 x52y23 x53y23 x54y23 x55y23
x32y22 x33y22 x34y22 x35y22 x36y22 x37y22 x38y22 x39y22 x40y22 x41y22 x42y22 x43y22 x44y22 x45y22 x46y22 x47y22 x48y22 x49y22 x50y22 x51y22 x52y22 x53y22 x54y22 x55y22
x32y21 x33y21 x34y21 x35y21 x36y21 x37y21 x38y21 x39y21 x40y21 x41y21 x42y21 x43y21 x44y21 x45y21 x46y21 x47y21 x48y21 x49y21 x50y21 x51y21 x52y21 x53y21 x54y21 x55y21
x32y20 x33y20 x34y20 x35y20 x36y20 x37y20 x38y20 x39y20 x40y20 x41y20 x42y20 x43y20 x44y20 x45y20 x46y20 x47y20 x48y20 x49y20 x50y20 x51y20 x52y20 x53y20 x54y20 x55y20
x32y19 x33y19 x34y19 x35y19 x36y19 x37y19 x38y19 x39y19 x40y19 x41y19 x42y19 x43y19 x44y19 x45y19 x46y19 x47y19 x48y19 x49y19 x50y19 x51y19 x52y19 x53y19 x54y19 x55y19
x32y18 x33y18 x34y18 x35y18 x36y18 x37y18 x38y18 x39y18 x40y18 x41y18 x42y18 x43y18 x44y18 x45y18 x46y18 x47y18 x48y18 x49y18 x50y18 x51y18 x52y18 x53y18 x54y18 x55y18
x32y17 x33y17 x34y17 x35y17 x36y17 x37y17 x38y17 x39y17 x40y17 x41y17 x42y17 x43y17 x44y17 x45y17 x46y17 x47y17 x48y17 x49y17 x50y17 x51y17 x52y17 x53y17 x54y17 x55y17
x32y16 x33y16 x34y16 x35y16 x36y16 x37y16 x38y16 x39y16 x40y16 x41y16 x42y16 x43y16 x44y16 x45y16 x46y16 x47y16 x48y16 x49y16 x50y16 x51y16 x52y16 x53y16 x54y16 x55y16
$3FB3 $3FB4 $3FB5 $3FB6 $3FB7 $3FB8 $3FB9 $3FBA $3FBB $3FBC $3FBD $3FBE $3FBF $3FC0
V0.97 BYTE-ROW
WT5082
3FC1 3FC2 3FC3 3FC4 3FC5 3FC6 3FC7 3FC8 3FC9 3FCA 3FCB 3FCC 3FCD 3FCE 3FCF 3FD0 3FD1 3FD2 3FD3 3FD4 3FD5 3FD6 3FD7 3FD8 3FD9 3FDA 3FDB 3FDC 3FDD 3FDE 3FDF 3FE0 3FE1 3FE2
x0y31 x1y31 x2y31 x3y31 x4y31 x5y31 x6y31 x7y31 x8y31 x9y31 x10y31 x11y31 x12y31 x13y31 x14y31 x15y31 x16y31 x17y31 x18y31 x19y31 x20y31 x21y31 x22y31 x23y31 x24y31 x25y31 x26y31 x27y31 x28y31 x29y31 x30y31 x31y31 x32y31 x33y31
x0y30 x1y30 x2y30 x3y30 x4y30 x5y30 x6y30 x7y30 x8y30 x9y30 x10y30 x11y30 x12y30 x13y30 x14y30 x15y30 x16y30 x17y30 x18y30 x19y30 x20y30 x21y30 x22y30 x23y30 x24y30 x25y30 x26y30 x27y30 x28y30 x29y30 x30y30 x31y30 x32y30 x33y30
x0y29 x1y29 x2y29 x3y29 x4y29 x5y29 x6y29 x7y29 x8y29 x9y29 x10y29 x11y29 x12y29 x13y29 x14y29 x15y29 x16y29 x17y29 x18y29 x19y29 x20y29 x21y29 x22y29 x23y29 x24y29 x25y29 x26y29 x27y29 x28y29 x29y29 x30y29 x31y29 x32y29 x33y29
x0y28 x1y28 x2y28 x3y28 x4y28 x5y28 x6y28 x7y28 x8y28 x9y28 x10y28 x11y28 x12y28 x13y28 x14y28 x15y28 x16y28 x17y28 x18y28 x19y28 x20y28 x21y28 x22y28 x23y28 x24y28 x25y28 x26y28 x27y28 x28y28 x29y28 x30y28 x31y28 x32y28 x33y28
x0y27 x1y27 x2y27 x3y27 x4y27 x5y27 x6y27 x7y27 x8y27 x9y27 x10y27 x11y27 x12y27 x13y27 x14y27 x15y27 x16y27 x17y27 x18y27 x19y27 x20y27 x21y27 x22y27 x23y27 x24y27 x25y27 x26y27 x27y27 x28y27 x29y27 x30y27 x31y27 x32y27 x33y27
x0y26 x1y26 x2y26 x3y26 x4y26 x5y26 x6y26 x7y26 x8y26 x9y26 x10y26 x11y26 x12y26 x13y26 x14y26 x15y26 x16y26 x17y26 x18y26 x19y26 x20y26 x21y26 x22y26 x23y26 x24y26 x25y26 x26y26 x27y26 x28y26 x29y26 x30y26 x31y26 x32y26 x33y26
x0y25 x1y25 x2y25 x3y25 x4y25 x5y25 x6y25 x7y25 x8y25 x9y25 x10y25 x11y25 x12y25 x13y25 x14y25 x15y25 x16y25 x17y25 x18y25 x19y25 x20y25 x21y25 x22y25 x23y25 x24y25 x25y25 x26y25 x27y25 x28y25 x29y25 x30y25 x31y25 x32y25 x33y25
x0y24 x1y24 x2y24 x3y24 x4y24 x5y24 x6y24 x7y24 x8y24 x9y24 x10y24 x11y24 x12y24 x13y24 x14y24 x15y24 x16y24 x17y24 x18y24 x19y24 x20y24 x21y24 x22y24 x23y24 x24y24 x25y24 x26y24 x27y24 x28y24 x29y24 x30y24 x31y24 x32y24 x33y24
V0.97
WT5082
$3FE3 $3FE4 $3FE5 $3FE6 $3FE7 $3FE8 $3FE9 $3FEA $3FEB $3FEC $3FED $3FEE $3FEF $3FF0 $3FF1 $3FF2 $3FF3 $3FF4 $3FF5 $3FF6 $3FF7 $3FF8
x34y31 x35y31 x36y31 x37y31 x38y31 x39y31 x40y31 x41y31 x42y31 x43y31 x44y31 x45y31 x46y31 x47y31 x48y31 x49y31 x50y31 x51y31 x52y31 x53y31 x54y31 x55y31
x34y30 x35y30 x36y30 x37y30 x38y30 x39y30 x40y30 x41y30 x42y30 x43y30 x44y30 x45y30 x46y30 x47y30 x48y30 x49y30 x50y30 x51y30 x52y30 x53y30 x54y30 x55y30
x34y29 x35y29 x36y29 x37y29 x38y29 x39y29 x40y29 x41y29 x42y29 x43y29 x44y29 x45y29 x46y29 x47y29 x48y29 x49y29 x50y29 x51y29 x52y29 x53y29 x54y29 x55y29
x34y28 x35y28 x36y28 x37y28 x38y28 x39y28 x40y28 x41y28 x42y28 x43y28 x44y28 x45y28 x46y28 x47y28 x48y28 x49y28 x50y28 x51y28 x52y28 x53y28 x54y28 x55y28
x34y27 x35y27 x36y27 x37y27 x38y27 x39y27 x40y27 x41y27 x42y27 x43y27 x44y27 x45y27 x46y27 x47y27 x48y27 x49y27 x50y27 x51y27 x52y27 x53y27 x54y27 x55y27
x34y26 x35y26 x36y26 x37y26 x38y26 x39y26 x40y26 x41y26 x42y26 x43y26 x44y26 x45y26 x46y26 x47y26 x48y26 x49y26 x50y26 x51y26 x52y26 x53y26 x54y26 x55y26
x34y25 x35y25 x36y25 x37y25 x38y25 x39y25 x40y25 x41y25 x42y25 x43y25 x44y25 x45y25 x46y25 x47y25 x48y25 x49y25 x50y25 x51y25 x52y25 x53y25 x54y25 x55y25
x34y24 x35y24 x36y24 x37y24 x38y24 x39y24 x40y24 x41y24 x42y24 x43y24 x44y24 x45y24 x46y24 x47y24 x48y24 x49y24 x50y24 x51y24 x52y24 x53y24 x54y24 x55y24
BYTE-ROW ICON LINE
$3FF9 $3FFA $3FFB $3FFC $3FFD $3FFE $3FFF x07y32 x15y32 x23y32 x31y32 x39y32 x47y32 x55y32 x06y32 x14y32 x22y32 x30y32 x38y32 x46y32 x54y32 x05y32 x13y32 x21y32 x29y32 x37y32 x45y32 x53y32 x04y32 x12y32 x20y32 x28y32 x36y32 x44y32 x52y32 x03y32 x11y32 x19y32 x27y32 x35y32 x43y32 x51y32 x02y32 x10y32 x18y32 x26y32 x34y32 x42y32 x250y32 x01y32 x09y32 x17y32 x25y32 x33y32 x41y32 x49y32 x00y32 x08y32 x16y32 x24y32 x32y32 x40y32 x48y32
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