LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition System AD7890 O
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FEATURES Fast 12-Bit with Conversion Time Eight Single-Ended Analog Input Channels Selection Input Ranges: AD7890-10 4.096 AD7890-4 AD7890-2 Allows Separate Access Multiplexer On-Chip Track/Hold Amplifier On-Chip Reference High Speed, Flexible, Serial Interface Single Supply, Power Operation max) Power-Down Mode typ)
LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition System AD7890
OUT/ SIGNAL SCALING* SIGNAL SCALING* SIGNAL SCALING* SIGNAL SCALING* SIGNAL SCALING* SIGNAL SCALING* SIGNAL SCALING* SIGNAL SCALING* TRACKHOLD OUTPUT/CONTROL REGISTER CONVST 12-BIT +2.5V REFERENCE
VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8
AD7890
CEXT
GENERAL DESCRIPTION
CLOCK
AD7890 eight-channel 12-bit data acquisition system. part contains input multiplexer, on-chip track/hold amplifier, high-speed 12-bit ADC, +2.5 reference high speed, serial interface. part operates from single supply accepts analog input range (AD7890-10), +4.096 (AD7890-4) +2.5 (AD7890-2). multiplexer part independently accessible. This allows user insert antialiasing filter signal conditioning, required, between multiplexer ADC. This means that antialiasing filter used eight channels. Connection external capacitor allows user adjust time given multiplexer settling include external delays filter signal conditioning circuitry. Output data from AD7890 provided high speed bidirectional serial interface port. part contains on-chip control register, allowing control channel selection, conversion start power-down serial port. Versatile, high speed logic ensures easy interfacing serial ports microcontrollers digital signal processors. addition traditional accuracy specifications such linearity, full-scale offset errors, AD7890 also specified dynamic performance parameters including harmonic distortion signal-to-noise ratio.
AGND AGND DGND
SCLK DATA DATA SMODE SCALING AD7890-2
Power dissipation normal mode part placed standby (power-down) mode required perform conversions. AD7890 fabricated Analog Devices' Linear Compatible CMOS (LC2MOS) process, mixed technology process that combines precision bipolar circuits with power CMOS logic. part available 24-pin, 0.3" wide, plastic hermetic dual-in-line package 24-pin small outline package (SOIC).
PRODUCT HIGHLIGHTS
Complete 12-Bit Data Acquisition System Chip AD7890 complete monolithic combining eight-channel multiplexer, 12-bit ADC, +2.5 reference track/hold amplifier single chip. Separate Access Multiplexer AD7890 provides access output multiplexer allowing antialiasing filter eight channels-a considerable saving over eight antialiasing filters required multiplexer internally connected ADC. High Speed Serial Interface part provides high speed serial interface easy connection serial ports microcontrollers processors.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Analog Devices, Inc., 1996 Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AGND DGND +2.5 AD7890-SPECIFICATIONS =OUT connect IN.=AllV,specifications
external, unless otherwise noted.)
Parameter DYNAMIC PERFORMANCE Signal (Noise Distortion) Ratio2 Total Harmonic Distortion (THD)2 Peak Harmonic Spurious Noise2 Intermodulation Distortion Order Terms Order Terms Channel-to-Channel Isolation2 ACCURACY Resolution Minimum Resolution Which Missing Codes Guaranteed Relative Accuracy2 Differential Nonlinearity2 Positive Full-Scale Error2 Full-Scale Error Match4 AD7890-2, AD7890-4 Unipolar Offset Error2 Unipolar Offset Error Match AD7890-10 Only Negative Full-Scale Error2 Bipolar Zero Error2 Bipolar Zero Error Match ANALOG INPUTS AD7890-10 Input Voltage Range Input Resistance AD7890-4 Input Voltage Range Input Resistance AD7890-2 Input Voltage Range Input Current OUTPUT Output Voltage Range Output Resistance (AD7890-10, AD7890-4) (AD7890-2) INPUT Input Voltage Range Input Current REFERENCE OUTPUT/INPUT Input Voltage Range Input Impedance Input Capacitance5 Output Voltage Error +25°C TMIN TMAX Temperature Coefficient Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Capacitance, CIN5
Versions1
Versions
Version
Units Bits Bits
Test Conditions/Comments Using External CONVST. Channel Sine Wave, fSAMPLE kHz3 Sine Wave, fSAMPLE kHz3 Sine Wave, fSAMPLE kHz3 kHz, kHz, fSAMPLE kHz3
Sine Wave
+4.096 +2.5 +2.5 +2.5 2.375/2.625
+4.096 +2.5 +2.5 +2.5 2.375/2.625
+4.096 +2.5 +2.5 +2.5 2.375/2.625
Volts Volts Volts Volts min/k Volts min/V ppm/°C Resistor Connected Internal Reference Node
Assuming Driven from Impedance
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AD7890
Parameter LOGIC OUTPUTS Output High Voltage, Output Voltage, Serial Data Output Coding AD7890-10 AD7890-4 AD7890-2 CONVERSION RATE Conversion Time Track/Hold Acquisition Time2, POWER REQUIREMENTS (Normal Mode) (Standby Mode)6 +25°C Power Dissipation Normal Mode Standby Mode +25°C Versions1 Versions Version Units Test Conditions/Comments ISOURCE ISINK
Complement Straight (Natural) Binary Straight (Natural) Binary fCLK MHz, Connected
Specified Performance Logic Inputs Logic Inputs Typically
NOTES Temperature ranges follows: Versions: -40°C -85°C; Version: -55°C +125°C. Terminology. This sample rate only achievable when tiling part external clocking mode. Full-scale error match applies positive full scale AD7890-2 AD7890-4. applies both positive negative full scale AD7890-10. Sample tested +25°C ensure compliance. Analog inputs AD7890-10 must achieve correct power-down current. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS*
+25°C unless otherwise noted)
AGND -0.3 DGND -0.3 Analog Input Voltage AGND AD7890-10, AD7890-4 AD7890-2 Reference Input Voltage AGND -0.3 Digital Input Voltage DGND -0.3 Digital Output Voltage DGND -0.3 Operating Temperature Range Commercial Versions) -40°C +85°C Extended Version) -55°C +125°C Storage Temperature Range -65°C +150°C Junction Temperature +150°C Plastic Package, Power Dissipation Thermal Impedance 105°C/W Lead Temperature (Soldering, sec) +260°C Cerdip Package, Power Dissipation Thermal Impedance 70°C/W Lead Temperature (Soldering, sec) +300°C SOIC Package, Power Dissipation Thermal Impedance 75°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ORDERING GUIDE
Model
AD7890AN-2 AD7890BN-2 AD7890AR-2 AD7890BR-2 AD7890SQ-2 AD7890AN-4 AD7890BN-4 AD7890AR-4 AD7890BR-4 AD7890SQ-4 AD7890AN-10 AD7890BN-10 AD7890AR-10 AD7890BR-10 AD7890SQ-10
Temperature Range
-40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C
Linearity Error
Package Option*
N-24 N-24 R-24 R-24 Q-24 N-24 N-24 R-24 R-24 Q-24 N-24 N-24 R-24 R-24 Q-24
NOTE Plastic DIP; Cerdip; SOIC.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7890 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
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AD7890 TIMING CHARACTERISTICS1, connected IN.)
Parameter fCLKIN3 tCLK tCLK tCONVERT tCST Self-Clocking Mode External-Clocking Mode t145 t175 t196 t19A6 Limit TMIN, TMAX Versions) tCLK tCLK tCLK tCLK tCLK tCLK Units
(VDD
AGND DGND +2.5 fCLK external,
Conditions/Comments Master Clock Frequency. Specified Performance Master Clock Input Time Master Clock Input High Time Digital Output Rise Time. Typically Digital Output Fall Time. Typically Conversion Time CONVST Pulse Width SCLK Falling Edge Data Valid Delay SCLK High Pulse Width SCLK Pulse Width SCLK Rising Edge Data Valid Delay SCLK Rising Edge Delay Relinquish Time after Rising Edge SCLK SCLK Falling Edge Data Valid Falling Edge Setup Time Address Bit) Data Valid SCLK Falling Edge Setup Time Data Valid SCLK Falling Edge Hold Time SCLK Falling Edge Hold Time SCLK Falling Edge Setup Time Data Valid Delay SCLK High Pulse Width SCLK Pulse Width SCLK Rising Edge Data Valid Delay SCLK Falling Edge Hold Time Relinquish Time after Rising Edge Relinquish Time after Rising Edge SCLK SCLK Falling Edge Setup Time Data Valid SCLK Falling Edge Setup Time Data Valid SCLK Falling Edge Hold Time SCLK Falling Edge Hold Time
NOTES Sample tested -25°C ensure compliance. input signals specified with (10% timed from voltage level Figures AD7890 production tested with MHz. guaranteed characterization operate kHz. Specified using points waveform interest. These numbers measured with load circuit Figure defined time required output cross These numbers derived from measured time taken data output change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that times quoted timing characteristics true relinquish times part such independent external loading capacitances.
1.6mA
OUTPUT 50pF 200µA
+2.1V
Figure Load Circuit Access Time Relinquish Time
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AD7890
FUNCTION DESCRIPTION
Mnemonic AGND SMODE
Description Analog Ground. Ground reference track/hold, comparator DAC. Control Input. Determines whether part operates External Clocking (slave) Self-Clocking (master) serial mode. With SMODE logic low, part Self-Clocking serial mode with SCLK outputs. This Self-Clocking mode useful connection shift registers serial ports processors. With SMODE logic high, part External Clocking serial mode with SCLK inputs. This External Clocking mode useful connection serial port microcontrollers such 8XC51 68HCXX connection serial ports processors. Digital Ground. Ground reference digital circuitry. External Capacitor. external capacitor connected this determine length internal pulse (see CONVST input Control Register section). Larger capacitances this extend pulse allow settling time delays through external antialiasing filter signal conditioning circuitry. Convert Start. Edge-triggered logic input. high transition this input puts track/hold into hold initiates conversion provided that internal pulse timed (see Control Register section). internal pulse active when CONVST goes high, track/hold will into hold until pulse times out. internal pulse timed when CONVST goes high, rising edge CONVST drives track/hold into hold initiates conversion. Clock Input. external TTL-compatible clock applied this input provide clock source conversion sequence. Self-Clocking serial mode, SCLK output derived from this pin. Serial Clock Input. External Clocking (slave) mode (see Serial Interface section) this externally applied serial clock which used load serial data control register access data from output register. Self-Clocking (master) mode, internal serial clock, which derived from clock input (CLK IN), appears this pin. Once again, used load serial data control register access data from output register. Transmit Frame Synchronization Pulse. Active logic input with serial data expected after falling edge this signal. Receive Frame Synchronization Pulse. External Clocking mode, this active logic input with provided externally strobe framing pulse access serial data from output register. Self-Clocking mode, active output which internally generated provides strobe framing pulse serial data from output register. applications which require that data transmitted received same time, should connected together. Serial Data Output. Sixteen bits serial data provided with leading zero, preceding three address bits Control register bits conversion data. Serial data valid falling edge SCLK sixteen edges after goes low. Output coding from complement AD7890-10 straight binary AD7890-4 AD7890-2. Serial Data Input. Serial data loaded control register provided this input. first five bits serial data loaded control register first five falling edges SCLK after goes low. Serial data subsequent SCLK edges ignored while remains low. Positive supply voltage, Multiplexer Output. output multiplexer appears this pin. output voltage range from this output +2.5 nominal analog input range selected channel. output impedance this output nominally external antialiasing filter required, should connected Track/Hold Input. input on-chip track/hold applied this pin. high impedance input input voltage range +2.5 Analog Ground. Ground reference track/hold, comparator DAC. Analog Input Channel Single-ended analog input. analog input range (AD7890-10), +4.096 (AD7890-4) +2.5 (AD7890-2). channel converted selected using bits control register. multiplexer guaranteed break-before-make operation.
DGND CEXT
CONVST
SCLK
DATA
DATA
AGND VIN1
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AD7890
Mnemonic VIN2 Description Analog Input Channel Single-ended analog input. analog input range (AD789010), +4.096 (AD7890-4) +2.5 (AD7890-2). channel converted selected using bits control register. multiplexer guaranteed break-before-make operation. Analog Input Channel Single-ended analog input. analog input range (AD789010), +4.096 (AD7890-4) +2.5 (AD7890-2). channel converted selected using bits control register. multiplexer guaranteed break-before-make operation. Analog Input Channel Single-ended analog input. analog input range (AD789010), +4.096 (AD7890-4) +2.5 (AD7890-2). channel converted selected using bits control register. multiplexer guaranteed break-before-make operation. Analog Input Channel Single-ended analog input. analog input range (AD789010), +4.096 (AD7890-4) +2.5 (AD7890-2). channel converted selected using bits control register. multiplexer guaranteed break-before-make operation. Analog Input Channel Single-ended analog input. analog input range (AD789010), +4.096 (AD7890-4) +2.5 (AD7890-2). channel converted selected using bits control register. multiplexer guaranteed break-before-make operation. Analog Input Channel Single-ended analog input. analog input range (AD789010), +4.096 (AD7890-4) +2.5 (AD7890-2). channel converted selected using bits control register. multiplexer guaranteed break-before-make operation. Analog Input Channel Single-ended analog input. analog input range (AD789010), +4.096 (AD7890-4) +2.5 (AD7890-2). channel converted selected using bits control register. multiplexer guaranteed break-before-make operation. Voltage Reference Output/Input. part used with either internal reference with external reference source. on-chip +2.5 reference voltage provided this pin. When using this internal reference reference source part, should decoupled AGND with disc ceramic capacitor. output impedance this reference source typically When using external reference source reference voltage part, reference source should connected this pin. This overdrives internal reference provides reference source part. input buffered on-chip. nominal reference voltage correct operation AD7890 +2.5
CONFIGURATION SOIC
AGND SMODE DGND CEXT CONVST SCLK OUT/REF VIN8 VIN7 VIN6 VIN5
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
OUT/REF
AD7890
VIEW (Not Scale)
VIN4 VIN3
VIN2 VIN1
DATA DATA
AGND
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AD7890
TERMINOLOGY Signal (Noise Distortion) Ratio This measured ratio signal (noise distortion) output converter. signal amplitude fundamental. Noise nonfundamental signals half sampling frequency (fS/2), excluding ratio dependent upon number quantization levels digitization process; more levels, smaller quantization noise. theoretical signal (noise distortion) ratio ideal N-bit converter with sine wave input given Signal (Noise Distortion) (6.02N 1.76) Thus 12-bit converter, this
Total Harmonic Distortion Channel-to-Channel Isolation
Channel-to-channel isolation measure level crosstalk between channels. measured applying fullscale signal other seven inputs determining much that signal attenuated channel interest. figure given worst case across eight channels.
Relative Accuracy
Relative accuracy endpoint nonlinearity maximum deviation from straight line passing through endpoints transfer function.
Differential Nonlinearity
Total harmonic distortion (THD) ratio harmonics fundamental. AD7890, defined
This difference between measured ideal change between adjacent codes ADC.
Positive Full-Scale Error (AD7890-10)
This deviation last code transition 111) from ideal LSB) after Bipolar Zero Error been adjusted out.
Positive Full-Scale Error (AD7890-4)
where amplitude fundamental amplitudes second through sixth harmonics.
Peak Harmonic Spurious Noise
This deviation last code transition 111) from ideal (1.638 LSB) after Unipolar Offset Error been adjusted out.
Positive Full-Scale Error (AD7890-2)
Peak harmonic spurious noise defined ratio value next largest component output spectrum fS/2 excluding value fundamental. Normally, value this specification determined largest harmonic spectrum, parts where harmonics buried noise floor, will noise peak.
Intermodulation Distortion
This deviation last code transition 111) from ideal (REF LSB) after Unipolar Offset Error been adjusted out.
Bipolar Zero Error (AD7890-10)
This deviation midscale transition (all from ideal (AGND).
Unipolar Offset Error (AD7890-2, AD7890-4)
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation terms those which neither equal zero. example, second order terms include fb), while third order terms include (2fa fb), (2fa fb), 2fb) 2fb). AD7890 tested using CCIF standard where input frequencies near input bandwidth used. this case, second third order terms different significance. second order terms usually distanced frequency from original sine waves while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamental expressed dBs.
This deviation first code transition 001) from ideal (AGND).
Negative Full-Scale Error (AD7890-10)
This deviation first code transition 001) from ideal LSB) after Bipolar Zero Error been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time time required output track/hold amplifier reach final value, within ±1/2 LSB, after conversion (the point which track/hold returns track mode). also applies situations where change selected input channel takes place where there step input change input voltage applied selected input AD7890. means that user must wait duration track/hold acquisition time after conversion after channel change/step input change before starting another conversion, ensure that part operates specification.
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AD7890
CONTROL REGISTER CONVERTER DETAILS
Control Register AD7890 contains bits information described below. serial clock pulses must provided part order write data Control Register (seven write required part Standby Mode). returns high before serial clock cycles then data transfer takes place Control Register write cycle will have restarted write data Control Register. however, CONV register (see below) Logic then conversion will initiated whenever Control Register write takes place regardless many serial clock cycles remains for. default (power-on) condition bits Control Register
CONV STBY
AD7890 eight-channel, 12-bit, single supply, serial data acquisition system. provides user with signal scaling, multiplexer, track/hold, reference, converter versatile serial logic functions single chip. signal scaling allows part handle input signals (AD7890-10) +4.096 input signals (AD7890-4) while operating from single supply. AD7890-2 contains signal scaling accepts analog input range +2.5 part operates from +2.5 reference which provided from part's internal reference from external reference source. Unlike other single chip data acquisition solutions, AD7890 provides user with separate access multiplexer converter. This means that flexibility separate multiplexer solutions sacrificed with one-chip solution. With access multiplexer output, user implement external signal conditioning between multiplexer track/hold. means that antialiasing filter used output multiplexer provide antialiasing function eight channels. Conversion initiated AD7890 either pulsing CONVST input writing Logic CONV Control Register. When using hardware CONVST input, rising edge CONVST signal, on-chip track/hold goes from track hold mode conversion sequence started provided internal pulse timed out. This internal pulse (which appears CEXT pin) initiated whenever multiplexer address loaded AD7890 Control Register. This pulse goes from high when serial write part initiated. starts discharge sixth falling clock edge SCLK serial write operation part. track/hold cannot into hold conversion cannot initiated until CEXT crossed trigger point discharge time voltage CEXT depends upon value capacitor connected CEXT (see CEXT Functioning section). fact that pulse initiated every time write control register takes place means that software conversion start track/hold signal always delayed internal pulse. conversion clock part generated from clock signal applied part. Conversion time AD7890 from rising edge hardware CONVST signal track/hold acquisition time obtain optimum performance from part, data read operation Control Register write operation should occur during conversion during prior next conversion. This allows part operate throughput rates external clocking mode achieve data sheet specifications. part operate slightly higher throughput rates kHz), again external clocking mode with degraded performance (see Timing Control section). throughput rate self-clocking mode limited serial clock rate kHz. unused inputs should connected voltage within nominal analog input range avoid noise pickup. AD7890-10, input channels which being converted goes more negative than interfere with conversion selected channel.
Address Input. This input most significant address input multiplexer channel selection. Address Input. This most significant address input multiplexer channel selection. Address Input. Least significant address input multiplexer channel selection. When address written control register, internal pulse initiated, pulse width which determined value capacitance CEXT pin. When this pulse active, ensures conversion process cannot activated. This allows multiplexer settling time track/hold acquisition time before track/hold goes into hold conversion initiated. applications where there antialiasing filter between filter settling time taken into account before input sampled. When internal pulse times out, track/hold goes into hold conversion initiated. Conversion Start. Writing this initiates conversion similar manner CONVST input. Continuous conversion starts take place when there this location. internal pulse conversion process initiated after sixth serial clock cycle write operation written this bit. With this bit, hardware conversion start i.e., CONVST input, disabled. Writing this enables hardware CONVST input. Standby Mode Input. Writing this places device standby power-down mode. Writing this places device normal operating mode. part does enter standby mode until seventh falling edge SCLK write operation. Therefore, part requires seven serial clock pulses serial write operation required part into standby.
CONV
STBY
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AD7890
CIRCUIT DESCRIPTION Analog Input Section
AD7890 offered three part types, AD7890-10 which handles input voltage range, AD7890-4 which handles +4.096 input range AD7890-2 which handles +2.5 input voltage range. AD7890-10 Figure shows analog input section AD7890-10. analog input range each analog inputs into input resistance typically This input benign with dynamic charging currents with resistor attenuator stage followed multiplexer cases where connected this followed high input impedance stage track/hold amplifier. designed code transitions occur successive integer values (i.e., LSB, LSBs, LSBs.). Output coding complement binary with FS/4096 V/4096 4.88 ideal input/ output transfer function shown Table
+2.5V REFERENCE
tions occur successive integer values (i.e., LSB, LSBs, LSBs Output coding straight (natural) binary with FS/4096 4.096 V/4096 ideal input/output transfer function shown Table
+2.5V REFERENCE
OUT/
REFERENCE CIRCUITRY
VINX 9.38k AGND
200*
AD7890-4
*EQUIVALENT ON-RESISTANCE MULTIPLEXER
Figure AD7890-4 Analog Input Structure
Table Ideal Input/Output Code Table AD7890-4
REFERENCE CIRCUITRY
OUT/
Analog Input1 +FSR LSB2 (4.095 +FSR LSBs (4.094 +FSR LSBs (4.093 AGND LSBs (0.003 AGND LSBs (0.002 AGND (0.001
Digital Output Code Transition
7.5k VINX AGND 200*
AD7890-10
*EQUIVALENT ON-RESISTANCE MULTIPLEXER
Figure AD7890-10 Analog Input Structure
NOTES full-scale range 4.096 with +2.5 FSR/4096 with +2.5
Table Ideal Input/Output Code Table AD7890-10 Analog Input1 +FSR/2 LSB2 (9.995117 +FSR/2 LSBs (9.990234 +FSR/2 LSBs (9.985352 AGND (0.004883 AGND (0.000000 AGND (-0.004883 -FSR/2 LSBs (-9.985352 -FSR/2 LSBs (-9.990234 -FSR/2 (-9.995117 Digital Output Code Transition
AD7890-2 analog input section AD7890-2 contains biasing resistors selected analog input connects multiplexer cases where connected this followed high input impedance stage track/ hold amplifier. analog input range therefore, +2.5 into high impedance stage with input current less than designed code transitions occur successive integer values (i.e., LSB, LSBs, LSBs FS-1 LSBs). Output coding straight (natural) binary with FS/4096 V/4096 0.61 ideal input/output transfer function shown Table III.
Table III. Ideal Input/Output Code Table AD7890-2
NOTES full-scale range with +2.5 FSR/4096 4.883 with +2.5
Analog Input1 +FSR LSB2 (2.499390 +FSR LSBs (2.498779 +FSR LSBs (2.498169 AGND LSBs (0.001831 AGND LSBs (0.001221 AGND (0.000610
Digital Output Code Transition
AD7890-4 Figure shows analog input section AD7890-4. analog input range each analog inputs into input resistance typically This input benign with dynamic charging currents with resistor attenuator stage followed multiplexer cases where connected this followed high input impedance stage track/hold amplifier. designed code transi-
NOTES full-scale range with +2.5 FSR/4096 0.61 with +2.5
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AD7890
Track/Hold Section
input AD7890 connects directly input stage track/hold amplifier. This high impedance input with input leakage currents less than Connecting directly connects multiplexer output directly track/hold amplifier. input voltage range this input +2.5 external circuitry connected between then user must ensure that input voltage range input +2.5 ensure that full dynamic range converter utilized. track/hold amplifier AD7890 allows accurately convert input sine wave full-scale amplitude 12-bit accuracy. input bandwidth track/hold greater than Nyquist rate even when operated maximum throughput rate (i.e., track/hold handle input frequencies excess kHz). track/hold amplifier acquires input signal 12-bit accuracy less than operation track/hold essentially transparent user. track/hold amplifier goes from tracking mode hold mode start conversion. start conversion rising edge CONVST (assuming internal pulse timed out) hardware conversion starts software conversion starts point where internal pulse timed out. aperture time track/hold (i.e., delay time between external CONVST signal track/hold actually going into hold) typically software conversion starts, time depends internal pulse widths. Therefore, software conversion starts, sampling instant very well defined. sampling systems which require well defined, equidistant sampling, possible achieve optimum performance from part using software conversion start. conversion, part returns tracking mode. acquisition time track/ hold amplifier begins this point.
Reference Section
application requires reference with tighter tolerance AD7890 needs used with system reference, then user option connecting external reference this OUT/REF pin. external reference will effectively overdrive internal reference thus provide reference source ADC. reference input buffered nominal resistor connected AD7890's internal reference. Suitable reference sources AD7890 include AD680, AD780 REF-43 precision +2.5 references.
Timing Control Section
AD7890 capable interface modes, selected SMODE input. first these self-clocking mode where part provides frame sync, serial clock serial data conversion. this mode serial clock rate determined master clock rate part input). second mode external clocking mode where user provides frame sync serial clock signals obtain serial data from part. this second mode, user control serial clock rate maximum MHz. modes discussed more detail Serial Interface section. part also provides hardware software conversion start features. former provides well-defined sampling instant with track/hold going into hold rising edge CONVST signal. software conversion start, write CONV Control Register initiates conversion sequence. However, software conversion start internal pulse time before input signal sampled. This pulse, plus difficult maintaining exactly equal delays between each software conversion start command, means that dynamic performance AD7890 have difficulty meeting spec when used software conversion start mode. AD7890 provides separate channel select conversion start control. This allows user optimize throughput rate system. Once track/hold gone into hold mode, input channel updated input voltage settle value while present conversion progress. Assuming internal pulse timed before CONVST pulse exercised, conversion will consist 14.5 master clock cycles. self-clocking mode, conversion time defined time from rising edge CONVST falling edge (i.e., when device starts transmit conversion result). This time includes 14.5 master clock cycles plus updating output register delay time outputting signal, resulting total conversion time maximum. Figure shows conversion timing AD890 when used Self-Clocking (Master) Mode with hardware CONVST. timing diagram assumes that internal pulse active when CONVST signal goes high. ensure this, channel address converted should selected writing Control Register prior CONVST pulse. Sufficient setup time should allowed between Control Register write CONVST ensure that internal pulse timed out. duration internal pulse (and hence duration setup time) depends value CEXT.
AD7890 contains single reference pin, labelled OUT/REF which either provides access part's +2.5 reference which external +2.5 reference connected provide reference source part. part specified with +2.5 reference voltage. Errors reference source will result gain errors AD7890's transfer function will specified full-scale errors part. AD7893-10, will also result offset error injected attenuator stage. AD7890 contains on-chip +2.5 reference. this reference reference source AD7890, simply connect disc ceramic capacitor from OUT/ AGND. voltage which appears this internally buffered before being applied ADC. this reference required external AD7890, should buffered source impedance this output nominal. tolerance internal reference 25°C with typical temperature coefficient ppm/°C maximum error over temperature
-10-
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AD7890
CONVST TRACK/HOLD GOES INTO HOLD
tCONVERT
SCLK
THREE-STATE DATA NOTE SIGNIFIES INPUT; SIGNIFIES OUTPUT. PULL-UP RESISTOR SCLK.
Figure Self-Clocking {Master) Mode Conversion Sequence
When using device External-Clocking Mode, output register read time most up-to-date conversion result will obtained. However, reading data from output register writing data Control Register during conversion during prior next CONVST will result reduced performance from part. read operation output register most effect performance with signal-to-noise ratio likely degrade especially when higher serial clock rates used while code flicker from part will also increase (see AD7890 Performance section). Figure shows timing control sequence required obtain optimum performance from part external clocking mode. sequence shown, conversion initiated rising edge CONVST data available output register AD7890 later. Once read operation taken place, further should allowed before
next rising edge CONVST optimize settling track/hold before next conversion initiated. diagram shows read operation write operation taking place parallel. sixth falling edge SCLK write sequence internal pulse will initiated. Assuming connected required between this sixth falling edge SCLK rising edge CONVST allow full acquisition time track/hold amplifier. With serial clock rate maximum MHz, achievable throughput rate part (conversion time) plus (six serial clock pulses before internal pulse initiated) plus (acquisition time). This results minimum throughput time (equivalent throughput rate kHz). part operated with slower serial clock, will impact achievable throughput rate optimum performance.
CONVST
SCLK
tCONVERT
500ns
CONVERSION INITIATED TRACK/HOLD GOES INTO HOLD
CONVERSION ENDS 5.9µs LATER
SERIAL READ WRITE OPERATIONS
READ WRITE OPERATIONS SHOULD 500ns PRIOR NEXT RISING EDGE CONVST
NEXT CONVERSION START COMMAND
Figure External Clocking (Slave) Mode Timing Sequence Optimum Performance
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-11-
AD7890
CONVST
SCLK
tCONVERT
500ns
CONVERSION INITIATED TRACK/HOLD GOES INTO HOLD
CONVERSION ENDS 5.9µs SERVICE POLLING LATER ROUTINE
SERIAL READ WRITE OPERATIONS
READ WRITE OPERATIONS SHOULD 500ns PRIOR NEXT RISING EDGE CONVST
NEXT CONVST RISING EDGE
Figure CONVST Used Status Signal External Clocking Mode
Self-Clocking Mode, AD7890 indicates when conversion complete bringing line initiating serial data transfer. external clocking mode, there indication when conversion complete. many applications, this will problem data read from part during conversion after conversion. However, applications which want achieve optimum performance from AD7890 will have ensure that data read does occur during conversion during prior rising edge CONVST. This achieved either ways. first ensure software that read operation initiated until after rising edge CONVST. This will only possible software knows when CONVST command issued. second scheme would CONVST signal both conversion start signal interrupt signal. simplest this would generate square wave signal CONVST with high times (see Figure Conversion initiated rising edge CONVST. falling edge CONVST occurs later used either active falling edge-triggered interrupt signal tell processor read data from AD7890. Provided read operation completed before rising edge CONVST, AD7890 will operate specification. This scheme limits throughput rate 11.8 minimum. However, depending upon response time microprocessor interrupt signal time taken processor read data, this fastest which system could have operated. case, CONVST signal does have have 50:50 duty cycle. This tailored optimize throughput rate part given system. Alternatively, CONVST signal used normal narrow pulse width. rising edge CONVST used active high rising edge-triggered interrupt. software delay then implemented before data read from part.
CEXT FUNCTIONING
CEXT input AD7890 provides means determining long after channel address written part that conversion take place. reason behind this two-fold. Firstly, when input channel AD7890 changed, input voltage this channel likely very different from previous channel voltage. Therefore, part's track/hold acquire voltage before accurate conversion take place. internal pulse delays conversion start command well signal send track/ hold into hold) until after this pulse timed out. second reason allow user connect external antialiasing signal conditioning circuitry between This external circuitry will introduce extra settling time into system. CEXT provides means user extend internal pulse take this extra settling time into account. Basically, varying value capacitor CEXT varies duration internal pulse. Figure shows relationship between value CEXT capacitor internal delay.
INTERNAL PULSE WIDTH
1000
1250
1500
1750
2000
CEXT CAPACITANCE
Figure Internal Pulse Width CEXT
-12-
REV.
AD7890
duration internal pulse seen CEXT pin. CEXT goes from high when serial write part initiated falling edge TFS). starts discharge sixth falling edge SCLK serial write operation. Once CEXT discharged crossing nominal trigger point internal pulse timed out. internal pulse initiated each time write operation Control Register takes place. result, pulse initiated conversion process delayed software conversion start commands. hardware conversion start, possible separate conversion start command from internal pulse. multiplexer output (MUX OUT) connected directly track/hold input (SHA IN), then external settling taken into account internal pulse width. applications where multiplexer switched conversion initiated until more than after channel changed possible with hardware conversion start), user does have worry about connecting capacitance CEXT pin. equates track/hold acquisition time AD7890. applications where multiplexer switched conversion initiated same time (such with software conversion start), capacitor should connected CEXT allow acquisition time track/hold before conversion initiated. external circuitry connected between then extra settling time introduced this circuitry will have taken into account. case where multiplexer change command conversion start command separated, they need separated greater than acquisition time AD7890 plus settling time external circuitry user does have worry about CEXT capacitance. applications where multiplexer switched conversion initiated same time (such with software conversion start), capacitor CEXT needs allow acquisition time track/hold plus settling-time external circuitry before conversion initiated.
SERIAL INTERFACE
AD7890's serial communications port provides flexible arrangement allow easy interfacing industry-standard microprocessors, microcontrollers digital signal processors. serial read AD7890 accesses data from output register DATA line. serial write AD7890 writes data Control Register DATA line. different modes operation available, optimized different types interface where AD7890 either master system provides serial clock data framing signal) acts slave external serial clock framing signal provided AD7890). These modes, labelled Self-Clocking Mode External Clocking Mode, discussed detail following sections. Self-Clocking Mode AD7890 configured Self-Clocking Mode tying SMODE device logic low. this mode, AD7890 provides serial clock signal serial data framing signal used transfer data from AD7890. This Self-Clocking Mode used with processors which allow external device clock their serial port including most digital signal processors.
Read Operation
Figure shows timing diagram reading from AD7890 Self-Clocking mode. conversion, goes serial clock (SCLK) serial data (DATA OUT) outputs become active. Sixteen bits data transmitted with leading zero, followed three address bits Control Register, followed 12-bit conversion result starting with MSB. Serial data clocked device rising edge SCLK valid falling edge SCLK. output remains duration sixteen clock cycles. sixteenth rising edge SCLK, output driven high DATA disabled.
SCLK
DATA 3-STATE LEADING ZERO
DB11 DB10 3-STATE
NOTE SIGNIFIES INPUT; SIGNIFIES OUTPUT. PULL-UP RESISTOR SCLK.
Figure Self-Clocking (Master) Mode Output Register Read
REV.
-13-
AD7890
SCLK
DON'T CARE DON'T CARE DON'T CARE
DATA
CONV
STBY
NOTE SIGNIFIES INPUT; SIGNIFIES OUTPUT. PULL-UP RESISTOR SCLK.
Figure Self-Clocking (Master) Mode Control Register Write
Write Operation
Figure shows write operation Control Register AD7890. input taken indicate part that serial write about occur. going initiates SCLK output this used clock data processors serial port into Control Register AD7890. AD7890 Control Register requires only five bits data. These loaded first five clock cycles serial clock with data subsequent clock cycles being ignored. However, part requires serial clock cycles load data Control Register. Serial data written AD7890 must valid falling edge SCLK.
External-Clocking Mode
AD7890 configured external clocking mode tying SMODE device logic high. this mode, SCLK AD7890 configured inputs. This external-clocking mode designed direct interface systems which provide serial clock output which synchronized serial data output including microcontrollers such 80C51, 87C51, 68HC11 68HC05 most digital signal processors.
Read Operation
transmitted with leading zero, followed three address bits Control Register, followed 12-bit conversion result starting with MSB. goes during high time SCLK, leading zero clocked from falling edge Figure 10). goes during time SCLK, leading zero clocked next rising edge SCLK. This ensures that, regardless whether goes during high time time SCLK, leading zero valid first falling edge SCLK after goes low, provided adhered Serial data clocked device rising edge SCLK valid falling edge SCLK. read operation, DATA line three-stated rising edge either SCLK inputs, whichever occurs first. serial read from output register progress when conversion complete, updating output register deferred until serial data read complete returns high.
Write Operation
Figure shows timing diagram reading from AD7890 external-clocking mode. goes access data from AD7890. serial clock input does have continuous. serial data accessed number bytes. However, must remain duration data transfer operation. Once again, sixteen bits data
Figure shows write operation Control Register AD7890. with Self-Clocking mode, input goes indicate part that serial write about occur. before, AD7890 Control Register requires only five bits data. These loaded first five clock cycles serial clock with data subsequent clock cycles being ignored. However, part requires serial clocks load data Control Register. Serial data written AD7890 must valid falling edge SCLK.
SCLK
t19A
3-STATE
DATA LEADING ZERO DB11
DB10
NOTE SIGNIFIES INPUT; SIGNIFIES OUTPUT
Figure External Clocking (Slave) Mode Output Register Read
-14-
REV.
AD7890
SCLK
DATA CONV STBY DON'T CARE DON'T CARE DON'T CARE
NOTE SIGNIFIES INPUT; SIGNIFIES OUTPUT.
Figure External Clocking (Slave) Mode Control Register Write
SIMPLIFYING INTERFACE minimize number interconnect lines AD7890, user connect lines AD7890 together read write from part simultaneously. this case, control register data should provided DATA line selecting input channel possibly providing conversion start command while part provides result from conversion just completed DATA line. self-clocking mode, this means that part provides signals serial interface. does require that microprocessor data written Control Register available output register when part brings line low. external clocking mode, means that user only supply single frame synchronization signal control both read write operations. Care must taken with this scheme that read operation completed before next conversion starts user wants obtain optimum performance from part. case software conversion start, conversion command written Control Register sixth serial clock edge. However, read operation continues another serial clock cycles. avoid reading during sampling instant during conversion, user should ensure that internal pulse width sufficiently long choosing CEXT) that read operation completed before next conversion sequence begins. Failure this will result significantly degraded performance from part, both terms signal-to-noise ratio parameters. case hardware conversion start, user should ensure that delay between sixth falling edge serial clock write operation next rising edge CONVST greater than internal pulse width.
MICROPROCESSOR/MICROCONTROLLER INTERFACE
AD7890-8051 Interface
Figure shows interface between AD7890 8XC51 microcontroller. AD7890 configured external clocking mode while 8XC51 configured Mode serial interface mode. diagram shown Figure makes provisions monitoring when conversion complete AD7890 (assuming hardware conversion start used). monitor conversion time AD7890 scheme such outlined previously with CONVST used. This implemented ways. connect CONVST line another parallel port which configured input. This port then polled determine when conversion complete. alternative interrupt driven system which case CONVST line should connected INT1 input 8XC51. Since 8XC51 contains only serial data line, DATA DATA lines AD7890 must connected together. This means that 8XC51 cannot communicate with output register Control Register AD7890 same time. 8XC51 outputs first write operation care should taken arranging data which transmitted AD7890. Similarly, AD7890 outputs first during read operation while 8XC51 expects first. Therefore, data that read into serial port needs rearranged before correct data word from AD7890 available microcontroller. serial clock rate from 8XC51 limited significantly less than allowable input serial clock frequency with which AD7890 operate. result, time read data from part will actually longer than conversion time part. This means that AD7890 cannot maximum throughput rate when used with 8XC51.
SMODE P1.0 P1.1
AD7890's flexible serial interface allows easy connection serial ports processors microcontrollers. Figures through show AD7890 interfaced number different microcontrollers processors. some interfaces shown, AD7890 configured master system, providing serial clock frame sync read operation while others acts slave with these signals provided microprocessor.
AD7890
8XC51
DATA P3.0 DATA
P3.1
SCLK
Figure AD7890 8XC51 Interface
REV.
-15-
AD7890
AD7890-68HC11 Interface interface circuit between AD7890 68HC11 microcontroller shown Figure interface shown, AD7890 configured external clocking mode while 68HC11's port used 68HC11 configured single-chip mode. 68HC11 configured master mode with CPOL logic zero CPHA logic one. with previous interface, there provisions monitoring when conversion complete AD7890. monitor conversion time AD7890 scheme, such outlined previous interface with CONVST, used. This implemented ways. connect CONVST line another parallel port which configured input. This port then polled determine when conversion complete. alternative interrupt driven system which case CONVST line should connected input 68HC11.
DVDD DVDD SMODE SCLK DATA DATA
scheme shown, maximum serial clock frequency which ADSP-2101 provide 6.25 MHz. This allows AD7890 operated sample rate kHz. desirable operate AD7890 maximum throughput rate kHz, external serial clock provided drive serial clock input both AD7890 ADSP-2101. monitor conversion time AD7890 scheme, such outlined previous interfaces with CONVST, used. This implemented connecting CONVST line directly IRQ2 input ADSP-2101. alternative this, where user does have worry about monitoring conversion status, operate AD7890 SelfClocking Mode. this scheme, actual interface connections would remain same Figure AD7890 provides serial clock receive frame synchronization signals. Using AD7890 Self-Clocking Mode, limits throughput rate system serial clock rate limited MHz.
AD7890-DSP56000 Interface
68HC11
MISO MOSI
AD7890
Figure shows interface circuit between AD7890 DSP56000 processor. AD7890 configured external clocking mode. DSP56000 configured normal mode, synchronous operation with continuous clock. also 16-bit word with outputs. DSP56000 should inputs AD7890 connected together data transmitted from AD7890 same time. With DSP56000 synchronous mode, provides common frame synchronization pulse read write operations output. This inverted before being applied inputs AD7890. monitor conversion time AD7890 scheme, such outlined previous interface examples with CONVST, used. This implemented connecting CONVST line directly IRQA input DSP56000.
DVDD SMODE
Figure AD7890 68HC11 Interface
serial clock rate from 68HC11 limited significantly less than allowable input serial clock frequency with which AD7890 operate. result, time read data from part will actually longer than conversion time part. This means that AD7890 cannot maximum throughput rate when used with 68HC11. AD7890-ADSP-2101 Interface interface circuit between AD7890 ADSP-2101 processor shown Figure AD7890 configured external clocking mode with ADSP-2101 providing serial clock frame synchronization signals. RFS1 TFS1 inputs outputs configured active operation.
DVDD SMODE RFS1 TFS1 SCLK DATA DATA
DSP56000
AD7890
SCLK DATA DATA
Figure AD7890 DSP56000 Interface
AD7890
ADSP-2101
SCLK1
AD7890-TMS320C25/30 Interface
Figure AD7890 ADSP-2101 Interface
Figure shows interface circuit between AD7890 TMS320C25/30 processor. AD7890 configured Self-Clocking Mode where provides serial clock frame synchronization signals. However, TMS320C25/30 requires continuous serial clock. scheme outlined here, AD7890's master clock signal, used provide serial clock processor. AD7890's output SCLK,
-16-
REV.
AD7890
which serial data referenced, delayed version signal. typical delay between SCLK will more than over supplies temperature. Therefore, there will still sufficient setup time DATA clocked into edges signal. When writing data AD7890, processor's data hold time sufficiently long cater delay between clocks. AD7890's signal connects both inputs processor. processor generate signal required interface modified that signals separated processor generates signal which connected input AD7890. scheme outlined here, user does have worry about monitoring conversion. Once conversion complete, AD7890 takes care transmitting back conversion result processor. Once sixteen bits data have been received processor into serial shift register, generates internal interrupt. Since connected together, data transmitted Control Register AD7890 whenever AD7890 transmits conversion result. user just ensure that word written AD7890 Control Register prior conversion. part interrupt routine which recognizes that data been read processor data which going write Control Register next time around.
INPUT
driven from impedance stage. This will remove effects from variation part's multiplexer on-resistance with input signal voltage will also remove effects high source impedance sampling input track/hold. With external antialiasing filter place, additional settlingtime associated with filter should accounted using larger capacitance CEXT.
AD7890 PERFORMANCE Linearity
linearity AD7890 primarily determined on-chip 12-bit converter. This segmented which laser trimmed 12-bit integral linearity differential linearity. Typical relative numbers part while typical errors LSB.
Noise
converter, noise exhibits itself code uncertainty applications noise floor FFT, example) applications. sampling converter like AD7890, information about analog input appears baseband from sampling frequency. input bandwidth track/hold exceeds Nyquist bandwidth and, therefore, antialiasing filter should used remove unwanted signals above fS/2 input signal applications where such signals exist. Figure shows histogram plot 8192 conversions input using AD7890. analog input centre code transition. timing control sequence used Figure where optimum performance achieved. same performance will achieved selfclocking mode where part transmits data after conversion complete. seen that almost codes appear output indicating very good noise performance from ADC. noise performance AD7890-2 above plot Since analog input range, hence size, AD7893-4 1.638 times what AD7893-2, same output code distribution results output noise AD7893-4. AD7890-10, with size eight times that AD7890-2, code distribution represents output noise
9000 SAMPLING FREQUENCY 102.4kHz +25°C
SMODE
TMS320C25/C30
CLKX CLKR
AD7890
SCLK
DATA DATA
Figure AD7890 TMS320C25/30 Interface
OCCURRENCES CODE
8000 7000 6000 5000 4000 3000 2000 1000
ANTIALIASING FILTER
AD7890 provides separate access multiplexer pins. reasons this allow user implement antialiasing filter between multiplexer ADC. Inserting antialiasing filter this point advantage that antialiasing filter suffice eight channels rather than separate antialiasing filter each channel they were placed prior multiplexer. antialiasing filter inserted between pins will generally low-pass filter remove high frequency signals which could possibly aliased back in-band during sampling process. recommended that this filter active filter, ideally with AD7890 driving high impedance stage part being
(X-4) (X-3) (X-2) (X-1)
CODE
(X+1) (X+2) (X+3) (X+4)
Figure Histogram 8192 Conversions Input
REV.
-17-
AD7890
external clocking mode, possible write data Control Register read data from output register while conversion progress. same data presented Figure Figure except that this case output data read device occurs during conversion. These results achieved with serial clock rate MHz. higher serial clock rate used, code transition noise will degrade from that shown plot Figure This effect injecting noise onto while decisions being made this increases noise generated AD7890. histogram plot 8192 conversions same input shows larger spread codes with noise AD7890-2 increasing This effect will vary depending where serial clock edges appear with respect trials conversion process. possible achieve same level performance when reading during conversion when reading after conversion depending relationship serial clock edges trial points (i.e., relationship serial clock edges edges). decision points AD7890 falling edges master clock (CLK during conversion process. Clocking data bits these points (i.e. rising edge SCLK) most critical from noise standpoint. most critical decisions MSBs, achieve level performance outlined Figure reading within after rising edge CONVST should avoided.
8000 7000
OCCURRENCES CODE
8000 7000 SAMPLING FREQUENCY 102.4kHz +25°C
OCCURRENCES CODE
6000 5000 4000 3000 2000 1000 (X-4) (X-3) (X-2) (X-1) CODE (X+1) (X+2) (X+3) (X+4)
Figure Histogram 8192 Conversions with Write During Conversion
Dynamic Performance
SAMPLING FREQUENCY 102.4kHz +25°C
AD7890 contains on-chip track/hold, allowing part sample input signals input channels. Many AD7890's applications will simply require sequence through frequency input signals across eight channels. There some applications, however, which dynamic performance converter input frequency interest. recommended these wider band sampling applications that hardware conversion start method used reasons outlined previously. These applications require information ADC's effect spectral content input signal. Signal (Noise Distortion), total harmonic distortion, peak harmonic spurious intermodulation distortion specified. Figure shows typical plot kHz, +2.5 input after being digitized AD7890-2 operating 102.4 sampling rate. signal (Noise Distortion) 71.5 total harmonic distortion should noted that reading data from part during conversion serial clock does have significant impact dynamic performance. Therefore, sampling applications, recommended read data during conversion.
SAMPLE RATE 102.4 INPUT FREQUENCY 71.5 +25°C
6000 5000 4000 3000 2000 1000 (X-4) (X-3) (X-2) (X-1) CODE (X+1) (X+2) (X+3) (X+4)
SIGNAL AMPLITUDE
Figure Histogram 8192 Conversions with Read During Conversion
Writing data Control Register also effect introducing digital activity onto part while conversion progress. However, since there output drivers active during write operation, amount current flowing less than read operation. Therefore, amount noise injected into less than read operation. Figure shows effect write operation during conversion. histogram plot 8192 conversions same input shows larger spread codes than ideal conditions smaller than read operation. resulting noise AD7890-2 this case, serial clock frequency MHz.
-120 25.6 FREQUENCY SIGNAL (NOISE DISTORTION) RATIO. 51.2
Figure AD7890 Plot
-18-
REV.
AD7890
Effective Number Bits
EFFECTIVE NUMBER BITS
formula Signal (Noise Distortion) Ratio (See Terminology section) related resolution number bits converter. Rewriting formula, below, gives measure performance expressed effective number bits (N): (SNR 1.76)/6.02 where Signal (Noise Distortion) Ratio
effective number bits device calculated from measured Signal (Noise Distortion) Ratio. Figure shows typical plot effective number bits versus frequency AD7890-2 from kHz. sampling frequency 102.4 kHz. plot shows that AD7890 converts input sine wave effective numbers bits which equates Signal (Noise Distortion) level
11.5
10.5
INPUT FREQUENCY
Figure Effective Number Bits Frequency
REV.
-19-
AD7890
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
Plastic (N-24)
0.260 0.001 (6.61 0.03)
1.228 (31.19) 1.226 (31.14) 0.130 (3.30) 0.128 (3.25)
0.32 (8.128) 0.30 (7.62)
SEATING PLANE 0.02 (0.5) 0.016 (0.41) 0.11 (2.79) 0.09 (2.28) 0.07 (1.78) 0.05 (1.27)
0.011 (0.28) 0.009 (0.23)
NOTES LEAD IDENTIFIED NOTCH PLASTIC LEADS WILL EITHER SOLDER DIPPED PLATED ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
Cerdip (Q-24)
1.290 (32.77) 0.225 (5.715) 0.125 (3.175) 0.021 (0.533) 0.015 (0.381) 0.110 (2.794) 0.090 (2.286) 0.065 (1.651) 0.055 (1.397) 0.180 (4.572) 0.012 (0.305) 0.008 (0.203) 0.320 (8.128) 0.290 (7.366) 0.295 (7.493)
0.070 (1.778) 0.020 (0.508) SEATING PLANE
LEAD IDENTIFIED NOTCH. CERDIP LEADS WILL EITHER PLATED SOLDER DIPPED ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
SOIC (R-24)
15.6 (0.614) 15.2 (0.598) 0.419 (10.65) 0.394 (10.00)
0.299 (7.6) 0.291 (7.4)
0.050 (1.27)
0.019 (0.49) 0.014 (0.35)
0.104 (2.65) 0.093 (2.35)
0.03 (0.75) 0.01 (0.25) 0.013 (0.32) 0.009 (0.23)
0.012 (0.3) 0.004 (0.1) 0.005 (1.27) 0.016 (0.40)
-20-
REV.
PRINTED U.S.A.
C1822-6-7/93
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