ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS* RECOMMENDED OPERATING COND
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PRELIMINARY W925E/C625 8-bit Microcontroller
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS* RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS GAIN CONTROL OP-AMPLIFIER ELECTRICAL CHARACTERISTICS
PACKAGE.
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
FIGURE W925E/C625 CONFIGURATION FIGURE PROGRAM MEMORY FIGURE MEMORY FIGURE SCRATCHPAD RAM/REGISTER ADDRESSING FIGURE STRUCTURE FLAGS FIGURE MODE MODE TIMER/COUNTER FIGURE MODE TIMER/COUNTER FIGURE WATCHDOG TIMER FIGURE TIMING SERIAL PORT INPUT FUNCTION FIGURE TIMING SERIAL PORT OUTPUT FUNCTION FIGURE 6-10 CONFIGURATION COMPARATOR FIGURE 6-11 RELATION BETWEEN DTMF KEYPAD FIGURE 6-12 MODULATOR FIGURE 6-13 13/14-BIT DIVIDER FIGURE 6-14 ALTERNATING FREQUENCY (FLCD) CIRCUIT DIAGRAM. FIGURE 6-15 BIAS POWER CONNECTION FIGURE 6-16 WAVEFORM BIAS FIGURE 6-17 BLOCK DIAGRAM FIGURE 6-18 APPLICATION CIRCUIT RING DETECTOR FIGURE 6-19 DIFFERENTIAL INPUT GAIN CONTROL CIRCUIT FIGURE 6-20 SINGLE-ENDED INPUT GAIN CONTROL CIRCUIT. FIGURE 6-21 GUARD TIME WAVEFORM ALERT TONE SIGNAL DETECTION FIGURE 6-22 WAVEFORM DTMF DETECTION FIGURE 6-23 DETECTION ENABLE CARRIER PRESENT ABSENT TIMING FIGURE 6-24 SERIAL DATA INTERFACE TIMING DEMODULATION FIGURE 6-25 INTERNAL GAIN CONTROL REGISTER SETTING WAVEFORM FIGURE 6-26 APPLICATION CIRCUIT FIGURE 6-27 INPUT OUTPUT TIMING BELLCORE N-HOOK DATA TRANSMISSION FIGURE 6-28 INPUT OUTPUT TIMING BELLCORE FF-HOOK TRANSMISSION FIGURE 6-29 INPUT OUTPUT TIMING IDLE STATE (ON-HOOK) DATA TRANSMISSION FIGURE 6-30 INPUT OUTPUT TIMING LOOP STATE (OFF-HOOK) DATA TRANSMISSION FIGURE 6-31 INPUT OUTPUT TIMING CALLER DISPLAY SERVICE DATA TRANSMISSION
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
GENERAL DESCRIPTION
W925E/C625 all-in-1 single 8-bit micro-controller with widely used Calling Identity Delivery (CID) function. 8-bit core based 8051 family; therefore, instructions compatible Turbo 8051 series. part consists decoder, DTMF receiver, CPE* Alert Signal (CAS) detector Ring detector. Also built-in DTMF generator generator with baud rate 1200 (bits/sec). Using W925E/C625 easily implement adjunct feature phone Short Message Service (SMS) phone with function. main features listed next section.
FEATURES
APPLICATION: phone with function adjunct box. CPU: 8-bit micro-controller similar 8051 family. Operating voltage: volt. CID: volt. Dual-clock operation: Main oscillator: 3.58MHz crystal DTMF function. built-in oscillator. oscillator: 32768Hz crystal. Main oscillators enable/disable control individually. ROM: bytes internal flash EEPROM/MASK type. bytes program ROM. total bytes look-up table ROM. RAM: bytes chip scratch-pad RAM. bytes chip MOVX instruction. bytes chip RAM. LCD: matrix control method. 1792 dots: Segments Common, bias. CID: Compatible with Bellcore TR-NWT-000030 SR-TSV-002476, British Telecom(BT) SIN227, U.K. Cable Communication Association(CCA) specification. modulator/demodulator: Bell ITU-T V.23 with 1200 baud rate. detector: dual tones Bellcore Idle State Loop State Dual Tone Alert Signal (DTAS). DTMF generator/receiver; DTMF receiver programmed tone detector. Ring detector: line reversal ring burst ring signal Bellcore. independent amps with adjustable gain Tip/Ring Telephone Hybrid connections. I/O: pins. byte addressable. mode controlled. Open drain type. P1~P3: byte addressable. Pull high mode controlled. Byte addressable Pull high mode controlled.
note: "CPE*" Customer Premises Equipment
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Power mode: Normal mode: Normal operation Dual-clock slow operation mode: System operated sub-oscillator (Fosc=Fs stopped) Idle mode: hold. clock halted, interrupt, timer watchdog timer block work normally function disabled. Power down mode: activity completely stopped power consumption less than Timer: 13/16-bit timers, 8-bit auto-reload timers, that Timer0 Timer1. Watchdog timer: programmed user serve system monitor. Interrupt: interrupt sources with levels priority. interrupts from INT0, INT1, INT2 INT3. interrupts from Timer0, Timer1. interrupt from Serial port. interrupt from CID. interrupt from 13/14-bit Divider. interrupt from Comparator. interrupt from Watch Timer. Divider: 13/14 divider, clock source from sub-oscillator, therefore, DIVF every 0.25/0.5 Sec. Comparator: Comparator: analog inputs from VNEG pin, reference input pins, from VPOS another from internal 1.0v regulator output. Serial port: 8-bit serial transceiver with SCLK SDATA. Package: 160pin
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
CONFIGURATION
Figure shows assignment. package type 160pin QFP.
SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 VLCD5 VLCD4 VLCD3 VLCD2 VLCD1 RESET/VPP TEST/MODE P44/VPOS P42/VNEG
SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47
W925E/C625
DTMF/FSK EA/DATA XOUT2 XIN2 XIN1 XOUT1
SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 INP2 INN2 GCFB2 GCFB1 INN1 INP1 VREF RNGDI RNGRC
Figure W925E/C625 Configuration
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
DESCRIPTION
TEST pin. version, works Mode select programming mode. version(Mask type), this with internal pull-low resistor test mode. high normal function. version, works Data pin. version, this with internal pull-high resistor. RESET pin. pulse causes whole chip reset. version, this work which supply programming voltage. version, this with internal pull-high resistor. Ring Detect Input (Schmitt trigger input). Used ring detection line reversal detection. Must maintain voltage between VAS. Ring (Open drain output Schmitt trigger input). Used time interval from RNGDI inactive condition RNGON pin. external resistor must connected capacitor connected VSS, time interval time constant. Must connected 0.1µF capacitor VSS. Reference Voltage. Nominally, VDD/2 used bias input gain control op-amp. Op-amp1 Feed-back Gain Control signal. Select input gain connecting this INN1 with feed-back resistor. recommended that op-amp1 unity gain. Inverting Input gain control op-amp1. Non-inverting Input gain control op-amp1. Op-amp2 Feed-back Gain Control signal. Select input gain connecting this INN2 with feed-back resistor. recommended that op-amp2 unity gain. Inverting Input gain control op-amp2. Non-inverting Input gain control op-amp2. Analog voltage supply. Analog ground. Digital voltage supply. Digital ground. Output main-oscillator. Connected 3.58MHz crystal function. Input main-oscillator. Connected 3.58MHz crystal function. Output sub-oscillator with internal oscillation capacitor. Connected 32.768KHz crystal only. Input sub-oscillator must external capacitor about 15pF ground(VSS) accuracy oscillator. Connected 32.768KHz crystal only. FTE=0, Dual-Tone Multi-Frequency(DTMF) signal output FTE=1, signal output
TEST/MODE
/DATA
I,I/O
RESET /VPP RNGDI RNGRC
VREF GCFB1
INN1 INP1 GCFB2
INN2 INP2 XOUT1 XIN1 XOUT2 XIN2
DTMF/FSK
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
P00-P07 Buzzer output pin. buzzer function disabled, floating state. Input/Output port0. Port0 data controlled. mode controlled P0IO register. Port0 open drain type when configured output mode. Input/Output port1 with pull high resistors. Port1 data controlled. mode controlled P1IO register. P10-P13 P14-P17 indicates external interrupt pins(INT2 INT3) Input/Output port2 with pull high resistors. Port2 data controlled. mode controlled P2IO register. Input/Output port3 with pull high resistors. Port3 data controlled. mode controlled P3IO register. special function port3 referred description register. Contents byte controlled. Pull high mode controlled. special function referred description register. comparator analog input pins. Share with P4.2 P4.4 Connection terminals voltage doublers capacitor. Positive voltage supply terminals. segment output pins. common output pins.
P10-P17
P20-P27 P30-P37
P40-P47 VPOS, VNEG DH1,DH2 VLCD1-5 SEG0SEG55 COM0COM31
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
BLOCK DIAGRAM
Internal interface
RNGDI RNGRC INP1 INN1 GCFB1 INP2 INN2 GCFB2 VREF CIDE FSKE CASE
Fosc
FSK,CAS (W91030)
ALGO CASH,CASL
CASPT CASAT
DTMFD
DTMFPT DTMFAT
DTMFE
DTMF RECEIVER
DCLK
DATA
DCLK FDATA FD7~FD0
DTMFH DTMFL
DD3~DD0
D-latch
RNGF ALGOF FDRF DTMFDF
8-bit
modulator
TEST/MODE
SEG00 SEG55
COM00 COM31
VLCD1 VLCD5
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
FUNCTIONAL DESCRIPTION
W925E/C625 8-bit micro-controller with function. 8-bit micro-control same instruction 8051 family, with addition: DPTR (op-code A5H, DPTR decreased addition, W925E/C625 contains on-chip bytes MOVX RAM. ROM: There bytes EEPROM/MASK ROM. total bytes EEPROM/MASK used program code. completely bytes EEPROM/MASK used look-up table memory. On-chip Data RAM: W925E/C625 normal Bytes discontinuity which address from 0000H 0FFFH 2000H 20FEH. only accessed MOVX instruction; this onchip optional under software control. bytes RAM, which appends bytes RAM, used RAM. on-chip data used executable program memory. There conflict overlap among bytes scratchpad Bytes MOVX they different addressing modes separate instructions. CID: functions include decoder, tone alert signal detector, DTMF decoder ring detector. modulator: Support ITU-T V.23 Bellcore transmit modulate signal DTMF modulator: W925E/C625 built-in Dual tone multi-frequency generator. Ports: W925E/C625 five 8-bit ports giving total lines. Port0 Port3 used 8-bit general port with bit-addressable. mode each port controlled PxIO registers. Port Port have internal pull high resistors enabled/disabled registers. Port0 open-drain type output mode. Serial port: serial port, through P4.0 (SCLK) P4.1 (SDATA), 8-bit synchronous serial interface. Timers: W925E/C625 13/16-bit timers bits auto-reload timers. independent watchdog timer used System Monitor very long time period timer. divider produce divider interrupt every period 0.5S 0.25S. Comparator: W925E/C625 internal comparator with external analog signal input path VNEG external path VPOS regulator voltage reference input REF1. LCD: display 1792 dots bias with segments commons. display voltage from internal regulator external voltage source. Interrupts: W925E/C625 provides interrupt resources with priority level, including external interrupt sources, timer interrupts, interrupt, divider interrupt, serial port interrupt, comparator interrupt watchdog timer interrupt. Power Management: -9Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
W925E/C625 IDLE POWER DOWN modes operation. IDLE mode, clock core stopped however functions timers, divider, interrupts active continuously. POWER DOWN mode, both system clock stop oscillating chip operation completely stopped. POWER DOWN mode state lowest power consumption.
Memory Organization
W925E/C625 separates memory into separate sections, Program Memory Data Memory. Program Memory used store instruction op-codes look-up table data, while Data Memory used store data memory mapped devices. Program Memory: Program Memory W925E/C625 bytes. total bytes EEPROM/MASK used store op-codes whole used store look-up table data.
00000
bytes EEPROM MASK
0FFFF
Figure Program Memory Data Memory: W925E/C625 contains on-chip bytes MOVX Data Memory, which only accessed MOVX instructions from address 0000H 0FFFH from 2000H 20FEH. addition, W925E/C625 bytes on-chip scratchpad RAM. This accessed either direct addressing indirect addressing. There also Special Function Registers (SFRs), which only accessed direct addressing. Since scratchpad only bytes, used only when data contents small. event that larger data contents present, only selection on-chip MOVX RAM. on-chip MOVX only accessed MOVX instruction. However, on-chip fastest access times. memory shown Figure Figure shows scratchpad RAM/Register addressing.
-10-
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PRELIMINARY W925E/C625 8-bit Microcontroller
Indirect Addressing Direct Indirect Addressing
SFRs Direct Addressing only
20FEH 2000H
LCDRAM0FE LCDRAM000
0FFFH
byte SRAM chip
0000H
Figure Memory
-11-
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PRELIMINARY W925E/C625 8-bit Microcontroller
Indirect Direct
Bank Bank Bank Bank
Addressable 20H-
Figure Scratchpad RAM/Register Addressing
-12-
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PRELIMINARY W925E/C625 8-bit Microcontroller
Special Function Registers
W925E/C625 uses Special Function Registers (SFRs) control monitor peripherals their Modes. SFRs reside register locations 80-FFh accessed direct addressing only. Some SFRs addressable. This very useful cases where wishes modify particular without changing others. SFRs that addressable those whose addresses list SFRs follows. table condensed with eight locations row. Empty locations indicate that there registers these addresses. content reserved bits registers guaranteed. Table Special Function Register Location Table CIDGD CIDGA WDCON DIVC SCON1 SBUF1 REGVC STATUS FSKTC FSKTB DTMFG COMPR IRC1 IRC2 CASPT CASAT CIDR CIDFG CIDPCR FSKDR DTMFDR DTMFPT DTMFAT P4IO P1EF EXIF P1SR P0IO P1IO P2IO P3IO TCON TMOD CKCON1 CKCON2 DPL1 DPH1 PCON
Note: SFRs column with dark borders bit-addressable.
brief description SFRs follows. PORT Bit: P0.7 P0.6 P0.5 P0.4 P0.3 (initial=FFh, input mode) P0.2 P0.1 P0.0
Mnemonic:
Address:
selected input output mode P0IO register, initial reset, P0IO FFH, used input mode. When P0IO used CMOS open drain mode. STACK POINTER Bit: SP.7 SP.6 SP.5 SP.4 SP.3 (initial=07H) SP.2 SP.1 SP.0
Mnemonic: -13-
Address: Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Stack Pointer stores scratchpad address where stack begins. other words, always points stack. (initial=00H) DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
DATA POINTER Bit: DPL.7
Mnemonic: DPL: This byte standard 8052 16-bit data pointer. DATA POINTER HIGH Bit: DPH.7 DPH.6 DPH.5 DPH.4 DPH.3
Address:
(initial=00H) DPH.2 DPH.1 DPH.0
Mnemonic: DPH: This high byte standard 8052 16-bit data pointer. DATA POINTER LOW1 Bit:
Address:
(initial=00H)
DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
DPL1:
Mnemonic: DPL1 Address: This byte additional 16-bit data pointer that been added W925E/C625. user switch between DPL, DPL1, DPH1 simply setting register DPS.0 instructions that DPTR will access DPL1 DPH1 place DPH. they required they used conventional register locations user. (initial=00H)
DATA POINTER HIGH1 Bit:
DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 Address:
Mnemonic: DPH1 DPH1:
This high byte additional 16-bit data pointer that been added W925E/C625. user switch between DPL, DPL1, DPH1 simply setting register instructions that DPTR will access DPL1 DPH1 place DPH. they required they used conventional register locations user. (initial=00H) DPS.0
DATA POINTER SELECT Bit:
Mnemonic: Address: This used select either DPL,DPH pair DPL1,DPH1 pair active Data Pointer. When DPL1,DPH1 will selected, otherwise DPL,DPH will selected. DPS.1-7:These bits reserved, will read DPS.0: POWER CONTROL -14(initial=00H) Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Bit: IDLT
IDLT:
GF1-0:
IDL:
Mnemonic: PCON Address: This controls idle mode type. idle mode when idle mode released interrupt, IDLT=1 will jump corresponding interrupt; IDLT=0 will jump corresponding interrupt. These bits general purpose user flags. Setting this causes W925E/C625 into POWER DOWN mode. this mode clocks stopped program execution frozen. Power down mode released INT0~INT3 ring detection interrupt. Setting this causes W925E/C625 into IDLE mode. type idle mode selected IDLT. this mode clocks stopped, program execution frozen. clock path timers blocks interrupt blocks stopped, these blocks continue operating. (initial=00H)
TIMER CONTROL Bit:
Mnemonic: TCON Address: TF1: Timer overflow flag. This when Timer overflows. cleared automatically when program does timer interrupt service routine. Software also clear this bit. TR1: Timer control. This cleared software turn timer off. TF0: Timer overflow flag. This when Timer overflows. cleared automatically when program does timer interrupt service routine. Software also clear this bit. TR0: Timer control. This cleared software turn timer off. IE1: Interrupt edge detect: hardware when edge/level detected INT1. This cleared hardware when service routine vectored only interrupt edge triggered. Otherwise follows pin. Interrupt type control: Set/cleared software specify falling edge/ level triggered external inputs. Interrupt edge detect: hardware when edge/level detected INT0 This cleared hardware when service routine vectored only interrupt edge triggered. Otherwise follows pin. Interrupt type control. Set/cleared software specify falling edge/ level triggered external inputs. (initial=00H) GATE Address:
IT1: IE0:
IT0:
TIMER MODE CONTROL Bit: GATE
Mnemonic: TMOD Bit7~4 control timer bit3~0 control timer0 GATE: Gating control. When this set, Timer enabled only while INTx high control set. When cleared, Timer enabled whenever control set. -15Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Timer Counter Select. When cleared, timer incremented internal clocks. When set, timer counts high-to-low edges pin.
Note: either Mode Select bits: Mode Mode 13-bits timer Mode 16-bits timer Mode 8-bits with auto-reload from Reserved (initial=00H) TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
TIMER BYTE Bit:
Mnemonic: TL0.7-0: Timer byte register. TIMER BYTE Bit: TL1.7 TL1.6 TL1.5 TL1.4 TL1.3
Address:
(initial=00H) TL1.2 TL1.1 Address:
TL1.0
Mnemonic: TL1.7-0: Timer byte register. TIMER HIGH BYTE Bit: TH0.7 TH0.6 TH0.5 TH0.4 TH0.3
(initial=00H) TH0.2 TH0.1 TH0.0
Mnemonic: TH0.7-0: Timer high byte register. TIMER HIGH BYTE Bit: TH1.7 TH1.6 TH1.5 TH1.4 TH1.3
Address: (initial=00H) TH1.2 TH1.1 TH1.0
Mnemonic: TH1.7-0: Timer high byte register.
Address:
-16-
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PRELIMINARY W925E/C625 8-bit Microcontroller
CLOCK CONTROL1 Bit: T1S1 T1S0 T0S1 (initial=00H) T0S0 DIVS Address:
Mnemonic: CKCON1
WD1-0: Watchdog timer mode select bits: These bits determine time-out period watchdog timer. four time-out options reset time-out clocks more than interrupt time-out period. Interrupt time-out Reset time-out Fosc/212 Fosc/212 Fosc/2 Fosc/2 Fosc/2 Fosc/2 Fosc/2 Fosc/2 T0S0-1&T1S0-1: Timer0 Timer1 clock source mode select bits. These bits determine timer0 timer1 clock source. T0S1 T0S0 Prescale clock (T1S1) (T1S0) source Fosc/2 Fosc/2 Fosc/2 DIVS: Divider clock source control DIVS Fs/2 DIVS= Fs/2 System clock source control Fosc XIN1 Fosc XIN2 CLOCK CONTROL2 Bit: ENBUZ BUZSL (initial=00H)
Mnemonic: CKCON2 Address: ENBUZ: When ENBUZ=1 works buzzer output, otherwise floating state. BUZSL: Buzzer output selection. When BUZSL=0 output octave tone. When BUZZL=1, output tone. KT1-0: tone frequency sources from divider. When divider enable, determines tone frequency. tone frequency 512Hz 1024Hz 2048Hz
-17-
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PRELIMINARY W925E/C625 8-bit Microcontroller
PORT Bit: P1.7 P1.6 P1.5 P1.4 P1.3 (initial=FFh, input mode) P1.2 P1.1 P1.0 Address:
Mnemonic:
P1.7-0: selected input output mode P1IO register initial reset P1IO used input mode When P1IO used CMOS output mode When P1EF P1IO input mode used external interrupt source. functions listed below P1.0 INT2.0 P1.1 INT2.1 P1.2 INT2.2 P1.3 INT2.3 P1.4 INT3.0 P1.5 INT3.1 P1.6 INT3.2 P1.7 INT3.3 External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt (initial=00H) COMPF DIVF CIDF
EXTERNAL INTERRUPT FLAG Bit:
Mnemonic: EXIF Address: COMPF: Comparator flag. hardware when RESC from high. DIVF: Divider overflow flag. CIDF: interrupt flag. hardware when least flags set. IE3: External Interrupt flag. hardware when falling edge detected INT3. IE2: External Interrupt flag. hardware when falling edge detected INT2. PINS STATUS Bit: (initial=00H) P1.7SR P1.6SR P1.5SR P1.4SR P1.3SR P1.2SR P1.1SR P1.0SR
Mnemonic: P1SR Address: P1SR: when falling edge detected corresponding pin, clear software. PORT CONTROL Bit: P0.7IO P0.6IO P0.5IO P0.4IO P0.3IO (initial=FFH) P0.2IO P0.1IO P0.0IO
Mnemonic: P0IO P0IO: pins control. input mode output mode
Address:
-18-
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PRELIMINARY W925E/C625 8-bit Microcontroller
PORT CONTROL Bit: P1.7IO P1.6IO P1.5IO P1.4IO P1.3IO (initial=FFH) P1.2IO P1.1IO P1.0IO
Mnemonic: P1IO P1IO: pins control. input mode output mode PORT CONTROL Bit: P2.7IO P2.6IO P2.5IO P2.4IO P2.3IO
Address:
(initial=FFH) P2.2IO P2.1IO P2.0IO
Mnemonic: P2IO P2IO: pins control. input mode output mode PORT CONTROL Bit: P3.7IO P3.6IO P3.5IO P3.4IO P3.3IO
Address:
(initial=FFH) P3.2IO P3.1IO P3.0IO
Mnemonic: P3IO P3IO: pins control. input mode output mode PINS INTERRUPT EABLE Bit:
Address:
(initial=00H)
P1.7EF P1.6EF P1.5EF P1.4EF P1.3EF P1.2EF P1.1EF P1.0EF Address:
Mnemonic: P1EF P1EF: pins interrupt function enabled/disabled register disable enable PULL-HIGH CONTROL Bit: P1.7H P1.6H P1.5H P1.4H P1.3H
(initial=00H) P1.2H P1.1H P1.0H
P1H:
Mnemonic: Port1 pins pull-high resistor enable/disable enable disable
Address:
PULL-HIGH CONTROL -19-
(initial=00H) Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Bit: P2.7H P2.6H P2.5H P2.4H P2.3H P2.2H P2.1H P2.0H
P2H:
Mnemonic: Port1 pins pull-high resistor enable/disable enable disable
Address:
PULL-HIGH CONTROL Bit: P3.7H P3.6H P3.5H P3.4H P3.3H
(initial=00H) P3.2H P3.1H P3.0H
P3H:
Mnemonic: Port1 pins pull-high resistor enable/disable enable disable
Address:
PORT Bit: P2.7 P2.6 P2.5 P2.4 P2.3
(initial=FFh, input mode) P2.2 P2.1 P2.0
Mnemonic:
Address:
P2.7-0: Port port with internal pull-high resistor. selected input output mode P2IO register. initial reset, used input mode. When P2IO used CMOS output mode. HIGH BYTE REGISTER Bit: HB.7 HB.6 HB.5 HB.4 HB.3 (initial=00H) HB.2 HB.1 HB.0
Mnemonic:
Address:
This register contains high byte address during execution MOVX @Ri, instructions. PULL-HIGH CONTROL Bit: P4.7H P4.6H P4.5H P4.4H P4.3H (initial=00H) P4.2H P4.1H P4.0H
P4H:
Mnemonic: Port4 pins pull-high resistor enable/disable enable disable
Address:
-20-
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
PORT P4.7 Mnemonic: Bit: P4.6 P4.5 P4.4 P4.3 (initial=FFh, input mode) P4.2 P4.1 Address: P4.0
P4.7-0: Port port with internal pull-high resistor. selected input output mode P4IO register, initial reset, P4IO 0FFh, used input mode. When P4IO 00h, used CMOS output mode. Special function described below. P4.4 VPOS Positive input comparator P4.2 VNEG Negative input comparator P4.1 SDATA Serial port data P4.0 SCLK Serial port clock
INTERRUPT ENABLE Bit:
(initial=00H)
ES1: ET1: EX1: ET0: EX0:
Mnemonic: Global enable. Enable/disable interrupts. Enable Serial port interrupt Enable Timer interrupt Enable external interrupt Enable Timer interrupt Enable external interrupt
Address:
PORT CONTROL Bit: P4.7IO P4.6IO P4.5IO P4.4IO P4.3IO
(initial=FFH) P4.2IO P4.1IO P4.0IO
Mnemonic: P4IO P4IO: pins control. input mode output mode
Address:
-21-
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PRELIMINARY W925E/C625 8-bit Microcontroller
PORT Bit: P3.7 P3.6 P3.5 P3.4 P3.3 (initial=FFh, input mode) P3.2 P3.1 P3.0
Mnemonic: Address: P3.7-0: selected input output mode P3IO register, initial reset, P3IO 0FFH, used input mode. When P3IO 00h, used CMOS output mode. Special function described below. P3.5 Timer/Counter external count input P3.4 Timer/Counter external count input P3.3 External interrupt INT1 P3.2 External interrupt INT0 REGISTER Bit: (initial=00H,read only)
FCLK FDATA DTMFD ALGO Mnemonic: CIDR Address: This indicates signal immediately. Register data cleared hardware only. FCLK: serial clock with baud rate 1200Hz. FDATA: serial data. FCD: when carrier detected. Cleared when carrier disappeared. DTMFD: when DTMF decoded data ready. Cleared when DTMF signal ends. FDR: when bits data ready. Cleared before next start comes ALGO: Dual tone Alert signal Guard time detect signal. when guard time qualified dual tone alert signal been detected. Cleared when guard time qualified dual tone alert signal absent. RNG: Ring detection bit. High indicate detection line reversal and/or ringing. FLAG GENERATOR Bit: (initial=00H) RNGF
DTMFDF FDRF ALGOF Mnemonic: CIDFG Address: FSF: when Latch clock high. Cleared software DTMFDF: when DTMFD high. Cleared software FDRF: when high. Cleared software. ALGOF: when ALGO high. Cleared software. RNGF: when high. Cleared software. POWER CONTROL REGISTER Bit: (initial=00H)
CIDE FSKE CASE Mnemonic: CIDPCR Address: CIDE: Global enable function. disable functions parts. -22-
DTMFE
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
FSKE: Enable demodulation circuit. CASE: Enable Dual Tone Alert Signal detection circuit. DTMFE: Enable DTMF demodulation circuit. DATA REGISTER Mnemonic: FSKDR bits demodulated data. Bit: (initial=XXH) Address:
FD7-0:
DTMF DATA REGISTER CASH CASL DTMFH DTMFL Mnemonic: DTMFDR CASH: when Dual Tone Alert Signal high tone detected. CASL: when Dual Tone Alert Signal tone detected. DTMFH: when DTMF high tone detected. DTMFL: when DTMF tone detected. DD3-0: bits DTMF demodulated data. DTMF PRESENT TIME REGISTER Bit: Bit:
(initial=XXH) Address:
(initial=19H)
DPT6 DPT5 DPT4 DPT3 DPT2 DPT1 DPT0 DPT7 Mnemonic: DTMFPT Address: clock period guard-time timer 0.8582mS. default DTMF present time 21.45mS. DPT7-0: pre-set data register counting DTMF present time. When DTMF detected(Est high), guard timer starts up-count from 00H. guard timer equal value DTMFPT, exist DTMF accepted. changes state stop reset counter. DTMF ABSENT TIME REGISTER Bit: (initial=19H)
DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 Mnemonic: DTMFAT Address: clock period guard-time timer 0.8582mS. default DTMF absent time 21.45mS. DAT7-0:The pre-set data register counting DTMF absent time. When DTMF absent(Est high low), guard timer starts up-count from 00H. guard timer equal value DTMFAT, finish DTMF recognized. changes state stop reset counter.
INTERRUPT PRIORITY -23-
(initial=00H) Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Bit:
IP.7: PS1: PT1: PX1: PT0: PX0:
Mnemonic: Address: This un-implemented will read high. This defines Serial port interrupt priority. sets higher priority level This defines Timer interrupt priority. sets higher priority level. This defines External interrupt priority. sets higher priority level. This defines Timer interrupt priority. sets higher priority level. This defines External interrupt priority. sets higher priority level. (initial=00H) Address:
DTMF GENERATOR REGISTER DTGE Mnemonic: DTMFG Bit:
Selected tone 1209Hz 1336Hz 1477Hz 1633Hz 697Hz 770Hz 852Hz 941Hz Enable group frequency output. Enable high group frequency output. DTGE: Enable dual tone output DTMF pin. COMPARATOR REGISTER Bit: RESC (initial=00H) COMPEN
RESC:
Mnemonic: COMPR Address: Result comparator. when positive analog input voltage is(VPOS 1.0v internal regular output) higher than negative analog input voltage(VNEG) RESC read only bit. REF=0 reference input from analog input voltage(VPOS/P4.4) pin. REF=1 reference input from internal regulator output. COMPEN=0 Disable comparator COMPEN=1 Enable comparator
REF: COMPEN:
IDLE RELEASED CONDITION REGISTER -24-
(initial=00H) Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Bit: IRCS1 IRCT1 IRCX1 IRCT0 IRCX0
Mnemonic: IRC1 Address: IRC1 IRC2 will hardware record idle released condition when idle mode released. IRC1 IRC2 hardware software. IRCS1: Idle mode released Serial port interrupt flag. IRCT1: Idle mode released Timer interrupt flag. IRCX1: Idle mode released external interrupt flag. IRCT0: Idle mode released Timer interrupt flag. IRCX0: Idle mode released external interrupt flag. IDLE RELEASED CONDITION REGISTER Bit: IRCWDI IRCCOMP IRCDIV IRCCID (initial=00H) IRCX3 IRCX2
Mnemonic: IRC2 Address: IRC1 IRC2 will hardware record idle released condition when idle mode released. IRC1 IRC2 hardware software. IRCWDI: Idle mode released Watchdog timer interrupt flag. IRCCOMP: Idle mode released comparator interrupt flag. IRCDIV: Idle mode released Divider interrupt flag. IRCCID: Idle mode released interrupt flag. IRCX3: Idle mode released External Interrupt flag. IRCX2: Idle mode released External Interrupt flag. TONE PRESENT TIME REGISTER Bit: (initial=0FH)
CASPT7 CASPT6 CASPT5 CASPT4 CASPT3 CASPT2 CASPT1 CASPT0 Mnemonic: CASPT Address: clock period guard-time timer 0.8582mS. default alert tone present time 12.87mS. CASPT7-0: pre-set data register counting tone present time. When tone detected (ALGR high), guard timer starts up-count from 00H. guard timer equal value CASPT, exist tone accepted. ALGR changes state stop reset counter. TONE ABSENT TIME REGISTER Bit: (initial=0FH)
CASAT7 CASAT6 CASAT5 CASAT4 CASAT3 CASAT2 CASAT1 CASAT0 Mnemonic: CASAT Address: clock period guard-time timer 0.8582mS. default alert tone absent time 12.87mS. CASAT7-0: pre-set data register counting tone absent time. When tone absent (ALGR high low), guard timer starts up-count from 00H. guard timer equal value CASAT, finish tone recognized. ALGR changes high state stop reset counter. SERIAL PORT CONTROL -25(initial=00H) Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Bit: LCDON REGON REN1 SEDG CLKIO
Mnemonic: SCON1 Address: SF1: Serial port interrupt flag. When 8-bits data transceived completely, hardware. cleared when serial interrupt routine executed cleared software. LCDON: waveform enable control. Disable display, Enable display. REGON: Regulator on/off control. disable regulator, regulator. REN1: REN1 from start serial port1 receive 8-bit serial data. SFQ: SFQ=0 Serial clock output frequency equal fOSC SFQ=1 Serial clock output frequency equal fOSC /256 SEDG: SEDG=0 Serial data latched falling edge clock, SCLK=Low initially. SEDG=1 Serial data latched rising edge clock, SCLK=High initially. CLKIO: CLKIO=0 P4.0(SCLK) work output mode CLKIO=1 P4.0(SCLK) work input mode SIO: SIO=0 P4.0 P4.1 work normal SIO=1 P4.0 P4.1 work Serial port1 function (initial=00H) Read Only
SERIAL DATA BUFFER Bit:
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0 Mnemonic: SBUF1 Address:
SBUF1.7-0: Serial data serial port read from written this location. actually consists separate internal 8-bit registers. receive register, other transmit buffer. read access gets data from receive data buffer, while write access transmit data buffer. REGULATOR VOLTAGE CONTROL REGISTER Bit: (initial=00H) REGVC.3 REGVC.2 REGVC.1 REGVC.0 Address:
Mnemonic: REGVC REGVC.3-0: bits tune regulator output voltage. POWER MANAGEMENT REGISTER Bit: XT/RG RGMD RGSL X2OFF X1OFF
(initial=XXX00XX1B)
Mnemonic: Address: XT/RG :Crystal/RC Oscillator Select. Setting this selects crystal external clock system clock source. Clearing this selects on-chip oscillator clock source. X1UP (STATUS.4) must X1OFF (PMR.3) must cleared before this set. Attempts this without obeying these conditions will ignored. This after power-on reset unchanged other forms reset. RGMD: Mode Status. This indicates current clock source micro-controller. When cleared, operating from external crystal oscillator. When set, -26Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
operating from on-chip oscillator. This cleared after power-on reset unchanged other forms reset. RGSL: Oscillator Select. This selects clock source following resume from Power Down Mode. Setting this allows device operating from oscillator when resume from Power Down Mode. When this cleared, device will hold operation until crystal oscillator warmed-up following resume from Power Down Mode. This cleared after power-on reset unchanged other forms reset. X2OFF: disable sub-oscillator (32KHz oscillator) X1OFF:Crystal Oscillator Disable. Setting this disables external crystal oscillator. This only while micro-controller operating from oscillator. Clearing this restarts crystal oscillator, X1UP (STATUS.4) will after crystal oscillator warmed-up completed. Note: bit0 this must STATUS REGISTER Bit: X2UP X1UP
(initial=00H)
Mnemonic: STATUS Address: X2UP:Sub-crystal oscillator warm-up status. When set, this indicates crystal oscillator completed warm-up delay. When X2OFF set, hardware will clear this bit. There options which selected option code warm-up delay, 1024 clocks warm-up delay, other 65536 clocks warm-up delay. HIP: High Priority Interrupt Status. When set, indicates that software servicing high priority interrupt. This will cleared when program executes corresponding RETI instruction. LIP: Priority Interrupt Status. When set, indicates that software servicing priority interrupt. This will cleared when program executes corresponding RETI instruction. X1UP:Crystal Oscillator Warm-up Status. when set, this indicates crystal oscillator completed 65536 clocks warm-up delay. Each time crystal oscillator restarted exit from power down mode X1OFF set, hardware will clear this bit. This after power-on reset. When this cleared, prevents software from setting XT/RG enable operation from crystal oscillator. There options which selected option code warm-up delay, 4096 clocks warm-up delay, other 65536 clocks warm-up delay. TRANSIMT CONTROL REGISTER Bit: (initial=00H)
Mnemonic: FSKTC FTE: transmit Enable; Enable:1, Disable=0 FTM: signal Standard; Bellcore:1, V.23=0 FDS: data sending status LO0, LO1: transmit level option output level -27-
Address:
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
150mV 120mV 95mV 75mV TRANSMIT DATA BUFFER Bit: (initial=00H)
FSKTB.7 FSKTB.6 FSKTB.5 FSKTB.4 FSKTB.3 FSKTB.2 FSKTB.1 FSKTB.0 Address: (initial=01H) DIVA
Mnemonic: FSKTB FSKTB.0:Only This will latched send signal DIVIDER CONTROL Bit:
Mnemonic: DIVC Address: DIVA: Divider available control bit. This cleared software enable/disable divider. DIVA=1 enable divider. DIVA=0 disable divider. DIVA reset after reset. PROGRAM STATUS WORD Bit: (initial=00H)
Mnemonic:
Address:
Carry flag. arithmetic operation which results carry being generated from ALU. also used accumulator operations. Auxiliary carry. when previous operation resulted carry from high order nibble. User flag General purpose flag that cleared user. RS.1-0: Register bank select bits: Register bank Address 00-07h 08-0Fh 10-17h 18-1Fh Overflow flag. when carry generated from seventh from result previous operation, vice-versa. User Flag General purpose flag that cleared user software. Parity flag. Set/cleared hardware indicate odd/even number accumulator.
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PRELIMINARY W925E/C625 8-bit Microcontroller
WATCHDOG CONTROL Bit: WDIF (initial: note) WTRF
Mnemonic: WDCON Address: POR: Power-on reset flag. Hardware will this flag when system powered this flag cleared only software. WFS: Watchdog Timer Frequency Select. select clock input. Clear select FOSC clock input. WDIF: Watchdog Timer Interrupt flag. This whenever time-out occurs watchdog timer. Watchdog interrupt enabled (EIE.5), then interrupt will occur global interrupt enable other interrupt requirements met). Software reset clear this bit. WTRF: Watchdog Timer Reset Flag. Hardware will this when watchdog timer causes reset. Software read must clear manually. power-fail reset will also clear bit. This helps software determining cause reset. watchdog timer will have effect this bit. EWT: Enable Watchdog timer Reset. Setting this will enable Watchdog timer Reset function. RWT: Reset Watchdog Timer. This helps putting watchdog timer into known state. also helps resetting watchdog timer before time-out occurs. Failing before time-out will cause interrupt, EWDI (EIE.4) set, clocks after that watchdog timer reset will generated set. This self-clearing hardware. Note: WDCON 0x000xx0b external reset. WTRF Watchdog timer reset, power on/down resets. WTRF altered external reset. power-on reset. Power-on reset unaffected other resets. ACCUMULATOR Bit: ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 (initial=00H) ACC.2 ACC.1 ACC.0
Mnemonic: ACC.7-0:The register. EXTENDED INTERRUPT ENABLE Bit: EWDI ECOMP EDIV
Address:
(initial=00H) ECID
Mnemonic: EIE.7-6:Reserved bits. EWDI: Enable Watchdog timer interrupt. ECOMP: Enable comparator interrupt. EDIV: Enable Divider interrupt. ECID: Enable interrupt. EX3: Enable External Interrupt EX2: Enable External Interrupt -29-
Address:
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
REGISTER Bit: (initial=00H)
Mnemonic: B.7-0:The register serves second accumulator. EXTENDED INTERRUPT PRIORITY Bit: PWDI PCOMP PDIV
Address:
(initial=00H) PCID
Mnemonic: Address: PWDI: Watchdog timer interrupt priority. priority, High priority. PCOMP: Comparator interrupt priority. priority, High priority. PDIV: Divider Interrupt Priority. priority, High priority. PCID: Interrupt Priority. priority, High priority. PX3: External Interrupt Priority. priority, High priority. PX2: External Interrupt Priority. priority, High priority. GAIN CONTROL DATA Bit: BIT7 BIT6 BIT5 BIT4 BIT3 (initial=00H) BIT2 BIT1 BIT0
Mnemonic: CIDGD Address: CIDGD.7-0: data value programmable input filter gain hysteresis. GAIN CONTROL ADDRESS Bit: BIT3 (initial=00H) BIT2 BIT1 BIT0
Mnemonic: CIDGA CIDGA.3:
Address:
CIDGD latch control signal. Rising high pulse latch CIDGD into gain control register. CIDGA.2-0: address indicate input gain control registers.
Instruction
W925E/C625 executes instructions standard 8032 family. However, timing these instructions different. W925E/C625, each machine cycle consists clock periods, while standard 8032 consists clock periods. Also, W925E/C625 there only fetch machine cycle i.e. clocks fetch, while standard 8032 there fetches machine cycle, which works clocks fetch. Table Instructions that affect Flag settings
Instruction INC,DEC ADDC SUBB Carry Overflow Auxiliary Carry Instruction SETB Carry Overflow Auxiliary Carry
-30-
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
CJNE
indicates that modification result instruction. indicates that flag effected instruction.Table Instruction Timing W925E/C625
Instruction
direct #data ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC direct ADDC #data ACALL addr11
Op-Code
71,91,B1, 11,31,51, D1,F1 01,21,41, 61,81,A1, C1,E1
Bytes
Machine Cycles
Instruction
direct #data direct, direct, #data /bit CJNE direct, CJNE #data, CJNE @R0, #data, CJNE @R1, #data, CJNE #data, CJNE #data, CJNE #data, CJNE #data, CJNE #data, CJNE #data,
Op-Code
Bytes
Machine Cycles
AJMP ADDR11
CJNE #data,
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Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Table Instruction Timing W925E/C625, continued Instruction
CJNE #data, direct DPTR DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ direct, direct DPTR @A+DPTR
Op-Code
Bytes
Machine Cycles
Instruction
bit, bit, bit, LCALL addr16 LJMP addr16 direct #data direct direct direct direct direct direct direct direct #data #data #data #data #data #data #data #data @R0, @R1, @R0, direct
Op-Code
Bytes
Machine Cycles
-32-
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Table Instruction Timing W925E/C625, continued Instruction
@R1, direct @R0, #data @R1, #data direct, direct, direct, direct, direct, direct, direct, direct, direct, direct, direct, direct, direct direct, #data DPTR, #data MOVC @A+DPTR MOVC @A+PC MOVX MOVX MOVX @DPTR MOVX @R0, MOVX @R1, MOVX @DPTR, bit, direct #data direct, direct, #data /bit PUSH direct direct RETI
Op-Code
Bytes
Machine Cycles
Instruction
SETB SETB SWAP SJMP SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB direct SUBB #data XCHD XCHD direct direct #data direct, direct, #data
Op-Code
Bytes
Machine Cycles
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Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Power Management
W925E/C625 operation mode, normal mode, idle mode power down mode manage power consumption. Normal Mode Normal mode used normal operation status. functions worked normal mode. Idle Mode user device into idle mode writing PCON.0. instruction that sets idle last instruction that will executed before device goes into Idle Mode. Idle mode, clock halted, Interrupt, Timer, Watchdog timer, Divider, Comparator blocks. This forces state frozen; Program counter, Stack Pointer, Program Status Word, Accumulator other registers hold their contents. port pins hold logical states they time Idle activated. Idle mode terminated ways. Since interrupt controller still active, activation enabled interrupt wake processor. This will automatically terminate Idle mode clear Idle bit. IDLT(PCON.4) cleared Interrupt Service Routine(ISR) will executed, else idle mode released directly without execution ISR. After ISR, execution program will continue from instruction, which device into Idle mode. Idle mode also exited activating reset. device into reset either applying external RESET power on/fail reset condition Watchdog timer reset. external reset held least machine cycles i.e. clock periods recognized valid reset. reset condition program counter reset 0000h SFRs reset condition. Since clock still running period external reset therefore instruction executed immediately. Idle mode, Watchdog timer continues run, enabled, time-out will cause watchdog timer interrupt which will wake device. software must reset Watchdog timer order preempt reset which will occur after clock periods time-out. Power Down Mode device into Power Down mode writing PCON.1. instruction that does this will last instruction executed before device goes into Power Down mode. Power Down mode, clocks stopped device comes halt. activity completely stopped power consumption reduced lowest possible value. port pins output values held their respective SFRs. W925E/C625 will exit Power Down mode reset external interrupts ring detected. external reset used exit Power down state. RESET terminates Power Down mode, restarts clock. on-chip hardware will provide delay 65536 clock, which used provide time oscillator restart stabilize. Once this delay complete, internal reset activated program execution will restart from 0000h. Power down mode, clock stopped, Watchdog timer cannot used provide reset exit Power down mode. W925E/C625 woken from Power Down mode forcing external interrupt activated ring detected, provided corresponding interrupt enabled, while global enable(EA) set. While power down released, device will experience warm-up delay 65536 clock cycles ensure stabilization oscillation. Then device executes interrupt service routine corresponding external interrupt interrupt. After interrupt service routine completed, program returns instruction after one, which device into Power Down mode continues from there. When RGSL(PMR.5) will internal oscillator instead crystal exit Power Down mode. -34Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
micro-controller will automatically switch from oscillator crystal after warm-up delay 65536 crystal clocks. oscillator runs approximately MHz. Using oscillator exit from Power Down mode saves time waiting crystal start-up. useful power system which usually awakened from short operation then returns Power Down mode.
Reset
user several hardware related options placing W925E/C625 into reset condition. general, most register bits their reset value irrespective reset condition, there flags that initial states dependant source reset. User recognize cause reset reading flags. There three ways putting device into reset state. They External reset, Power reset Watchdog reset. External Reset device continuously samples RESET state every machine cycle. Therefore, RESET must held least machine cycles ensure detection valid RESET low. reset circuitry then synchronously applies internal reset signal. Thus, reset synchronous operation requires clock running cause external reset. Once device reset condition, will remain long RESET Even after RESET deactivated, device will continue reset state machine cycles, then begin program execution from 0000h. There flag associated with external reset condition. However, since some flags indicate cause other reset, external reset considered default reset those flags cleared. Watchdog Timer Reset Watchdog timer free running timer with programmable time-out intervals. user reset watchdog timer time avoid producing flag WDIF. Watchdog reset enabled flag WDIF high, watchdog timer reset performed after additional clocks come. This places device into reset condition. reset condition maintained hardware machine cycles. Once reset removed device will begin execution from 0000h.
Interrupt
W925E/C625 priority levels interrupt structure with interrupt sources. Each interrupt sources individual priority bit, flag, interrupt vector enable bit. addition, interrupts globally enabled disabled. Interrupt Sources External Interrupts INT0 INT1 either edge triggered level triggered, depending bits IT1. bits TCON register flags which checked generate interrupt. edge triggered mode INT0 INT1 inputs sampled every machine cycle. sample high cycle next, then high transition detected interrupts request flag TCON set. flag requests interrupt. Since external interrupts sampled every machine cycle, they have held high least complete machine cycle. flag automatically cleared when service routine called. level triggered mode selected, then requesting source hold until interrupt serviced. flag will cleared hardware entering service routine. interrupt continues held even after service routine completed, then processor acknowledge another interrupt request from same source. Note that external interrupts INT2 INT3 edge triggered only. -35Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
TF0, flags generate Timer Interrupts. These flags overflow Timer Timer flags automatically cleared hardware when timer interrupt serviced. Watchdog timer used system monitor simple timer. either case, when time-out count reached, Watchdog timer interrupt flag WDIF (WDCON.3) set. enable EIE.5 enables interrupt, then interrupt will occur. Serial block generate interrupts reception transmission. There interrupt sources from Serial block, which obtained SCON1. cleared automatically when serial port interrupt serviced. divider interrupt generated DIVF that when divider overflows. DIVF hardware cleared when divider interrupt serviced. divider interrupt enable/disable EDIV high/low. comparator interrupt produced COMPF, which when RESC changed from high. RESC, which real-time result comparator, when voltage reference input higher than voltage analog input. interrupt generated CIDF. CIDF logic output flags which hardware cleared software. structure flags shown Figure 6-4. Each individual interrupts enabled disabled setting clearing corresponding bits SFR. which located IE.7, global control enable/disable interrupt. When zero interrupts disable when high each interrupt enable individually corresponding bit.
RNGF FDRF ALGOF DTMFDF CIDF
System clock Clear software
Figure Structure Flags Priority Level Structure There priority levels interrupts, high low. interrupt sources individually either high levels. Naturally, higher priority interrupt cannot interrupted lower priority interrupt. However there exists pre-defined hierarchy amongst interrupts themselves. This hierarchy comes into play when interrupt controller resolve simultaneous requests having same priority level. This hierarchy defined shown below; interrupts numbered starting from highest priority lowest. Table Interrupt table. Flag Location Location TCON.1 IE.0 TCON.5 TCON.3 TCON.7 IE.1 IE.2 IE.3
Interrupt External interrupt Timer0 overflow External interrupt Timer1 overflow
Flag Name
Priority
(highest)
Flag Cleared hardware software hardware software hardware software hardware software
Interrupt Vector
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PRELIMINARY W925E/C625 8-bit Microcontroller
Serial port External interrupt External interrupt Divider overflow Compare difference Watchdog timer CIDF DIVF COMPF WDIF SCON1.7 EXIF.0 EXIF.1 EXIF.2 EXIF.3 EXIF.4 WDCON.3 ECID EDIV ECOMP EWDI IE.6 EIE.0 EIE.1 EIE.2 EIE.3 EIE.4 EIE.5
(lowest)
hardware software hardware software hardware software software hardware software hardware software software
flags marked italic font bit-addressable. interrupt flags sampled every machine cycle. same machine cycle, sampled interrupts polled their priority resolved. certain conditions then hardware will execute internally generated LCALL instruction which will vector process appropriate interrupt vector address. conditions generating LCALL interrupt equal higher priority currently being serviced. current polling cycle last machine cycle instruction currently being executed. current instruction does involve write registers RETI. these conditions met, then LCALL will generated. polling cycle repeated every machine cycle, with interrupts being sampled same machine cycle. interrupt flag active cycle responded active when above conditions met, denied interrupt will serviced. This means that active interrupts remembered. Note that every polling cycle new. Execution continues from vectored address until RETI instruction executed. execution RETI instruction, processor pops content Stack processor notified anything content stack changed. Note that instruction would perform exactly same process RETI instruction, would inform Interrupt Controller that interrupt service routine completed, would leave controller still thinking that service routine underway.
Programmable Timers/Counters
W925E/C625 16-bit timer/counters. There 8-bit registers perform 16-bit counting register every timer/counter. timer/counter upper bits register lower bits register. Similarly timer/counter have 8-bit registers, TL1. Each timer/counter kind clock sources which Fosc/4, Fosc/64, Fosc/1024 There operating modes each timer/counter operating modes timer/ counter0 identical timer/counter1. overflow signal each timer/counter sampled phase every system machine cycle, therefore when system clock timer/counter clock both from sub-oscillator, overflow frequency higher than Fs/4 overflow flag sampled correctly. Only overflow flag sampled machine cycle others will missed. MODE
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PRELIMINARY W925E/C625 8-bit Microcontroller
Mode timer/counters 13-bit timer/counters. bits consist bits lower bits TLx. upper bits ignored. negative edge clock causes content register increase one. When fifth moves from then count register incremented. When count moves from 00h, then overflow flag set. counted input enabled only either GATE=0 INTx When then will count clock cycles, then will count transitions (P3.4) timer (P3.5) timer When 13-bit count reaches 1FFFh, next count will cause rollover 0000h. timer overflow flag relevant timer enabled interrupts will occur. Note that when they used timer, bits CKCON1 select time-base. MODE1 Mode similar Mode except that counting register forms 16-bit counter, rather than counter.
TM0=CKCON1.2, CKCON1.3 (TM1=CKCON1.4, CKCON1.5)
Fosc/4 Fosc/64 Fosc/1024 P3.4 P3.5) TCON.4 (TR1 TCON.6) GATE TMOD.3 (GATE TMOD.7) INT0 P3.2 (INT1 P3.3)
TMOD.2 (C/T TMOD.6) (TL1)
M1,M0 TMOD.1,TMOD.0 (M1,M0 TMOD.5,TMOD.4) (TH1)
(TF1)
Interrupt
Functions timer1 shown brackets
Figure Mode Mode Timer/Counter MODE Mode Auto Reload Mode. mode acts 8-bit count register, while holds reload value. When register overflows from 00h, reloaded with content THx, counting process continues from reloaded TLx. reload operation leaves content register unchanged. Counting controlled proper setting GATE INTx pins. BUZZER mode timer output arbitrary frequency programming bit6 bit7 CKCON2. configured tone (KT) output setting BUZSL high. When disable buzzer output clearing ENBUZ low, output floating status. -38Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
case where timer clock input desired frequency output (255 preset value (HZ).
CKCON2.5, CKCON2.4 512Hz 1024Hz 2048Hz
TM0=CKCON1.2, CKCON1.3 (TM1=CKCON1.4, CKCON1.5) Fosc/4 Fosc/64 Fosc/1024
CKCON2.6 CKCON2.7 =BUZSL =ENBUZ
From
floating
TMOD.2 (C/T TMOD.6)
(TL1)
P3.4 P3.5) TCON.4 (TR1 TCON.6) GATE TMOD.3 (GATE TMOD.7) INT0 P3.2 (INT1 P3.3)
(TF1)
Interrupt
(TH1)
Functions timer1 shown brackets
Figure Mode Timer/Counter When equals 32768 depending preset value TM0, will output single tone signal tone frequency range from 16384 relation between tone frequency preset value shown table below.
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PRELIMINARY W925E/C625 8-bit Microcontroller
Table relation between tone frequency preset value
octave
Tone frequency preset value frequency 131.07 138.84 146.28 156.03 165.49 174.30 184.09 195.04 207.39 221.40 234.05
octave
Tone frequency 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88 preset value frequency 260.06 277.69 292.57 309.13 327.68 348.58 372.35 390.08 420.10 442.81 468.11 496.4
octave
Tone frequency 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.23 987.77 preset value frequency 528.51 564.96 585.14 630.15 655.36 712.34 744.72 780.19 819.20 862.84 910.22 963.76
130.81 138.59 146.83 155.56 164.81 174.61 185.00 196.00 207.65 220.00 233.0
246.94 248.24 Note: Central tone (440 Hz).
WATCHDOG TIMER Watchdog timer free-running timer that programmed user serve system monitor, time-base generator event timer. basically dividers that divides system clock. divider output selectable determines time-out interval. condition timer-out expiring, interrupt reset executed corresponding enable control bits set. interrupt will occur individual interrupt enable global enable set. interrupt reset functions independent each other used separately together depending users software.
Fsub Fosc
WD1,WD0
WDIF
Interrupt
WFS(WDCON.4)
EWDI(EIE.5)
Time-out
WTRF
selector
Reset Watchdog (WDCON.0)
clock delay
Reset
Enable Watchdog timer reset EWT(WDCON.1)
Figure Watchdog Timer Watchdog timer should first restarted using RWT. This ensures that timer starts from known state. used restart watchdog timer. This self clearing, -40Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
i.e. after writing this software will automatically clear watchdog timer will count clock cycles. time-out interval selected bits (CKCON.7 CKCON.6). When selected time-out occurs, Watchdog interrupt flag WDIF (WDCON.3) set. After time-out occurred, watchdog timer waits additional clock cycles. software must issue reset watchdog before clocks have elapsed. Watchdog Reset (WDCON.1) enabled, then clocks after time-out, there RWT, system reset Watchdog timer will occur. This will last machine cycles, Watchdog timer reset flag WTRF (WDCON.2) will set. This indicates software that watchdog cause reset. When used simple timer, reset interrupt functions disabled. timer will WDIF flag each time timer completes selected time interval. WDIF flag polled detect time-out allows software restart timer. Watchdog timer also used very long timer. interrupt feature enabled this case. Every time time-out occurs interrupt will occur global interrupt enable set. Table Time-out values Watchdog timer Watchdog Fosc= Reset Number Fosc= 32768 Clocks Interval Clocks 3.579545 4096 1.14 0.125 4608
32786 262144
9.15 73.23
33280 262656
2097152 585.87 2097664 Watchdog timer will disabled power-on/fail reset. Watchdog timer reset does disable watchdog timer, will restart general, software should restart timer into known state. control bits that support Watchdog timer discussed below. WATCHDOG CONTROL WDIF: WDCON.3 Watchdog Timer Interrupt flag. This whenever time-out occurs watchdog timer. Watchdog interrupt enabled (EIE.5), then interrupt will occur global interrupt enable other interrupt requirements met). Software reset clear this bit. WTRF: WDCON.2 Watchdog Timer Reset flag. This whenever watchdog reset occurs. This useful determined cause reset. Software must read clear manually. Power-fail reset will clear this bit. then this will affected watchdog timer. EWT: WDCON.1 Enable Watchdog timer Reset. This when will enable Watchdog timer reset function. Setting this will disable Watchdog timer reset function, will leave timer running RWT: WDCON.0 Reset Watchdog Timer. This used clear Watchdog timer restart This self-clearing, after software writes hardware will automatically clear Watchdog timer reset enabled, then user within clocks time-out. this done then Watchdog timer reset will occur.
CLOCK CONTROL
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PRELIMINARY W925E/C625 8-bit Microcontroller
WD1,WD0: CKCON.7, CKCON.6 Watchdog Timer Mode select bits. These bits select time-out interval watchdog timer. reset time longer clocks time than interrupt time-out value. default Watchdog time-out clocks, which shortest time-out period. EWT, WDIF bits protected Timed Access procedure. This prevents software from accidentally enabling disabling watchdog timer. More importantly, makes highly improbable that errant code enable disable watchdog timer.
Serial Port
P4.0 P4.1 used 8-bit serial input/output port1. P4.0 serial port clock P4.1 serial port data pin. serial port controlled SCON1 register which described below. SF1: Serial port interrupt flag. When 8-bits data transceived completely, hardware. cleared when serial interrupt1 routine executed cleared software. REN1: REN1 from start serial port1 receive 8-bit serial data. SFQ: SFQ=0 Serial clock output frequency equal fOSC SFQ=1 Serial clock output frequency equal fOSC SEDG: CLKIO: SEDG=0 Serial data latched falling edge clock, SCLK=Low initially. SEDG=1 Serial data latched rising edge clock, SCLK=High initially. CLKIO=0 P4.0(SCLK) work output mode CLKIO=1 P4.0(SCLK) work input mode SIO=0 P4.0 P4.1 work normal SIO=1 P4.0 P4.1 work Serial port1 function
SIO:
instruction causes write SBUF1 will start transmission serial port REN1 from serial port begins receive byte into SBUF1 frequency serial clock. REN1 could cleared software after receive function begins. transmitted/ received first. mode serial clock controlled CLKIO. User take care initial state serial port pins. REN1
SEDG=1, rising latch
P4.0 P4.0
SEDG=0, falling latch
P4.1
Data Input
NOTE: serial clock frequency fosc/2
Figure Timing Serial Port Input Function -42Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Ins. P4.0
serial instruction
SEDG=1, falling changed
SEDG=0, rising changed
P4.0
P4.1
Data output
NOTE: serial clock frequency fosc/2
Figure Timing Serial Port Output Function
Comparator
built-in comparator compare analog signal. There analog input paths from VNEG. reference inputs, from VPOS other from regulator output. When voltage positive input higher than negative input, comparator output will high. RESEC(COMPR.3) result comparison. internal rising signal RESC produces interrupt flag COMPF (EXIF.4). flag COMPF cleared when comparator interrupt routine executed cleared software. COMPEN enable comparator function.
VNEG(P4.2) VPOS(P4.4) REF1
X.XV REGULATOR RESET
RESC
EXIF.4 (COMPF)
COMPF=0
COMPEN SCON1.5(REGON)
Figure 6-10 Configuration Comparator
6.10 DTMF Generator
W925E/C625 provides DTMF generator which outputs dual tone multi-frequency signal DTMF pin. DTMF generator work well operating frequency 3.58MHz. DTMF generator register DTMFG controls DTMF output specifies desired low/high frequency. tones divided into groups (low group high group). When -43Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
generator disable, DTMF tri-state. relation between DTMF signal corresponding touch tone keypad shown Figure 6-11.
Row/Col Frequency 1209 1336 1477 1633
Figure 6-11 Relation Between DTMF Keypad DTGE Mnemonic: DTMFGR Bit: Address:
Selected tone 1209Hz 1336Hz 1477Hz 1633Hz 697Hz 770Hz 852Hz 941Hz Enable group frequency output. Enable high group frequency output. DTGE: Enable dual tone output DTMF pin.
6.11 Generator
W925E/C625 provides generator which outputs signal DTMF pin. output share with DTMF output pin. signal with 1200Hz baud rate ITU-T V.23 Bellcore signal. transmit data register (FSKTB) specifies desired output data. Transmit Control Register (FSKTC) control whether signal will output not. relation timing shown Figure 6-12.
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Enable signal (FTE) Latch clock [FSF] Data latch Flag (FDS) Data (FSKTB) bit0 Auto clear
Interrupt occur when rising edge
Hi-Z
Hi-Z
Signal (DTMF pin)
833us Figure 6-12 Modulator TRANSIMT CONTROL REGISTER Bit: FFDS Mnemonic: FSKTC FTE: transmit Enable. Enable=1, Disable=0 FTM: signal Standard. Bellcore 202=1, V.23=0 FDS: data sending status LO0, LO1: transmit level option output level 150mV 120mV 95mV 75mV (initial=00H) Address:
TRANSMIT DATA BUFFER (initial=00H) Bit: FSKTB.7 FSKTB.6 FSKTB.5 FSKTB.4 FSKTB.3 FSKTB.2 FSKTB.1 FSKTB.0 Mnemonic: FSKTB Address: FSKTB.0: Only This will latched send signal When enable will high enable internal latch clock 1200Hz. When high state, FSKTB bit0 will sent modulator rising edge latch clock. could cleared software inform more data will sent after last sent completely. cleared then will become next rising latch clock disable modulator clear hardware automatically. When set, modulation flag (FSF) will every rising edge latch clock produce interrupt shared with interrupt routine. interrupt occurs, user check know this interrupt caused modulator. only stop signal immediately disable software. -45Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
6.12 Ports
There 8-bit ports named from W925E/C625. ports configured input output mode. Except every port pull high resistor enable/disable register. After reset initial state each port input mode value registers from FFh. port described below: mode controlled P0IO. Only output open drain mode without pull high resistor. mode controlled P1IO. Pull high controlled P1H. P1.0~P1.3 work INT2, P1.4~P1.7 work INT3. Falling edge pins produce INT2 INT3 flag. configured INT2/INT3 P1EF register. mode controlled P2IO. Pull high controlled P2H. mode controlled P3IO. Pull high controlled P3H. P3.5 Timer/counter external count input P3.4 Timer/counter external count input P3.3 External interrupt INT1 P3.2 External interrupt INT0 mode controlled P4IO. Pull high controlled P4H. Special function described below. P4.4 Vpos Positive input comparator P4.2 Vneg Negative input comparator P4.1 SDATA Serial port output P4.0 SCLK Serial port input
6.13 Divider
built-in 13/14-bit binary up-counter designed generate periodic interrupt. clock source from sub-oscillator. When frequency sub-crystal 32768Hz, provides divider interrupt period 0.25/0.5 second. DIVS controls degree divider. When DIVA high enable divided counter, when DIVA reset divider stop counting. divider overflows, divider interrupt flag DIVF set. DIVF clear software serving divider interrupt routine.
DIVS (CKCON1.1) overflow
DIVF
(EXIF.3)
DIVA (DIVC.0)
Executing Clear software
Figure 6-13 13/14-bit Divider
6.14
1792 dots: Segments Common, bias
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internal voltage pump enable/disable option code. on/off controlled LCDON (SCON1.6). voltage pump enable, when LCDON high pump voltage waveform output pins according memory, when LCDON turn voltage pump. voltage internal regulator base voltage voltage pump which times base voltage. output voltage regulator tunable bits regulator voltage control register (REGVC). When REGVC equal 0AH, output voltage 1.0V. higher value REGVC lower voltage output regulator. adjustable voltage range about from 0.72V 1.48V Accordingly, contrast controlled value REGVC. variation voltage depends VDD. Following table REGVC regulator voltage.
Regvc Loading(3V) Loading(5V) With Loading(3v) With Loading(5v)
1.497 1.4464 1.3941 1.3426 1.2899 1.238 1.186 1.1352 1.081 1.029 0.976 0.924 0.869 0.815 0.762 0.7112 1.500 1.449 1.397 1.345 1.292 1.241 1.188 1.137 1.083 1.031 0.978 0.925 0.87 0.816 0.763 0.712 1.46 1.41 1.36 1.31 1.26 1.21 1.16 1.11 1.05 0.95 0.85 0.80 0.75 0.71
1.484 1.433 1.381 1.330 1.278 1.227 1.176 1.125 1.072 1.024 0.975 0.926 0.874 0.825 0.773 0.723
Frequency alternating frequency 16Hz, 32Hz, 64Hz 128Hz that determined bits option code. structure alternating frequency (FLCD) shown Figure 6-14.
Sub-oscillator clock
bits option code
optoin code LCDT1
Figure 6-14 alternating frequency (FLCD) circuit diagram 32.768 KHz, frequency shown table below. Table7 relationship between FLCD bits option code Option Code FLCD 16Hz 32Hz 64Hz 128Hz memory address list below. Each controlled corresponding content high light dot. OUTPUT COM0 COM1 COM2 COM3 S55-S48 BIT7-0 2006H 200EH 2016H 201EH S47-S40 BIT7-0 2005H 200DH 2015H 201DH S39-S32 BIT7-0 2004H 200CH 2014H 201CH -47S31-S24 BIT7-0 2003H 200BH 2013H 201BH S23-S16 BIT7-0 2002H 200AH 2012H 201AH S15-S08 BIT7-0 2001H 2009H 2011H 2019H S07-S00 BIT7-0 2000H 2008H 2010H 2018H
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PRELIMINARY W925E/C625 8-bit Microcontroller
COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 2026H 202EH 2036H 203EH 2046H 204EH 2056H 205EH 2066H 206EH 2076H 207EH 2086H 208EH 2096H 209EH 20A6H 20AEH 20B6H 20BEH 20C6H 20CEH 20D6H 20DEH 20E6H 20EEH 20F6H 20FEH 2025H 202DH 2035H 203DH 2045H 204DH 2055H 205DH 2065H 206DH 2075H 207DH 2085H 208DH 2095H 209DH 20A5H 20ADH 20B5H 20BDH 20C5H 20CDH 20D5H 20DDH 20E5H 20EDH 20F5H 20FDH 2024H 202CH 2034H 203CH 2044H 204CH 2054H 205CH 2064H 206CH 2074H 207CH 2084H 208CH 2094H 209CH 20A4H 20ACH 20B4H 20BCH 20C4H 20CCH 20D4H 20DCH 20E4H 20ECH 20F4H 20FCH 2023H 202BH 2033H 203BH 2043H 204BH 2053H 205BH 2063H 206BH 2073H 207BH 2083H 208BH 2093H 209BH 20A3H 20ABH 20B3H 20BBH 20C3H 20CBH 20D3H 20DBH 20E3H 20EBH 20F3H 20FBH 2022H 202AH 2032H 203AH 2042H 204AH 2052H 205AH 2062H 206AH 2072H 207AH 2082H 208AH 2092H 209AH 20A2H 20AAH 20B2H 20BAH 20C2H 20CAH 20D2H 20DAH 20E2H 20EAH 20F2H 20FAH 2021H 2029H 2031H 2039H 2041H 2049H 2051H 2059H 2061H 2069H 2071H 2079H 2081H 2089H 2091H 2099H 20A1H 20A9H 20B1H 20B9H 20C1H 20C9H 20D1H 20D9H 20E1H 20E9H 20F1H 20F9H 2020H 2028H 2030H 2038H 2040H 2048H 2050H 2058H 2060H 2068H 2070H 2078H 2080H 2088H 2090H 2098H 20A0H 20A8H 20B0H 20B8H 20C0H 20C8H 20D0H 20D8H 20E0H 20E8H 20F0H 20F8H
Power Connection power connection bias shown Figure 6-15
Bias
0.1uF VLCD5 VLCD4 VLCD3 VLCD2 Regulator VLCD1 0.1uF
C1=C2=C3=C4=C5=C6=0.1uF
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Figure 6-15 Bias Power Connection Waveform waveform type. Figure 6-16 example bias waveform.
COM0
COM1
COM2
COM3
outputs only seg. COM0 COM2 side being
Figure 6-16 waveform bias
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6.15 Calling Identity Delivery (CID)
W925E/C625 provides type type system. Type on-hook calling with message type off-hook call waiting. function includes decoder, dual tone alert signal detector, ring detector DTMF receiver. demodulation function demodulate Bell ITU-T V.23 Frequency Shift keying (FSK) with 1200 baud rate. Tone Alert Signal detect function detect dual tones Bellcore Customer Premises Equipment(CPE) Tone Alerting Signal(CAS) Idle State Loop State Tone Alert Signal. line reversal ring burst ring signal Bellcore detected ring detector. compatible with Bellcore TR-NWT-000030 ST-TSV-002476, British Telecom(BT) SIN227, U.K. Cable Communications Association(CCA) specification. DTMF receiver programmed DTMF decoder decode DTMF signals tone detector detect signal which frequency DTMF band. tone detector auxiliary detector improve performance detecting tone alerting signal(CAS), said talk down-off, type system. decoder, alert tone detector DTMF receiver enable/disable individually bits FSKE, CASE DTMFE DATA REGISTER(FSKDR). CIDE global control enable/disable decoder, alert tone detector DTMF receiver. However, ring detector always active.
CIDGD CIDGA DTMFE
<7:4>
Input Pre-processor
High Tone Bandpass Filter PHAD<3:0>
High Tone Detector
INP2 INN2 GCFB2
Guard Time Timer
Decode data Latch
PGAF <3:0>
Anti-alias Filter
<3:0>
Tone Bandpass Filter
DTMFD
Tone Detector
DD3-DD0
FSKE
DTMFPT/DTMFAT
FDATA
Demodulation Circuit
Bandpass Filter
Demodulator
PHFL<7:4>
Input Pre-processor
Data Output Interface
INP1 INN1 GCFB1 VREF CIDE,RST VADD
FD7-FD0
PGAF <7:4>
Anti-alias Filter
Carrier Detector
DATE
internal circuit
High Tone
PHFL<3:0>
Dual Tone Alert Signal Detection Circuit High Tone Detector
PHAD<7:4>
Bias Voltage Generator
Bandpass Filter
Guard Time Circuit
Interrupt Generator
ALGO CASPT/CASAT
Tone Bandpass Filter
Tone Detector
Clock Driver
VASS
Ring Detector internal circuit
RNGDI
RNGRC
signals noted italic underline type pins chip. Figure 6-17 Block Diagram
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Ring Detector application circuit Figure 6-18 illustrates relationship between RNGDI, RNGRC signals. combination RNGDI RNGRC used detect increase RNGDI voltage from ground level above Schmitt trigger high going threshold voltage VT+.
C1=0.1uF Tip/A R3=200K R1=470K
RNGDI
C1=0.1uF Ring/B R2=470K
R4=300K
R5=150K RNGRC
C3=0.22uF
Allowance minimal ring voltage (peak peak) (max ring) (VT+(max) 0.7)
Tolerance noise between Ring Vpeak (max noise) T+(min) Time constant [VDD (VDD VT+)] VT+(min) VT+(max) from 500K ohm. from 0.68
Figure 6-18 Application Circuit Ring Detector time constant RNGRC used delayed output pulse flag going edge RNGDI. This edge goes from above voltage Schmitt trigger going threshold voltage VT-. time constant must greater than maximum period ring signal, ensures minimum high interval filter ring signal envelope output. rising signal will RNGF(CIDFG.0) high cause flag(CIDF) high. diode bridge shown Figure 6-18 works both single ended ring signal balanced ringing. used maximum loading must equal value achieve balanced loading both ring line. form resistor divider supply reduced voltage RNGDI input. attenuation value determined detection minimal ring voltage maximum noise tolerance between tip/ring ground. Input Pre-Processor input signal processed Input Pre-Processor, which comprised amps bias source(VREF). gain OP-amps used bias input voltage with VREF signal voltage. VREF VAD/2 typically, this recommended connect capacitor VAS. gain adjustable amps sued select input gain connecting feedback resistor between GCFB pins. Figure 6-19 shows differential input configuration Figure 6-20 shows single-ended configuration. -51Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
VREF
0.1uF
GCFB
Voltage Gain Input Impedance
Differential Input Amplifier
Figure 6-19 Differential Input Gain Control Circuit
0.1uF
VREF
GCFB
Voltage Gain
Figure 6-20 Single-Ended Input Gain Control Circuit CAS/DTAS Detection off-hook services (type II), detection CAS/DTAS will affect quality call waiting service. When CAS/DTAS sent from end, sometimes near user maybe still talking. must able detect CAS/DTAS successfully presence near speech. detect CAS/DTAS from telephone hybrid receiver pair improves detection. However on-hook system CAS/DTAS detection from Tip/Ring pair. dual tone alert signal separated into high tones detected high/low tone detector. When alert tone recognized detector, ALGO will high rising signal will ALGOF CIDFG produce flag(CIDF). Figure 6-21 shows guard time waveform detecting alert tone. total recognition time tREC =tDP+tGP, where tone present detect time tone present guard time. total absent guard time tABS=tDA+tGA where tone absent detect time tone absent guard time. tone present/absent guard time determined guard-time timer which input clock period 0.858mS. When alert tone detected internal signal ALGR will rising edge ALGR resets guard-time timer timer starts counting from 00H. content timer same register CASPT, timer stops counting ALGO will rising edge ALGO triggers flag ALGOF become high. -52Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
counting tone absent time similar counting tone present time falling edge ALGR/ ALGO replaces rising edge CASAT replaces CASPT. ALGO controlled hardware only. flag ALGOF rising edge ALGO cleared software.
Dual Alert Tone Signal
ALGR*
ALGO
ALGOF
Guard time timer reset starts count from 00H. Guard time timer reset starts count from 00H. content guard-time timer reaches content ASPT/ASAT.
*ALGR internal signal Clear software.
Figure 6-21 Guard Time Waveform Alert Tone Signal Detection DTMF Decoder DTMF decoder shares same input pre-processor with decoder. dual tone separated into group high group SCFs (switched capacitor filter. method DTMF detection same alert tone detection. present/absent guard time adjusted registers DTMFPT/DTMFAT. DTMF signal recognized decoded, DTMFD will decoded DTMF data stored bit0 bit3 register DTMFDR. rising edge DTMFD produces flag DTMFDF. DTMFD controlled hardware only. flag DTMFDF rising edge DTMFD cleared software.
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Dual Alert Tone Signal
ALGR*
ALGO
ALGOF
Guard time timer reset starts count from 00H. Guard time timer reset starts count from 00H. content guard-time timer reaches content ASPT/ASAT.
*ALGR internal signal Clear software.
Figure 6-22 Waveform DTMF Detection Tone Detector off-hook state, said type system, detecting tone alert signal(CAS) easily interfered human' voice other noise voice band. Sometimes interference makes falsely recognizing noise CAS(talk-off), lost detecting real CAS(talk-down). DTMF programmed tone detector setting DTMFR2. frequency band tone detector DTMF frequency from 697Hz 1633Hz. Once tone detector gets signals band, DTMFH DTMFL register DTMFDR will become high immediately. User poll these bits check tone exists tip/ring. input gain tone detector same DTMF receiver. Decoder carrier detector provides indication present signal within frequency band. output amplitude band-pass filter sufficient detected continuously carrier detected will high will released band-pass filter output amplitude able detected greater than hysteresis carrier detector. Figure 6-23 shows timing carrier detection.
Tip/Ring FSKE FSKE
Note
Analog Signal
Analog Signal
Figure 6-23 Detection Enable Carrier Present Absent Timing demodulation function demodulate Bell ITU-T V.23 Frequency Shift keying (FSK) with 1200 baud rate. When decoder receives serial data, serial data will demodulated into FDATA with 1200 baud rate mean time synchronous clock signal output FCLK. decoder receives byte, internal serial-to-parallel circuit sets converts 8-bit serial data into byte register FSKDR. rising edge will flag FDRF produce interrupt FDRF cleared software. User -54Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
data reading register FSKDR sampling FDATA. timing demodulation shown Figure 6-24.
byte data start stop start byte data start stop start byte data stop start byte data stop start
Tip/Ring
FDATA
1/fDCLK0
FCLK
FDRF FSKDR Mark redundant stop bit(s), will omitted. Clear software.
byte data byte data
Figure 6-24 Serial Data Interface Timing Demodulation Input Gain Control input gain input hysteresis controllable internal gain control registers. CIDGD CIDGA registers determine internal gain control registers. gain control data register (CIDGD) presents data bus. lower bits gain control address register (CIDGA) presents address. rising edge CIDGA.4 will latch CIDGD corresponding internal gain control register. internal gain control registers addressed following table. Setting registers suggestion value guarantees spec. Address Internal Gain Control Register Suggestion (CIDGA.2-0) Value DTMFR1: DTMF register1 0000 0001B DTMFR2: DTMF register2 011X PGAF: Programmable gain control alert tone PGAD: Programmable gain control DTMF PHAD: Programmable hysteresis alert tone DTMF PHFL: Programmable hysteresis pass filter
DTMF receiver works DTMF decoder, DTMF receiver works tone detector.
signals internal gain control registers shown Figure 6-25
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CIDGA CIDGA<2:0>
CIDGD
CIDGD
CIDGA.3
Rising latch
Figure 6-25 Internal Gain Control Register Setting Waveform DTMFR1 DTMFR1[7:4] reserved bits must 0000b. Bit3~Bit0 Acceptable error percentage sample period freq. 0000 0.6% (default) 0001 2.5% 001X 3.5% 01XX Reserved 1XXX Reserved DTMFR2 Bit3~Bit0 Acceptable error percentage sample period freq. 0000 0.5% (default) 0001 1.5% 001X 2.5% 01XX Reserved 1XXX Reserved acceptable error percentage have small variation different test environments. DTMFR2.4=0 DTMFR2.4=1 DTMFR2.5=0 DTMF receiver works DTMF receiver DTMF receiver works tone detector DTMF counter counter type, change detected frequency does effect counter DTMFR2.5=1 DTMF counter counter type, change detected frequency resets DTMF counter DTMFR2.6=0 DTMF counter up-down counter type, counting when DTMF detected, down counting DTMF detected again. DTMFR2.6=1 DTMF counter counter type, counting when DTMF detected, pause counting DTMF detected again. DTMFR2.7: reserved
There programmable gain arrays, shown Figure 6-17, determined Low/High nibbles PGxx. following table lists input gain corresponding value nibble PGxx.
log((40+15*X)/(230-(40+15*X)))
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log((40+15*X)/(230-(40+15*X)))
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PRELIMINARY W925E/C625 8-bit Microcontroller
-13.53 -10.05 -7.18 -4.64 -2.28 0.00 2.28 4.64 7.18 10.05 13.53 value nibble PGxx
There programmable hysteresis input buffer, shown Figure 6-17, determined Low/ High nibbles PHxx. hysteresis control formulas list below. Alert tone hysteresis HAT=13mv 3mv*X X=PHAD<7:4> DTMF hysteresis HDTMF=6mv 3mv*X X=PHAD<3:0> hysteresis HFSK=13mv 3mv*X X=PHFL<7:4> detector hysteresis HFSKD=13mv 3mv*X X=PHFL<3:0> Application Circuit analog interface circuit W925E/C625 shown Figure 6-26 typical system. gain control op-amp unit gain allow electrical characteristics this application circuit.
22nF 430K
Tip/A INP2 INN2
22nF 430K 53K6 464K 60K4
Ring/B
0.1uF 0.1uF 470K 150K 200K 0.1uF 470K 464K Microphone Ring 464K 22nF TxRx+ RxSpeaker
GCFB2 VREF RNGDI RNGRC
100K 60K4
0.47u
60K4
INP1 INN1
Speech Network
464K 22nF
464K
GCFB1
Resistor must have tolerance Resistor must have tolerance
Figure 6-26 Application Circuit
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Application Environment There three major timing differences sequences, Bellcore, CCA. Figure 6-27 timing diagram Bellcore on-hook data transmission Figure 6-28 timing diagram Bellcore off-hook data transmission. Figure 6-29 timing diagram caller display service on-hook data transmission Figure 6-30 timing diagram caller display service off-hook data transmission. Figure 6-31 timing diagram caller display service on-hook data transmission. flag (CIDF) must cleared software when each time interrupt routine serviced. global enable signal (CIDE) must high.
Tip/Ring Ring CIDF seizure Mark Message Ring
FSKE
FCLK
FDATA
.101010.
Data
typical 250-500mS 250mS 150mS depend data length C+D+E 200mS
Figure 6-27 Input Output Timing Bellcore On-hook Data Transmission
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goes off-hook mutes handset disables keypad sends Tip/Ring Mark Message unmutes handset enable keypad
CIDF
ALGO
FSKE
FCLK
FDATA
Data
85mS 100mS 65mS 500mS 75mS depends data length 50mS
Figure 6-28 Input Output Timing Bellcore Off-hook Data Transmission
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Line Reversal
Wires
Alert Signal
Seizure
Mark
Message
Ring
RNGON
CIDF
ALGO
load
120uA
(optiona) Current wetting pulse (Refer SIN227)
load
Note
(Refer SIN227)
Note
FSKE
Note
FCDN
FDRN
DCLK
DATA
.101010.
Data
100mS 100mS 45mS 5Sec) 262mS 75mS 2.5S (500mS typical) 200mS
Figure 6-29 Input Output Timing Idle State (On-hook) Data Transmission
Note: SIN227 specifies that loads should applied after dual tone alert signal. SIN227 specifies that loads should removed between 150mS after signal. FSKE should disable decoder when expected. tone alerting signal speech DTMF tones same frequency band signal.
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PRELIMINARY W925E/C625 8-bit Microcontroller
goes off-hook Start Point Tip/Ring Note Note mutes handset disables keypad sends Mark Message unmutes handset enable keypad
CIDF
ALGO
FSKE
Note
Note
Note
FCLK
FDATA
Data
50mS 85mS 100mS 75mS 100mS 75mS depends data length 100mS
Figure 6-30 Input Output Timing Loop State (Off-hook) Data Transmission
Note: where power available, designer choose switch over line power when goes off-hook battery power while on-hook. FSKE prevent alert tone, speech other in-band noise decoded demodulator give false data when dual tone alert signal expected. FSKE controlled micro-controller, FSKE must always placed high state micro controller must give decoded data when signal expected. exchange will have already disabled speech path distant customer both transmission directions. FSKE should high soon finished sending acknowledge signal ACK. FSKE after last byte (check sum) been decoded become inactive. unsuccessful attempts where exchange does send signal, should disable FSKE, un-mute handset enable keypad after this interval.
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Line Reversal First Ring Cycle Seizure Mark Message
Wires
Ring Burst
CIDE
Note
CIDF
load
load
Note
Note
FSKE
Note
FCLK
FDATA
.101010.
Data
450mS 500mS 262mS 262mS 2.5sec (500ms typical) 200mS
Figure 6-31 Input Output Timing Caller Display Service Data Transmission
Notes: designer choose FSKE always high while on-hook signal expected. TW/P E/312 specifies that loads should applied between after ring burst. TW/P E/312 specifies that loads should removed between after signal. enable first ring cycle after data been processed.
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ELECTRICAL CHARACTERISTICS
Maximum Ratings*
Parameter Supply Voltage with respect Voltage other than supplies (note Current other than supplies Storage Temperature Symbol Rating -0.3 -0.7 Units
(Voltage referenced pin)
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect lift reliability device. should excess maximum rating supply voltage.
Recommended Operating Conditions
Symbol fOSC fSUB Rating 3.579545 32768 -0.1 +0.1 Unit
Characteristics Power Supplies (Analog) Power Supplies (Digital) Main Clock Frequency Clock Frequency Tolerance Clock Frequency Operation Temperature
Electrical Characteristics
Symbol IOP1 IOP2 IOP3 IOP4 IOP5 IOP6 Condition dual clock, normal Off, dual clock, normal off, slow run, main stopped Idle mode, dual clock Idle mode, main stopped Power down mode Typ* Unit Note
Parameter Operating Current
0.7VDD 0.3VDD
Ports Input High Voltage Ports Input Voltage Ports Output High Voltage
2.0mA -63-
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Ports Output Voltage Output High Voltage Output High Voltage Current DTMF Output Level DTMF Distortion DTMF Output Voltage Pre-emphasis Output Level Distortion Output Voltage Port Pull High Resistor Schmitt Input High Threshold Schmitt Input High Threshold Schmitt Hysteresis RNGRC Sink Current Input Current VBOH VBOL ILCD VTDC DTHD 2.0mA 3.5mA 3.5mA Seg. 2.5-3.8 2.5-3.8 group, Col/Row 2.5-3.8 2.5-3.8 RNGDI, RNGRC RNGDI, RNGRC RNGDI, RNGRC RNGRC INPx, INNx, RNGDI 0.48VAD 0.28VAD 0.5VAD 0.5VAD 1000 0.68VAD 0.48VAD load
VFDC FTHD VTVHYS IRNGL
Reference Output VREF VREF voltage Reference Output RREF VREF Resistance Typical figure temperature
-64-
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Electrical Characteristics Gain Control OP-Amplifier
(Electrical characteristics supersede recommended operating conditions unless otherwise stated.)
Parameter Input Leakage Current
Symbol
Units
Test Conditions
Input Resistance Input Offset Voltage Power Supply Rejection Ratio PSRR Maximum Capacitive Load (GCFBx) Maximum Resistive Load (GCFBx) Note: Typical figure temperature
production testing.
ripple
design aids only, guaranteed subject
Electrical Characteristics
timing characteristics supersede recommended operating conditions unless otherwise stated.)
Dual Tone Alert Signal Detection Interface Parameter Symbol Tone Frequency High Tone Frequency Frequency Deviation accept Frequency Deviation reject Maximum Input Signal Level Input Sensitivity tone Reject Signal Level tone Positive negative twist accept Noise Tolerance SNRTONE
2130 2750
0.22
Units
Notes
Notes: decibels with reference power into ohms, 0.7746 Vrms. Twist amplitude amplitude). Both tones have same amplitude. Both tones nominal frequencies. Band limited random noise 3400 Present only when tone present. Range within which tones accepted. Ranges outside which tones rejected. These characteristics temperature
Dual Tone Alert Signal Detection Parameter Condition Symbol Alert Signal present detect time ALGR Alert Signal absent detect time Typical figure temperature design aids
production testing.
Units Notes
only, guaranteed subject
-65-
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Detection Interface Parameter Input Frequency Detection Bell Mark (logic Bell Space (logic ITU-T V.23 Mark (logic ITU-T V.23 Space (logic Maximum Input Signal Level Input Sensitivity Transmission Rate Input Noise Tolerance Symbol fMark fSpace fMark fSpace 1188 2178 1280.5 2068.5 1188 1200 2200 1300 2100 1212 2222 1319.5 2131.5 -5.78 1212 Units Notes
1200
SNRTONE
baud
Notes: Both mark space have same amplitude. Both mark space nominal frequencies. Band limited random noise 3400 Present only when signal present. These characteristics temperature
Detection Parameter detection enable time Input high delay Input delay Data Ready Time Rate Input DATA delay Frequency High Time Time DCLK delay
Condition FSKE DATA DCLK DCLK,
Symbol tFSK tIDD fDCLK tCRD
1212 1204
1188 1201.6
1200 1202.8
Units
Notes
Note input data rate 1200 baud. OSCI frequency 3.579545 0.1%. Typical figure temperature design aids only, guaranteed subject production testing.
DTMF Decoder Parameter Input Sensitivity tone Positive negative twist accept Frequency Deviation accept Frequency Deviation reject Tone Tolerance Noise Tolerance Dial tone Tolerance
Symbol
Units
Notes 1,2,3 1,2,3 1,2,4
Note signal consists DTMF tones. Tone duration 40mS least, tone pause duration 40mS least. Referenced lowest level frequency component DTMF signal. Referenced minimum valid accept level.
DTMF Detection Interface -66Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
Parameter DTMF present detect time DTMF absent detect time DTMF Detected Duration DTMF Signal Ignore Time DTMF Pause Accept Time Typical figure
production testing.
Condition DTMFD=1 DTMFD=0 DTMFD=1
Symbol tDPA
Units Notes
temperature design aids only, guaranteed subject
-67-
Release Date 2002/5/13 Revision
PRELIMINARY W925E/C625 8-bit Microcontroller
PACKAGE
160L (28X28 footprint 3.2mm)
Detail Seating Plane
Detail
control dimensions
Symbol
Dimension inch
Dimension
0.004 0.122 0.008 0.004 1.097 1.097 0.022 1.217 1.217 0.025 0.055
0.145
0.10
0.127 0.012 0.006 1.102 1.102 0.026 1.228 1.228 0.031 0.063
0.132 0.016 0.010 1.107 1.107 0.030 1.240 1.240 0.037 0.071 0.004
3.10 0.20 0.10 27.87 27.87 0.55 30.90 30.90 0.65 1.40
3.23 0.30 0.15 28.00 28.00 0.65 31.20 31.20 0.80 1.60
3.35 0.40 0.25 28.13 28.13 0.75 31.50 31.50 0.95 1.80 0.10
-68-
Release Date 2002/5/13 Revision
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