PanelLinkTechnology High Speed Transmitter Receiver Data Sheet Re

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PanelLinkTechnology High Speed Transmitter Receiver Data Sheet Re

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65100/101
PanelLinkTechnology High Speed Transmitter Receiver
Data Sheet Revision July 1996
Copyright Notice Copyright© 1996 Chips Technologies, Inc. RIGHTS RESERVED. This manual copyrighted Chips Technologies, Inc. reproduce, transmit, transcribe, store retrieval system, translate into language computer language, form means electronic, mechanical, magnetic, optical, chemical, manual, otherwise part this publication without express written permission Chips Technologies, Inc. Restricted Rights Legend Use, duplication, disclosure Government subject restrictions forth subparagraph (c)(1)(ii) Rights Technical Data Computer Software clause 252.277-7013. Trademark Acknowledgment CHIPS Logo, PEAK, PRINTGINE, SCAT, WINGINE registered trademarks Chips Technologies, Inc. HiQVideo, HiQV32, HiQV64, HiQV64P, HiQV100, Unified Architecture, Unified Memory, XRAM Video Cache trademarks Chips Technologies, Inc. Brooktree RAMDAC trademarks Brooktree Corporation. Hercules trademark Hercules Computer Technology. Inmos trademark Inmos Corporation. 386SX, i387, 486, i486, Pentium trademarks Intel Corporation. IBM, PS/2 Personal System/2 registered trademarks International Business Machines Corporation. trademark International Business Machines Corporation. Microsoft registered trademark Microsoft Corporation. MS-DOS Windows trademarks Microsoft Corporation. TRI-STATE registered trademark National Semiconductor Corporation. MultiSync trademark Nippon Electric Company (NEC). PanelLink technology licensed Chips Technologies, Inc. from Silicon Image, Inc. Palo Alto, PanelLink trademark Silicon Image, Inc. VESA registered trademark Video Electronics Standards Association. VL-Bus trademark Video Electronics Standards Association. Weitek registered trademark Weitek Inc. other trademarks property their respective holders. Disclaimer This document provides general information customer. Chips Technologies, Inc., reserves right modify information contained herein necessary customer should ensure that most recent revision document. CHIPS makes warranty products bears responsibility errors which appear this document. customer should notice that many different parties hold patents products, components, processes within personal computer industry. Customers should ensure that their products does infringe upon patents. CHIPS respects patent rights third parties shall participate direct indirect patent infringement.
Revision History
Revision History
Revision 0.11 0.13 0.15 0.17 0.18 Date 11/95 11/95 12/95 1/96 1/96 Comment Internal Draft. First Draft. Added identification. Removed PixelBlaster. Added signal mapping Bypass 18/24/36-bit mode. Added control signal mapping description 36-bit mode section. Added packaging diagrams. Added additional information Product Summary Section Added connects (N/C) 65101 description. Added further DE/Data edge description Data Capture Logic section 3.1. DCLK changed ODCK Panel Interface Logic section 4.1. Added CHIPS font formatting. Specifications. Modified Electrical Mechanical
2/96 3/96
Added diagrams. Revised according etc. Modified Mechanical Specifications. Signals were changed simplify interfaces between controller PanelLink CHIPSet. HSYNC VSYNC IDCK IVCC ODCK OVCC OGND DCLK DVCC DCLK DVCC DGND
4/96 5/96 7/96
requirement removed. Modified functional diagrams. Added diagrams text. description feature changes.
Revision
7/29/96
Advance Product Information 65100/101 Subject change without notice
Table Contents
Table Contents
Revision History. Table Contents List Tables List Figures Features Introduction/Overview Description 65100 Diagram 65101 Diagram 65100 Functional Description Data Capture Logic Bypass Encoder Mode DC-Balanced Encoder 65101 Functional Description Impedance Matching Circuit Data Recovery Block Channel Synchronization Block Decoder Block Panel Interface Logic Block Panel Interface Logic Signal Mapping Electrical Specifications Timing Diagrams Mechanical Specifications
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List Tables
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Panel Data Timing Falling Edge DCLK Input Data Timing Rising Edge DCLK Toggling Results Signal Mapping Bypass Mode Signal Mapping 18/24-Bit Mode Signal Mapping 36-Bit Mode Absolute Maximum Conditions Normal Operating Conditions CMOS Signals Characteristics Differential Receiver Specifications Differential Transmitter Specifications Characteristics
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List Figures
List Figures
Figure PanelLink 65100 65101 Application Diagram Figure Transmitter (65100) Diagram Figure Receiver (65101) Diagram Figure 65100 Functional Block Diagram Figure 65100 Timing Diagrams Figure 65101 Functional Bloc Diagram Figure Timing Diagram: Relationship Between DCLK Output Data, PIXS DCKINV Figure Timing Diagram: Relationship Between DCLK Output Data, PIXS DCKINV High Figure Timing Diagram with Figure Timing Diagram with High Figure Transmitter Small Signal Transition Times Figure Receiver Digital Output Transition Times Figure Transmitter/Receiver Clock Cycle/High/Low Times Figure Data Setup/Hold Times from Falling/Rising Edge DCLK Transmitter (65100) Figure Time Delay from Rising Edge DCLK Data Receiver (65101) Figure Time Delay from Falling Edge DCLK Data Receiver (65101) Figure Transmitter (65100) 64-Pin Plastic TQFP Figure Receiver (65101) 80-Pin Plastic TQFP
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Features
Features
High Speed Serial Receiver Transmitter 65100 PanelLink Transmitter 65101 PanelLink Receiver Count Packages 64-pin TQFP 65100 80-pin TQFP 65101 High Speed Operation Three low-voltage swing differential data links capable transferring data MBytes/sec Impedance matching reduce noisy reflections Transition minimized coding reduce data edges Power core voltage operation Low-voltage swing differential transceiver/receiver power/low cost CMOS technology Powerdown mode Direct Interface CHIPS HiQVideoPortable Graphics Accelerator Family Compatible with many graphics controllers High Speed Trims jitter less than Flexible Panel Interface 65101 programmable 24-bit pixel/clock) 36-bit pixels/clock) panel interface control signals supported addition Display Enable (DE) High Integration Three low-swing differential data links transfer both data control signals clock link Display control signals transmitted without requiring additional data links Integrated with external components DC-Balanced Encoder 65100) Decoder 65101) Reliable Data Transmission Full Color High Resolution Display Supports 24-bit/pixel panel 16.7 colors/pixel) Supports 1024x768 Active Matrix Liquid Crystal Display (AMLCD) panels pixel clock
65100 Transmitter Data Pairs
65101 Receiver Data (24/36) Decoder
Data (24) Encoder Flat Panel Graphics Controller Serializer Controls
Data Recovery Panel Interface Clock Pair
Controls Panel Control ASIC Flat Panel
Clock (max MHz)
Clock
Figure PanelLink 65100 65101 Application Diagram
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Introduction/Overview
Introduction/Overview
PanelLink 65100 65101 High Speed Digital Video/Graphics Interconnect CHIPSet that solve issues associated with high speed displays. Capable supporting true color Active Matrix Liquid Crystal Display (AMLCD) panels, transmitter (65100) takes parallel video/graphics data from host graphics controller transmits serially receiver (65101). PanelLink technology reduces system cost, minimizes board space requirements, reduces signal line count, most importantly, lowers EMI.
Design Flexibility
Using PanelLink technology, notebook designers motherboard panel interface design support resolutions from color depths bits pixel. This provides CHIPS family graphics accelerators with common interface. addition, panel manufacturers choose either pixels clock cycle half frequency output data pins 65101 receiver. 65101 transmit pixels clock (36-bit interface) 18-bit pixel modes reduce clock speeds. Also, control lines available supporting additional features that exist panel side.
Several leading edge design features this CHIPSet lower system EMI. receiver (65101) provides variable on-chip resistors lower cable/connector noise reflections cable/connector systems. 65101's variable resistance control feature allows notebook design engineers adjust receiving chip impedance match characteristic impedance cable/connector system used, significantly reducing noise reflections. addition, on-chip design both 65100 65101 limits noise motherboard. Since radiated proportional transmitted edges, reducing number edges transmitted data bytes another objective PanelLink design. This proprietary, patented encoding method reduce number transitions data byte. PanelLink solution reduces notebook board space requirements square inches eliminating need T-filters terminating resistors typically used reduction standard high speed digital systems such SVGA notebook.
Jitter Filtering
PanelLink design trims input jitter from graphics controller less than This filtering technique ensures high quality video/graphics data flat panel display.
Cost Long Distance Cable Fiber Optics
transmitter drive lower cost cables over longer distances since voltage swing adjustable higher levels, video/graphics data inherently DCbalanced. transformer coupling needed drive panels distant locations with different power sources than those host system. Additionally, coupling required before optical converters used optical fiber transmission video/graphics data over long distances. inherently DC-balanced signals ideal transformer coupling.
Skew Tolerant Transmission
prevent synchronization errors pixel "corruption," red, green, blue data channels reference clock line force synchronization after each display line transmitted flat panel display.
Power
operating reducing capacitance load drive requirements from graphics controller display, PanelLink technology consumes minimal power saves overall system power. Transition minimization reduce number edges transmitted, frequency PLL, power down (deep sleep) mode also lower power consumption. programmable interface voltage levels (3.3 allow matching voltage levels interface between graphics controller panel interface controller.
Compatibility
devices described this data sheet have their operation verified CHIPS using CHIPS' graphics controllers. Other manufacturers' devices will readily interface with PanelLink technology. Before choosing particular graphics controller, verify that input clock jitter data set-up hold times compatible.
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Description
Description
65100 Diagram
65100 available 64-pin TQFP package, shown below.
DVCC
CLT0 CLT1 CLT2 CLT3 DEDGE CEDGE DCLK BYPASS TESTIN PLLCK
TESTOUT SUPV EXT_RES
65100 Transmitter 64-Pin TQFP
Figure Transmitter (65100) Diagram
Analog Output Digital Input Ground Digital Output
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RESERVED
AGND
AGND
AGND
AVCC
AVCC
TX0+
TX1+
PGND
PVCC
TXC+
TX2+
TXC-
TX0-
TX1-
TX2-
Description
65100 Description
Name DCLK Type Pixel clock. Data latched either falling rising edge DCLK selected DEDGE. Used internal PLL, this clock needs free running well constant frequency. panel applications, this clock same SHFCLK output from controller. maximum frequency MHz. Display Enable. This signal qualifies active display area. Description Flat panel data bits 23-0. Data synchronized with pixel clock (DCLK). Data toggle when high. While low, data will transmitted.
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Description
65100 Description (Cont'd)
Name Type Description Latch Pulse. Flat panel equivalent HSYNC. FLM, CLT[3:0] toggle when low. While high, information from these signals will transmitted. First Line Marker. Flat panel equivalent VSYNC. General input control signal CLT[3:0] used transfer additional control signals. General input control signal General input control signal General input control signal Clock latching edge data. level indicates that panel data (P[23:0]) latched falling edge DCLK while high level indicates that data latched rising edge DCLK. Clock latching edge display enable (DE) control signals (LP, FLM, CLT[3:0]). level indicates that display enable control signals latched falling edge DCLK while high level indicates that display enable control signals latched rising edge DCLK. Bypass control signal. level indicates normal operation. high level (for test purposes only) indicates that input signals transmitted directly transmitter bypassing encoder block. Input threshold voltage control signal. high level indicates that input signal voltage level level indicates that input signal voltage level 3.3V. Power Down mode (active low). high level indicates normal operation level indicates power down mode. During power down mode, data (P[23:0]), display enable (DE), clock (DCLK) control signals (LP, FLM, CLT[3:0]) input buffers disabled, analog logic powered down. This active during both normal operation test modes. Output ring test mode. Manufacturing ring test mode. level indicates normal operation high level indicates ring test mode. Power supply input display interface signals from graphics controller. This supplies power input protection devices. This must input signals input signals Core VCC. These pins supply power input buffers core digital logic must
CLT0 CLT1 CLT2 CLT3 DEDGE
CEDGE
BYPASS
SUPV
TESTOUT TESTIN DVCC Power
Power Power
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Description
65100 Description (Cont'd)
Name TX0+ TX0TX1+ TX1TX2+ TX2TXC+ TXCRSVD Type Description Ground Digital GND. Ground Ground Ground Analog voltage swing differential output data pairs. Analog Analog Analog Analog Analog Analog voltage swing differential output clock pair. Analog -Reserved. This should left open. Voltage Swing Adjust. resistor between this AVCC will adjust differential signal voltage swing. relationship resistance voltage swing characterized follows: 0.5V (500 where differential voltage swing resistance EXT_RES pin. AVCC AVCC AGND AGND AGND PVCC PGND PLLCK Power Power Transmitter Analog VCC. Must
EXT_ Analog
Ground Transmitter Analog GND. Ground Ground Power Analog VCC. Must
Ground Analog GND. Internal clock test characteristics. operating frequency 2.5x that DCLK.
Note:
Refer Signal Mapping (pages 20-21) description data coordination between data-in 65100 data-out 65101.
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Description
65101 Diagram
Receiver (65101) available 80-pin TQFP package shown below. Output data currently limited bits; therefore, pixel/clock output data format, maximum number bits pixel pixel/clock output data format, maximum number bits pixel remains
EXT_RES
DCKINV
Z0CONT
AGND
AGND
AVCC
AVCC
PGND
RXC+
PVCC
RX0+
RX1+
RX2+
RXC-
RX0-
RX1-
RX2-
PLLCK TESTIN BYPASS PIXS CLT0 CLT1 CLT2 CLT3 DGND DVCC
DVCC DGND
65101 Receiver 80-Pin TQFP
DGND
DCLK
DVCC
Figure Receiver (65101) Diagram
Analog Input Digital Input Ground Digital Output
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Description
65101 Description
Name RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXCNC EXT_RES Type Description Analog voltage swing differential input data pairs. Analog Analog Analog Analog Analog Analog voltage swing differential input clock pair. Analog Reserved. This should left open.
Analog Impedance matching control pin. pull-up resistor cable impedance should connected this pin. case cable between 65100 65101, external resistor should connected between this minimize signal reflection. relationship applies regardless Z0CONT setting. Power Power Receiver Analog VCC. Must
AVCC AVCC AGND AGND PVCC PGND PLLCK BYPASS
Ground Receiver Analog GND. Ground Power Analog VCC. Must
Ground Analog GND. Internal clock test characteristics. operating frequency 2.5x DCLK. Bypass control signal. level indicates normal operation. high level indicates that data transmitted directly panel interface logic bypassing decoder block. Pixel Select option. level indicates that output data pixel 24bit) clock high level indicates that output data pixels 36bit) clock. DCLK mask. level allows DCLK continuously high level enables DCLK mask: DCLK stopped (LOW) when (Display Enable) low. Connect Connect Termination resistance range selection. logic level selects range logic high level selects range These ranges apply each signal each differential pair. Note: silicon revisions prior this reserved.
PIXS
Z0CONT
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Description
65101 Description (Cont'd)
Name DCLK DCKINV Type Description Display Enable. Pixel Clock Output generated from RXC+ /RXC-. panel applications, this SHFCLK panel. Panel data bits P[35:0] synchronized with pixel clock (DCLK). When PIXS P[35:24] driven output from P[23:0] bits/pixel data. When PIXS high, odd-numbered pixels output from P[35:18] evennumbered pixels output from P[17:0]. When TESTIN high, used output ring test.
DCLK polarity selection. logic level selects normal DCLK output; that output data controls synchronized rising edge DCLK (typically with panels that sample data falling edge clock). logic high level selects inverted DCLK output. This internal pull-down resistor select normal DCLK unless pulled high externally. Note: silicon revisions prior this reserved.
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Description
65101 Description (Cont'd)
Name CLT0 CLT1 CLT2 CLT3 Type Description Latch Pulse. Flat panel equivalent HSYNC. First Line Marker. Flat panel equivalent VSYNC. General output control signal General output control signal General output control signal General output control signal When BYPASS high, Display Enable (DE) signal internally routed CLT3, CLT3 unavailable general control signal BYPASS mode. Power Down mode (active low). high level indicates normal operation level indicates power down mode. During power down mode, data (P[35:0]), display enable (DE), clock (DCLK) control signals (LP, FLM, CLT[3:0]) outputs driven low, internal clock stopped analog logic powered down. This active during both normal operations test modes. Manufacturing ring test mode. level indicates normal operation high level indicates ring test mode. Power display interface output signals going into panel. This supplies power output buffers input protection devices. This must output signals output signals
TESTIN DVCC DVCC DVCC DGND DGND DGND
Power Power Power
Ground Ground pins DVCCs. Ground Ground Power Power Core VCC. These pins supply power input buffers core digital logic must
Ground Digital ground. Ground
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65100 Functional Description
65100 Functional Description
EXT_RES SUPV P[23:0] P[15:8] CLT0 CLT1 CLT2 CLT3 DEDGE CEDGE Q_CK2 BYPASS TESTIN P[23:16] TX2+ TX2DE Q_CK0 P[7:0]
Swing Control Circuit
Swing_Cont.
Encoder
TX0+ TX0-
Data Capture Logic
TX1+ TX1-
Encoder
Q_CK1
Encoder
Test Logic
CHPLL
P_CK ECK[3:0]
TXC+ TXC-
DCLK
Figure 65100 Functional Block Diagram
above drawing indicates, 65100 consists data capture logic, three encoders, three transmitters, small swing clock transmitter, charge pump PLL, swing control circuit, test logic. data capture logic catches 24-bit data P[23:0], 6-bit control signals FLM, CLT[3:0]. Data control signals latched rising falling edge DCLK depending CEDGE DEDGE signal. When DEDGE signal HIGH (LOW), data latched rising (falling) edge DCLK. When CEDGE signal HIGH (LOW), control signals latched rising (falling) edge DCLK. combinations DEDGE CEDGE signals, output signals data capture logic synchronized transmitted encoder blocks.
Each encoder receives 8-bit data, 2-bit control signals, signal. When HIGH, 8-bit data converted 10-bit coded data which DC-free transition-minimized. transition-minimized, coded data guarantees power consumption during data transmission. When LOW, 2-bit control signals converted four 10-bit control characters. Functionally, 10-bit coded data sent each transmitter. transmitter converts 10-bit coded data into serial data stream whose maximum data rate Mbps. Mbps serial data transmitted through twisted pair cable. combined structure transmitter swing control circuit guarantees small swing data transmission with normal amplitude small swing data transmission guarantees high-speed, low-power operation significantly reduces EMI.
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65100 Functional Description
Data Capture Logic
following vertical horizontal timing diagrams Flat Panel Display Graphics Controllers demonstrate relationship between controller's output data (P[23:0]) 65100's Input Clock (DCLK):
Horizontal Timing:
ACTIVE DISPLAY BLANK TIME
HSYNC DCLK DCLK IDCK P[23:0] P[23:0] D[23:0]
HORIZONTAL DISPLAYED LINE HORIZONTAL BLANK
Vertical Timing:
VSYNC
HSYNC
VERTICAL DISPLAYED FRAME VERTICAL BLANK
Data Timing:
IDCK DCLK TSDF D[23:0] P[23:0] TSDR THDR THDF
Figure 65100 Timing Diagrams
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65100 Functional Descri ption
above diagram signals shown with positive polarity. must always have positive polarity whereas other control signals (CLT0, CLT1, CLT2, CLT3) have either positive negative polarity. Display Enable (DE) signal used differentiate between "active" "non-active" (blank time) display areas. 65100 requires active high Display Enable (DE) signal. described earlier, there restriction polarity control signals; however, control signals only change during "blank" time. Pixel data P[23:0] Display Enable (DE) normally valid falling edge DCLK. Transmitter (65100) P[23:0] latched rising falling edge DCLK. data P[23:0] setup hold times must meet 65100 electrical timing specifications. Internal latching P[23:0] controlled DEDGE CEDGE pins. DEDGE controls latching data P[23:0]. When DEDGE low, P[23:0] must latched using falling edge DCLK. When DEDGE high, P[23:0] latched using rising edge DCLK. CEDGE controls latching control signals FLM, CLT0, CLT1, CLT2, CLT3. When CEDGE low, other control signals must latched using falling edge DCLK. When CEDGE high, other control signals must latched using rising edge DCLK. timing between P[23:0] with respect DCLK falling/rising edge requires close attention. Timing considerations between other control signals DCLK restrictive since panel timing requirements relaxed. most Flat Panel Display Graphics Controllers P[23:0] have same similar timing;
therefore, DEDGE CEDGE need same level. However, P[23:0] latched using rising edge DCLK latched using falling edge DCLK, then will latched half clock cycle earlier with respect P[23:0]. Subsequently, P[23:0] synchronized output data capture logic (see 65100 timing diagram previous page). Table below specifies input timing data when they latched falling edge DCLK. Table below specifies input timing data when they latched rising edge DCLK. During normal operation (TESTIN LOW), highlevel BYPASS signal indicates that input data transmitted directly transmitter, bypassing encoder block.
Bypass Encoder Mode
This mode intended test purposes only suitable driving panel end-user environment. Since transmitters designed transmit bits/DCLK, byte data bits control signals DCLK transmitted without encoding. When "Bypass Mode," delivered through transmitter that normally transmits CLT3; thus, CLT3 input needs ignored. example, bits composed P[7:0] transmitted through Channel P[15:8] CLT0 CLT1 transmitted through Channel P[23:16] CLT2 transmitted through Channel Bypass Encoder Mode, preamble sent receiver before 10-bit data transmitted. This pattern permits phase byte synchronization receiver. This mode operation useful determining reliability transmitter independent encoder. addition, this mode permits control signals change during "active" display, data change without restriction during horizontal/vertical "blank" time.
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65100 Functional Descri ption
Table Panel Data Timing Falling Edge DCLK Symbol TCKF TSDF THDF Parameter DCLK falling time P[23:0] setup time from falling edge P[23:0] hold time from falling edge Unit
Table Input Data Timing Rising Edge DCLK Symbol TCKR TSDR THDR Parameter DCLK rising time P[23:0] setup time from rising edge P[23:0] hold time from rising edge Unit
DC-Balanced Encoder
Each encoder unit encodes bits data display enable (DE) bits control signals. Three functionally identical encoders used transmit data control signals. encoder generates 10-bit DC-balanced codes. Control signals assumed change only during "blank" time when low/inactive; therefore, level control signals assumed constant during active data area when high. innovative PanelLink encoding method guarantees transition-minimized DC-free data codes support power operation guarantee DCbalancing. Four kinds special, proprietary characters used level encoding control signals include sufficient number transitions phase synchronization receiver. characters contain byte-sync information. encoding scheme supports existing future function transitionminimized data codes.
encoder generates four kinds special characters according level when LOW. From four special characters, digital receiver (65101) achieves phase byte synchronization. When high, 8-bit data converted 10-bit coded data. Adjustable Voltage Swing pull-up resistance between 65100 EXT_RES used adjust voltage swing differential signals. larger voltage swing, more reliable transmission system. result, longer cables used. However, larger voltage swing, higher power consumption 65100 65101. Adjustable Receiver Impedance order balance impedance over transmission lines between 65100 65101, control mechanism (EXT_RES) included 65101 minimize producing effects. characteristic impedance cable then needs connected between 65101 EXT_RES VCC.
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65101 Functional Description
65101 Functional Description
following figure shows 65101 functional block diagram:
PIXS RXCK Ext_Res Impedance Matching Circuit CLT3 CLT2 Sync Sync P[35:0] DCLK
Sync
Sync
DATA RECOVERY
CHANNEL SYNC
DECODER
CLT1 CLT0
PANEL INTERFLM FACE LOGIC
Sync
Sync
CHPLL
Figure 65101 Functional Block Diagram 65101 consists five blocks: Impedance Matching Circuit, Data Recovery, Channel Synchronization, Decoder, Panel Interface. required termination resistance. recommended value EXT_RES resistor which will internal VCRs Then VCR's internal termination resistors.
Impedance Matching Circuit
minimize impedance matching circuit (see next section) controls channels, each with Voltage Controlled Resistor (VCR). impedance matching circuit equalizes impedance VCRs characteristic impedance transmission lines. EXT_RES should connected through resistor, this resistor value should times desired receiver termination resistor. Internal VCR's (Voltage Controlled Resistor) controlled impedance matching circuit adjusted have resistor value equivalent
Data Recovery Block
Data Recovery Block receives small swing differential signal with maximum data rate Mbps from twin-axial cable. period horizontal vertical blank LOW), four special characters received which have sufficient number transitions guarantee phase byte synchronization. digital accomplishes phase synchronization finds frame from special characters. result, digital recovers 10-bit parallel data synchronized MHz.
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65101 Functional Description
Channel Synchronization Block
During "blanking" time, 65101 designed recover from synchronization error.
Table Toggling Results Description Normal mode DCLK runs continuously DCLK stopped (low) when
Decoder Block
Decoder Block receives 10-bit data synchronization signals from Channel Synchronization Block, then decodes data 8-bit data, 2bit control signals (Display Enable) signal.
Panel Interface Logic
panel interface logic takes output data from Decoder Block formats data output panel. decoder generates three sets data using three clocks. Because clocks distributed symmetrically, these clocks have very small skew aligned with DCLK. mentioned previously, output data format determined state PIXS pins. When PIXS DCKINV pins both low, output data from decoder latched rising edge DCLK. output data format bits DCLK P[23:0] pins. rising edge DCLK used output data control signals. following timing diagram shows relationship between DCLK output data format timing when PIXS DCKINV pins low.
Panel Interface Logic Block
Panel Interface Logic receives bits data, 6-bit control signals 3-bit signals from Decoder Block. 65101 configured modes PIXS pin: 24-bit data with bits pixel 36bit data with bits pixel). When PIXS LOW, panel interface logic generates bits data with bits pixel synchronized DCLK. When PIXS HIGH, panel interface logic generates bits data with bits pixel 32.5 DCLK. Both panel interface configurations send control signals well. modifies output data follows.
DCLK ODCK
Q[35:24] P[35:24]
Q[23:0] P[23:0]
FIRST DATA
SECOND DATA
THIRD DATA
Figure Timing Diagram: Relationship Between DCLK Output Data, PIXS DCKINV When DCKINV high, DCLK signal inverted timing relationship shown above still valid (referenced falling edges DCLK instead rising edges). When PIXS high DCKINVpin low, DCLK generated dividing this mode, output data format bits DCLK bits pixel. this configuration, least significant bits each byte
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65101 Functional Description
output data discarded (not used). first 18-bit data pins P[17:0] second 18-bit data pins P[35:18] shown below.
ODCK DCLK
Q[35:18] P[35:18]
SECOND DATA
FOURTH DATA
Q[17:0] P[17:0]
FIRST DATA
THIRD DATA
Figure Timing Diagram: Relationship Between DCLK Output Data, PIXS DCKINV High When DCKINV high, DCLK would just inverted timing relationship shown above would still valid. will modify output DCLK when (Blank Time). compatible with panels, DCLK runs continuously when tied low. compatible with STN-DD panels, DCLK inactive (low) when high low. This relationship shown timing diagrams below.
DCLK ODCK
HSYNC
Figure Timing Diagram with
DCLK ODCK
HSYNC
Figure Timing Diagram with High
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65101 Functional Description
Signal Mapping
Using Chips Technologies' Graphics Controller, CHANNEL transmits BLUE, CHANNEL transmits GREEN, CHANNEL transmits RED. Table Signal Mapping Bypass Mode
65100
CHANNEL (blue) P[7:0] P[15:8] CLT0 CLT1 P[23:16] CLT2
65101
P[7:0] P[15:8] CLT0 CLT1 P[23:16] CLT2 CLT3
CHANNEL (green)
CHANNEL (red)
Note: 65100 CLT3 unavailable general control signal transfer bypass mode since CLT3 65101 used recover
Table Signal Mapping 18/24-Bit Mode
65100
18bpp CHANNEL (blue) P[7:2] P[15:10] CLT0 CLT1 P[23:18] CLT2 CLT3 24bpp P[7:0] P[15:8] CLT0 CLT1 P[23:16] CLT2 CLT3 18bpp
65101
24bpp P[7:0] P[15:8] CLT0 CLT1 P[23:16] CLT2 CLT3
P[[7:2] P[15:10] CLT0 CLT1 P[23:18] CLT2 CLT3
CHANNEL (green)
CHANNEL (red)
Note: 18-bit mode, Graphics Controller interface 65100 same 24-bit mode; however, bits channel (color) transmitted instead bits. unused data bits low.
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65101 Functional Description
36-bit panels, following table represents sequence pixels sent from Graphics Controller 65100 transmitter 18-bit data (one pixel clock). data then transmitted 65101 receiver DC-free, transition minimized data. After data received with 65101, 18-bit pixels transferred panel clock cycle. Table Signal Mapping 36-Bit Mode
65100 (pixel
CHANNEL (blue) CHANNEL (green) CHANNEL (red) clock P[7:2] P[15:10] P[23:18] clock [N+1] P[7:2] P[15:10] P[23:18] clock [N+2] P[7:2] P[15:10] P[23:18] clock [N+3] P[7:2] P[15:10] P[23:18]
65101
clock P[5:0] P[11:6] P[17:12] clock P[23:18] P[29:24] P[35:30] clock[N+1] P[5:0] P[11:6] P[17:12] clock[N+1] P[23:18] P[29:24] P[35:30]
(pixel
CHANNEL (blue) CHANNEL (green) CHANNEL (red)
(pixel
CHANNEL (blue) CHANNEL (green) CHANNEL (red)
(pixel
CHANNEL (blue) CHANNEL (green) CHANNEL (red)
Note: 36-bit mode, frequency 65100 that 65101 clock. LSBs 8-bit decoded data will ignored generate (3x6) pixels. indicated above mapping table, first pixel (Pixel received through P[17:0] second pixel (Pixel received through P[35:18]. Similarly, evennumbered pixels received through P[17:0], odd-numbered pixels received through P[35:18]. LP/FLM transmitted through Channel CLT0/CLT1 transmitted through Channel CLT2/CLT3 transmitted through Channel
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65101 Functional Description
(Blank Page)
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7/29/96
Advance Product Information 65100/101 Subject change without notice
Electrical Specifications
Electrical Specifications
values included following tables were made available CHIPS Silicon Image, Inc. Palo Alto, Table Absolute Maximum Conditions Symbol TSTG Parameter Supply Voltage Input Voltage Output Voltage Ambient Temperature (with power applied) Storage Temperature Package Power Dissipation -0.3 -0.3 -0.3 Typica Units
Notes: Permanent device damage occur Absolute Maximum Conditions exceeded. Functional operation should restricted conditions described under Normal Operating Conditions. Table Normal Operating Conditions Symbol VCC3 VCC5 Parameter Supply Voltage Supply Voltage Ambient Temperature (with power applied) Typica 70.0 Units
Revision
7/29/96
Advance Product Information 65100/101 Subject change without notice
Electrical Specifications
following table values refers normal operating conditions unless specified otherwise. Table CMOS Signals Characteristics Symbol Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input Clamp Voltage Input Current Input Leakage Current Output Short Circuit Current Conditions SUPV SUPV DVCC 3.3V DVCC 5.0V -18mA VCC, DVCC 3.3V VOUT Data VOUT 3.3V, Data VOUT Clock VOUT 3.3V, Clock DVCC 5.0V VOUT Data VOUT Data VOUT Clock VOUT Clock High Impedance Note below. Typical +/-5 VCC+0.3 VCC+0.3 Units
0.25 -1.1 +/-12 10.4 21.3 23.4 37.5 20.7
Output Leakage Current Power-down Current
-100
Notes: minimum power-down current, CMOS inputs must either GND. following three tables values refer normal operating conditions unless specified otherwise. Table Differential Receiver Specifications Symbol VEXT Parameter Voltage EXT_RES Input Dynamic Range (Detectable Differential Swing) Input Current Output High Drive Output Drive Output High Drive Output Drive Receiver Supply Current 3.3V Conditions connected VEXT SWING VCC-0.5 3.3V, 2.8V VOUT Data VOUT Data VOUT DCLK VOUT DCLK DCLK DCLK Typical VCC-0.5 Units mVp-p
IOHD IOLD IOHC IOLC ICCR
108.8
Revision
7/29/96
Advance Product Information 65100/101 Subject change without notice
Electrical Specifications
Table Differential Transmitter Specifications Symbol ICCT Parameter Differential Output Voltage High-level Output Voltage Low-level Output Voltage Output Short Circuit Current Output Tri-state Current Transmitter Supply Current 3.3V Table Characteristics Symbol SLHT SHLT DLHT Parameter Small Swing Low-to-High Transition Time Small Swing High-to-Low Transition Time Digital Output Low-to-High Transition Time Conditions DVCC Data DVCC Data DVCC Clock DVCC Clock DVCC Data DVCC Data DVCC Clock DVCC Clock Typical Units Conditions VOUT VOUT DCLK DCLK Typical 3.25 2.78 2.97 Units
77.5
0.4T 0.4T 0.4T 0.4T
0.5T 0.5T
0.6T 0.6T
DHLT
Digital Output High-to-Low Transition Time
TCIP TCIH TCIL TSDF THDF TSDR THDR RCIP RCIH RCIL TOCKDER TOCKDEF
IDCK Cycle Time IDCK High Time IDCK Time Data Setup Time from IDCK falling edge Data Hold Time from IDCK falling edge Data Setup Time from IDCK rising edge Data Hold Time from IDCK rising edge DCLK Cycle Time DCLK High Time DCLK Time Time delay from rising edge DCLK data receiver Time delay from falling edge DCLK data Receiver IDCK jitter requirement
CEDGE DEDGE CEDGE DEDGE CEDGE DEDGE CEDGE DEDGE
DCKINV= DCKINV=
0.5T 0.5T
0.6T 0.6T
Revision
7/29/96
Advance Product Information 65100/101 Subject change without notice
Electrical Specifications
(Blank Page)
Revision
7/29/96
Advance Product Information 65100/101 Subject change without notice
Timing Diagrams
Timing Diagrams
SLHT
SHLT
Figure Transmitter Small Signal Transition Times
65101 SiI101
15pF
DLHT
DHLT
Figure Receiver Digital Output Transition Times
TCIP RCIP TCIH RCIH
TCIL RCIL
Figure Transmitter/Receiver Clock Cycle/High/Low Times
Revision
7/29/96
Advance Product Information 65100/101 Subject change without notice
Timing Diagrams
DCLK IDCK
TSDF THDF TSDR THDR
P[23:0] D[23:0]
Figure Data Setup/Hold Times from Falling/Rising Edge DCLK Transmitter (65100)
ODCK DCLK TOCKDER Q[35:0] P[35:0]
Figure Time Delay from Rising Edge DCLK Data Receiver (65101)
DCLK ODCK
TOCKDEF
P[35:0] Q[35:0]
Figure Time Delay from Falling Edge DCLK Data Receiver (65101)
Revision
7/29/96
Advance Product Information 65100/101 Subject change without notice
Mechanical Specifications
Mechanical Specifications
Lead Length Lead Width 0.22 Lead Pitch 0.50
MARKING
Body Size 10.00 1.20
CHIPS Part Revision Date Assembly Code
T65100
YYWW
BOTTOM MARKING
Vendor Code
TMXXXXX
XXXXXXX.X
Body Thickness 1.00 Clearance Body Size 10.00 Footprint 12.00
Figure Transmitter (65100) 64-Pin Plastic TQFP
Revision
7/29/96
Advance Product Information 65100/101 Subject change without notice
Footprint 12.00
Mechanical Specifications
Lead Length Lead Width 0.22 Lead Pitch 0.50
MARKING
Body Size 12.00 1.20
CHIPS Part Revision Date Assembly Code
T65101
YYWW
BOTTOM MARKING
Vendor Code
TMXXXXX
XXXXX.X
Body Thickness 1.00 Clearance Body Size 12.00 Footprint 14.00
Figure Receiver (65101) 80-Pin Plastic TQFP
Revision
7/29/96
Advance Product Information 65100/101 Subject change without notice
Footprint 14.00
Chips Technologies, Inc. 2950 Zanker Road Jose, California 95134 Phone: 408-434-0600 FAX: 408-894-2080
65100/101 PanelLink Technology High Speed Transmitter Receiver Publication No.: API33.4 Stock No.: 011033-004 Revision No.: Date: 7/29/96 Title:

PanelLinkTechnology High Speed Transmitter Receiver Data Sheet Re

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