LC72133M, 72133V Frequency Synthesizer Electronic Tuning Ove
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Ordering number EN5427A
LC72133M, 72133V
Frequency Synthesizer Electronic Tuning
Overview
LC72133M LC72133V phase-locked loop frequency synthesizer circuits radio tuners. supports low-voltage (2.7 operation implement high-performance AM/FM tuners easily.
Package Dimensions
unit: 3036B-MFP20
[LC72133M]
Functions
High speed programmable dividers FMIN: .pulse swallower (built-in divide-by-two prescaler), .pulse swallower (built-in divide-by-two prescaler), AMIN: .pulse swallower .direct division counter IFIN: .AM/FM counter Reference frequencies Twelve selectable frequencies (4.5 crystal) 3.125, 6.25, 12.5, Phase comparator Dead zone control Unlock detection circuit Deadlock clear circuit Built-in transistor forming active low-pass filter ports Dedicated output ports: Input output ports: Support clock time base output Serial data Support format communication with system controller. Operating ranges Supply voltage.2.7 Operating temperature.-20 +70°C Package MFP20 SSOP20
SANYO: MFP20
unit: 3179A-SSOP20
[LC72133V]
SANYO: SSOP20
trademark SANYO ELECTRIC CO., LTD. SANYO's original format addresses controlled SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
22897HA (OT)/63196HA (OT) 5427-1/22
LC72133M, 72133V Assignment
Block Diagram
5427-2/22
LC72133M, 72133V
Specifications
Absolute Maximum Ratings 25°C,
Parameter Supply voltage Symbol VIN1 Maximum input voltage VIN2 VIN3 Maximum output voltage Maximum output current Allowable power dissipation Operating temperature Storage temperature Topr Tstg XIN, FMIN, AMIN, IFIN IO1, XOUT, BO4, IO1, IO2, AOUT AOUT, BO4, IO1, 70°C: LC72133M 70°C: LC72133V Pins Ratings -0.3 +5.5 -0.3 +5.5 -0.3 -0.3 -0.3 +5.5 -0.3 -0.3 +125 Unit
Allowable Operating Ranges +70°C,
Parameter Supply voltage Input high-level voltage Input low-level voltage Output voltage fIN1 fIN2-1 fIN2-2 Input frequency fIN2-3 fIN3 fIN4 fIN5 VIN1 VIN2-1 VIN2-2 Input amplitude VIN3 VIN4 VIN5-1 VIN5-2 Supported crystals Xtal Symbol VIH1 VIH2 IO1, IO1, BO4, IO1, IO2, AOUT FMIN FMIN FMIN AMIN AMIN IFIN FMIN FMIN AMIN AMIN IFIN IFIN XIN, XOUT VIN1 VIN2-1 VIN2-2 VIN2-1, VIN3, VIN4, VIN5 fIN1 fIN2-1, fIN2-3 fIN2-2 fIN3, fIN4, fIN5, fIN6, Pins Conditions Unit mVrms mVrms mVrms mVrms mVrms mVrms mVrms
Note: Recommended crystal oscillator values: (For crystal) (For crystal) <Sample Oscillator Circuit> Crystal oscillator: HC-49/U (manufactured Kinseki, Ltd.), circuit constants crystal oscillator circuit depend crystal used, printed circuit board pattern, other items. Therefore recommend consulting with manufacturer crystal evaluation reliability.
5427-3/22
LC72133M, 72133V Electrical Characteristics Allowable Operating Ranges +70°C,
Parameter Symbol Built-in feedback resistance Built-in pull-down resistor Hysteresis Output high level voltage Rpd1 Rpd2 VHIS VOH1 VOL1 VOL2 Output level voltage VOL3 VOL4 VOL5 IIH1 IIH2 Input high level current IIH3 IIH4 IIH5 IIH6 IIL1 IIL2 Input level current IIL3 IIL4 IIL5 IIL6 Output leakage current High level three-state leakage current level three-state leakage current Input capacitance IOFF1 IOFF2 IOFFH IOFFL IDD1 FMIN AMIN IFIN FMIN AMIN IO1, 0.01 0.01 Xtal MHz, fIN2 MHz, VIN2 mVrms block stopped (PLL INHIBIT), Xtal oscillator operating (Xtal MHz) block stopped Xtal oscillator stopped 0.25 0.75 0.25 1.25 Pins Conditions Unit
BO4, IO1, AOUT IO1, FMIN, AMIN IFIN IO1, FMIN, AMIN IFIN BO4, AOUT, IO1, FMIN
Current drain
IDD2
IDD3
5427-4/22
LC72133M, 72133V Functions
Symbol Type Functions Circuit configuration
XOUT
Xtal
Crystal resonator connection (4.5/7.2 MHz)
FMIN
Local oscillator signal input
FMIN selected when serial data input input frequency range from MHz. input signal passes through internal divide-bytwo prescaler input swallow counter. divisor range 65535. However, since signal passed through divide-by-two prescaler, actual divisor twice value.
Operating FMIN input frequency conditions Operating power- supply voltage Operating input levels mVrms mVrms mVrms
AMIN
Local oscillator signal input
AMIN selected when serial data input When serial data input input frequency range MHz. signal directly input swallow counter. divisor range 65535, divisor used will value set. When serial data input input frequency range MHz. signal directly input 12-bit programmable divider. divisor range 4095, divisor used will value set.
Chip enable
this high when inputting (DI) outputting (DO) serial data.
Clock
Used synchronization clock when inputting (DI) outputting (DO) serial data.
Data input
Inputs serial data transferred from controller LC72133.
Data output
Outputs serial data transferred from LC72133 controller. content output data determined serial data DOC0 DOC2.
Power supply
LC72133 power supply (VDD power reset circuit operates when power first applied.
Continued next page. 5427-5/22
LC72133M, 72133V
Continued from preceding page.
Symbol
Type
Functions
Circuit configuration
Ground
LC72133 ground
Output port
Dedicated output pins output states determined bits serial data. Data: open, time base signal output from pin. (When serial data Care required when using pin, since higher impedance than other output ports (pins BO4). data (open) state selected after power-on reset.
port
dual-use pins direction (input output) determined bits IOC1 IOC2 serial data. Data: input port, output port When specified input ports: state input transmitted controller over pin. Input state: data value high data value When specified output ports: output states determined bits serial data. Data: open, These pins function input pins following power reset.
Charge pump output
charge pump output When frequency generated dividing local oscillator frequency higher than reference frequency, high level output from pin. Similarly, when that frequency lower, level output. goes high impedance state when frequencies match.
AOUT
amplifier transistor
n-channel transistor used active low-pass filter.
IFIN
counter
Accepts input frequency range MHz. input signal directly transmitted counter. result output starting counter using pin. Four measurement periods supported:
5427-6/22
LC72133M, 72133V Serial Data Methods LC72133 inputs outputs data using Sanyo (computer control bus) audio serial format. This adopts 8-bit address format CCB.
mode Address Function
(82)
Control data input mode (serial data input) data bits input. Control Data (serial data input) Structure" item details meaning input data.
(92)
Control data input mode (serial data input) data bits input. Control Data (serial data input) Structure" item details meaning input data.
(A2)
Data output mode (serial data output) number bits output equal number clock cycles. Output Data (Serial Data Output) Structure" item details meaning output data.
5427-7/22
LC72133M, 72133V Control Data (Serial Data Input) Structure Mode
Mode
5427-8/22
LC72133M, 72133V Control Data Functions
Control block/data Functions Related data
Programmable divider data Data that sets programmable divider. binary value which MSB. changes depending SNS. don't care) DVS, Divisor setting 65535 65535 4095 Actual divisor Twice value setting value setting value setting
Note: ignored when LSB. Selects signal input (AMIN FMIN) programmable divider, switches input frequency range. don't care) Input FMIN AMIN Input frequency range
AMIN Note: "Programmable Divider" item more information. Reference divider data Reference frequency (fref) selection data. Reference frequency (kHz) 12.5 6.25 3.125 3.125 INHIBIT Xtal STOP
INHIBIT Note: INHIBIT programmable divider block counter block stopped, FMIN, AMIN, IFIN pins pull-down state (ground), charge pump goes high impedance state. Crystal resonator selection frequency selected after power-on reset. counter measurement start data Counter start Counter reset Determines counter measurement period. port specification data IOC1, IOC2 Output port data BO4, IO1, Measurement time (ms) Wait time (ms)
counter control data GT0,
Note: Counter" item more information. Specifies direction bidirectional pins IO2. Data: input mode, output mode Data that determines output from BO4, output ports Data: open, data (open) state selected after power-on reset. IOC1 IOC2
Continued next page. 5427-9/22
LC72133M, 72133V
Continued from preceding page.
Control block/data control data DOC0, DOC1, DOC2 Functions Data that determines output DOC2 DOC1 DOC0 state Open when unlock state detected end-UC*1 Open Open state*2 state*2 Open Related data
open state selected after power-on reset. Note: end-UC: Check counter measurement completion UL0, UL1, CTE, IOC1, IOC2
When end-UC counter started (i.e., when changed from zero one), automatically goes open state. When counter measurement completes, goes indicate measurement completion state. Depending serial data (CE: high) goes open state. Goes open state specified output port. Caution: state during data input period mode period with high) will open, regardless state control data (DOC0 DOC2). Also, during data output period mode period with high) will output contents internal serial data synchronization with signal, regardless state control data (DOC0 DOC2). Unlock detection data UL0, Selects phase error detection width checking lock. phase error excess specified detection width seen unlocked state. detection width Stopped ±0.55 ±1.11 Open output directly extended extended Detector output DOC0, DOC1, DOC2
Note: unlocked state goes serial data becomes zero. Phase comparator control data DZ0, Controls phase comparator dead zone. Dead zone mode
Dead zone widths: Clock time base Charge pump control data Setting causes duty clock time base signal output from pin. (BO1 data invalid this mode.) Forcibly controls charge pump output. (10) Normal operation Forced Charge pump output
Note: deadlock occurs control voltage (Vtune) going zero oscillator stopping, deadlock cleared forcing charge pump output setting Vtune VCC. (This deadlock clearing circuit.)
Continued next page. 5427-10/22
LC72133M, 72133V
Continued from preceding page.
(11) Control block/data counter control data test data TEST TEST (12) Functions Note that this value zero system enters input sensitivity degradation mode, sensitivity reduced rms. Counter Operation" item details. test data TEST0 TEST1 These values must TEST2 These test data automatically after power-on reset. (13) Don't care. This data must Related data
Output Data (Serial Data Output) Mode
Output Data
Control block/data port data Functions Latched from states ports. These values follow states regardless input output setting. Data latched point where circuit enters data output mode (OUT mode). state state unlock data counter binary data High: Low: UL0, CTE, GT0, Related data
IOC1, IOC2
Latched from state unlock detection circuit. Unlocked Locked detection stopped mode Latched from value counter (20-bit binary counter). binary counter binary counter
5427-11/22
LC72133M, 72133V Serial Data Input (IN1/IN2) tSU, tHD, tEL, tES, 0.75 0.75
Serial Data Output (OUT) tSU, tHD, tEL, tES, 0.75 tDC, 0.35
Note: Since n-channel open-drain circuit, time data change (tDC tDH) will differ depending value pull-up resistor printed circuit, board capacitance.
5427-12/22
LC72133M, 72133V
Serial Data Timing
Parameter Data setup time Data hold time Clock low-level time Clock high-level time wait time setup time hold time Data latch change time
Symbol
Pins
Conditions
0.75 0.75 0.75 0.75 0.75 0.75 0.75
Unit
0.75 Differs depending value pull-up resistor printed circuit board capacitances.
Data output time
0.35
5427-13/22
LC72133M, 72133V Programmable Divider Structure
Input FMIN AMIN AMIN
divisor 65535 65535 4095
Actual divisor: Twice value value value
Input frequency range (MHz)
Note: Don't care.
Programmable Divider Calculation Examples steps (DVS FMIN selected) 80.0 -10.7 MHz) 69.3 fref 69.3 VCO) (fref) (FMIN: divide-by-two prescaler) 1386 056A (HEX)
steps (DVS AMIN high speed side selected) 21.75 +450 kHz) 22.20 fref 22.2 VCO) (fref) 4440 1158 (HEX)
steps (DVS AMIN low-speed side selected) 1000 +450 kHz) 1450 fref 1450 VCO) (fref) (HEX)
5427-14/22
LC72133M, 72133V Counter Structure LC72133 counter 20-bit binary counter. result, i.e., counter's MSB, read serially from pin.
Measurement time Measurement period (GT) (ms) Wait time (twu) (ms)
frequency (Fc) measured determining many pulses were input counter specified measurement period, Count value (number pulses)
Counter Frequency Calculation Examples When measurement period (GT) count 53980 hexadecimal (342400 decimal): frequency (Fc) 342400 10.7
When measurement period (GT) count hexadecimal (3600 decimal): frequency (Fc) 3600
5427-15/22
LC72133M, 72133V Counter Operation
Before starting count, counter must reset advance setting serial data count started changing serial data from serial data latched LC72133 when dropped from high low. signal must supplied IFIN period between point goes wait time latest. Next, value counter measurement period must read during period that This because counter reset when Note: When operating counter, control microprocessor must first check state IF-IC (station detect) signal only after determining that signal present turn buffer output execute count operation. Autosearch techniques that only counter recommended, since possible buffer leakage output cause incorrect stops points where there station. IFIN minimum input sensitivity standard
(MHz) Normal mode Degradation mode mVrms (0.5 mVrms) mVrms mVrms) mVrms mVrms mVrms mVrms) mVrms mVrms)
Note: Values parentheses actual performance values presented reference data.
5427-16/22
LC72133M, 72133V Unlock Detection Timing Unlock Detection Determination Timing Unlocked state detection performed reference frequency (fref) period (interval). Therefore, principle, unlock determination requires time longer than period reference frequency. However, immediately after changing divisor (frequency) unlock detection must performed after waiting least periods reference frequency.
Figure Unlocked State Detection Timing example, fref kHz, i.e., period after changing divisor system must wait least before checking unlocked state.
Figure Circuit Structure
5427-17/22
LC72133M, 72133V Unlock Detection Software
Figure Unlocked State Data Output Using Serial Data Output LC72133, once unlocked state occurs, unlocked state serial data (UL) will reset until data input output) operation performed. data output point Figure although frequency stabilized (locked), since data output been performed since divisor changed unlocked state data remains unlocked state. result, even though frequency stabilized (locked), system remains (from standpoint data) unlocked state. Therefore, unlocked state data acquired data output which occurs immediately after divisor changed, should treated dummy data output ignored. second data output (data output following outputs valid data.
Locked State Determination Flowchart Directly Outputting Unlocked State Data from (Set control data) Since locking state (high locked, unlocked) output directly from pin, dummy data processing described section above required. After changing divisor locking state checked after waiting least reference frequency periods.
5427-18/22
LC72133M, 72133V Clock Time Base Usage Notes pull-up resistor used clock time base output (BO1) should least Also, prevent chattering recommend using Schmitt input controller (microprocessor) that receives this signal. This prevent degrading characteristics when loop filter formed using built-in low-pass filter transistor. Since clock time base output low-pass filter have common ground internal necessary minimize time base output current fluctuations suppress their influence low-pass filter.
Other Items Notes Phase Comparator Dead Zone
Dead zone mode Charge pump ON/ON ON/ON OFF/OFF OFF/OFF Dead zone
Since correction pulses output from charge pump even locked when charge pump ON/ON state, loop easily become unstable. This point requires special care when designing application circuits. following problems occur ON/ON state. Side band generation reference frequency leakage Side band generation both correction pulse envelope frequency leakage Schemes which dead zone present (OFF/OFF) have good loop stability, have problem that acquiring high ratio difficult. other hand, although easy acquire high ratio with schemes which there dead zone, difficult achieve high loop stability. Therefore, effective select DZB, which have dead zone, applications which require ratio excess which increased stereo pilot margin desired. other hand, recommend selecting DZD, which provide dead zone, applications which require such high signal-to-noise ratio which either stereo used adequate stereo pilot margin achieved.
5427-19/22
LC72133M, 72133V Dead Zone phase comparator compares reference frequency (fr) shown Figure Although characteristics this circuit (see Figure such that output voltage proportional phase difference (line region (the dead zone) which possible compare small phase differences occurs actual internal circuit delays other factors (line dead zone small possible desirable products that must provide high ratio. However, since larger dead zone makes this circuit easier use, larger dead zone appropriate popularlypriced products. This because possible signals leak from mixer modulate popularly-priced products presence strong inputs. When dead zone narrow, circuit outputs correction pulses this output further modulate generate beat frequencies with signal.
Figure
Figure
Notes FMIN, AMIN, IFIN Pins Coupling capacitors must placed close possible their respective pin. capacitance about desirable. particular, capacitance 1000 over used pin, time reach bias level will increase incorrect counting occur relationship with wait time. Notes Counting must used conjunction with counting time When using counting, always implement counting having microprocessor determine presence IF-IC (station detect) signal turn counter buffer only signal present. Schemes which auto-searches performed with only counting recommended, since they stop points where there signal leakage output from counter buffer. Usage Techniques addition data output mode times, also used check counter count completion unlock detection output. Also, input state output unchanged through input controller. Power Supply Pins capacitor least 2000 must inserted between power supply pins noise exclusion. This capacitor must placed close possible pins.
5427-20/22
LC72133M, 72133V States After Power Reset
Application System Example
No.5427-21/22
LC72133M, 72133V
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information February, 1997. Specifications information herein subject change without notice. No.5427-22/22
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