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AN1271 (Motorola Order Number) 12/95
PowerPC Microprocessor AD1848 CODEC Interface
This document describes interface Analog Devices SoundPort® Stereo CODEC (AD1848) PowerPC local bus. AD1848 integrates audio data conversion control functions into single integrated circuit. intended provide complete, single-chip audio solution business audio multimedia applications provides direct interface Industry Standard Architecture (ISA) bus. AD1848, which supports Microsoft Windows Sound System, currently widely used throughout personal computer industry. this document, term "60x" used denote 32-bit microprocessor from PowerPC architecture family. PowerPC processors implement PowerPC architecture specified 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types bits, floating-point data types bits (single-precision double-precision). PowerPC family microprocessors high performance, RISC processors that conform PowerPC architectural specifications. With on-chip caches, superscalar operation, powerful instruction set, high-operating frequencies, this family general-purpose microprocessors used perform signal processing functions. addition, PowerPC microprocessors also have very similar system buses allowing design generic interface logic. local CODEC interface (LCI), used with PowerPC 601, PowerPC 603, PowerPC 604microprocessors.
CODEC Interface
PowerPC name PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC trademarks International Business Machines Corporation used Motorola under license from International Business Machines Corporation. SoundPort registered trademark Analogue Devices, Inc. Microsoft Windows Sound System trademark Microsoft Corporation. This document contains information product under development Motorola. Motorola reserves right change discontinue this product without notice.
Motorola Inc. 1995. rights reserved.
Figure provides block diagram PowerPC AD1848 interface.
PowerPC
SYSCLK/PCLK_EN A0-A3 TT1, HRESET TBST AACK
Interrupt Controller
IRQ1-IRQ3
AD1848
PWRDWN PDAK CDAK PDRQ CDRQ
control DH0-DH7 control DH8-DH15 A27, 74F646 A0-A1 74F646 D0-D7
Figure PowerPC AD1848 Interface Block Diagram
AD1848's system interface allows near-glueless interface solution ISA-bus based systems. There however, number market areas (for example, games video-on-demand) which non-ISA based systems required deliver high quality audio. This document describes possible PowerPC-based solution these market areas.
Part Interface Issues
AD1848 CODEC features sets handshake lines that enable direct-memory access (DMA) data transfers with host computer bus. addition, CODEC supports programmed (PIO) cycles both control register accesses also data transfers systems that lack capability. advantage PIO-cycle-only interface simplicity; disadvantage that software polling CODEC required perform data transfers. Although interface described here intended PowerPC systems with local controller, designed work with CODEC's dual-channel mode. supports this configuration converting each assertion AD1848 request signal into interrupt request translating PowerPC accesses specific memory areas into AD1848 cycles. When implemented efficiently, this emulation reduces bandwidth required service CODEC. This represents important feature local-bus design. addition CODEC's CDRQ PDRQ lines, AD1848K's output also used generate interrupt PowerPC processor. PowerPC devices supported design only have general-purpose interrupt input, this design AD1848 provides three sources, interrupt controller required combine signals enable system determine cause interrupt. number different types transfers supported AD1848, ranging from 8-bit mono cycles 16-bit stereo cycles. Note that, implement this interface using MACH210 device, 8bit mono transfers supported. limiting factor here number product terms generated master state machine. however, suitable logic device used, 8-bit mono capability easily
PowerPC Microprocessor AD1848 CODEC Interface
incorporated. state machine shown Figure indicates dashed lines) extra transition paths required support 8-bit mono cycles. single-channel mode allows AD1848K used systems with only single channel. dual-channel mode been supported preference single-channel mode former facilitates simultaneous playback capture virtually simple implement.
Count
Assert Read Strobe
Negate Read Strobe
Count Count Latch Data
Assert Read Strobe
Latch Data
Count
Negate Read Strobe
Read Cycles
8-bit Mono Support (Not Implemented) CODEC Read
Wait (>66MHz)
Count
Negate Chip Select
Assert Chip Select
Wait
Count
Disable Outputs
Assert Chip Select/Latch Data
CODEC Write
Enable Output2 PIO) Output1 DMA)
Reset asserted CODEC Access CODEC Access
Negate Write Strobe
Write Access
Wait (>66MHz)
Count
Assert Write Strobe
8-bit Mono Support (Not Implemented)
Assert Write Strobe
Count
Count
Negate Write Strobe
Enable Output2
Count
Disable Output1
Figure State Machine CODEC_sm
AD1848 designed little-endian systems which least-significant byte multi-byte data item (that byte occupying lowest memory address) transferred first. addition their default big-endian operating mode, PowerPC microprocessors also support little-endian mode. Since this littleendian mode changes physical address data items rather than their internal byte order, actually support both PowerPC byte-ordering conventions (the address modification depends width addressed item. Only three least-significant address lines affected. Addresses shown based
PowerPC Microprocessor AD1848 CODEC Interface
access data width specified Table However, since physical address space occupied CODEC fixed hardware, different logical addresses required big- little-endian modes. Table shows physical addresses AD1848 registers, space, LCI-control areas. also provides logical addresses (assuming PowerPC address translation disabled) that will generate appropriate physical addresses both modes. Since, little-endian mode, physical address output PowerPC microprocessor depends width addressed data item, accesses must conform widths shown final column table. addresses shown Table reveal, through number unconditional terms, that majority PowerPC address lines used selection CODEC registers, space control locations. example, access region $6000 0000 $6FFF FFFF will cause AD1848's PWRDWN line asserted (driven low). PWRDWN will also asserted HRESET asserted. both these cases, PWRDWN signal will only negated access region $7000 0000 $7FFF FFFF. Table also shows that microprocessor accesses h4xxx xxxx converted into AD1848 cycles. Half-word loads from h4xxx xx00 emulate stereo read/capture cycles half-word stores emulate stereo write/playback cycles. seen Figure CODEC processor data buses connected 8-bit transceiver/registers. order emulate 16-bit stereo cycle, which bits data transferred, processor must perform accesses. From CODEC's perspective, these accesses must sequential. processor attempts another PIO/DMA cycle interval between 16-bit stereo accesses, terminates cycle asserting TEA. Furthermore, although state machine implementation shown Figure does support 8-bit mono cycles, design easily modified support these. this case, Table indicates appropriate address data width accesses.
Table Address
CODEC Registers/Interface Control Locations Indexed address register Indexed data register Status register data register CODEC DMA(8-/16-bit stereo) CODEC DMA(8-bit mono) CODEC power down (assert) CODEC power down (negate) PowerPC Physical Address $5xxx xx00 $5xxx xx08 $5xxx xx10 $5xxx xx18 $4xxx xxx0 $4xxx xxx1 $6xxx xxxx $7xxx xxxx Big-Endian Logical Address $5xxx xx00 $5xxx xx08 $5xxx xx10 $5xxx xx18 $4xxx xxx0 $4xxx xxx1 $6xxx xxxx $7xxx xxxx Little-Endian Logical Address $5xxx xx07 $5xxx xx0F $5xxx xx17 $5xxx xx1F $4xxx xxx6 $4xxx xxx6 $6xxx xxxx $7xxx xxxx Access Data Width Byte Byte Byte Byte Half-word Byte width width
PowerPC Microprocessor AD1848 CODEC Interface
Part Frequency Operation
Since controlled state machines clocked PowerPC 60x's frequency, work over wide range microprocessor's clock frequencies. order generate signals relatively slower CODEC interface, employs state machine CODEC_time (see Figure serve counter/ timer. CODEC timing intervals generated counting appropriate number PowerPC clocks. Since changing microprocessor's clock frequency proportional effect timing generated LCI, longer counts generally required higher processor speeds. However, since counter actually PLD-based state machine, count values cannot changed dynamically. maximum frequency operation therefore limited values PLD-compile time. over range frequencies, count values used must reflect maximum operating speed required. (The interface will still work lower frequencies will lose some efficiency.) maximum frequency also determined type data transceivers used, speed MACH210, PowerPC family member. IDT74FCT162646 transceivers used with 7-nanosecond (ns) MACH210, operate clock frequency with with 603.
Reset !Reset
!Read Delay Cycle !Write Delay Cycle !Reset
Reset
(RD8 WR9) Reset
!(RD8 #WR8 WR9) !Reset
Figure State Machine CODEC_Time
PowerPC Microprocessor AD1848 CODEC Interface
Table shows relationship between state machines, CODEC buffer control lines AD1848 timing parameters.
Table CODEC Latch Control Control Logic
STATE Read Read Write Assert Wait action Assert Write Negate Write Negate Store Enable action Disable Clocks Clocks Clocks tSTW tCSHD/TSUDK2 tCSHD tCSSU Assert CDAK Wait action Assert Read Negate Read Assert Read Negate Read Negate CDAK H(L) H(L) H(L) Idle Change action Store Store Enable Disable Clocks Clocks tDKHDb tSUDK1/tBWND Clocks Clocks tBWND tSTW Clocks tDKSU tDKSU@>66 tSTW Assert Wait action Assert Read Negate Read Negate Idle high action Store Enable Disable 24,5 Clocks Clocks tCSHD/tSUDK2 tCSHD Clocks tSTW tCSSU CODEC ACTION CDAK PDAK LATCH ACTION DURATION PARAMETER
PowerPC Microprocessor AD1848 CODEC Interface
Table CODEC Latch Control Control Logic (Continued)
STATE Write Idle Assert PDAK Wait action Assert Write Negate Write Assert Write Negate Write Negate PDAK H(L) H(L) H(L) Idle Store Enable action Disable Enable Disable Clocks Clocks Clocks tSTW tDKHDb tSUDK1/tBWND Clocks Clocks tSTW tBWND CODEC ACTION CDAK PDAK LATCH ACTION DURATION PARAMETER
Notes: State refers state before rising edge clock, indicates that output follows clock rising edge Parameter refers AD1848 timing parameters indicates digital indicates digital Enable/Disable indicates enable/disable outputs latch [IC3 schematics] Enable/Disable indicates enable/disable outputs latch [IC4 schematics] indicates alternative state dependent previous CODEC access Store indicates store data latch [IC3/4]
Part Design Description
interface control logic, shown Figure implemented using MACH210 device (refer Part "IC2 Equations List"). This device implements logic required convert PowerPC transactions into AD1848-compatible cycles. decodes CODEC accesses, drives CODEC data latch inputs generates appropriate response PowerPC microprocessor AACK, lines. design features state machines shown Figure CODEC_time used generate AD1848 timing intervals from fast PowerPC SYSCLK CODEC_sm, shown Figure provides main control CODEC transactions. Figure schematic which shows connectivity required implement interface. Based largely state CODEC_sm, drives AD1848 control lines affect either transactions. also drives transceiver control lines ensure that data read written correctly. 74F646 octal transceivers/registers (IC3, IC4) double density equivalent such IDT74FCT162646 used. reset, MACH210 programmed assert CODEC's PWRDWN line; this negated (and asserted) PowerPC access specific area memory map. Finally, MACH device used generate active interrupt signals (IRQ2, IRQ3) from IC1's PDRQ CDRQ outputs. remaining circuitry schematics made either general-support circuitry AD1848 (IC1), buffering microphone input, line outputs, line input (all stereo). Refer PowerPC RISC Microprocessors User's Manual (MPC601UM/AD), PowerPC RISC Microprocessors User's Manual (MPC603UM/AD), Analogue Devices Parallel-Port 16-Bit SoundPort® Stereo CODEC AD1848K data sheet (Rev. 0.1) more information.
PowerPC Microprocessor AD1848 CODEC Interface
AACK
TT0-TT4 A0-A31 TBST
POWERPC MICROPROCESSOR
LATCH1
MACH210
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 CLK0/I2 I/O15 I/O16 I/O17 CLK1/I5 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
CPAB CPBA
F646
CDRQ PRDQ
HRESET
SYSCLK
LATCH2
L_OUT R_OUT XCTL0 XCTL1 DBDIR DBEN F646 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
CPAB CPBA
PWRDWN ADR1 CYPRESS ADR0 AD1848 CDAK PDAK XTAL1I XTAL1O
XTAL2I
XTAL2O
DH0-DH15
R_FILT R_LINE R_MIC L_MIC L_LINE L_FILT VRE/2_25 VREF_F/BYPASS L_AUX2 L_AUX1 R_AUX1 R_AUX2 GNDA GNDD
HST_IRQ
PD_IRQ INTERRUPT CONTROLLER
CD_IRQ
other circuitry such power supply connections, analogue shown this schematic.
Figure PowerPC Local CODEC Interface Schematic
PowerPC Microprocessor AD1848 CODEC Interface
Part Equations List
Name Partno Date Revision Designer Company Assembly Location Device FORMAT cmach5; p00001; 08/01/95; 1.0; Colin MacDonald; Motorola Copyright (C); CoreX; IC1; Mach210;
DESCRIPTION: State Machine CODEC Control History: CMACH2 version MACH devices CMACH4 generates CODEC_sel Could improve solution further latching processor signals giving earlier writes CMACH5 uses e_tea allow coincident aack Improved timing little WR8T5->WR8T0 Assignments clk; !g2; tt1; tt3; !reset; int; !ts; !tbst; !pwrdwn; !hst_irq; !aack; !tea; !ta; pdrq; cdrq; !cs_; !wr_; !g1; !pdak; !cdak; cp2; cp1; dir;
PowerPC clock 74F646 Latch1 enable address address address address line line hreset AD1848 host (IN) transfer start burst signal CODEC PWRDWN input (OUT) generated (OUT) address acknowledge (OUT) transfer error (OUT) transfer acknowledge (OUT) AD1848 PDRQ output AD1848 PDRQ output AD1848 input AD1848 input 74F646 Latch1 enable AD1848 pdak input AD1848 cdak input 74F646 Latch2 clock 74F646 Latch1 clock 74F646 Latch1
PowerPC Microprocessor AD1848 CODEC Interface
!rd_; !pd_irq; !cd_irq;
AD1848 input IRQ2 from AD1848 PDRQ IRQ3 from AD1848 CDRQ
Pinnode Assignments Pinnode time0; time/state Pinnode time1; time/state Pinnode time3; time/state Pinnode time2; time/state Pinnode state4; time/state Pinnode state0; time/state Pinnode state2; time/state Pinnode state1; time/state Pinnode state3; time/state Pinnode !e_ta; early Pinnode !cdc_sel; CODEC chip select Pinnode !e_tea; Early central cntl GROUP BLOCK_A GROUP BLOCK_D g1,cdc_sel;
Field CODEC_sm [state4.0]; $define 'b'00000 $define 'b'00001 $define 'b'00010 $define 'b'00011 $define 'b'00100 $define 'b'00101 $define 'b'00110 $define 'b'00111 $define 'b'01000 $define 'b'01001 $define 'b'01010 $define 'b'01011 extra wait state >66MHz operation $define $define $define $define $define $define $define $define $define $define $define 'b'10001 'b'10010 'b'10011 'b'10100 'b'10101 'b'10110 'b'10111 'b'11000 'b'11001 'b'11010 'b'11011
extra wait state >66MHz operation
Field CODEC_time [time3.0]; $define 'b'0000 $define 'b'0001 $define 'b'0010 $define 'b'0011 $define 'b'0100 $define 'b'0101 $define 'b'0110
PowerPC Microprocessor AD1848 CODEC Interface
$define $define $define $define $define $define RD10 IDLE XTRD WRTN XTWR
'b'0111 'b'1000 'b'1001 'b'1010 'b'1011 'b'1100 CODEC_sm:R01; CODEC_sm:R02; CODEC_sm:R03; CODEC_sm:R04; CODEC_sm:R05; CODEC_sm:R06; CODEC_sm:R07; CODEC_sm:R08; CODEC_sm:R09; CODEC_sm:R10; CODEC_sm:RW0; CODEC_sm:RXT; CODEC_sm:W01; CODEC_sm:W03; CODEC_sm:W04; CODEC_sm:W05; CODEC_sm:W06; CODEC_sm:W07; CODEC_sm:W08; CODEC_sm:W09; CODEC_sm:W10; CODEC_sm:WXT;
CODEC_time:T00; CODEC_time:T03; CODEC_time:T05; TM12 time3 time2; TM12 don't care time1 time0 save terms CPU_RD CPU_WR MEM_CYCLE ADD_ONLY BURST RD_DEL WR_DEL CODEC_TS CDMA_ADD PDMA_ADD PIO_ADD PDN_ADD PUP_ADD CDMA_START tt1; !tt1; tt3; !tt3; tbst; cdc_sel !a3; cdc_sel (RD3 RD9); (WR3 WR9); tt1; !tt1; !a3; CODEC_TS !ADD_ONLY !BURST CDMA_ADD;
PowerPC Microprocessor AD1848 CODEC Interface
PDMA_START PIO_START PDN_START PUP_START
CODEC_TS !ADD_ONLY !BURST PDMA_ADD; CODEC_TS !ADD_ONLY !BURST PIO_ADD; CODEC_TS !ADD_ONLY !BURST PDN_ADD; CODEC_TS !ADD_ONLY !BURST PUP_ADD;
Active enough prod terms implement hold-off Need careful with DMA3 PIO3 WRITE READ !reset; !reset; (WR1 WRTN XTWR); !WRITE;
sequenced CODEC_time present !(RD_DEL WR_DEL) !reset next T00; (RD_DEL WR_DEL) !reset next T01; reset next T12; present next T02; present next T03; present next T04; present next T05; present (RD8 WR9) !reset next T12; !(RD8 WR9) !reset next T06; reset next T12; present next T07; present next T08; present next T09; present next T10; present next T11; present next T12; present reset next T12; !reset next T00; sequence CODEC_sm present !(DMA PIO) reset (DMA CPU_RD CPU_RD) !reset (DMA CPU_WR CPU_WR) !reset present present Don't need this step <66MHz present present !TM12 TM12 present !DMA present !TM12 TM12
next RW0; next R01; next W01; next R02; next RXT; next R03; next R03; next R04; next R05; next R08; next R05; next R06;
PowerPC Microprocessor AD1848 CODEC Interface
sufficient product terms have generic state machine 8-bit mono 8-bit stereo/16-bit mono. This insufficient terms this only support 16-bit cycles Terms generic-replace existing term with: present if!TM12 TM12 cdrq TM12 !cdrq /*-*/ present present present present present present next W02; present next WXT; Don't need this step <66MHz present present !TM12 next W03; TM12 TM12 !TM12 TM12 !TM12 TM12 !TM12 TM12
next R05; next R06; next R09;
next R06; next R07; next R08; next R08; next R09; next R09; next R10; next RW0;
next W03; next W04; next W08;
Problem with this jump that should enabled writes. cycle, enabled WR6, contention WR6,WR7 since low. Can't solve changing jump point enough product terms need elsewhere present present sufficient product terms have generic state machine 8-bit mono 8-bit stereo/16-bit mono. 22V10 insufficient terms this only support 16-bit cycles Terms generic-replace existing term with: present pdrq !pdrq /*-*/ present present present present !TM12 next W04; TM12 next W05;
next W06;
next W06; next W08;
!TM12 TM12 !TM12 TM12 !TM12
next W07; next W07; next W08; next W08; next W09; next W09;
PowerPC Microprocessor AD1848 CODEC Interface
present cdc_sel.d
TM12 next RW0;
next W10;
PIO_START CDMA_START PDMA_START cdc_sel !e_ta
!(pdak cdak) !pdak !cdak !reset;
e_ta.d
pwrdwn.d
(WR8 TM0) (RD8 TM5); N.B. RD8/TM5 timing critical address were latched could give early writes*/ reset PDN_START pwrdwn !PUP_START Must assert after reset PIO_START PIO_START CDMA_START PDMA_START CODEC_TS CODEC_TS e_ta PDN_START PUP_START; int; active CODEC active e_tea; e_ta e_tea; pdrq; active CODEC active cdrq; active CODEC active XTWR WRTN IDLE XTRD DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 pdrq !reset pdak 16-bit stereo support pdak !reset 16-bit stereo support pdak !reset; 16-bit stereo support DMA3 DMA3 DMA3 DMA3 DMA3 pdak cdak pdak cdak BURST ADD_ONLY;
e_tea.d
ta.d
hst_irq tea.d aack.d pd_irq cd_irq pdak.d
cdak.d
PowerPC Microprocessor AD1848 CODEC Interface
DMA3 DMA3 DMA3 DMA3 cdak !reset cdrq This term supports 16-bit stereo cycles. determine 16-bit stereo test cdrq asserted negated after rd_/wr_ negated asserted then either 16-bit stereo cycle 16-bit mono. occurs times (TM1-5/12) only cdrq continues asserted will cdak continue asserted. once negated can't asserted again until RD10 cdak !reset 16-bit stereo support IDLE cdak !reset; 16-bit stereo support rd_.d RD7;
latch data here PIO/DMA latch data here only*/
wr_.d
WR7; XTRD XTWR XTWR XTWR PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 PIO3; !reset !reset PIO3 !reset PIO3 !reset PIO3 !reset !reset !reset; !reset !reset !reset !reset !reset
cs_.d
g2.d
cntrls 8-bit latch DH0-DH7. Using gives accesses lwrd locns Don't need qualify cycles never here wrts WR3->WR8 included
g1.d
DMA3 DMA3 DMA3 DMA3;
Don't need qualify cycles never here
dir.d
XTRD
!reset !reset !reset !reset !reset !reset
PowerPC Microprocessor AD1848 CODEC Interface
cp1.d
RD10
!reset !reset !reset !reset !reset; !reset DMA3 !reset; !reset PIO3 !reset !reset; byte CODEC
cp2.d
puts data DH0-DH7 reads skip this state writes both
Clocks [state4.0].ckmux [time3.0].ckmux e_ta.ckmux pwrdwn.ckmux ta.ckmux aack.ckmux rd_.ckmux wr_.ckmux cs_.ckmux g1.ckmux g2.ckmux cp1.ckmux cp2.ckmux dir.ckmux cdak.ckmux pdak.ckmux tea.ckmux e_tea.ckmux cdc_sel.ckmux Resets state0.ar state1.ar state2.ar state3.ar state4.ar time0.ar time1.ar time2.ar time3.ar e_ta.ar rst_pla.ar pwrdwn.ar aack.ar tea.ar e_tea.ar ta.ar pdak.ar cdak.ar rd_.ar
clk; clk; clk; clk; clk; clk; clk; clk; clk; clk; clk; clk; clk; clk; clk; clk; clk; clk; clk;
'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0;
PowerPC Microprocessor AD1848 CODEC Interface
wr_.ar cs_.ar cp1.ar cp2.ar dir.ar g1.ar g2.ar cdc_sel.ar Enables pwrdwn.oe hst_irq.oe aack.oe tea.oe ta.oe pdak.oe cdak.oe rd_.oe wr_.oe cs_.oe cp1.oe cp2.oe dir.oe g1.oe g2.oe
'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0; 'b'0;
'b'1; 'b'1; 'b'1; 'b'1; 'b'1; 'b'1; 'b'1; 'b'1; 'b'1; 'b'1; 'b'1; 'b'1; 'b'1; 'b'1; 'b'1;
PowerPC Microprocessor AD1848 CODEC Interface
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