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SN54AHC240 PACKAGE SN74AHC240 DGV, PACKAGE (TOP VIEW) description
Top Searches for this datasheetSN54AHC240, SN74AHC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SN54AHC240 PACKAGE SN74AHC240 DGV, PACKAGE (TOP VIEW) description These octal buffers/drivers designed specifically improve performance density 3-state memory-address drivers, clock drivers, bus-oriented receivers transmitters. 'AHC240 devices organized 4-bit buffers/line drivers with separate output-enable (OE) inputs. When low, device passes data from inputs outputs. When high, outputs high-impedance state. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. SN54AHC240 PACKAGE (TOP VIEW) ORDERING INFORMATION PDIP SOIC -40°C 85°C SSOP TSSOP TVSOP CDIP -55°C 125°C LCCC PACKAGE Tube Tube Tape reel Tape reel Tape reel Tape reel Tape reel Tube Tube Tube ORDERABLE PART NUMBER SN74AHC240N SN74AHC240DW SN74AHC240DWR SN74AHC240NSR SN74AHC240DBR SN74AHC240PWR SN74AHC240DGVR SNJ54AHC240J SNJ54AHC240W SNJ54AHC240FK AHC240 HA240 HA240 HA240 SNJ54AHC240J SNJ54AHC240W SNJ54AHC240FK TOP-SIDE MARKING SN74AHC240N AHC240 Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. Copyright 2002, Texas Instruments Incorporated products compliant MIL-PRF-38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters. PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303 DALLAS, TEXAS 75265 SN54AHC240, SN74AHC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS FUNCTION TABLE (each 4-bit buffer/driver) INPUTS OUTPUT logic diagram (positive logic) absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Output voltage range, (see Note -0.5 Input clamp current, Output clamp current, VCC) Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 70°C/W package 92°C/W package 58°C/W package 69°C/W package 60°C/W package 83°C/W Storage temperature range, Tstg -65°C 150°C Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD 51-7. POST OFFICE 655303 DALLAS, TEXAS 75265 SN54AHC240, SN74AHC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS recommended operating conditions (see Note SN54AHC240 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current 3.85 1.65 SN74AHC240 3.85 1.65 UNIT ns/V Input transition rise fall rate Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS GND, (OE) GND, 2.58 3.94 0.36 0.36 ±0.1 ±0.25 25°C SN54AHC240 2.48 ±2.5 SN74AHC240 2.48 0.44 0.44 ±2.5 UNIT products compliant MIL-PRF-38535, this parameter production tested parameter includes input leakage current. POST OFFICE 655303 DALLAS, TEXAS 75265 SN54AHC240, SN74AHC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 5.3* 5.3* 6.6* 6.6* 7.8* 7.8* 10.3 10.3 7.5* 7.5* 10.6* 10.6* 11.5* 11.5* 14.1 14.1 1.5** SN54AHC240 12.5* 12.5* 12.5* 12.5* 12.5 12.5 SN74AHC240 12.5 12.5 12.5 12.5 12.5 12.5 UNIT tsk(o) products compliant MIL-PRF-38535, this parameter production tested. products compliant MIL-PRF-38535, this parameter does apply. switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 3.6* 3.6* 4.7* 4.7* 5.2* 5.2* 5.5* 5.5* 7.3* 7.3* 7.2* 7.2* SN54AHC240 6.5* 6.5* 8.5* 8.5* 8.5* 8.5* 10.5 10.5 10.5 10.5 SN74AHC240 10.5 10.5 10.5 10.5 UNIT tsk(o) products compliant MIL-PRF-38535, this parameter production tested. products compliant MIL-PRF-38535, this parameter does apply. POST OFFICE 655303 DALLAS, TEXAS 75265 SN54AHC240, SN74AHC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS noise characteristics, 25°C (see Note PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic Quiet output, minimum dynamic Quiet output, minimum dynamic High-level dynamic input voltage SN74AHC240 -0.6 UNIT VIL(D) Low-level dynamic input voltage NOTE Characteristics surface-mount packages only. operating characteristics, 25°C PARAMETER Power dissipation capacitance TEST CONDITIONS load, UNIT POST OFFICE 655303 DALLAS, TEXAS 75265 SN54AHC240, SN74AHC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS PARAMETER MEASUREMENT INFORMATION Open From Output Under Test (see Note Test Point From Output Under Test (see Note TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open LOAD CIRCUIT TOTEM-POLE OUTPUTS LOAD CIRCUIT 3-STATE OPEN-DRAIN OUTPUTS Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES tPZL tPZH Output Waveform (see Note tPLZ tPHZ Input VOLTAGE WAVEFORMS PULSE DURATION Input tPLH In-Phase Output tPHL Out-of-Phase Output tPHL Output Control tPLH Output Waveform (see Note VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement. Figure Load Circuit Voltage Waveforms POST OFFICE 655303 DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. 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