(For Internal Users Only) SYNTEK ===========STK96C100==========

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(For Internal Users Only) SYNTEK ===========STK96C100==========

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STK96C100
(For Internal Users Only)
SYNTEK ===========STK96C100==========
Flat Panel Display Scaler
Ver.
DESIGN CENTER FENG BLDG. SUNG-CHANG RD., TAIPEI, TAIWAN, R.O.C. TEL: 886-2-25056383 FAX: 886-2-25064323
HEADQUARTER NO.24-2, INDUSTRY E.RD., SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C. TEL: 886-3-5773181 FAX: 886-3-5778010
yrriightt SYNTEKT SEMIICONDUCT rrporrattiion Liicen sorrs ((20 00)).Alll rriightts rreserrved. SYNTEKT CONDUCT
Caution!
STK96C100
information this document subject change without notice does represent commitment part vendor, assumes liability responsibility errors that appear this data sheet. warranty representation, either expressed implied, made with respect quality, accuracy, fitness particular part this document. event shall manufacturer liable direct, indirect, special, incidental consequential damages arising from defect error this data sheet product. Product names appearing this data sheet identification purpose only, trademarks product names brand names appearing this document property their respective owners. This data sheet contains materials protected under International Copyright Laws. rights reserved. part this data sheet reproduced, transmitted, transcribed without expressed written permission manufacturer authors this data sheet.
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STK96C100 STK96C100 Application Note
Table Contents Item Page
GENERAL DESCRIPTION FEATURES ESCRIPTION 1.2.1 Interface 1.2.2 Oscillator Interface 1.2.3 Interface. 1.2.4 Panel Interface 1.2.5 Interface. 1.2.6 Power Pins REGISTER ESCRIPTION 1.3.1 Clock Generator Misc. Control. 1.3.2 Input Video Timing Control 1.3.3 Panel Timing Control (Horizontal) 1.3.4 Panel Timing Control (Vertical). 1.3.5 Expansion Control.11 1.3.6 OSD(On-Screen Display) Control.11 1.3.7 Panel Output Control Parameters 1.3.8 Auto-Adjustment Control. 1.3.9 Auto-Adjustment Status. CHIP BLOCK IAGRAM. SYSTEM BLOCK IAGRAM. FUNCTIONAL DESCRIPTION INPUT DATA CAPTURE BLOCK. 2.1.1 Capture Window Definition. 2.1.2 Input Data Format 2.1.3 Conversion. 2.1.4 Clamping Pulse 2.1.5 Composite Sync. Process. PANEL UTPUT BLOCK 2.2.1 Panel Timing Description. 2.2.2 Operating Mode. 2.2.3 Buffer-less Timing Description. 2.2.4 Scaling-up Control 2.2.5 Scaling-up Filter. 2.2.6 Panel Clock 2.2.7 OSD(On-Screen Display) Control.
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STK96C100
2.2.8 Contrast Brightness Control. 2.2.9 Gamma Table Configuration. 2.2.10 Dithering Control. 2.2.11 Panel Border Color. 2.2.12 Debug Mode AUTO-ADJUSTMENT. 2.3.1 Threshold 2.3.2 Source Timing Measurement 2.3.3 Source Level Measurement. 2.3.4 Source Clock Phase Measurement 2.3.5 Buffer Status Detection APPENDIX LIST DISPLAY MODE. APPENDIX QUICK START.
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STK96C100 General Description Features Single-chip video scaling solution external memory required Support independent horizontal vertical linear scaling Providing advanced filter smooth scaling-up image Auto-adjustment frequency, phase, position, white balance On-chip brightness contrast control Single pixel bits) dual pixel bits) input Dependent panel RGB/16-bit YCbCr 4:2:2 video input Build-in YCbCr(CCIR-601) color space converter Support dithering capability On-chip programmable monitor user interface. Font downloadable fonts with 12*18 font size Internal SRAM allowing characters, with programmable frame size position Each independently zoomed times horizontal vertical axis Support transparent blinking effects Support shadow effect frame colors foreground display, colors background display selected from internal color palette Single pixel/clock bits) double pixel/clock bits) digital output Maximum output resolution 1280*1024 60Hz Support 8051 compatible parallel interface 0.35-µm CMOS technology with tolerance input 160-pin PQFQ package
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STK96C100 Description
1.2.1 Interface Interface
NAME RIN_E[7.0] GIN_E[7.0] Drive Description even pixel input Y[7:0] data input Green even pixel input UV[7:0] data input Blue even pixel input control signals Href Vref Hsync Vsync Field LLC2 pixel input Green pixel input Blue pixel input Video input sampling clock horizontal sync. input Original horizontal sync. input vertical sync. input extracted from composite sync. input External input Coast signal composite sync. Fixed polarity clamp pulse output Fixed polarity output Fixed polarity output 137.144 155.160, Notes
BIN_E[7.0]
13.20
RIN_O[7.0] GIN_O[7.0] BIN_O[7.0] VCLK ExtDE MaskVS Clamp
146.153 4.11 22.29
1.2.2 Oscillator Interface
NAME RefCLKI RefCLKO Drive
Oscillator Interface Description
Crystal Oscillator Input Crystal Output
Notes
1.2.3 Interface Interface
NAME OSD_R OSD_G OSD_B Drive Description External Input External Green Input External Blue Input External fast blanking control signal input Notes
Connected ground when used.
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STK96C100
1.2.4 Panel Interface Panel Interface
NAME PE_R[7.0] PE_G[7.0] PE_B[7.0] PO_R[7.0] PO_G[7.0] PO_B[7.0] DCLK ExtPCLK Drive Description even data output Green even data output Blue even data output data output Green data output Blue data output Data clock output panel Horizontal sync. output panel Vertical sync. output panel Data enabled output panel External panel clock input 91.98 82.89 73.80 64.71 55.62 46.53 Notes
1.2.5 Interface Interface
NAME uP_AD[7.0] uP_RD uP_WR uP_ALE uP_CE GPIO[6.0] Drive Description Address/Data Read Strobe from active Write Strobe from active Address Latch Enabled, latch address Enable interface, active System reset General Purpose Port output option 121.128 107.113 Notes
1.2.6 Power Pins Power Pins
NAME AVDD AGND 3-State output. 3-State output with pull-up. Description Analog Power Analog Ground Kernel Power Kernel Ground 12,30,40,54,72,90,101, 106,129,136,154 3,21,32,45,63,81,99, 105,115,145 Notes
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STK96C100 Register Description
1.3.1 Clock generator Misc. control Clock generator Misc. control
Address 0x00 Name RstFlag EnVIU EnVOU Mute1 Mute EnPNL LCDOE3 LCDOE2 LCDOE1 LCDOE0 SelPCLK PLL_PD PLL_RST PLL_MX[1.0] Description Note Reset auto-adjustment flags, auto restore after write Enable input video sampling unit. Enable video output unit. bits panel output "0". Enable image output, including BGC. Enable panel output. Enable panel [1.0] output. Enable panel even [1.0] output. Enable panel [7.2] output. Enable panel even [7.2] control signals output (including DCLK, PHS, PVS, PDE). Select internal/external clock source panel clock normal operation; power-down. normal operation, reset PLL. Select panel clock generator output. normal operation, Fout Fin, Fout. ~Fin. Select panel clock generator output divider. divided 1,01 divided divided divided Panel clock generator numerator setting Panel clock generator denominator setting select external RefCLK, divided incoming VCLK clock source. Adjust output panel clock phase from internal panel clock. many incoming horizontal lines delay sync panel timing every frame many incoming horizontal pixels delay sync panel timing every frame Enable free running output blanking period. Enable output timing sync. incoming timing every incoming frame. Enable output timing sync. incoming timing every incoming horizontal line Select GPIO/PWM output GPIO[3.0] GPIO output value; when GPIO treats input value value value value Enter test mode when 0110xxxx, 1001xxxx, 0110xxxx, xxxxabcd, group data sequence, were written this register, which will carry [bcd] sets internal signals output panel data. Each signal contains internal nodes. enable memory interface address output.
0x01
0x02
PLL_OD[1.0]
0x03 0x04 0x05 0x06 0x07
PLL_M[6.0] PLL_N[4.0] PreDIV[3:0] AdjDCLK[3.0] DlyLine[1.0] DlyPxl[5.0]
0x08
EnFreeBlank EnSyncV EnSyncH SelPWM GPO[7.0] PWM0[7.0] PWM1[7.0] PWM2[7.0] PWM3[7.0] EnTest[7.0]
0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
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STK96C100
1.3.2 Input video timing control Input video timing control
Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 Name HBP[7.0] HBP[8] HDISP[7.0] HDISP[10.8] VBP[7.0] VBP[8] VDISP[7.0] VDISP[10.8] ClampWd[4.0] Description
Horizontal back porch length incoming video signal, unit
Note
number video clocks
Active display area length horizontal scan line, unit
number video clocks
Vertical back porch length incoming video signal, unit
number scan lines
Active display area length vertical frame, unit number
scan lines
Clamp pulse width, unit external clocks RefCLK
0x19
SelVSI SelVSD SelEdgeH SelEdgeV SetHS SetVS SelRef
0x1A
SelMask SetMask MaskType[1.0] MaskBW[1.0] MaskFW[1.0] AdjOdd ADC_Type[1.0] IHT[7.0] IHT[10.8] EnYUV SetVref SetHref SetLLC SetField AdjEvenF AdjOddF
0x1B
0x1C 0x1D 0x1E
ClampWd[4] adjust Clamp pulse output positive/negative Select from VSI, Select from Select original Select synced Select front/back edge used Select front/back edge used incoming polarity positive/negative incoming polarity positive/negative Select external RefCLK/(RefCLK/2) clamp polarity detect circuit Select mask synced front/back edge mask polarity positive/negative Select type mask; disable, original expanded backward expansion width mask forward expansion width mask Adjust incoming video clock polarity type; dual pixel interleaved, dual pixel parallel, single pixel Total number pixel horizontal line. Select (4:2:2) format input polarity signal "Vref" positive/negative polarity signal "Href" positive/negative polarity signal "LLC" positive/negative polarity signal "Field" positive/negative line delay even field line delay field
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STK96C100
1.3.3 Panel timing control (horizontal) Panel timing control (horizontal)
Address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C Name PHS1[7.0] PHS1[10:8] PHS2[7.0] PHS2[10:8] PHDE2[7.0] PHDE2[10.8] PHXDE1[7.0] PHXDE1[ 10.8] PHXDE2[7.0] PHXDE2[10.8] PHT[7.0] PHT[10.8] DE_Polarity VS_Polarity HS_Polarity MaskPHS[7.0] Description
Panel horizontal sync left edge position Panel horizontal sync right edge position Panel signal right edge position Panel image output left edge position Panel image output right edge position total length horizontal scan line, unit number
Note
0x2D 0x2E 0x2F
PHSB[7.0] PHSB[10.8]
DCLK polarity PDE, positive, negative polarity PVS, positive, negative polarity PHS, positive, negative Indicate many horizontal line after panel start inhibit panel output until panel start Panel horizontal sync left edge blanking period(right edge PHT)
1.3.4 Panel timing control (vertical) Panel timing control (vertical)
Address 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B Name PVS1[7.0] PVS1[10.8] PVS2[7.0] PVS2[10.8] PVDE2[7.0] PVDE2[10.8] PVXDE1[7.0] PVXDE1[10.8] PVXDE2[7.0] PVXDE2[10.8] PVT[7.0] PVT[10.8] Description
Panel Vertical sync edge position Panel Vertical sync bottom edge position Panel signal bottom edge position Panel image output edge position Panel image output bottom edge position total number scan lines vertical frame
Note
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STK96C100
1.3.5 Expansion control Expansion control
Address 0x40 0x41 0x42 0x43 0x44 Name HSR[7.0] HSR[15.8] VSR[7.0] VSR[15.8] FilterON FilterType[2.0] Description horizontal expansion ratio Expansion ration (INres/OUTres) 65536
Note
vertical expansion ratio Expansion ration (INres/OUTres) 65536
Turn scalar filter scalar filter strength, blur, sharp
1.3.6 control control
Address 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 Name StartH[7.0] StartH[10.8] StartV[7.0] StartV[10.8] Width[5.0] Length[5.0] BorderV[3.0] BorderH[3.0] BdrColor[3.0] ShadowV[3.0] ShadowH[3.0] RstOSD DplH DplV CharOnly
width OSD's window, unit char length window, unit char
Description OSD's window horizontal start position
Note
OSD's window vertical start position
0x5A 0x5B 0x5C 0x5D
EnOSD MultiColorFont[4.0] SetAdr[7.0] WrChr[7.0] WrAttr[7.0]
0x5E 0x5F
WrFont[7.0] WrColor[7.0]
length border, unit line width OSD's border, unit pixel color OSD's border, mapping color pallet length shadow, unit line width OSD's shadow, unit pixel reset unit, auto restore when write read doubling horizontal char size doubling vertical char length write into char attribute memory interval when write sequence Only write into char memory when write sequence enable output number multi-color font address memory, used char, attribute, font, color-pallet etc. Write data into char memory, address write SetAdr, address auto increase after write, mean blinking Write data into attribute memory, address write SetAdr, address auto increase after write foreground attribute, select color from colors pallet background attribute, select color from colors pallet Transparent when value Write data into font memory, Font write SetAdr, address auto increase after write Write data into color-pallet memory, Color write SetAdr, address auto increase after write
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STK96C100
1.3.7 Panel output control parameters Panel output control parameters
Address 0x60 0x61 0x62 0x63 0x64 Name GainR[5.0] GainG[5.0] GainB[5.0] DC[7.0] Description Panel output red/green/blue gain adjustment Range 0x00 0x20 0x3F dark normal bright
Panel output level adjustment
Note
BGC[5.0]
0x65
GammaWr EnGamma EnFRC EnDIT
0x66 0x67
SetGamma WrGamma
Range 0x80 0x00 0x7F dark normal bright Panel output background color BGC[1.0] BGC[3.2] BGC[5.4] Enable modify (Blue[6], Green[5], Red[4]) GAMMA table Enable GAMMA correction Enable dynamic dithering Enable dithering Select single pixel output mode dual pixel output mode dual pixel output mode single pixel output mode address GAMMA table write Write data into GAMMA table
1.3.8 Auto-adjustment control Auto-adjustment control
Address 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 Name GateR[7.0] GateG[7.0] GateB[7.0] SetX[7.0] SetX[11.8] SetY[7.0] SetY[11.8] DetBlank SelDE Slope GateDif[4.0] Description Note minimum margin incoming video data eliminate noise influence auto-adjustment. minimum margin incoming green video data eliminate noise influence auto-adjustment. minimum margin incoming blue video data eliminate noise influence auto-adjustment. Define horizontal position pixel read auto adjustment circuit from input video data Define vertical position pixel read auto adjustment circuit from input video data Select detect blank minimum value Select external auto-adjustment. up/down slope detect minimum value slope accept phase adjustment
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STK96C100
1.3.9 Auto-adjustment Status Auto-adjustment Status (Read Only)
Address 0x80 Name Over Under HCT[7.0] HCT[11.8] VCT[7.0] VCT[11.8] VSHC[7.0] VSHC[11.8] HPOSL[7.0] HPOSL[10.8] HPOSR[7.0] HPOSR[10.8] VPOS[7.0] HPOSLC[7.0] HPOSLC[10.8] HPOSRC[7.0] HPOSRC[10.8] TGX[7.0] TGX[11.8] TGY[7.0] TGY[10.8] TogRate[3.0] LVD[7.0] LVD[15.8] EQC[4.0] MinR[7.0] MinG[7.0] MinB[7.0] MaxR[7.0] MaxG[7.0] MaxB[7.0] Description Note indicate Line-Buffer Over (write speed greater then read speed), Clear this setting RstCHS `0'. indicate Line-Buffer Under (read speed greater then write speed) Clear this setting RstCHS `0'. V-sync polarity detected internal detector positive, =negative. H-sync polarity detected internal detector positive, negative. Vperiod[11.0] counter overflow, this will `1', Clear this setting RstCHS `0'. Hperiod[10.0] counter overflow, this will `1', Clear this setting RstCHS `0'. Input fixed polarity vertical sync. Indicate input scan line total width, which counted external fixed frequency clock RefCLK. Indicate number input scan line frame, which counted input H-sync pulse. Indicate width from last H-sync V-sync, which counted RefCLK. Indicate minimum left edge incoming video frame. Indicate maximum right edge incoming video frame. Indicate position incoming video. Report many horizontal lines same minimum HPOSL value. Report many horizontal lines same maximum HPOSR value. Indicate search result horizontal position maximum toggled pixel sequence. Indicate search result vertical position maximum toggled pixel sequence. Report toggle rate maximum toggled pixel sequence. pixel latched position given SetX SetY. Report many pixels equal between frame latched same position. Report minimum value incoming video data display area. Report minimum value incoming green video data display area. Report minimum value incoming blue video data display area. Report minimum value incoming video data display area. Report minimum value incoming green video data display area. Report minimum value incoming blue video data display area.
0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D
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STK96C100
Auto-adjustment Status (cont.)
0x9E 0x9F 0xA0 0XA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC Track[7.0] Track[15.8] Track[23.16] Track[28.24] SyncPosH[7.0] SyncPosH[10.8] SyncPosV[7.0] SyncPosV[10.8] PosSyncH[7.0] PosSyncH[10.0] ReadR[7:0] ReadG[7:0] ReadB[7:0] BufUsage[7:0] BufUsage[11:8] Name Report tracking value
Report position panel horizontal timing when incoming frame sync arriv Report position panel vertical timing when incoming frame sync arrival. Report position panel horizontal timing when incoming line sync arrival. Read incoming video data SetX, SetY position. Read incoming video green data SetX, SetY position. Read incoming video blue data SetX, SetY position. Report Line-Buffer usage. Description Note
Address
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STK96C100 Chip Block Diagram
Input Sampling Convert Internal Buffer Scale Filter Brightness Contrast
PxlIn
AutoAdjustment
Gamma Correction Dithering Control Output Mixer Output Timing Control PxlOut PxlOut
DCLK
Interface
Panel clock Generator
System Block Diagram
Composite S-Video
Video Decoder Video Panel-link Receiver Scaler Controller
Video
Panel
Digital Video
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STK96C100
Function Description
Input Data Capture Block
2.1.1 Capture Window Definition HBP[8:0] {0x11, 0x10} HDISP[10:0] {0x13, 0x12} VBP[8:0] {0x15, 0x14} VDISP[10:0] {0x17, 0x16} IHT[10:0] {0x1D, 0x1C}
V-sync Pulse Width
H_Back_Proch HDISP H_Display_Size H_Sync_Width H_Back_Proch H_Display_Size H_Front_Proch V_Back_Porch VDISP V_Display_Size
H-sync Pulse Width
Input Sampling Area
VDISP
HDISP
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STK96C100
2.1.2 Input Data Format Single pixel input ADC_Type[1:0] {0x1B[1:0]}
RO[7:0] GO[7:0] BO[7:0] VCLK RIN_ E[7:0] GIN_ E[7:0] BIN_ E[7:0] VCLK
Scaler
Dual pixels parallel input ADC_Type[1:0] {0x1B[1:0]}
RO_A[7:0] GO_A[7:0] BO_A[7:0] RO_B[7:0] B[7:0] BO_B[7:0] VCLK RIN_ E[7:0] GIN_ E[7:0] BIN_ E[7:0] RIN_O[7:0] GIN_O[7:0] BIN_O[7:0] VCLK
Scaler
Dual pixels interleaved input ADC_Type[1:0] {0x1B[1:0]}
RO_A[7:0] GO_A[7:0] BO_A[7:0] RO_B[7:0] B[7:0] BO_B[7:0] VCLK RIN_ E[7:0] GIN_ E[7:0] BIN_ E[7:0] RIN_O[7:0] GIN_O[7:0] BIN_O[7:0] VCLK
Scaler
input EnYUV
Y[7:0] YU[7:0] Href Vref Hsync Vsync Field LLC2
{0x1E[6]}
RIN_ E[7:0] GIN_ E[7:0] BIN_ E[7] BIN_ E[6] BIN_ E[5] BIN_ E[4] BIN_ E[3] BIN_ E[2]
Decoder
Scaler
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STK96C100
Digital input
RO[7:0] GO[7:0] BO[7:0] VCLK RIN_ E[7:0] GIN_ E[7:0] BIN_ E[7:0] VCLK ExtDE
TMDS Receiver
Scaler
2.1.3 conversion Such Scaler allow input format 4:2:2 EnYUV {0x1E[6]} set. external circuit Scaler will convert format into that RGB, which depicted following conversion formula: 1.371 128) 0.336 128) 0.698 128) 1.732 128) 2.1.4 Clamping Pulse ClampWd[4:0] {0x18} external requires group signals apprise when dark level video signal comes; however, Scaler must generate group CLAMP signals situated back porch input Hsync. signal with width approx. 0.5~1us. ClampWd [3:0] adjust width CLAMP signal. When SelRef {0x19[0]}, width CLAMP signal ClampWd[3:0] RefCLK. When SelRef {0x19[0]}, width CLAMP signal ClampWd[3:0] RefCLK. ClampWd[4] adjust polarity CLAMP signal.
RefCLK H-sync CLAMP
CLAMP Width (1~16) RefCLK
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STK96C100
2.1.5 Composite sync process SelVSI {0x19[6]} MaskBW[1:0] {0x1A[3:2] MaskFW[1:0] {0x1A[1:0] When input signal Composite Sync., external loop utilized extract vertical signal, then select input vertical signal (SelVSI MaskBW MaskFW meanwhile generate MaskVS signal lock external frequency phase Vsync. signal. Composite sync input
MaskVS
coast
Scaler
MaskVS MaskFW
MaskBW
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STK96C100 Panel Output Block
2.2.1 Panel Timing Description PHS1[10:0] {0x21, 0x20} PHS2[10:0] {0x23, 0x22} PHDE2[10:0] {0x25, 0x24} PHXDE1[10:0] {0x27, 0x26} PHXDE2[10:0] {0x29, 0x28} PHT[10:0] {0x2B, 0x2A} PVS1[10:0] PVS2[10:0] PVDE2[10:0] PVXDE1[10:0] PVXDE2[10:0] PVT[10:0] {0x31, 0x30} {0x33, 0x32} {0x35, 0x34} {0x37, 0x36} {0x39, 0x38} {0x3B, 0x3A}
Blanking
PVXDE1
Panel Real Display
PVS2 PVS1 PVDE2 PVXDE2
PHXDE1 PHXDE2 PHDE2 PHS1 PHS2
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STK96C100
2.2.2 Operating Mode Because there external frame buffer (SDRAM) serving frame rate converter, bear following points mind: output vertical frequency equal input vertical frequency. output video (PCLK) regularly proportional input video (VCLK) PCLK VCLK RateH *RateV RateH means rate output horizontal resolution input horizontal resolution. RateV means rate output vertical resolution input vertical resolution. strictly confirmed that sync. width, front porch, back porch included calculation horizontal resolution vertical resolution. This Scaler provides operating modes: Free EnSyncV {0x08[1]} EnSyncH {0x08[0]} this mode, input vertical timing fully impact output vertical timing. output horizontal period vertical period respectively. this mode, even input signal comes, output timing still generated. Sync Input EnSyncV {0x08[1]} EnSyncH {0x08[0]} this mode, vertical timing other than horizontal timing impact output vertical timing. output horizontal period PHT; output vertical period same input vertical period. rating maximum. advantage this mode, output horizontal periods equal; disadvantage this mode, when some errors result real output video (PCLK) ideal output video (VCLK*RateH*RateV), Buffer overrun underrun will happen internally accumulation errors. Sync Input EnSyncV {0x08[1]} EnSyncH {0x08[0]} this mode, input timing impact output horizontal vertical timing; output horizontal period gained where input horizontal period multiplied expansion rate vertical dots (RateV). value will neglected; output vertical period input vertical period equal. advantage this mode, when some errors result real output video (PCLK) ideal output video (VCLK*RateH*RateV), Buffer overrun underrun will happen internally accumulation errors; disadvantage this mode, each output horizontal period somewhat different.
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STK96C100
2.2.3 Buffer-less Timing Description DlyLine[1:0] {0x07} DlyPxl[5:0] {0x07} video output circuit does start output operation until input circuit fills internal buffer considerable extent. Register adjust filling extent internal buffer. Recommendation: Input Video Output
DlyLine First Start output from this point
Input Video VCLK Output
DlyPxl VCLK
real output video different from ideal output video, panel display abnormal last horizontal period being short; however, make this problem decrease setting input Hsync. mode (EnSyncH{0x08[0]} Additionally, still Reg. Shown below fully release this bottleneck. PHSB[10:0] {0x2F, 0x2E} EnFreeBlank {0x08[2]} input Hsync. mode (EnSyncH{0x08[0]} output horizontal timing synchronized with input Hsync. signal when EnFreeBlank 0,the output Hsync. signal, during output vertically visible blanking period, PHS1 PHS2,and abandoned. output vertically blanking period, output Hsync. signal PHSB PHT. When EnFreeBlank=1,the output Hsync. signal, during output vertically visible period, PHS1 PHS2.In output vertically blanking period, output horizontal timing isn't synchronized with input Hsync. signal; output Hsync. signal PHSB PHT.
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STK96C100
SyncH Output Output
PHS1 PHS2 PHSB
Last frame
MaskPHS[7:0]
{0x2D}
such Reg. confine each unit Hsync. signal during output vertical back porch fear last Hsync. period being short. Output Output Output
MaskPHS Stop
First frame
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STK96C100
2.2.4 Scaling Control HSR[15:0] {0x41, 0x40} VSR[15:0] {0x43, 0x42} formula calculate enlarged scale shown follows: Scaling Factor (ResIN ResOUT) 65536 ResIN means resolution input video. ResOUT means resolution output video. formula calculate horizontal vertical scale same that shown above. example: input image 640x480, output image 1024x768. Horizontal scaling factor (640 1024) 65536 40960 0xA000 Vertical scaling factor (480 768) 65536 40960 0xA000 Input Image size 1024 -0xFFFF -0xC800 0xFFFF 0xA000 0xCCCC Input Image size -0xFFFF -0xC800 0xFFFF 0x9600 0xC000
1024 1280
0xFFFF 0xCCCC 0xA000 0x8000
1280 -0xFFFF
Output Image Size
1024
0xFFFF 0xCCCC 0xA000 0x6000
1024 -0xFFFF
2.2.5 Scaling Filter FilterON {0x44[3]} FilterType[2:0] {0x44[2:0]} When output video amplified, "FilterNO=1" enable internal Filter then adjust video quality scaled output video. value FilterType adjust intensity Filter; higher value more distinct video keeps!
Output Image Size
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STK96C100
2.2.6 Panel Clock SelPCLK {0x02[6]} PLL_M[6:0] {0x03} PLL_N[4:0] {0x04} PLL_OD[1:0] {0x02[1:0]} PreDiv[3:0] {0x05} AdjDCLK[3:0] {0x06} video output (PCLK) either input externally generated internal PLL;the internal input frequency gained where fixed frequency(RefCLK) inputvideo (VCLK) divided fixed value PreDiv[3:0]. When value 0,the fixed frequency (RefCLK) selected input frequency.
ExtPCLK RefCLK VCLK
SelPCLK
panel interface unit
formula calculate output frequency shown follows: output frequency (PLL input frequency) ((PLL_M ((PLL_N NO)) Here when PLL_OD when PLL_OD when PLL_OD when PLL_OD Output Mode Frequency PLL_M PLL_N 800x600 1024x768 1280x1024 Assume reference clock from "RefCLK" 14.318 PLL_OD Output Freq. 40.01 65.03 108.04
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STK96C100
2.2.7 Control StartH[10:0] StartV[10:0] Width[5:0] Length[5:0] {0x51, 0x50} {0x53, 0x52} {0x54} {0x55} Panel Display Area
StartV
BorderV[3:0] BorderH[3:0] ShadowV[3.0] ShadowH[3.0]
{0x56} {0x56} {0x58} {0x58}
BorderV ShadowV
Length
BorderH StartH Width ShadowH
Architecture (On-Screen Display): This Scaler provides sets Chars. Attributes. Each Char. mapped internal 12*18 soft fonts;each Attribute mapped foreground colors background colors.When background colors 0Xf,the Chars appear transparent;when Char 1,the Char appears flicker.Each foreground background color mapped sets Color Pallets;each Color Pallet 24-bit true color.
MultiColor Path
Char Memory Address Counter Attribute Memory
Font Memory
F.G./B.G. Selector
Color Pallet
Mixer
Char
Mapped fonts Blinking control
Attribute
Foreground color Background color
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STK96C100
Char Attribute: SetAdr[7:0] {0x5B} WrChr {0x5C} WrAttr {0x5D} Driving Char display screen, first know address Char display window, convert memory address, then write Char into Char memory. converting formula Address shown follows: Address Width indicates Char horizontal position window, which unit Char. indicates Char vertical position window, which unit Chart. "Width" means duration window, which unit Chart. tips write Char shown below applied: write only Char (CharOnly {0x59[1]} After write Char, memory address will automatically increase then write next Char. Otherwise, write Char Attribute (CharOnly {0x59[1]} this tip, after write Char, memory address doesn't automatically increase 1;memory address doesn't increase until Attribute written steps Char Attribute shown follows: Calculate memory address. memory address. (write SetAdr) Char. (write WrChr) CharOnly step.5 Attribute. (write WrAttr) continuing next position Char, step.3; else step.1 recalculate address stop procedure. Color Pallet: WrColor {0x5F} This Scaler provides sets Color Pallets; each Color Pallet with bits color. steps Color Pallet shown follows: color pallet (write SetAdr) color current color pallet. (write WrColor) green color current color pallet. (write WrColor) blue color current color pallet. (write WrColor) continuing next color pallet No., step.2; else step.1 another color pallet stop this procedure.
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Architecture Font: This Scaler provides 12*18 fonts downloadable; each font Occupies bytes memory space, formula calculate mapped memory address shown below: Address Font Font 127. Font writing sequence: WrFont {0x5E} Calculate Font memory address. Font memory address. (write SetAdr {0x5B}) Write Bytes bit-map data into Font memory sequentially. (write WrFont) continue write next Font step.3 else step.1 another Font stop procedure.
Byte ROW-00 ROW-01 ROW-02 ROW-03 ROW-04 ROW-05 ROW-06 ROW-07 ROW-08 ROW-09 ROW-10 ROW-11 ROW-12 ROW-13 ROW-14 ROW-15 ROW-16 ROW-17 Byte
0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22
Font
Multi-Color Font MultiColorFont[4:0] {0x5A} Reg. capture color fonts; each color font occupies monochrome fonts. color font increased,4 monochrome fonts available will decreased. example, when Reg. color fonts used; number monochrome font starts from 8,the font mapped same color font, font mapped same color font. output color font also mapped 24-bit color through Color Pallet.
Bit-0 Bit-1 Bit-2
Combine 4-bits color Font
Font Font 4N+1 Font 4N+2 Font 4N+3
Bit-3
Double Size DplH {0x59[3]} DplV {0x59[2]} Reg. enlarge horizontal vertical direction twice, which effect only font (On-Screen Display) else than Border Shadow OSD.
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2.2.8 Contrast Brightness Control GainR[5:0] {0x60} GainG[5:0] {0x61} GainB[5:0] {0x62} DC[7:0] {0x63} GainR, GainG, GainB respectively adjust Contrast OutputR, OutputG.and OutputB. value adjusted; Contrast will increase value higher than 32,and Contrast will decrease value lower than 32.The range adjustment from DC[7:0], brightness OutputR,OutputG.and OutputB adjusted. range adjustment from -127 +127. ASCII, 0x80 Brightness minimum, which goes 0xFF, 0x00 Brightness keeps constant, 0x7F Brightness maximum. 2.2.9 Gamma Table Configuration GammaWr[2:0] {0x65[6:4]} EnGamma {0x65[3]} SetGamma[7:0] {0x66} WrGamma[7:0] {0x67} This Scaler internally provides 256*8 bits serve Gamma-Correction RGB. contents Gamma Table input from image data through address Gamma Table converted into mapped data output. From scaler Image data From SetGamma[7:0]
A[7:0] DO[7:0] DI[7:0]
From WrGamma[7:0]
Dithering Control Program Gamma Table: Requiring program Gamma Table, will first disable function (EnGamma then decide which Gamma Table write; Gamma Table written respectively together same time, only mapped GammaWr[2] Blue, GammaWr[1] Green, GammaWr[0] must set. steps shown follows: Disable Gamma Correction. (EnGamma GammaWr decide which program. (write GammaWr) SetGamma decide which address start program. (write SetGamma)
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Write data into Gamma Table. (write WrGamma) continuing write next address, step.4; else change another address step.3, change another Gamma Table step.2, stop write Gamma Table step.6. Enable Gamma Correction. (EnGamma 2.2.10 Dithering Control EnDIT {0x65[1]} EnFRC {0x65[2]} Connecting panel with minimum bit(s) (ex. 18-bit panel), enable function (EnDIT=1) simulate 24-bit panel, enable dynamic Dithering (EnFRC=1) enhance effect Dithering. 2.2.11 Panel Border Color BGC[5:0] {0x64} When input video resolution inferior output couldn't enhanced output video resolution, Reg. change panel border color filled input video. Reg., [1:0], [3:2], [5:4] means maximum bits respectively; other bits 2.2.12 Debug Mode EnTest[7:0] {0x0F} Write Reg[0F] 0x60, 0x90, 0x60 proper order enter Debug Mode. This moment, internal signal this Scaler will output Panel Pixel output pins. Write last Byte select which internal signals output. Mode EvenD[7] EvenD[6] OddD[23] OddD[22] OddD[15] OddD[14] OddD[7] OddD[6] EvenD[23] EvenD[22] EvenD[15] EvenD[14] HSIP VSIP LatCLK DISP DispH DispV IClrOV EmptyH EmptyV PCLK ExpH ExpV iEnRdH iEnRdV iClrOH SyncH SyncV EnOUT PHDE PVDE HXDE VXDE iOSD_B[5] iOSD_B[4] iOSD_B[3] iOSD_B[2] iOSD_B[1] iOSD_B[0] iOSD_G[5] iOSD_G[4] iOSD_G[3] iOSD_G[2] iOSD_G[1] iOSD_G[0] iOSD_B[7] iOSD_B[6] iOSD_R[5] iOSD_R[4] iOSD_R[3] iOSD_R[2] iOSD_R[1] iOSD_R[0] iOSD_G[7] iOSD_G[6] DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[3] DOUT[2] DOUT[1] DOUT[0] iWVC[1] iWVC[0] iRVC[1] iRVC[0] DOUT[13] DOUT[22] DOUT[15] DOUT[14] IEnRdH iEnRdV iClrOH iClrOV PCLK EmptyH ExpH1 ExpV1 POUT[7] POUT[6] POUT[5] POUT[4] POUT[3] POUT[2] POUT[1] POUT[0] LatGPO iMask iSetPosEQ iNewMaxTog POUT[23] POUT[22] POUT[15] POUT[14] GmaAdr GmaData iWrTbl[2] iWrTbl[1] iWrTbl[0] iINC[2] iINC[1] iINC[0]
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STK96C100 Auto-Adjustment
2.3.1 Threshold GateR[7:0] {0x70} GateG[7:0] {0x71} GateB[7:0] {0x72} Using auto. Detecting circuit adjust input captured image, first Threshold input signal auto. Detecting circuit avoid noise affecting operation auto. Detecting circuit.GateR, GateG, GateB means Threshold Red, Green, Blue input signal respectively. input signal level higher than setting value will allowed auto. Detecting circuit. Video Level GateX
2.3.2 Source Timing Measurement {0x80[1]} 2048 RefCLK H-Sync missing {0x80[2]} 2048 Lines V-Sync missing {0x80[3]} 96/192 RefCLK H-Sync polarity {0x80[4]} Line V-Sync polarity HCT[11:0] {0x82, 0x81} RefCLK Horizontal period VCT[11:0] {0x84, 0x83} Line Vertical period HPOSL[10:0] {0x88, 0x87} VCLK Horizontal display start HPOSR[10:0] {0x8A, 0x89} VCLK Horizontal display VSHC[11:0] {0x86, 0x85} VCLK Interlace input detect VPOS[7:0] {0x8B} Line Vertical display start auto. Detecting circuit provides following data user's adjustment: When Flag 1,no Hsync. input signal will show. When Flag 1,no Vsync. input signal will show. When Flags shown above RstFlag {0x00[2]} written clear RstFlag HSP: When Flag 0,the Hsync. input signal positive; contrary, negative. When input signal Composite during period Vsync., Flag inaccurate. VSP: When Flag 0,the Vsync. input signal positive; contrary, negative. HCT: 12-bit value indicates period Hsync. input signal, RefCLK reference frequency, each front porch Hsync. signal updated. VCT: 12-bit value indicates count horizontal line input signal; each Frame (the front porch Vsync. signal) updated. HPOSL: 11-bit value indicates position left porch input image, VCLK reference frequency, each Frame updated.
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HPOSR 11-bit value indicates position right porch input image, VCLK reference frequency, each Frame updated. VSHC: 12-bit value indicates that horizontal scanning line emerges Hsync. while input Vsync. signal emerges porch Vsync. data determine Interlace signal then determine Even field. VCLK reference frequency; each Frame updated. VPOS: 8-bit value indicates upper porch input video, number horizontal scanning line(HS) unit, each Frame updated.
V-sync Pulse Width
VPOS
H-sync Pulse Width
HPOSL
Input Sampling Area
HPOSR
VSHC
2.3.3 Source Level Measurement MinR[7:0] {0x98} MaxR[7:0] {0x9B} MinG[7:0] {0x99} MaxG[7:0] {0x9C} MinB[7:0] {0x9A} MaxB[7:0] {0x9D} auto. Detecting circuit detect minimum maximum input video data Contrast adjustment external ADC.
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When DetBlank ({0x77[7]}) data image captured area will detected;when DetBlank data input image will detected.
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2.3.4 Source Clock Phase Measurement auto. Detecting circuit provides methods shown below detect frequency phase input video suitable. SetX[11:0] {0x74, 0x73} TGX[11:0] {0x91, 0x90} SetY[11:0] {0x76, 0x75} TGY[11:0] {0x93, 0x92} TogRate[3:0] {0x94} LVD[15:0] {0x96, 0x95} EQC[4:0] {0x97} auto. Detecting circuit find which changing level video data input video more frequent then reveals position (TGX, TGY) changing level (TogRate). With this information, captured position (SetX, SetY) capture data input video. adjoin input video data (LVD) continuously captured each Frame, video data captured last Frame will automatically compared. result after compared will EQC. Threshold GateR, GateG, GateB will confine video data captured. Track[28:0] {0xA1, 0xA0, 0x9F, 0x9E} Slope {0x77[5]} GateDif[4:0] {0x77[4:0]} other provided auto. Detecting circuit count variable input video data. parameters must set: select changing direction (Slope) decide Threshold (GateDif) changing slope when condition meets setting slope changing slope GateDif, changing slope (Pn) will accumulated, each Frame will output Track.
Video Level
Slope Slope
2.3.5 Buffer Status Detection SyncPosH[10:0] {0xA3, 0xA2} SyncPosV[10:0] {0xA5, 0xA4} PosSyncH[10:0] {0xA7, 0xA6} BufUsage[11:0] {0xAC, 0xAB} Over {0x80[6]} Under {0x80[5]} auto. Detecting circuit detects operation internal Buffer, which offers required information user's reference parameters. SyncPosH: When input video captured circuit dispatches signal require output circuit start output image, position horizontal counter will output. With parameter, will know last output Hsync, signal very close first output Hsync. signal necessary adjustment. parameter depends output video (PCLK).
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STK96C100
SyncPosV: When input video captured circuit dispatches signal require output circuit start output image, position vertical counter will output. When last output Hsync. signal very close first output Hsync. signal, MaskPHS parameter. parameter depends count output horizontal line. PosSyncH: input Hsync. mode, output horizontal period controlled ratio input horizontal period. Duty Output SyncH Duty Input RateV, know that when parameter means SyncH, position horizontal counter will output. BufUsage: Buffer (3*1280*24 bits) with horizontal lines long provided within Scaler This parameter indicates maximum required Buffer Frame. Over: When Flag 1,the internal Buffer Overrun happens.(Write RstFlag=0 clear Flag.) Under: When Flag internal Buffer Underrun Happens. (Write RstFlag=0 clear Flag.) Input Input Input Video Output Output Output SyncPosV SyncPosH Start output from this point SyncH Output Output
PosSyncH Last First
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Appendix List Display Mode
Horizontal Vertical Sync Back Display Front Total Sync Back Display Front Total Width Porch Width Porch Width Porch Size Porch 1024 1024 1024 1024 1152 1152 1152 1280 1280 1024 1280 1024 1280 1024 1024 1024 1024 1024 1152 1152 1152 1280 1280 1280 1280 Unit pixel 1024 1056 1040 1056 1048 1172 1344 1328 1312 1376 1600 1576 1556 1800 1688 1688 1728 1024 1024 1024 Unit line 1000 1066 1066 1072
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STK96C100
Appendix Quick Start
dual pixels parallel. Input mode 1024x768 60Hz, -/-. Output mode 1024x768 60Hz, DE/H/V +/+/+. Panel clock internal reference RefCLK 14.318MHz. GPIO[0:6] input. 40x5, center, border shadow, default off. Reg. Value Reg. Value Reg. Value Reg. Value Reg. Value Reg. Value Reg. After complete these registers setting, execute following steps active Scaler Step1. Send hardware reset pulse. Step2. Reg[02] 0x02 enable panel clock generator. Step3. Reg[00] 0x07 active scaler. Step4. Reg[01] 0x3F enable panel output. Value
Note(1) don't hold hardware reset signal during initial registers. Note(2) Reg[08] when there signals input, output free run. Note(3) Reg[59] enable OSD.
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(For Internal Users Only) SYNTEK ===========STK96C100==========

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