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Sitronix
PRELIMINARY Notice: This final specification. Some parameters subject change
ST8624
Segment Driver with Low-Voltage Drive
Features
Duty cycle 1/300 drive voltage: drive circuits Operating voltage: data Shift clock speed max/3 max/5 Shadowing correction circuit Display-off function Automatic generation chip enable signal Standby function
Description
ST8624 240-channel segment driver that drives matrix panel voltage. ST8624 operates with drive voltage logic drive voltage, used together with common driver ST8600. ST8624 also incorporates shadowing correction circuit suitable high-quality image processing. ST8624, packaged fine-pitch slim tape-carrier package (slim-TCP), makes possible reduce space round panel.
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0.12
EIO1 DISP EIO2 Y237 Y238 Y239 Y240
Sitronix
assignment (TCP)
view
Figure ST8624 assignment
2/28
ST8624
2001/Sep/08
Sitronix
ST8624
Block Diagram
Y1~Y240 drive circuit
DISP CC1~CC4
correction circuit
data shifter arithmetic circuit
latch circuit
latch circuit
latch circuit
D0~D7
Shift register
EIO1
EIO2
Block Functions
Drive Circuit (2.1) circuit compares cross talk correction signals 240-bit drive circuit generates three voltage levels which drive panel. these three levels output corresponding pin, depending data latch circuit (2), correction signals (CC1 CC4), DISP signal. (CCI CC2) from external circuits present output, determines whether effective value increased cross talk. effective value increased, output level reset level. (2.2) circuit compares present output data next output data. there data changes waveform distortion correction signals (CC3 CC4), Correction Circuit This circuit corrects shadowing volume. output level reset level. reset period adjusted using CC4. correction needed depends each output pin.
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Sitronix
Latch Circuit 240-bit latch circuit latches data input from latch circuit (1), outputs latched data correction circuit drive circuit, falling edge each clock (CL1) pulse. Data Shifter Arithmetic Circuit Latch Circuit Shift Register
ST8624
80-bit shift register generates outputs data latch signals latch circuit falling edge each clock (CL2) pulse.
data shifter shifts destinations data output when 240-bit latch circuit latches 8-bit parallel data input pins, outputs latched data latch circuit both according timing generated shift register. necessary. arithmetic circuit performs operations data signal
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Sitronix
ST8624
Description (TCP)
1~240 266,242 267,241 265,243 264, SYMBOL Y1~Y240 V0L, VML, V1L, VDD, Logic power supply Display data latch signal. drive signal corresponding display data output falling edge this signal. 260~253 D0~D7 Display data latch signal. Display data latched falling edge this signal. Changes drive outputs When display data (Vdd level), drive output level selection level liquid-crystal display when (GND level), they non-selection level off, respectively. control signal switch data output destination. section Switching Data Output Destination. 262,249 EIO1 EIO2 level, EIO1 inputs chip enable signal EIO2 outputs chip enable signal; level, opposite occurs. Enable input: chip enable-input first ST8624 must fixed level, other chip-enable input pins must connected chip enable-output pins previous ST8624. Enable output: chip enable-output must connected chip enable-input next ST8624. 248,247 DISP CC1, DISP level sets drive outputs Y240 level. Rising/Falling cross talk correction signal. V1/V0 output reset level when CC1/CC2 high. 246,245 CC3, Waveform distortion non-selected/selected (black/white) data correction signal. present output (non-selected/selected) next output (nonselected/selected) reset level when CC3/CC4 high. power drive-level voltage. DESCRIPTION Either level output according combination signal display data when DISP Vdd. figure
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Sitronix
ST8624
Figure Drive Level Voltage
Figure Selection Drive Output Level
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Sitronix
Switching Data Output Destination
ST8624
output destination data latched signal switched left right. this time, input output enable signal pins also switched. figure
Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240
Enable input EIO1 Enable output EIO2
Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240
Enable input EIO2 Enable output EIO1
Figure Data Output Destination
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Sitronix
Operation Timing Figure shows 8-bit data-latch timing when GND; that when EIO1 EIO2 Vdd, EIO1 chip-enable input chip-enable output. When chip-enable output
ST8624
simultaneously latches bits data falling edge each pulse. When latched bits data, sets EIO2 signal low. When latched bits data, automatically stops enters standby state, initiating next ST8624, provided EIO2 connected EIO1 next ST8624
EIO2 chip-enable input.
When chip-enable signal input EIO1 pin, ST8624 first released from data-standby state, then, falling edge following pulse, released entirely from standby state starts latching data.
ST8624 output line data from Y240 pins falling edge each pulse. Data output from d240 from Y240 when GND, output from Y240, d240 from when
Line
d240
d233
EIO2 EIO2 EIO2 EIO2 (10)
ST8624 latch data ST8624 latch data ST8624 latch data ST8624 (10) latch data
Y240
Figure Data Latch Timing
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Sitronix
Correction Circuit ST8624 include shadowing correction circuits. There types shadowing: caused cross talk, other waveform distortion. both types, correction circuits CCI, CC2, improve image quality. (shadowing caused cross talk) When ruled line displayed noise occurs common level panel segment change solid background reverse. This because many segments display solid background simultaneously changed, affecting common level (creating cross talk). effective voltage section solid background becomes low. other hand, effective voltage section becomes high. Shadowing
ST8624
occurs corresponding sections different voltages. ST8624 compare cross talk correction signals present output, determine whether effective value increased cross talk. increased, output level reset which corrects effective voltages suppresses shadowing. Figure shows example cross talk-correction-signal external circuit. basic potentials comparator AV') corrected according shadowing level output correction while high. corrects rising cross talk, corrects falling cross talk.
white Corresponding section
Normally black panel
white
white
white
waveform waveform Shadowing section
white black black black black white
Figure
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2001/Sep/08
Sitronix
ST8624
Before correction Waveform section Effective voltage decreaced
After correction
waveform Noise
waveform
Waveform section
waveform
waveform VM+V VM-V' Effective voltage increaced
Effective voltage increaced
Figure Effective Voltage Correction
Power supply circuit Comparator power supply
Comparator
Figure External Circuit Example
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Sitronix
ST8624
(Normally black panel)
waveform black
reversed white black
white corresponding sections
waveform black white white black
Figure
When background displayed grayscale (for example, check ball pattern), many segment levels changed section section (b). effective voltage section becomes because distortion occurs segment output waveform driver panel impedance. other hand, effective voltage section becomes high because waveform changed only slightly. Shadowing occurs corresponding sections different voltages.
ST8624 compare present output data next output data. data changed, output level reset which corrects effective voltages (b). high width corrected according shadowing level output correction while high. corrects non-selected output (black background), corrects selected output (white background).
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Sitronix
Before correction Waveform section Effective voltage decreaced After correction
ST8624
waveform
waveform Effective voltage correction
Waveform section
waveform
waveform
data change
Figure Effective Voltage Correction
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Sitronix
ST8624
D0~D7
(m-1) (n-4) (n-3) (n-2) (n-1)
invalid
Latch circuit Latch circuit Compared result correction circuit output
reset reset reset reset
(Mn-1) Current output data (Mn-1) Current output data
((n) (Mn)) Next output data ((n) (Mn)) Next output data ((m) n-1)) ((n) (Mn)) caculated result
n-1) Current output data n-1) Current output data n-1) Current output data n-1) Current output data reset (correction)
Next output data Next output data Next output data Next output data
Figure Compared result Correction Circuit
correction circuit compares present output data (latch circuit (2)) next output data (latch circuit (1)). Depending compared result, circuit resets high width output without data change data non-selected output ((c) figure 12). circuit resets high width data selected output ((d) figure input after last valid data transferred. forcibly resets output high width ((a)
figure 12). forcibly resets output high width ((3,) figure 12). Therefore, shadowing caused waveform distortion corrected with (non-selected selected), shadowing caused cross talk corrected with direction). Note: high period from should matched with shadowing level.
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ST8624
COM1 VDD, AMP, MODE0, MODE1 MWS0~4 RESET COM3 VLL,R VEEL,R VHL,R VLCDL,R VML,R COM2
PANEL
480X240 MATRIX
Controller DISPOFF DIO1
COM240
X1~X240
X1~X240
ST8624
ST8624
EIO1 GND, EIO2 EIO1
Application circuit
DISP D0~D7
DISP D0~D7
V0L,R V0SL,R V1L,R V1SL,R VML,R
Power Supply Circuit
Sitronix
V0L,R V0SL,R V1L,R V1SL,R VML,R
VLCD
GND,
SEG478 SEG479 SEG480
SEG1 SEG2 SEG3
DISP D0~D3
COM238 COM239
0.12
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2001/Sep/08
ST8600
X1~X240
Sitronix
ST8624
Absolute Maximum Ratings
Item Power supply Logic circuit drive circuit Input voltage Input voltage Operating temperature Storage temperature Symbol Topr Tstg Ratings -0.3 +7.0 -0.3 +7.0 -0.3 +110 Unit Notes
Notes: used beyond above maximum ratings, permanently damaged. should always used within specified operating range normal operation prevent malfunctions degraded reliability. reference point Applies SHL, EIO1 pins. EIO2 Applies VML, VMR, VIL, pins. shown figure users should conform following turn-on/off sequence power signals. Otherwise, will malfunction will permanently damaged. addition, reliability will affected.
DISP CL1, CL2,
2.7V
2.7V
DISP
Input signal clock data
Signal undefined period initilization period least frame) (0ms: minimun specification)
Figure Turn Turn timing
0.12
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2001/Sep/08
Sitronix
Turning power Turn power order GND-Vdd, GND-V0, VM/V1. Then, ground DISP pin. forcibly outputs level DISPOFF function. Even input signal disturbed immediately after applied, DISPOFF function priority. Input specific signal initialize registers driver. initialization period must least frame. preparation normal display completed. Apply level DISP cancel DISPOFF function. this time, level pins must rise specific potential. Turning power
ST8624
procedure basically reverse that used turn power. Ground DISP pin. Turn power order VMN1 GND-V0. Ground Vdd, input signal. this time, level pins must fall Since DISPOFF function stops when falls output level other than Therefore, display failure occur when power turned
0.12
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2001/Sep/08
Sitronix
ST8624
Electrical Characteristics
Characteristics (Vdd V0-GND =3.5
Item. Input high-level voltage Input level voltage Output high- level voltage Output low-level voltage Symbol Applicable CL1, CL2, SHL, EIO1 EIO2 DISP 0.3Vcc Min. 0.7Vcc Typ. Max. Unit Conditions Notes
EIO1 EIO2 Y240,
Vcc-0.4
-0.4
Vi-Yj resistance
Y240, toY240 CL1, CL2, SHL,
Vdd-GND
Input leakage current Input leakage current Current consumption Current consumption Current consumption
IIL1
EIO1 EIO2 DISP
-5.0
IIL2
VML, VMR, andV1R
-100
V0-GND Vdd=3.0V fCL2=25MHz fCL1
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Sitronix
Item. Input high-level voltage Symbol Applicable CL1, CL2, SHL, EIO1 EIO2 DISP Input level voltage Output high- level voltage Output low-level voltage 0.3Vcc 0.7Vcc Min. Typ. Max. Unit
ST8624
Conditions Notes
Characteristics 2(Vdd= V0-GND Ta=-30
EIO1 EIO2
Vcc-0.4
-0.4
Y240,
Vi-Yj resistance
Y240, toY240 CL1, CL2, SHL,
Vdd-GND
Input leakage current Input leakage current(2) Current consumption Current consumption Current consumption
IIL1
EIO1 EIO2 DISP
-5.0
IIL2
VML, VMR, andV1R
-100
V0-GND
Vdd=5.0V fCL2=40MHz fCL1
Notes: Indicates resistance between pins Y1-Y240 voltage supply pins, when load current applied pin; defined under following conditions: 5.5V (V0+V1) should near level, should near middle voltage between should within range
0.25 which range within which RON, drive circuits output impedance, stable. figure Input output currents excluded. When CMOS input left floating, excess current flows from power supply through input circuit. avoid this, must used GND, respectively. Standby current. voltage each signal shown figure
0.12
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2001/Sep/08
Sitronix
ST8624
0.25
Figure Relationship between Driver-Output Waveforms Each Level Voltage
Segment voltage
Segment waveform
Common waveform
Common voltage VH(38.0V)
V0(5.0V) Vcc(3.3V) VM(3.0V) V1(1.0V) GND(0.0V) Vcc(3.3V) VM(3.0V) GND(0.0V)
VL(-32.0V) Normal display period Display-off period Normal display period Display-off period
Figure Signal Voltage
0.12
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Sitronix
Item Clock cycle time Clock high-level width Clock low-level width Clock high-level width Clock setup time Clock hold time Clock rise time Clock fall time Data setup time Data hold time setup time hold time Output delay time setup time hold time Symbol tCYC tCWH2 tCWL2 tCWH1 tSCL tHCL tpd1 tCCS tCCH Y240 CC4, CC4, Applicable Pins Max.
ST8624
Unit
Characteristics (Vdd=2.7 4.5V, V0-GND=3.5 5.5V, Ta=-30 +75°C)
Note: load must less than between EIO1 EIO2 connections ST8624
0.12
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Sitronix
Item Clock cycle time Clock high-level width Clock low-level width Clock high-level width Clock setup time Clock hold time Clock rise time Clock fall time Data setup time Data hold time setup time hold time Output delay time setup time hold time Symbol tCYC tCWH2 tCWL2 tCWH1 tSCL tHCL tpd1 tCCS tCCH Y240 CC4, CC4, Applicable Pins Max.
ST8624
Unit
Characteristics (Vdd 5.5V, V0-GND=3.5 5.5V, +75°C)
Note: load must less than between EIO1 EIO2 connections ST8624 output delay time connect load circuit shown figure
Test point
10pF
Figure Load Circuit Output Delay Time
0.12
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Sitronix
tCWH2 0.7Vcc 0.3Vcc 0.7Vcc 0.3Vcc tCWL2 tCYC
ST8624
tCWH1 0.7Vcc 0.3Vcc
tSCL
tHCL
0.3Vcc 0.7Vcc 0.3Vcc
0.3Vcc tpd1
Y(n)
0.8V0 0.2V1
Figure Characteristics
0.12
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Sitronix
Last-1 tCCH tCCS Last
ST8624
Correct waveform after fetches last data. Complete correction before data from next line output falling edge
Figure Characteristics
0.12
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Sitronix
ST8624
Diagram
ST8624
chip size 14660 chip height=660um substrate connect ground unit:
Name DUMMY_PAD DUMMY_PAD DUMMY_PAD DUMMY_PAD V0SL V0SL V1SL V1SL EIO1 EIO1 DOFFB DOFFB DUMMY_PAD
-7259.8 -7272.3 -7227.2 -7105.9 -6860.8 -6774.6 -6470.6 -6384.4 -6102.2 -6016.0 -5736.0 -5649.8 -5345.8 -5259.6 -4981.0 -4839.5 -4247.3 -4161.3 -3569.0 -3482.8 -3182.8 -3096.6 -2796.6 -2710.4 -2410.4 -2110.4 -2024.2 -1724.2 -1638.0 -1338.0 -1251.8 -954.3 -656.3 -570.1 -270.1 -183.9 116.1 416.1 502.3 802.3 888.5
365.2 257.1 -344.4 -344.4 -353.5 -353.5 -353.5 -353.5 -353.5 -353.5 -353.5 -353.5 -353.5 -353.5 -304.4 -304.4 -273.6 -273.6 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5
Name Y157 Y156 Y155 Y154 Y153 Y152 Y151 Y150 Y149 Y148 Y147 Y146 Y145 Y144 Y143 Y142 Y141 Y140 Y139 Y138 Y137 Y136 Y135 Y134 Y133 Y132 Y131 Y130 Y129 Y128 Y127 Y126 Y125 Y124 Y123 Y122 Y121 Y120 Y119 Y118 Y117
2183.2 2123.2 2063.2 2003.2 1943.2 1883.2 1823.2 1763.2 1703.2 1643.2 1583.2 1523.2 1463.2 1403.2 1343.2 1283.2 1223.2 1163.2 1103.2 1043.2 983.2 923.2 863.2 803.2 743.2 683.2 623.2 563.2 503.2 443.2 383.2 323.2 263.2 203.2 143.2 83.2 23.2 -36.8 -96.8 -156.8 -216.8
352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6
0.12
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Sitronix
Name EIO2 EIO2 DUMMY_PAD DUMMY_PAD DUMMY_PAD DUMMY_PAD V1SR V1SR V0SR V0SR DUMMY_PAD DUMMY_PAD DUMMY_PAD DUMMY_PAD Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 Y232 Y231 Y230 Y229 Y228 Y227 Y226 Y225 1193.7 1279.9 1579.9 1666.1 1966.1 2052.3 2358.3 2600.0 2867.6 3166.2 3252.4 3552.4 3638.6 3938.6 4024.8 4324.8 4411.0 4665.6 4807.1 5057.1 5329.4 5415.6 5715.8 5802.0 6082.0 6168.2 6450.4 6536.6 6836.8 6923.0 7126.5 7235.9 7262.5 7250.0 7163.2 7103.2 7043.2 6983.2 6923.2 6863.2 6803.2 6743.2 6683.2 6623.2 6563.2 6503.2 6443.2 6383.2 6323.2 6263.2 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -273.5 -285.6 -332.9 -332.9 -332.9 -332.9 -332.9 -332.9 -332.9 -332.9 -332.9 -332.9 -322.5 -322.5 257.1 365.2 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 Name Y116 Y115 Y114 Y113 Y112 Y111 Y110 Y109 Y108 Y107 Y106 Y105 Y104 Y103 Y102 Y101 Y100 -276.8 -336.8 -396.8 -456.8 -516.8 -576.8 -636.8 -696.8 -756.8 -816.8 -876.8 -936.8 -996.8 -1056.8 -1116.8 -1176.8 -1236.8 -1296.8 -1356.8 -1416.8 -1476.8 -1536.8 -1596.8 -1656.8 -1716.8 -1776.8 -1836.8 -1896.8 -1956.8 -2016.8 -2076.8 -2136.8 -2196.8 -2256.8 -2316.8 -2376.8 -2436.8 -2496.8 -2556.8 -2616.8 -2676.8 -2736.8 -2796.8 -2856.8 -2916.8 -2976.8 -3036.8 -3096.8 -3156.8 -3216.8 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6
ST8624
0.12
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Sitronix
Name Y224 Y223 Y222 Y221 Y220 Y219 Y218 Y217 Y216 Y215 Y214 Y213 Y212 Y211 Y210 Y209 Y208 Y207 Y206 Y205 Y204 Y203 Y202 Y201 Y200 Y199 Y198 Y197 Y196 Y195 Y194 Y193 Y192 Y191 Y190 Y189 Y188 Y187 Y186 Y185 Y184 Y183 Y182 Y181 Y180 Y179 Y178 Y177 Y176 Y175 6203.2 6143.2 6083.2 6023.2 5963.2 5903.2 5843.2 5783.2 5723.2 5663.2 5603.2 5543.2 5483.2 5423.2 5363.2 5303.2 5243.2 5183.2 5123.2 5063.2 5003.2 4943.2 4883.2 4823.2 4763.2 4703.2 4643.2 4583.2 4523.2 4463.2 4403.2 4343.2 4283.2 4223.2 4163.2 4103.2 4043.2 3983.2 3923.2 3863.2 3803.2 3743.2 3683.2 3623.2 3563.2 3503.2 3443.2 3383.2 3323.2 3263.2 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 Name -3276.8 -3336.8 -3396.8 -3456.8 -3516.8 -3576.8 -3636.8 -3696.8 -3756.8 -3816.8 -3876.8 -3936.8 -3996.8 -4056.8 -4116.8 -4176.8 -4236.8 -4296.8 -4356.8 -4416.8 -4476.8 -4536.8 -4596.8 -4656.8 -4716.8 -4776.8 -4836.8 -4896.8 -4956.8 -5016.8 -5076.8 -5136.8 -5196.8 -5256.8 -5316.8 -5376.8 -5436.8 -5496.8 -5556.8 -5616.8 -5676.8 -5736.8 -5796.8 -5856.8 -5916.8 -5976.8 -6036.8 -6096.8 -6156.8 -6216.8 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6
ST8624
0.12
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Sitronix
Name Y174 Y173 Y172 Y171 Y170 Y169 Y168 Y167 Y166 Y165 Y164 Y163 Y162 Y161 Y160 Y159 Y158 3203.2 3143.2 3083.2 3023.2 2963.2 2903.2 2843.2 2783.2 2723.2 2663.2 2603.2 2543.2 2483.2 2423.2 2363.2 2303.2 2243.2 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 Name -6276.8 -6336.8 -6396.8 -6456.8 -6516.8 -6576.8 -6636.8 -6696.8 -6756.8 -6816.8 -6876.8 -6936.8 -6996.8 -7056.8 -7116.8 -7176.8 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6 352.6
ST8624
Gold bump information (um): Output Input Dummy Dummy 62.0 60.0 62.0 85.0 5~71 1,3,4,72,73,75 2,74 315~76 name Y1~Y240 (input) DUMMY_PAD DUMMY_PAD Area 2790 3480 5270 5270
Bump height 18um, strength
0.12
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2001/Sep/08
Sitronix
Appendix: Version 0.11.correct some typing error Version 0.12 .add pin1 information, chip height data, application circuit
ST8624
0.12
28/28
2001/Sep/08

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