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Sitronix
PRELIMINARY Notice: This final specification. Some parameters subject change.
ST2100
Microcontroller with bytes
FEATURES
8-bit static pipeline ROM: bits RAM: bits External memory control bits Operation voltage 2.4V CMOS Bi-directional programmable pins Hardware de-bounce option input port programmable PULL-UP input port Timer/Counter 8-bit timer/16-bit event counter 8-bit BASE timer powerful interrupt sources External interrupt (edge trigger) TIMER0 interrupt TIMER1 interrupt BASE timer interrupt PORTA[7~0] interrupt (transition trigger) reload interrupt 128-level deep stack Dual clock source OSCX: Crystal oscillator 32.768K OSCI: oscillator 500K OSCI,XIO: Resonator 500K (code option) Built-in oscillator with warm-up timer control driver area 5376 (48x112) dots 4096 (32X128) dots Programmable Sound Generator (PSG) includes Dual Tone generator (including Noise generator) level volume sound effect generator Digital speech tone Three power down modes WAI0 mode WAI1 mode mode
GENERAL DESCRIPTION
ST2100 single chip micro-controller designed with CMOS silicon gate technology. This single chip micro-controller useful business equipment other consumer applications. integrates with 8-bit core, SRAM, timer, driver, port mask program ROM. This chip built-in dual-oscillator enhance chip performance.
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Sitronix DIAGRAM
ST2100
DATAOUT
RESETB
BLANKB
OSCXO
OSCXI
OSCI
POFFB LOAD
EXT_MODE EXT_MEM CSB/CSB1 A22/CSB0
ST2100
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Sitronix BLOCK DIAGRAM
ST2100
PORT
TIMER
CLOCK GENERATOR
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Description 16,29,53,66 17-24 25-28,30-33 34-41 55-64,67-78 45-52 14,15 Designation RESET PORTA[0-7] PORTB [0-7] PORTC [0-7] A[0-21] A[22]/CSB0 D[0-7] CSB/CSB1 EXT_MEM OSCXO, OSCXI OSCI TEST LOAD POFFB DATAOUT BLANKB EXT_MODE reset input (active low) Ground Input chip sub-strate Description
ST2100
Programmable I/O, Transition Interrupt(edge active), INTX Interrupt Timer Prescaler PRE16 clock source programmable I/O,PSG output, output programmable Address expand memory Address expand memory Expand memory chip select signal Data expand memory Read write signal expand memory Expand memory chip select signal External memory enable/disable control signal Power supply OSCX pin. 32768Hz crystal used. oscillator pin, connected external resistor Test chip test, normal First line mark common signal(to driver ST2101) Load data into Segment common driver's data latch driver ST2101) alternating signal (connect driver ST2101) Control power generator voltage pumping circuit driver ST2101) OSCI,XIO resonator 500K (code option) Shift clock pulse segment driver driver ST2101) Output serial data segment driver driver ST2101) display turn directly external control. When BLANKB low, display automatically blank state driver ST2101). Select {CSB,A[22]} {CSB0,CSB1} Power supply
Legend: input, output, input/output, power.
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ST2100
Accumulator Index Register Index Register Program Counter Stack Pointer
REGISTER MODEL
microprocessor perform stack manipulations under direction either program interrupts (IRQ). stack allows simple implementation nested subroutines multiple level interrupts. stack pointer initialized user's software.
Accumulator
accumulator general purpose 8-bit register which stores results most arithmetic logic operations. addition, accumulator usually contains data words used these operations.
Program Counter (PC)
Index Registers (X,Y)
There 8-bit Index Registers which used count program steps provide index value used generating effective address. When executing instruction which specifies indexed addressing, fetches code base address, modifies address adding index register prior performing desired operation. post-indexing indirect addresses possible.
16-bit Program Counter register provides address which step microprocessor through sequential program instructions. Each time microprocessor fetches instruction from program memory, lower byte program counter (PCL) placed low-order bits address higher byte program counter (PCH) placed high-order bits. counter increment each time instruction data fetched from program memory.
Status Register
Stack Pointer
stack Pointer 8-bit register which used control addressing variable-length stack. It's range from 100H 1FFH total bytes (128 level deep). stack pointer automatically increment decrement under control
8-bit Processor Status Register contains seven status flags. Some flags controlled program, others controlled both program CPU. instruction contains member conditional branch instructions which designed allow testing these flags. Refer TABLE 5-1:
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TABLE 5-1:STATUS REGISTER
ST2100
Signed flag arithmetic Negative Positive Overflow signed Arithmetic flag Negative Positive interrupt flag interrupt occur interrupt occur Decimal mode flag Decimal mode Binary mode Interrupt disable flag Interrupt disable Interrupt enable Zero flag Zero zero Carry flag Carry carry
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Sitronix MEMORY CONFIGURATION
Memory
ST2100
ST2100 total bytes bytes inside. This used data memory program memory. Program Bank Pointer Register Data Bank Pointer Register. data address area ST2100 from $8000 $FFFF (32K bytes) program address from $4000 $7FFF(16K bytes).
0000 003F 0040 007F 0080
Control Register Region
000000~ 003FFF
004000~ 007FFF 008000~ 00BFFF
SRAM Region 0FFF 1000 12FF 1300 3FFF 4000 Mapping Region
00C000~ 00FFFF
Program Region (PPR) bytes
3F8000~ 3FBFFF
3FC000~ 3FFFFF 7FFF 8000
Data Region (DRR) bytes
7F0000~ 7F7FFF
7F8000~ 7FFFFF FFFF Memory Mapping Interrupt Vector Region Bytes
6.2.1
Bank Description
TABLE 6-1: CONTROL REGISTERS ($31~$32) Bit7 Bit6 Bit5 Bit4 Bit3 PRR[7] PRR[6] PRR[5] PRR[4] PRR[3] DRR[7] DRR[6] DRR[5] DRR[4] DRR[3]
Setting corresponding value register PRR(program memory) DRR(data memory) when user want different memory bank. Address Register Bit2 PRR[2] DRR[2] Bit1 PRR[1] DRR[1] Bit0 PRR[0] DRR[0]
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6.2.2 Memory Modes
internal bytes memory enabled disabled selecting input level EXT_MEM. When EXT_MEM equals "1", internal memory enabled. This normal option ST2100 common products. When EXT_MEM equals "0", internal memory disabled first bytes area will mapped external. This mode code generation when developing system using real-chip board.
ST2100
external memory accessed signals: CSB/CSB1, A22/CSB0, A[21:0], D[7:0]. kinds external memory mapping further defined EXT_MODE. Refer TABLE 6-2: memory modes mapping both internal external memory.
TABLE 6-2: Memory Modes External Address Mapping Internal External Memory Memory EXT_MODE CSB/CSB1 A22/CSB0 1~2MB 3~8MB 3~6MB 000000 200000~7FFFFF 200000~5FFFFF Address CSB0 Address ~1FFFFF
(CSB,A[22:0]=1) 3~4MB 5~6MB 7~8MB 3~4MB 5~6MB
CSB/CSB1
7~8MB 600000~7FFFFF
CSB1 Address 7~8MB
EXT_MEM Disable
1~8MB 000000~7FFFFF
Address 1~2MB 3~4MB 5~6MB 7~8MB
1~4MB 000000~3FFFFF
CSB0 Address 1~2MB 3~4MB
5~8MB 400000~7FFFFF
CSB1 Address 5~6MB 7~8MB
5FFFFF
DRR=FF
7FFFFF
DRR=FF
Expand Memory 1FFFFF
There upper Bytes
Expand Memory 3FFFFF PRR=FF,DRR=7F
PRR=FF,DRR=7F
000000 1FFFFF Internal 000000 EXT_MEM=1
PRR=80,DRR=40 PRR=7F,DRR=3F
PRR=0,DRR=0
000000 EXT_MEM=0 Disable internal Bytes
PRR=0,DRR=0
FIGURE 6-1: Bank Registers Memory Mapping
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mapping includes Control Registers, Data Stack RAM.
ST2100
Default
1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -000 0000 -000 0000 0000 0000 0000 0000 0000 -000 0000 0000 0000 0000 0000 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 0000 ???? ???? ???? ???? ???? ???? ???? ???? 0000 0000 -000 0000 0000
Address Name
$000 $001 $002 $008 $009 $00A $00F $010 $011 $012 $013 $014 PMCR PSG0L PSG0H PSG1L PSG1H
PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] PC[7] PC[6] PC[5] PC[4] PC[3] PC[2] PC[1] PC[0] PCA[7] PCA[6] PCA[5] PCA[4] PCA[3] PCA[2] PCA[1] PCA[0] PCB[7] PCB[6] PCB[5] PCB[4] PCB[3] PCB[2] PCB[1] PCB[0] PCC[7] PCC[6] PCC[5] PCC[4] PCC[3] PCC[2] PCC[1] PCC[0] PULL PDBN INTEG PSGO PSGB PSG0[7] PSG0[6] PSG0[5] PSG0[4] PSG0[3] PSG0[2] PSG0[1] PSG0[0] PSG0[11] PSG0[10] PSG0[9] PSG0[8] PSG1[7] PSG1[6] PSG1[5] PSG1[4] PSG1[3] PSG1[2] PSG1[1] PSG1[0] PSG1[11] PSG1[10] PSG1[9] PSG1[8] DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] PCK[2] PCK[1] PCK[0] PRBS C1EN C0EN DACE=0 $016 PSGC PCK[2] PCK[1] PCK[0] DMD[1] DMD[0] DACE=1 $017 VOL1[3] VOL1[2] VOL1[1] VOL1[0] VOL0[3] VOL0[2] VOL0[1] VOL0[0] $021 BBTM[3] BTM[2] BTM[1] BTM[0] PRS[7] PRS[6] PRS[5] PRS[4] PRS[3] PRS[2] PRS[1] PRS[0] $023 SRES SENA SENT $024 *R/W T0M[5] T0M[4] T0M[2] T0M[1] T0M[0] $025 T0C[7] T0C[6] T0C[5] T0C[4] T0C[3] T0C[2] T0C[1] T0C[0] $026 *R/W T1M[4] T1M[3] T1M[2] T1M[1] T1M[0] $027 T1C[7] T1C[6] T1C[5] T1C[4] T1C[3] T1C[2] T1C[1] T1C[0] $028 DMSL DMS[7] DMS[6] DMS[5] DMS[4] DMS[3] DMS[2] DMS[1] DMS[0] $029 DMSH DMS[15] DMS[14] DMS[13] DMS[12] DMS[11] DMS[10] DMS[9] DMS[8] $02A DMDL DMD[7] DMD[6] DMD[5] DMD[4] DMD[3] DMD[2] DMD[1] DMD[0] $02B DMDH DMD[15] DMD[14] DMD[13] DMD[12] DMD[11] DMD[10] DMD[9] DMD[8] $02C DCNTL DCNT[7] DCNT[6] DCNT[5] DCNT[4] DCNT[3] DCNT[2] DCNT[1] DCNT[0] DMAM DCNT[11] DCNT[10] DCNT[9] DCNT[8] $02D DCNTH $030 XSEL OSTP XSTP XBAK WSKP WAIT $031 PRR[7] PRR[6] PRR[5] PRR[4] PRR[3] PRR[2] PRR[1] PRR[0] $032 DRR[7] DRR[6] DRR[5] DRR[4] DRR[3] DRR[2] DRR[1] DRR[0] $033 DMR[7] DMR[6] DMR[5] DMR[4] DMR[3] DMR[2] DMR[1] DMR[0] $039 LCFG LCFG[7] LCFG[6] LCFG[5] LCFG[4] LCFG[3] LCFG[2] LCFG[1] LCFG[0] $03A LCTL LPWR BLANK CTR[3] CTR[2] CTR[1] CTR[0] $03B LCK[2] LCK[1] LCK[0] $03C IREQ IRBT IRPT IRT1 IRT0 IRDAC $03E IENA *R/W IEBT IEPT IET1 IET0 IEDAC These registers read written real chip, only written Emulation Board.
Note: Some addresses area, $3~$7, $B~$E, $15, $18~$20, $22, $2E~$2F, $34~$38, $3D, $3F, used. User should never undefined addresses bits. instructions write-only registers, such RMBx, SMBx. Must initial PRR, registers when system reset.
6.3.1
DATA ($0080~$0FFF)
DATA organized bytes from $0080~$0FFF.
6.3.2
STACK ($0100~$01FF)
STACK organized bytes. provides maximum 128-level subroutine stacks used data memory.
6.3.3
($1000~$12FF)
Resident LCD-RAM, accessible through write read instructions, 112*48 128*32 display. Note that this area also used data memory. Refer section 13.4.1 about detail usage.
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Sitronix INTERRUPTS
Interrupt description
ST2100
Instruction `BRK' will cause software interrupt when interrupt disable flag cleared. Hardware will push `PC', Register stack interrupt disable flag (I). Program counter then will loaded with vector from locations $7FFE $7FFF. RESET positive transition RESET will then cause initialization sequence begin. After system been operating, this line least clock cycles will cease ST2012 activity. When positive edge detected, there initialization sequence lasting clock cycles. Then interrupt mask flag set, decimal mode cleared program counter will loaded with restart vector from locations $7FFC (low byte) $7FFD (high byte). This start location program control. This input should high normal operation. INTX interrupt (INTX interrupt request) flag will while INTX edge signal occurs. INTX interrupt will active once (INTX interrupt enable) set, interrupt mask flag cleared. Hardware will push `PC', Register stack interrupt mask flag (I). Program counter will loaded with INTX vector from locations $7FF8 $7FF9. interrupt IRDAC (DAC interrupt request) flag will while reload signal occurs. Then interrupt will executed when IEDAC (DAC interrupt enable) set, interrupt mask flag cleared. Hardware will push `PC', Register stack interrupt mask flag (I). Program counter will loaded with vector from locations $7FF6 $7FF7.
interrupt IRT0 (TIMER0 interrupt request) flag will while overflows. With IET0 (TIMER0 interrupt enable) being set, interrupt will executed, interrupt mask flag will cleared. Hardware will push `PC', Register stack interrupt mask flag (I). Program counter will loaded with vector from locations $7FF4 $7FF5. interrupt IRT1 (TIMER1 interrupt request) flag will while overflows. With IET1 (TIMER1 interrupt enable) being set, interrupt will executed, interrupt mask flag will cleared. Hardware will push `PC', Register stack interrupt mask flag (I). Program counter will loaded with vector from locations $7FF2 $7FF3. interrupt IRPT (Port-A interrupt request) flag will while Port-A transition signal occurs. With IEPT interrupt enable)being set, interrupt will execute, interrupt mask flag will cleared. Hardware will push `PC', Register stack interrupt mask flag (I). program counter will loaded with vector from locations $7FF0 $7FF1. interrupt IRBT (Base timer interrupt request) flag will when Base Timer overflows. interrupt will executed once IEBT interrupt enable) interrupt mask flag cleared. Hardware will push `PC', Register stack interrupt mask flag (I). Program counter will loaded with vector from locations $7FEE $7FEF. interrupt vectors address listing TABLE 7-1:
TABLE 7-1:PREDEFINED VECTORS INTERRUPT
Name
RESET INTX
Signal
Internal External External Internal INT/EXT INT/EXT External Internal
Vector address
$7FFF,$7FFE $7FFD,$7FFC $7FFB,$7FFA $7FF9,$7FF8 $7FF7,$7FF6 $7FF5,$7FF4 $7FF3,$7FF2 $7FF1,$7FF0 $7FEF,$7FEE
Priority
RESET vector Reserved
Comment
Software operation vector
edge interrupt Reload data interrupt Timer0 interrupt Timer1 interrupt Port-A transition interrupt Base Timer interrupt
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Interrupt request clear
ST2100
Interrupt request flag cleared methods. write IENA, other initiate interrupt service
routine when interrupt occurs. Hardware will automatically clear Interrupt flag.
Address Name
$03C IREQ
TABLE 7-2:INTERRUPT REQUEST REGISTER (IREQ)
IRBT IRPT IRT1 IRT0 IRDAC
Default
0000
IRBT: Base Timer Interrupt Request Time base interrupt occurs Time base interrupt doesn't occur IRPT: Port-A Interrupt Request Port-A transition interrupt occurs Port-A transition interrupt doesn't occur IRT1: Timer1 Interrupt Request Timer1 overflow interrupt occurs Timer1 overflow interrupt doesn't occur IRT0: Timer0 Interrupt Request Timer0 overflow interrupt occurs Timer0 overflow interrupt doesn't occur IRDAC: reload Interrupt Request time interrupt occurs time interrupt doesn't occur IRX: INTX Interrupt Request INTX edge interrupt occurs INTX edge interrupt doesn't occur
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Address Name
$03E IENA
ST2100
*R/W
TABLE 7-3:INTERRUPT ENABLE REGISTER (IENA)
IEBT IEPT IET1 IET0 IEDAC
Default
0000
IEBT: Base Timer Interrupt Enable Time base interrupt enable Time base interrupt disable IEPT: Port-A Interrupt Enable Port-A transition interrupt enable Port-A transition interrupt disable IET1: Timer1 Interrupt Enable Timer1 overflow interrupt enable Timer1 overflow interrupt disable IET0: Timer0 Interrupt Enable Timer0 overflow interrupt enable Timer0 overflow interrupt disable IEDAC: reload Interrupt Enable time interrupt enable time interrupt disable IEX: INTX Interrupt Enable INTX edge interrupt enable INTX edge interrupt disable
These registers read written real chip, only written Emulation Board.
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General function
TABLE 8-1:I/O DESCRIPTION
PORT NAME NAME PA0/INTX TYPE FEATURE
ST2100
ST2100 three ports, PORT-A, PORT-B PORT-C. ST2100 provides maximum pins. detail assignment, please refer TABLE 8-1:
PORT
Programmable input/output
PORT
Programmable input/output
PORT
Programmable input/output
These ports have same feature control method their control register refer TABLE 8-2:
TABLE 8-2:PORT Control register
ress ister bit7 PCA7 PCB7 PCC7 PULL bit6 PCA6 PCB6 PCC6 PDBN bit5 PCA5 PCB5 PCC5 INTEG bit4 PCA4 PCB4 PCC4 bit3 PCA3 PCB3 PCC3 bit2 PCA2 PCB2 PCC2 bit1 PCC1 bit0 PCA0 PCB0 PCC0 direction control direction control direction control control
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8.2.1
ST2100
PORT-A
Port description
programmable pull-up MOS, interrupt de-bounce interrupt edge selection(PA0 only).
Port bit-programmable bi-direction port, which controlled register. provides user with
Address Name
$000 $008 $00F $03C $03E PMCR IREQ IENA
TABLE 8-3:SUMMARY PORT-A REGISTERS
PA[7] PCA[7] PULL PA[6] PCA[6] PDBN PA[5] PCA[5] INTEG IRBT IEBT PA[4] PCA[4] IRPT IEPT PA[3] PCA[3] IRT1 IET1 PA[2] PCA[2] IRT0 IET0 PA[1] PCA[1] PSG0 IRDAC IEDAC
PA[0] PCA[0] PSGB
Default
1111 1111 0000 0000 0000 0000
8.2.2
PORT-A control
output mode input mode.
Direction Port controlled PCA. Every PCA[7~0] mapped direction PA[7~0] correspondingly, with
Address Name
$008 7~0:
TABLE 8-4:PORT-A CONTROL REGISTER (PCA)
PCA[7] PCA[6] PCA[5] PCA[4] PCA[3] PCA[2] PCA[1]
PCA[0]
Default
0000 0000
PCA[7~0] Port directional bits Output mode Input mode
8.2.3
PORT PULL-UP OPTION
PULL(PMCR[7]) PORT CONTROL REGISTER PORT DATA REGISTER DATA INPUT RD_INPUT
PORT contains pull-up transistors. PULL control (PMCR[7]) controls on/off pull-up simultaneously. on/off every pull-up transistor will controlled port data register (PA) pull-up will enabled with data disable with data "0". Please refer FIGURE 8-1:
PULL-UP PMOS
FIGURE 8-1: Port-A Configuration Function Block Diagram
Address Name
$00F PMCR
TABLE 8-5:PORT CONDITION CONTROL REGISTER (PMCR)
PULL PDBN INTEG PSG0 PSGB
Default
PULL Enable pull-up function enable pull-up function disable pull-up function PDBN Enable Port-A interrupt de-bounce de-bounce Port-A interrupt de-bounce Port-A interrupt INTEG INTX interrupt edge select rising edge falling edge
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8.2.4 Port-A interrupt
Port-A, programmable I/O, used port interrupt when input mode. edge transition Port-A input will generate interrupt request. last state Port-A must kept before transition this accomplished reading Port-A. Operating Port-A interrupt step step
ST2100
When programmer enables INTX interrupts, trigger occur. INTX interrupts will therefore happen sequentially. Please refer FIGURE 8-1:
input mode. Read Port-A. Clear interrupt request flag (IRPT). interrupt enable flag (IEPT). Clear interrupt disable flag (I). Read Port-A before `RTI' instruction INT-Subroutine.
Example #$FF RMB4 <IREQ SMB4 <IENA INT-SUBROUTINE
;Set input mode. PULL-UP. ;Keep last state. ;Clear flag. ;Enable INT.
;Keep last state.
FIGURE 8-2: Port Interrupt Logic Diagram
RDPA PA[0] PCA[0] PA[1] PCA[1] PA[2] PCA[2] PA[3] PCA[3] XNOR2 PCA[7] XNOR2 PCA[6] PA[7] XNOR2 XNOR2 PCA[5] PA[6] XNOR2 XNOR2 PCA[4] PA[5] XNOR2 PA[4] XNOR2
PTIR High Level Interrupt NAND8
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8.2.5 Port-A interrupt debounce
ST2100ST2100 hardware debounce option Port-A interrupt. debounce will enabled with disable with PDBN. debounce will active when Port-A transition occurs, PDBN enable OSCX enable.
ST2100
debounce time OSCX cycles(about ms). Refer TABLE 9-6.
TABLE 8-6:PORT CONDITION CONTROL REGISTER (PMCR) Address Name
$00F PMCR
PULL
PDBN
INTEG
PSG0
PSGB
Default
PDBN Enable Port-A interrupt de-bounce de-bounce Port-A interrupt de-bounce Port-A interrupt
8.2.6
PA0/INTX
When programmer enables INTX interrupts, trigger will occur. Both INTX interrupts will happen sequentially. Pelase refer operating steps.
used external interrupt input(INTX). Falling Rising edge controlled INTEG(PMCR[5]) external interrupt with falling edge rising edge. Please refer Figure 9-3. Operating INTX interrupt step step into input mode. (PCA[0]) Select edge level. (INTEG) Clear INTX interrupt request flag. (IRX) INTX interrupt enable bits. (IEX) Clear interrupt mask flag (I).
Example RMB0 SMB5 RMB0 SMB0
<PCA <PMCR <IREQ <IENA
;Set input mode. ;Rising edge. ;Clear flag. ;Enable INTX interrupt.
FIGURE 8-3: INTX Logic Diagram
PMCR[5] 0/INTX
Falling Edge Interrupt
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8.3.1
ST2100
PORT-B PORT-C
General function
user with bit-programmable pull-up sound output port separately.
Port Port-C programmable bi-direction port, which controlled registers. also provides
Address Name
$001 $002 $009 $00A $00F PMCR
TABLE 8-7:SUMMARY PORT-B PORT-C REGISTERS
PB[7] PC[7] PCB[7] PCC[7] PULL PB[6] PC[6] PCB[6] PCC[6] PDBN PB[5] PC[5] PCB[5] PCC[5] INTEG PB[4] PC[4] PCB[4] PCC[4] PB[3] PC[3] PCB[3] PCC[3] PB[2] PC[2] PCB[2] PCC[2] PB[1] PC[1] PCB[1] PCC[1] PSG0 PB[0] PC[0] PCB[0] PCC[0] PSGB
Default
1111 1111 0000 0000 1111 1111 0000 0000
8.3.2
Input/Output control
direction PB[7~0] PC[7~0]) correspondingly, with output mode, input mode.
Direction Port-B Port-C) controlled PCC). Every PCB[7~0] PCC[7~0]) mapped into
Address Name
$009 7~0:
TABLE 8-8:PORT-B CONTROL REGISTER (PCB)
PCB[7] PCB[6] PCB[5] PCB[4] PCB[3] PCB[2] PCB[1]
PCB[0]
Default
0000 0000
PCB[7~0] Port-B directional bits Output mode Input mode
Address Name
$00A 7~0:
TABLE 8-9:PORT-C CONTROL REGISTER (PCC)
PCC[7] PCC[6] PCC[5] PCC[4] PCC[3] PCC[2] PCC[1]
PCC[0]
Default
0000 0000
PCC[7~0] Port-C directional bits Output mode Input mode
8.3.3
PORT-B PORT-C PULL-UP OPTION
PULL(PMCR[7]) PORT CONTROL REGISTER PCB,PCC PORT DATA REGISTER PB,PC DATA INPUT RD_INPUT PULL-UP PMOS
This port contains pull-up transistors which controlled software enabled disabled with with accordingly data port data register (PB,PC) when used input. PULL control PMCR also controls ON/OFF pull-up simultaneously. Please refer
FIGURE 9-4: Port-B Port-C Configuration Function Block Diagram
TABLE 8-10:PORT CONDITION CONTROL REGISTER (PMCR)
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Address Name
$00F PMCR
ST2100
PULL
PDBN
INTEG
PSG0
PSGB
Default
PULL Enable pull-up functions enable pull-up function disable pull-up function PSGO output enable data output output mode normal PSGB inverse signal output enable inverse data output output mode normal
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Sitronix OSCILLATOR
ST2100 with dual-clock system. Programmer choose between OSC(RC) OSCX(32.768kHz). both clock source through program. system clock(SYSCK) also switched between OSCX. will switch with OSCX will switch with XSEL. Whenever system
ST2100
clock switch, warm-up cycles occur same time. That confirm SYSCK really switched when read XSEL bit. driver, Timer1, Base Timer utilize these clock sources well.
TABLE 9-1:SYSTEM CONTROL REGISTER (SYS) Address Name
$030
XSEL
OSTP
XSTP
XBAK
WSKP
WAIT
Default
0000
XSEL System clock (SYSCK) select (write) confirm (read) OSCX OSTP stop control disable enable XSTP OSCX stop control disable OSCX enable OSCX XBAK OSCX driver heavy load OSCX normal load OSCX heavy load WSKP System warm-up control warm-up oscillation cycles warm-up oscillation cycles WAIT WAI-0 WAI-1mode select (Refer POWER DOWN MODE) instruction causes chip enter WAI-1 mode instruction causes chip enter WAI-0 mode
Note: XSEL(SYS[7]) will show which real working mode when read. System warm-up oscillation cycles when system clock (SYSCK) change power reset.
MUX2 OSCX OUTPUT Frequency divided SYSCK
XSEL
FIGURE 9-1: System Clock Diagram
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Sitronix TIMER EVENT COUNTER
10.1 Prescaller
10.1.1 Function Description
ST2100 three timers: Base timer, Timer Timer with pre-scaler PRES PREW. There clock
ST2100
sources PRES clock source(OSCX) PREW. Refer FIGURE 10-1:
Address Name
$021 B
TABLE 10-1:SUMMARY TIMER REGISTERS
Default
BTM[3] BTM[2] BTM[1] BTM[0] 0000 PRS[7] PRS[6] PRS[5] PRS[4] PRS[3] PRS[2] PRS[1] PRS[0] 0000 0000 $023 SRES SENA SENT $024 T0M[5] T0M[4] T0M[2] T0M[1] T0M[0] -000 *R/W $025 T0C[7] T0C[6] T0C[5] T0C[4] T0C[3] T0C[2] T0C[1] T0C[0] 0000 0000 $026 *R/W T1M[4] T1M[3] T1M[2] T1M[1] T1M[0] 0000 $027 T1C[7] T1C[6] T1C[5] T1C[4] T1C[3] T1C[2] T1C[1] T1C[0] 0000 0000 $030 XSEL OSTP XSTP XBAK WSKP WAIT 0000 $03C IREQ IRBT IRPT IRT1 IRT0 IRDAC 0000 $03E IENA *R/W IEBT IEPT IET1 IET0 IEDAC 0000 These registers read written real chip, only written Emulation Board.
PRES SYSCK INTX SENT SENA SRES-PULSE ENABLE CLEAR OUTPUT TCLK
TCLK/65536 TCLK/32768 TCLK/8192 TCLK/2048 TCLK/256 TCLK/32 TCLK/8 TCLK/2
TIMER
BASE TIMER
PREW OSCX/256 OSCX/128 OSCX RESET RESET OUTPUT OSCX/64 OSCX/32 OSCX/16 OSCX/4
TIMER
FIGURE 10-1: Prescaler Timers
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10.1.2 PRES
ST2100
prescaler PRES 8-bits counter shown Figure 11-6. Which provides four clock sources base timer timer1, controlled register PRS. instruction read toward will bring content PRES instruction write toward will reset, enable select clock sources PRES. When user external interrupt input PRES event counter, combining PRES Timer1 will 16bit-event counter.
Address Name
$023
TABLE 10-2:PRESCALER CONTROL REGISTER (PRS)
PRS[7] SRES PRS[6] SENA PRS[5] SENT PRS[4] PRS[3] PRS[2] PRS[1]
PRS[0]
Default
0000 0000
READ 7~0: PRS[7~0] PRES counter WRITE SRES Prescaler Reset Write reset prescaler (PRS[7~0]) SENA Prescaler enable Disable prescaler counting Enable prescaler counting SENT Clock source(TCLK) selection prescaller PRES Clock source from system clock "SYSCK" Clock source from external events "INTX"
10.1.3 PREW
prescaler PREW 8-bits counter shown Figure 11-6. PREW provides four clock source base timer timer1. stops counting only OSCX stops hardware reset occurs.
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10.2 Base timer
10.2.1 Function Description
ST2100
Base timer 8-bit counting timer. When overflows from $00, timer interrupt request IRBT will generated. Please refer FIGURE 10-2:
TCLK/65536 TCLK/32768 TCLK/8192 TCLK/2048 PRES TCLK/256 TCLK/32 TCLK/8 TCLK/2 BTM[2~0] MUX4-1 OSCX/256 OSCX/64 PREW OSCX/16 OSCX/4 BTM[1~0] BTM[3] Counter CLOCK IRBT
FIGURE 10-2: Structure Base Timer
10.2.2 Clock source control Base TimerSeveral clock sources selected Base Timer. Please refer TABLE 10-3: TABLE 10-3:CLOCK SOURCE BASE TIMER BTM[2] BTM[1] BTM[0] Base Timer source clock
STOP TCLK 65536 TCLK 32768 TCLK 8192 TCLK 2048 TCLK TCLK TCLK TCLK OSCX OSCX OSCX OSCX
SENA
BTM[3]
TCLK will stop when written SENA(PRS[6]).
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10.3 Timer
ST2100
10.3.1 Timer0 descriptionThe Timer0 8-bit counter. used timer event counter. T0C($25) real time read/write counter. When overflow from $00, timer interrupt request IRT0 will
generated. Timer0 will stop counting when system clock stops. Please refer FIGURE 10-3:
TCLK/65536 TCLK/32768 TCLK/8192 TCLK/2048 TCLK/256 TCLK/32 TCLK/8 TCLK/2 T0M[2~0] SYSCK
Counter T0M[4] T0M[5] Flip-Flop CLOCK Auto Reload Enable IRT0
PRES
FIGURE 10-3: Timer0 Structure Diagram
10.3.2 Clock source control Timer0Several clock source chosen from Timer0. It's very important that Timer0 keep counting long SYSCK
stays active. Refer TABLE 10-4:
TABLE 10-4:The clock source selected from system sources.
Clock Source TCLK/65536 TCLK/32768 TCLK/8192 TCLK/2048 TCLK/256 TCLK/32 TCLK/8 TCLK/2
T0M[4] Control automatic reload operation auto reload Auto reload T0M[5] Control Timer enable/disable Disable counting Enable counting SENA Prescaler enable TCLK stop TCLK counting
Address Name
$025 7-0:
TABLE 10-5:TIMER0 COUNTING REGISTER (T0C)
T0C[7] T0C[6] T0C[5] T0C[4] T0C[3] T0C[2] T0C[1]
T0C[0]
Default
0000 0000
T0C[7-0] Timer0 counter register
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10.4 Timer
ST2100
Timer1 8-bit up-counter. used timer/counter program specified. difference between base timer that Timer1 will halt during SBY, base timer will not. shown FIGURE 10-4:
TCLK/65536 TCLK/32768 TCLK/8192 PRES TCLK/2048 TCLK/256 TCLK/32 TCLK/8 TCLK/2 T1M[2~0] MUX4-1 OSCX/256 OSCX/128 PREW OSCX/64 OSCX/32 T1M[1~0] T1M[4] Counter CLOCK Auto Reload IRT1 T1M[3] SYSCK Flip-Flop
FIGURE 10-4: Timer1 Structure Diagram
Address Name
$027 7-0:
TABLE 10-6:TIMER1 COUNTING REGISTER (T1C)
T1C[7] T1C[6] T1C[5] T1C[4] T1C[3] T1C[2] T1C[1]
T1C[0]
Default
0000 0000
T1C[7-0] Timer1 counter register
TABLE 10-7:Timer mode register
T1M[3] T1M[2] T1M[1] T1M[0] Timer Clock Source TCLK/65536 TCLK/32768 TCLK/8192 TCLK/2048 TCLK/256 TCLK/32 TCLK/8 TCLK/2 OSCX/256 OSCX/128 OSCX/64 OSCX/32
T1M[4]: Control automatic reload operation auto reload auto reload SENA Prescaler enable TCLK stop TCLK counting
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11.1 Function description
ST2100
built-in dual channel Programmable Sound Generator (PSG) controlled register file directly. flexibility makes useful applications such music synthesis, sound effects generation, audible alarms tone signaling. order generate sound effects while allowing processor perform other tasks, continue produce sound after initial commands have been given CPU. structure shown FIGURE 11-2: clock Source shown FIGURE 11-1: ST2100 three playing type. channel0(C0) channel1(C1) square type tone sound playing. square tone sound noise sound. third sound playing type playing. FIGURE 11-1: Clock Source
Selector SYSCK OSCX Select PSGC[6~4] Output PSGCK PSGC PSGCK SYSCK/2 SYSCK/4 SYSCK/8 SYSCK/16 SYSCK OSCX
FIGURE 11-2: Program Sound Generator
Preload Data Before First Count DACE C1TEN DACE PSGC[2] C1NEN PSGC[3] Channel Tone Enable Output LOAD Channel Noise Enable Output C1Tone MUX2 OUTPUT C1out
C1Noise
MIXER Output C1out Vol_CH1 VOL[1~0] From Generator DACE
MUX2 OUTPUT Port MUX2 OUTPUT PSGOUTB PSGOUT
TABLE 11-1:SUMMARY REGISTERS
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Address Name
$00F $010 $011 $012 $013 $016 $017 PMCR PSG0L PSG0H PSG1L PSG1H PSGC
ST2100
PULL PSG0[7] PSG1[7] VOL1[3]
PDBN PSG0[6] PSG1[6] PCK[2] PCK[2] VOL1[2]
INTEG PSG0[5] PSG1[5] PCK[1] PCK[1] VOL1[1]
PSG0[4] PSG1[4] PCK[0] PCK[0] VOL1[0]
PSG0[3] PSG0[11] PSG1[3] PSG1[11] PRBS DMD[1] VOL0[3]
PSG0[2] PSG0[10] PSG1[2] PSG1[10] C1EN DMD[0] VOL0[2]
PSGO PSG0[1] PSG0[9] PSG1[1] PSG1[9] C0EN VOL0[1]
PSGB PSG0[0] PSG0[8] PSG1[0] PSG1[8] DACE=0 DACE=1 VOL0[0]
Default
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Address Name
$00F PMCR
TABLE 11-2:CONTROL REGISTER OUTPUT (PMCR)
PULL PDBN INTEG PSGO PSGB
Default
PSGO output enable data output output mode normal PSGB inverse signal output enable inverse data output output mode normal
Address Name
$017
TABLE 11-3:CONTROL REGISTER VOLUME (VOL)
VOL1[3] VOL1[2] VOL1[1] VOL1[0] VOL0[3] VOL0[2] VOL0[1] VOL0[0]
Default
0000 0000
3~0: VOL0[3~0] channel volume control 0000 sound output 0001 1/16 volume (PSGCK must 320K 0100 4/16 volume 1000 8/16 volume 1111 Maximum volume (PSGCK must 7~4: VOL1[3~0] channel volume control 0000 sound output 0001 1/16 volume (PSGCK must 320K 0100 4/16 volume 1000 8/16 volume 1111 Maximum volume (PSGCK must single channel enable then volume double level output. level volume control)
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11.2 Tone Generator
11.2.1 General Description
tone frequency decided PSGCK 12-bit programmable divider (PSG[11~0]). Please refer FIGURE 11-3: FIGURE 11-4:
Auto-reload Counter PSG0[11~8] PSG0[7~0] C0[11~8] C0[7~0] OUTPUT Tone
ST2100
Channel
LOAD C0EN PSGCK Latch Enable CLOCK
Frequency Channel Tone PSGCK/(1000H-PSG0[11~0])/2
FIGURE 11-3: Channel Tone Counter
Auto-reload Counter PSG1[11~8] PSG1[7~0] C1[11~8] C1[7~0] OUTPUT Tone
Channel
LOAD C1EN PSGCK Latch Enable CLOCK
Frequency Channel Tone PSGCK/(1000H-PSG1[11~0])/2
FIGURE 11-4: Channel Tone Counter
11.2.2 Tone programming
program tone generator, PSGO (PMCR[1]) PSGB (PMCR[ should order output mode. Tone function defined DACE, writing C1EN will enable tone generator when tone function. Noise tone function selected PRBS.
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Address Name
$016 PSGC
ST2100
TABLE 11-4:PSG CONTROL REGISTER (PSGC)
PCK[2] PCK[2] PCK[1] PCK[1] PCK[0] PCK[0] PRBS DMD[1] C1EN DMD[0] C0EN
DACE=0 DACE=1
Default
0000 0000
DACE Tone(Noise) Generator selection used generator used Tone(Noise) generator C0EN channel (Tone) enable PSG0 (Tone) enable PSG0 (Tone) disable C1EN channel (Tone Noise) enable PSG1 (Tone Noise) enable PSG1 (Tone Noise) disable PRBS Tone Noise generator selection Noise generator Tone generator
6~4: PCK[2~0] clock source selection SYSCK SYSCK SYSCK SYSCK SYSCK OSCX
11.3 Noise Generator Control
11.3.1 General description Noise generator shown FIGURE 11-5: which base frequency controlled PSG1[5~0].
FIGURE 11-5: Noise Generator Diagram
16-Stage White Noise Generator Noise Prescaler PSG1[5~0] PSGCK C1N[5~0] CLOCK OUTPUT CLOCK OUTPUT Noise
Frequency PSGCK/(40H-PSG1[5~0])
11.3.2 Noise programming
program noise generator, PSGO (PMCR[1]) PSGB (PMCR[0]) should order output. Noise function defined DACE. Writing C1EN will enable noise generator when noise mode.
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TABLE 12-1:SUMMARY REGISTERS Address Name
$00F $012 $013 $014 $016
ST2100
built-in digital analog sampling data voice signals. structure shown Figure 13-1. There interrupt signal from whenever data update needed same signal will decide sampling rate voice. mode, can't less
Default
PMCR PULL PDBN INTEG PSG0 PSGB PSG1L PSG1[7] PSG1[6] PSG1[5] PSG1[4] PSG1[3] PSG1[2] PSG1[1] PSG1[0] 0000 0000 PSG1H PSG1[11] PSG1[10] PSG1[9] PSG1[8] 0000 DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 0000 0000 PCK[2] PCK[1] PCK[0] PRBS C1EN C0EN DACE=0 00-0 PSGC PCK[2] PCK[1] PCK[0] DMD[1] DMD[0] DACE=1 0000
TABLE 12-2:DAC DATA REGISTER (DAC) Address Name
$014
DAC[7]
DAC[6]
DAC[5]
DAC[4]
DAC[3]
DAC[2]
DAC[1]
DAC[0]
Default
0000 0000
7~0: DAC[7~0] output data Note: Single-Pin Single Ended mode, effective output resolution bit.
TABLE 12-3:DAC CONTROL REGISTER (PSGC) Address Name
$016 PSGC
PCK[2] PCK[2]
PCK[1] PCK[1]
PCK[0] PCK[0]
PRBS DMD[1]
C1EN DMD[0]
C0EN
Default
DACE=0 00-0 DACE=1 0000
DACE play Tone(Noise) Generator selection used Generator used Tone(Noise) Generator output inhibit control output inhibit output enable
3~2: DMD[1~0] output mode selection Single-Pin mode resolution Two-Pin Ended mode resolution Reserved Two-Pin Push Pull mode resolution 6~4: PCK[2~0] PSGCK selection SYSCK SYSCK SYSCK SYSCK SYSCK OSCX mode, PSGCK must select SYSCK.
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12.2 Sampling Rate Control
ST2100
sample rate controlled PSG1L PSG1H. PSG1[11~7] controls sample rate/post scaling PSG1[6] must PSG1[5~0] must `1'. input clock source controlled PCK[2~0]. block diagram shown following:
FIGURE 12-1: Generator
DAC[7~0] DMD[0] DMD[1] Sample Rate Generator PSG1[11~0] PSGCK DACE PSG1[11~0] CK_IN Enable Output
Generator DAC[7~0]
DMD[0] DMD[1]
Reload_DAC
Enable Reload_DAC
Diagram
FIGURE 12-2: Clock Source
Selector SYSCK OSCX Select PSGC[6~4] Output PSGCK PSGC
PSGCK SYSCK/2 SYSCK/4 SYSCK/8 SYSCK/16 SYSCK OSCX
TABLE 12-4:Sample Rate description table
SAMPLE RATE ALGORITHM DESCRIPTION Sample-Rate PSGCK (20H-PSG1[11~7])
Note: PSG1[6] must PSG1[5~0] must mode.
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12.3 Mode Select
ST2100
generator three modes, Single-pin mode, Two-pin ended mode Two-pin push pull mode. They depended application used. mode controlled DMD[1~0]. (TABLE 13-3)
12.3.1 Single-Pin Mode (Accurate bits)
Single-pin mode designed with single-transistor amplifier. bits resolution. duty cycle proportional output value. output value duty cycle 50%. output value increases from duty cycle goes from being high time 100% high. value goes from -64, duty cycle decreases from high inverse PB1's waveform. Figure 13-3 shows wave-forms.
FIGURE 12-3: Single-Pin Wave-form
64+X
High
64-X
FIGURE 12-4: Single-Pin Application Circuit
ST2100
Speaker 8050
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12.3.2 Two-Pin Ended mode (Accurate bits)
Two-Pin Ended mode designed with single transistor amplifier. requires pins that PB1. When value positive, goes high with duty cycle proportional output value, while stays high. When value negative, goes with duty cycle proportional output value, while stays low. This mode offers resolution bits.
ST2100
Figure 13-5 shows examples output waveforms with different output values. Each pulse divided into segments sample period. positive output value 127, goes high segments while stays high. negative output value -127, goes segments while stays low.
FIGURE 12-5:
High
Two-Pin Ended Wave-form
High
128-X Where
High
128+X
High
Where -128 -128
FIGURE 12-6: Two-Pin Ended mode Application Circuit
Output 1:ON :OFF
ST2100
2.2K
8050
0.1u
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12.3.3 Two-Pin Push Pull mode (Accurate bits)
Two-Pin Push Pull mode designed buzzer. requires pins that PB1. When value both pins low. When value positive, goes high with duty cycle proportional output value, while stays low. When value negative, goes high with duty cycle proportional output value, while stays low. This mode offers resolution bits.
ST2100
Figure 13-7 shows examples output waveforms with different output values. Each pulse divided into segments sample period. positive output value 127, goes high segments while stays low. negative output value -127, goes high segments while stays low.
FIGURE 12-7:
High
Two-Pin Push Pull Wave-form
High
128-X Where
High
128+X
High
Where -128 -128
FIGURE 12-8: Two-Pin Push Pull Application Circuit
ST2100
Buzzer
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ST2100
Full-graphic modes supported this chip. graphic memory constructed *128
13.1 Features
Address: Straight binary Attributes: Display inversion Display blank Applicable duties 1/48 1/32.
13.2 Block Diagram
ADDRESS COUNTER TIME CONTROL
LOAD
LINE CONTER
OUTPUT REGISTER
COUNTER
CONTROL
8-BIT
DATAOUT
13.3 Description
LOAD DATAOUT Description alternating signal First line mark signal Load data into driver's data latch Shift clock pulse driver Output serial data driver
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13.4 Display Data Drivers
Following graph show data sequence transfer output data pin.
ST2100
DATAOUT
Segment 0~111 0~127
13.4.1 Display
There display mode ST2100 controlled register LCTL[4] 48*112 32*128 Mode: common segment (LCDM=0): Address from $1000 $12EF Address COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Address COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 Address Address Address Address COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 SEG0 1000H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1080H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1100H 1180H 1200H 1280H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG1 1001H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1081H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1101H 1181H 1201H 1281H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG2 1002H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1082H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1102H 1182H 1202H 1282H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG3 1003H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1083H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1103H 1183H 1203H 1283H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG4 1004H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1084H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1104H 1184H 1204H 1284H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG5 1005H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1085H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1105H 1185H 1205H 1285H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG111 106FH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 10EFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 116FH 11EFH 126FH 12EFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Notice: undefined area ($1070~$107F, $10F0~$10FF, $1170~$117F, $11F0~$11FF) under different display mode.
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Mode: common segment (LCDM=1): Address from $1000 $11FF Address COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Address COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 Address Address COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 SEG0 1000H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1080H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1100H 1180H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG1 1001H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1081H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1101H 1181H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG2 1002H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1082H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1102H 1182H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG3 1003H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1083H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1103H 1183H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG4 1004H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1084H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1104H 1184H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG5 1005H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1085H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1105H 1185H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG127 107FH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 10FFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 117FH 11FFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ST2100
Notice: undefined area ($1200~$126F, $1280~$12EF) under different display mode.
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13.4.2 Frame Pulse, Frame, Load
Timing Chart
stop line stop line stop line stop line
ST2100
stop
Memory Address LOAD
Segment Driver
line line line line line
most suitable frequency (For 50Hz about 20ms.) fFLM fFLM 268K 376K
13.5 control register
Address Register LCTL bit7 LPWR bit6 BLANK bit5 bit4 bit3 CTR[3] bit2 CTR[2] bit1 CTR[1] bit0 COMMENT CTR[0] Register
LPWR (LCTL[7]) BLANK (LCTL[6]) (LCTL[5]) CTR[3~0] (LCTL[3~0])
Control Driver power On/OFF (Default) Control panel display On/OFF Display Display Display Reverse Normal display Reverse display contrast control When DUTY 1/48 0000: contrast maximum (level (default) 0001: contrast maximum (level 0010: contrast maximum (level 0011: contrast maximum (level 0100: contrast level 0101: contrast level 1111: contrast minimum (level When DUTY 1/32 0000: contrast maximum (level (default) 0001: contrast level 0010: contrast level 0011: contrast level 0100: contrast level 0101: contrast level 1111: contrast minimum (level
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13.6 clock register
Address Name
$03B
ST2100
LCK[2]
LCK[1]
LCK[0]
Default
-000
LCK[2~0] clock control DUTY 1/48 23.25 frames/sec 46.5 frames/sec frames/sec frames/sec frames/sec
30.5
DUTY 1/32 frames/sec (For 4MHz) frames/sec (For 4MHz) frames/sec (For 4MHz) frames/sec (For 4MHz) frames/sec (For 4MHz)
13.7 configuration register
Address Name
$039 LCFG
Default
???? ????
LCFG[7] LCFG[6] LCFG[5] LCFG[4] LCFG[3] LCFG[2] LCFG[1] LCFG[0]
LCFG[7~0] configuration control (write only, preset value when power
Address register used display dimension, write SEG-1 first, then COM-1 next. Since word control, always write bytes into address. <Example> LCD_SEG Segment LCD_COM Common #LCD_SEG #LCD_COM
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Sitronix DIRECT MEMORY ACCESS (DMA)
ST2100
speed memory access this system, sequential direct memory access(DMA) controller designed-in. perform memory transfer function more efficient than does. While working, data register (DRR) will disable memory bank register (DMR) access ROM. After complete, bank control still return DRR. With help make across bank boundary smoothly, only valid DMS. automatic increase when across bank boundary.
14.1 Block Diagram
LCD_CTL
SRAM
14.2 Control register
control register shown followed:
Address $028 $029 $02A $02B $02C $02D $033 Register DMSL DMSH DMDL DMDH DCNTL DCNTH bit7 DMS7 DMS15 DMD7 DMD15 DCNT7 DMR7 bit6 DMS6 DMS14 DMD6 DMD14 DCNT6 DMR6 bit5 DMS5 DMS13 DMD5 DMD13 DCNT5 DMR5 bit4 DMS4 DMS12 DMD4 DMD12 DCNT4 DMAM DMR4 bit3 bit2 DMS3 DMS2 DMS11 DMS10 DMD3 DMD2 DMD11 DMD10 DCNT3 DCNT2 DCNT11 DCNT10 DMR3 DMR2 bit1 DMS1 DMS9 DMD1 DMD9 DCNT1 DCNT9 DMR1 bit0 DMS0 DMS8 DMD0 DMD8 DCNT0 DCNT8 DMR0 COMMENT Source register byte Source register high byte Desitination register byte Desitination register high byte Counter byte Counter high byte memory bank register
DCNT
H[4]: DMAM
destination counter mode increase mode (DMS++ DMD++ after every move) fixed mode (DMS++ fixed)
always move (DCNT+1) bytes data. maximum number bytes move bytes. will start right after write data into register DCNTL. During operation, hold, until transfer completed. register reset "$00" real chip, Emulation Board "unknown", recommend initial register before use. Before Read/Write have initial PRR, DRR, register when system reset.
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14.3 Programming Flowchart
Memory bank register
ST2100
(DMSH,L) Source address
(DMDH,L) Destination address
DCNTH Number Bytes
DCNTL Number Bytes
Start hold
14.4 Application program
This program fill "00" $1000~$12FF. $1000 DMSL #$10 DMSH DMDH #$01 DMDL #$02 DCNTH #$FE DCNTL "00" $1000 source $1000 destination $1001
move $2FF bytes
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14.5 Application program
This program $1080~$12FF move $1000~$127F. #$80 DMSL #$10 DMSH DMDH DMDL #$02 DCNTH #$7F DCNTL
ST2100
source $1080 destination $1000
move $280 bytes
14.6 Application program
This program $8000~$803F move $0200. DMSL #$80 DMSH DMDL #$02 DMDH #$10 DCNTH #$3F DCNTL
source $8000 destination $0200
move bytes
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Sitronix POWER DOWN MODE
ST2100 three power down modes: WAI-0, WAI-1 STP. instruction will enable mode WAI-0 WAI-1, which controlled WAIT(SYS[2]). instruction
ST2100
(WAI-0 WAI-1 modes) wake-up interrupt. However, instruction only wake-up hardware reset.
15.1 WAI-0 Mode:
When WAIT cleared, instruction lets enter WAI-0 mode. mean time, oscillator circuit active interrupts, timer/counter, will working. Under such circumstance, stops related instruction execution will stop. registers, RAM, pins will retain their states before enter standby mode. WAI-0 mode #$00 wake-up reset interrupt request. user disable interrupt(CPU register I='1'), will still wake-up into interrupt service routine. interrupt enabled(CPU register I='0'), corresponding interrupt vector will fetched interrupt service routines will executed. sample program showed followed:
mode
15.2 WAI-1 Mode:
When WAIT set, instruction enter WAI-1 mode. this mode, will stop, PSG, timer/counter won't stop clock source from OSCX. wake-up #$04 procedure same WAI-0. warm-up cycles occur when WAI-1 wake-up. sample program shown following:
mode
15.3 Mode:
instruction will force enter stop mode. this mode, stops, PSG, timer/counter won't stop clock source from OSCX. power-down mode, only wake-up hardware reset, warm-up cycles occur same time. sample program showed following:
TABLE 15-1:STATUS UNDER POWER DOWN MODE
(SYSCK source from OSC)
Mode Timer0,1 SYSCK
WAI-0 WAI-1 Stop Stop Stop Stop Stop Stop
OSCX
Base Timer
REG.
Wake-up condition
Reset, interrupt Reset, interrupt Reset
Retain Retain Retain
(SYSCK source from OSCX)
Mode Timer0,1 SYSCK
WAI-0 WAI-1
2.6c
OSCX
Base Timer
Retain Retain Retain
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REG.
Wake-up condition
Reset, interrupt Reset, interrupt Reset
2002-Jul-25
Stop Stop
Stop Stop
Sitronix ELECTRICAL CHARACTERISTICS
16.1 Absolute Maximum Ratings*
ST2100
*Notice: Stresses above those listed under "Absolute
Supply Voltage -0.3V +7.5V Operating Ambient Temperature 10°C +60°C Storage Temperature -10°C +125°C Maximum Ratings" cause permanent damage device. ranges stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposed absolute maximum rating conditions extended periods affect device reliability.
16.2 Electrical Characteristics (TBD.)
Standard operation conditions: 3.0V, 25°C, OSCX 32768Hz, unless otherwise specified Parameter Operating Voltage Operating Current voltage divider resistor Standby Current Standby Current Input High Voltage Symbol RLCD ISB1 ISB2 0.7VDD 0.85VDD Input Voltage -0.3 0.3*VDD 0.15*VDD Pull-up resistance Output high voltage Output voltage Output high voltage Output voltage Output high voltage Output voltage Output high voltage Output voltage Output high voltage VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 0.7VDD 0.7VDD 0.7VDD Min. Typ. Max. Unit Condition output pins unload, execute instruction Piece output pins unload (WAIT mode) output pins unload (STOP mode), PORT PORT PORT
RESET
PORT PORT PORT RESET
PORTA, PORTB, PORTC (IOH -37uA, VOH=0). PORTA, PORTB, PORTC (IOH -2.5mA). PORTA, PORTB, PORTC (IOL= 6mA). PSG, -2.5mA. PSG, IOL= 6mA. SEGx, -800uA, C=50P,rise time 200ns SEGx, 800uA SEG0 output port, -1mA. SEG0 output port, 2.5mA. COM4 output port, -1mA.
Output voltage VOL5 COM4 output port, 2.5mA. Lighting Normal size ILCD Oscillation start time TSTT [F(3.0)-F(2.5)]/F(3.0)(crystal oscillator) Frequency stability Frequency variation 25P. relationship between resistance frequency (OSCI) reference. Resistance Frequency 120K
2.6c
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Sitronix APPLICATION CIRCUITS
17.1 Application
Internal memory 1~2M bytes, Expand memory 3~8M bytes.
ST2100
PANEL
COM32 COM1 SEG48 SEG1
ST2101
BLANKB CP,CKP POFFB LOAD DI_1
DATAOUT LOAD RESET THERMISTER 0.1u BLANKB POFFB
OSCI
ST2100
Internal Memory 1~2M Bytes
A[22]/CSB0 EXT_MEM CSB/CSB1 EXT_MODE A[0~21] D[0~7]
OSCXO OSCXI 32.768KHz SUBSTRATE CONNECTS GND.
BUZZER
Expand Memory 3~6M Bytes
D[0~7] A[0~21]
D[0~7] A[0~21]
Expand Memory 7~8M Bytes
2.6c
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Sitronix
17.2 Application
Internal memory Disable, Expand memory 1~8M bytes.
ST2100
PANEL
COM32 COM1 SEG48 SEG1
ST2101
BLANKB CP,CKP POFFB LOAD DI_1
DATAOUT LOAD RESET THERMISTER 0.1u BLANKB POFFB
OSCI
ST2100
Internal Memory Disable
A[22]/CSB0 CSB/CSB1 EXT_MEM EXT_MODE A[0~21] D[0~7]
OSCXO OSCXI 32.768KHz SUBSTRATE CONNECTS GND.
BUZZER
Expand Memory 1~4M Bytes
D[0~7] A[0~21]
D[0~7] A[0~21]
Expand Memory 5~8M Bytes
2.6c
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Sitronix
17.3 Application
Internal memory Disable, Expand memory 1~8M bytes.
ST2100
PANEL
COM32 COM1 SEG48 SEG1
ST2101
BLANKB CP,CKP POFFB LOAD DI_1
DATAOUT LOAD RESET THERMISTER 0.1u BLANKB POFFB
OSCI
ST2100
Internal Memory Disable
CSB/CSB1 A[22]/CSB0 EXT_MEM EXT_MODE A[0~20] D[0~7]
OSCXO OSCXI 32.768KHz SUBSTRATE CONNECTS GND.
BUZZER
Expand Memory 1~8M Bytes
D[0~7] A[0~21]
A[22]
2.6c
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Sitronix
17.4 Application
Internal memory Enabled, Expand memory bytes. Code option: resonator 4MHz
ST2100
PANEL 48x32
COM32 COM1 SEG48 SEG1
ST2101C
RESET 0.47uF THERMISTER 0.1u SUBSTRATE CONNECTS GND. Crystal 4Mhz 15pF 0.1uF 4.7uF
Internal Memory Enabled 1~2M Bytes
ST2100
OSCI 15pF OSCXO OSCXI Crystal 32.768KHz 25pF
BUZZER
Expand Memory 3~6M Bytes
D[0~7] A[0~21]
D[0~7] A[0~20]
Expand Memory 7~8M Bytes
2.6c
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Sitronix BONDING INFORMATION
Name LOAD POFFB TEST DATOUT BLANKB OSCI RESETB OSCXO OSCXI 2341.1 2341.1 2341.1 2150.0 2039.8 1929.6 1819.4 1709.2 1599.0 1488.8 1378.6 1268.6 1158.2 1048.0 937.8 827.6 717.4 607.2 497.0 386.8 276.6 166.4 56.2 -54.1 -164.3 -274.5 -384.7 -494.9 -605.1 -715.3 -825.5 -935.7 -1045.9 -1156.1 -1266.3 -1376.5 -1486.7 -2341.1 -2341.1 2199.3 2309.5 2419.7 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 2561.8 1846.2 1736.0 Name EXT_MODE EXT_MEM CSB/CSB1 A22/CSB0 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 -2341.1 unit: 1625.8 1515.6 1405.4 1295.2 1185.0 1074.8 964.6 854.4 744.2 634.0 523.8 413.6 303.4 193.2 83.0 -27.2 -137.4 -247.6 -357.8 -468.0 -578.2 -688.4 -798.6 -908.8 -1019.0 -1129.2 -1239.4 -1349.6 -1459.8 -1570.0 -1680.2 -1790.4 -1900.6 -2010.8 -2121.0 -2231.2 -2341.4 -2451.6 -2561.8
ST2100
chip size 4890um 5330um substrate connect ground
2.6c
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Sitronix
Revisions Version 1.72(Eric): Page7 Page8
ST2100
section bytes space section 7.2.2 EXT_MEM mode
Version Page Timer registers. Page control register. Version Page Application circuits.
Version Page Features. Page diagram. Page description. Page Memory map. Page 44~47 Application circuits. Version Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Modify RAM. diagram. description. Modify RAM. Addition configuration register modify LCTL only write Modify RAM. Modify interrupt priority TABLE9-1:Pad number. 9.1.2~9.1.5 move 9.2. Modify oscillator TABLE10-1:bit7 description. Modify digital TABLE13-3 description. Modify LCTL[3~0]:contrast level define. Addition configuration register description. Modify description. Modify power down mode TABLE16-1 description. Modify electrical characteristics. Modify application circuits.
Version Page 8,38 15.2: DMSL(H),DMDL(H),DCNTL(H) only write, PRR,DRR,DMR R/W. Before Read/Write have initial PRR, DRR, register when system reset.
Version 1.73 modify description Version 1.8. bonding information Version 1.9. Change (improve noise immunity) Version 2.0. Modify application circuit, connect ST2101 POFFB ST2100 Version 2.1. change alternating signal name `DF' into `AC', correct AC,FLM description Version 2.2. split appendix section allocation section Version 2.3. correct A22/CSB0, type error page2 application circuit Version 2.4. Modify LCTL Description. Version 2.6. Page18 Modify PRES counter description. Version 2.6c. Modify memory mapping modes page8
2.6c
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