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SSD1773
Icon CSTN Segment Common COLOR Driver with Controller
This document contains information product. Specifications information herein subject change without notice. http://www.solomon-systech.com SSD1773 Series 1/73 2004 Copyright 2004 Solomon Systech Limited
TABLE CONTENT
GENERAL DESCRIPTION FEATURES ORDERING INFORMATION BLOCK DIAGRAM FLOOR PLAN
DESCRIPTION. FUNCTIONAL BLOCK DESCRIPTIONS COMMAND TABLE COMMAND DESCRIPTIONS MAXIMUM RATINGS CHARACTERISTICS CHARACTERISTICS APPLICATION EXAMPLES PACKAGE INFORMATION
Solomon Systech
2004
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SSD1773 Series
TABLE TABLE
Table Ordering Information. Table SSD1773 Series Bump Coordinates Table interface mode selection PS1-PS0. Table VOUT Relationship. Table Data selection modes Table Command Table E=1( unless specific setting stated) Table Read Command Table. Table arrangements 8-levels gray scale mode Table arrangements 16-levels gray scale mode Table arrangements 64-levels gray scale mode Table Arrangement modes Table Data arrangement different pixel mode Table Area scrolling selection modes. Table Maximum Ratings Table Characteristics. Table Characteristics Table Parallel 6800-series Timing Characteristics Table Parallel 8080-series Timing Characteristics Table 4-wires Serial Timing Characteristics Table 3-Wires Serial Timing Characteristics. Table Power Up/Down Timing Characteristics
SSD1773 Series
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Solomon Systech
TABLE FIGURE
Figure SSD1773 Block Diagram. Figure SSD1773 Floor Plan. Figure Read Display Data. Figure Graphic Display Data Map. Figure SSD1773 Hardware configurations Figure Oscillator structural block diagram Figure column page scan direction. Figure Area scrolling selection modes. Figure GDDRAM updates area scrolling Figure Example Specified Center Scroll Mode Figure Contrast Control Flow Segment Re-map. Figure Contrast Control Voltage Range Curve. Figure Partial display mode Figure programming circuitry. Figure Flow chart programming Procedure. Figure Parallel 6800-series Interface Timing Characteristics (PS0 Figure Parallel 8080-series Interface Timing Characteristics (PS0 Figure Serial 4-wires Timing Characteristics (PS0 =L). Figure 3-Wires Serial Timing Characteristics (PS0 Figure Initial Sequence power up/down Figure Power Figure Initial Code Timing Chart Figure Power save power power timing chart Figure Application Example (4-wires mode) Figure Application Example (6800 mode) Figure VDD, VDDIO, connection example.
Solomon Systech
2004
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SSD1773 Series
General Description
SSD1773 single-chip CMOS color driver with controller dot-matrix graphic liquid crystal display system. SSD1773 consists high voltage driving output pins driving maximum Segments, Commons CSTN panel. SSD1773 consists bits Graphic Display Data (GDDRAM). Data/Commands sent from common through 8-bit 6800-series 8080-series compatible Parallel Interface 3-wires 4wires Serial Peripheral Interface pins selection. SSD1773 embeds On-Chip Oscillator, DC-DC Converter, bias divider reduce number external component. With advanced design, power consumption, stable operating voltage flexible package layout, SSD1773 suitable portable battery-driven applications requiring long operation period with compact size.
FEATURES
Power Supply: VDDIO 2.4V 2.4V 3.6V 3.6V Driving Output Voltage: 13.5V Current Sleep Mode Maximum display size: columns rows icon. Display color support: 65K/4K/256 color selectable, with selectable gamma correction. 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, 3-wires Serial Peripheral Interface 4-wires Serial Peripheral Interface On-Chip (104 RGB) 134,784 bits Graphic Display Data Programmable partial display function Column Re-mapping Page scan direction control Software selection Center Screen Scrolling, Screen Scrolling, Bottom Screen Scrolling Whole Screen Scrolling On-Chip Voltage Generator External Driving Power Supply Selectable On-Chip DC-DC Converter Levels Internal Contrast Control Programmable Driving Voltage Temperature Compensation Coefficients On-Chip Bias Divider Programmable drive duty ratio: On-Chip Oscillator Non-Volatile Memory (OTP) calibration On-Chip Graphic Acceleration Engine featuring Line/Rectangle Drawing, Dim/Clear/Copy operation Window mode. 5bit Driving Scheme Interlace/progressive common pins sequence selectable
SSD1773 Series
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Solomon Systech
ORDERING INFORMATION
Ordering Part Number SSD1773Z 104x3 (312) 80+1 Package Form Gold Bump Reference Figure Page Remark
Table Ordering Information
Solomon Systech
2004
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SSD1773 Series
BLOCK DIAGRAM
ICON ROW0 ROW79 COL0 ~COL311
Common Driver Circuits
Segment Driver Circuits
VOUT
Display Data Latch Driving Voltage Generator Converter, Voltage Regulator, Contrast Control Bias Divider Temperature Compensation VCIX2
BUSY Display Timing Generator GDDRAM (104RGB) bits Page Address Control Circuit Colum Address Control Circuit Graphic Accelerator
VHREF VLREF
Oscillator
System Control Circuit
Status Register VDDIO CVSS
Command Decoder
Microprocessor Interface Logic
RVSS
(RD)
Figure SSD1773 Block Diagram
SSD1773 Series
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Solomon Systech
FLOOR PLAN
Note: Diagram showing face Coordinates reference center chip. Unit coordinates Size alignment marks alignment keys contain gold bump.
Size Thickness Typical Bump Height Bump Co-planarity (within die) 17.74 1.88 457±25
Figure SSD1773 Floor Plan
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2004
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SSD1773 Series
Table SSD1773 Series Bump Coordinates (Bump center)
Signal DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY TEST0
(SDA) (SDA) (SCK) (SCK) (SCK) (SDA) (SDA) (SDA)
X-pos Y-pos Signal X-pos Y-pos Signal -8706.0 -769.7 -4896.0 -769.7 -8629.8 -769.7 BUSY -4819.8 -769.7 -8553.6 -769.7 BUSY -4743.6 -769.7 -8477.4 -769.7 -4667.4 -769.7 -8401.2 -769.7 MUX68 -4591.2 -769.7 -8325.0 -769.7 -4515.0 -769.7 -8248.8 -769.7 TEST1 -4438.8 -769.7 -8172.6 -769.7 TEST2 -4362.6 -769.7 -8096.4 -769.7 TEST3 -4286.4 -769.7 -8020.2 -769.7 TEST4 -4210.2 -769.7 -7944.0 -769.7 TEST5 -4134.0 -769.7 -7867.8 -769.7 TEST6 -4057.8 -769.7 -7791.6 -769.7 TEST7 -3981.6 -769.7 -7715.4 -769.7 TEST8 -3905.4 -769.7 -7639.2 -769.7 -3829.2 -769.7 -3753.0 -769.7 -7563.0 -769.7 -3676.8 -769.7 -7486.8 -769.7 -3600.6 -769.7 -7410.6 -769.7 -3524.4 -769.7 -7334.4 -769.7 -3448.2 -769.7 -7258.2 -769.7 -3372.0 -769.7 -7182.0 -769.7 -3295.8 -769.7 -7105.8 -769.7 -3219.6 -769.7 -7029.6 -769.7 -3143.4 -769.7 -6953.4 -769.7 -3067.2 -769.7 -6877.2 -769.7 -2991.0 -769.7 -6801.0 -769.7 -2914.8 -769.7 RVSS -6724.8 -769.7 -2838.6 -769.7 RVSS -6648.6 -769.7 -2762.4 -769.7 RVSS -6572.4 -769.7 -2686.2 -769.7 CVSS -6496.2 -769.7 -2610.0 -769.7 CVSS -6420.0 -769.7 -2533.8 -769.7 CVSS -6343.8 -769.7 VDDIO -2457.6 -769.7 CVSS -6267.6 -769.7 VDDIO -6191.4 -769.7 VCIX2 -2371.7 -769.7 CVSS -2295.5 -769.7 CVSS -6115.2 -769.7 VCIX2 -2219.3 -769.7 CVSS -6039.0 -769.7 VCIX2 -2143.1 -769.7 CVSS -5962.8 -769.7 VCIX2 -2066.9 -769.7 CVSS -5886.6 -769.7 VCIX2 -1990.7 -769.7 CVSS -5810.4 -769.7 VCIX2 -1914.5 -769.7 CVSS -5734.2 -769.7 VCIX2 -1838.3 -769.7 CVSS -5658.0 -769.7 VCIX2 -1762.1 -769.7 CVSS -5581.8 -769.7 VCIX2 -1685.9 -769.7 CVSS -5505.6 -769.7 VHREF -1609.7 -769.7 CVSS -5429.4 -769.7 VLREF -1523.8 -769.7 CVSS -5353.2 -769.7 VCIX2 -1447.6 -769.7 CVSS -5277.0 -769.7 VLREF -1371.4 -769.7 CVSS -5200.8 -769.7 -1295.2 -769.7 CVSS -5124.6 -769.7 -1219.0 -769.7 CVSS -5048.4 -769.7 -1142.8 -769.7 CVSS -4972.2 -769.7
X-pos Y-pos -1066.6 -769.7 -990.4 -769.7 -914.2 -769.7 -838.0 -769.7 -761.8 -769.7 -685.6 -769.7 -609.4 -769.7 -533.2 -769.7 -457.0 -769.7 -380.8 -769.7 -304.6 -769.7 -228.4 -769.7 -152.2 -769.7 -76.0 -769.7 -769.7 76.4 -769.7 152.6 -769.7 228.8 -769.7 305.0 -769.7 381.2 -769.7 457.4 -769.7 533.6 -769.7 609.8 -769.7 686.0 -769.7 762.2 -769.7 838.4 -769.7 914.6 -769.7 990.8 -769.7 1067.0 -769.7 1143.2 -769.7 1219.4 -769.7 1295.6 -769.7 1371.8 -769.7 1448.0 -769.7 1524.2 -769.7 1600.4 -769.7 1676.6 -769.7 1752.8 -769.7 1829.0 -769.7 1905.2 -769.7 1981.4 -769.7 2057.6 -769.7 2133.8 -769.7 2210.0 -769.7 2286.2 -769.7 2362.4 -769.7 2438.6 -769.7 2514.8 -769.7 2591.0 -769.7 2667.2 -769.7
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Signal X-pos Y-pos Signal X-pos Y-pos CVSS 2743.4 -769.7 6563.1 -769.7 CVSS 2819.6 -769.7 TEST17 6639.3 -769.7 CVSS 2895.8 -769.7 VCIX2 6715.5 -769.7 CVSS 2972.0 -769.7 VHREF 6791.7 -769.7 TEST9 3048.2 -769.7 VHREF 6867.9 -769.7 TEST10 3124.4 -769.7 VOUT 6944.1 -769.7 TEST11 3200.6 -769.7 VOUT 7020.3 -769.7 TEST12 3276.8 -769.7 VOUT 7096.5 -769.7 TEST13 3353.0 -769.7 VOUT 7172.7 -769.7 TEST14 3429.2 -769.7 VOUT 7248.9 -769.7 TEST15 3505.4 -769.7 VOUT 7325.1 -769.7 TEST16 3581.6 -769.7 VOUT 7401.3 -769.7 3657.8 -769.7 VOUT 7477.5 -769.7 3734.0 -769.7 VOUT 7553.7 -769.7 3810.2 -769.7 VOUT 7629.9 -769.7 3886.4 -769.7 VOUT 7706.1 -769.7 3962.6 -769.7 VOUT 7782.3 -769.7 4038.8 -769.7 VOUT 7858.5 -769.7 4115.0 -769.7 7944.4 -769.7 4191.2 -769.7 8020.6 -769.7 4267.4 -769.7 8096.8 -769.7 4343.6 -769.7 8173.0 -769.7 4419.8 -769.7 DUMMY 8249.2 -769.7 4496.0 -769.7 DUMMY 8325.4 -769.7 4572.2 -769.7 DUMMY 8401.6 -769.7 4648.4 -769.7 DUMMY 8477.8 -769.7 4724.6 -769.7 DUMMY 8554.0 -769.7 4800.8 -769.7 DUMMY 8630.2 -769.7 4877.0 -769.7 DUMMY 8706.4 -769.7 4953.2 -769.7 5029.4 -769.7 5105.6 -769.7 5181.8 -769.7 5258.0 -769.7 5334.2 -769.7 5410.4 -769.7 5486.6 -769.7 VCIX2 5572.5 -769.7 VCIX2 5648.7 -769.7 5724.9 -769.7 5801.1 -769.7 5877.3 -769.7 5953.5 -769.7 6029.7 -769.7 6105.9 -769.7 6182.1 -769.7 6258.3 -769.7 6334.5 -769.7 6410.7 -769.7 6486.9 -769.7
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SSD1773 Series
Signal Name MUX68/80
DUMMY DUMMY ICON ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39
Signal Signal Color X-pos
6748.7 6705.3 6661.9 6618.5 6575.1 6531.7 6488.3 6444.9 6401.5 6358.1 6314.7 6271.3 6227.9 6184.5 6141.1 6097.7 6054.3 6010.9 5967.5 5924.1 5880.7 5837.3 5793.9 5750.5 5707.1 5663.7 5620.3 5576.9 5533.5 5490.1 5446.7 5403.3 5359.9 5316.5 5273.1 5229.7 5186.3 5142.9 5099.5 5056.1 5012.7 4969.3 4925.9 4882.5 4839.1 4795.7 4752.3 4708.9
MUX68/80 X-pos Y-pos Name =VDD) 68mux Vss)-80 DUMMY DUMMY 8745.1 754.3 COL311 DUMMY DUMMY 8701.7 754.3 COL310 ICON ICON 8658.3 754.3 COL309 COM0 COM0 8614.9 754.3 COL308 COM1 COM1 8571.5 754.3 COL307 COM2 COM2 8528.1 754.3 COL306 COM3 COM3 8484.7 754.3 COL305 COM4 COM4 8441.3 754.3 COL304 COM5 COM5 8397.9 754.3 COL303 COM6 COM6 8354.5 754.3 COL302 COM7 COM7 8311.1 754.3 COL301 COM8 COM8 8267.7 754.3 COL300 COM9 COM9 8224.3 754.3 COL299 COM10 COM10 8180.9 754.3 COL298 COM11 COM11 8137.5 754.3 COL297 COM12 COM12 8094.1 754.3 COL296 COM13 COM13 8050.7 754.3 COL295 COM14 COM14 8007.3 754.3 COL294 COM15 COM15 7963.9 754.3 COL293 COM16 COM16 7920.5 754.3 COL292 COM17 COM17 7877.1 754.3 COL291 COM18 COM18 7833.7 754.3 COL290 COM19 COM19 7790.3 754.3 COL289 COM20 COM20 7746.9 754.3 COL288 COM21 COM21 7703.5 754.3 COL287 COM22 COM22 7660.1 754.3 COL286 COM23 COM23 7616.7 754.3 COL285 COM24 COM24 7573.3 754.3 COL284 COM25 COM25 7529.9 754.3 COL283 COM26 COM26 7486.5 754.3 COL282 COM27 COM27 7443.1 754.3 COL281 COM28 COM28 7399.7 754.3 COL280 COM29 COM29 7356.3 754.3 COL279 COM30 COM30 7312.9 754.3 COL278 COM31 COM31 7269.5 754.3 COL277 COM32 COM32 7226.1 754.3 COL276 COM33 COM33 7182.7 754.3 COL275 select signal COM34 7139.3 754.3 COL274 select signal COM35 7095.9 754.3 COL273 select signal COM36 7052.5 754.3 COL272 select signal COM37 7009.1 754.3 COL271 select signal COM38 6965.7 754.3 COL270 select signal COM39 6922.3 754.3 COL269 COL268 COL267 COL266 COL265 COL264
Y-pos
754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3
SEG103
SEG102
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SSD1773 Series
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Name
COL263 COL262 COL261 COL260 COL259 COL258 COL257 COL256 COL255 COL254 COL253 COL252 COL251 COL250 COL249 COL248 COL247 COL246 COL245 COL244 COL243 COL242 COL241 COL240 COL239 COL238 COL237 COL236 COL235 COL234 COL233 COL232 COL231 COL230 COL229 COL228 COL227 COL226 COL225 COL224 COL223 COL222 COL221 COL220 COL219 COL218 COL217 COL216
Signal
SEG87
Color
X-pos
4665.5 4622.1 4578.7 4535.3 4491.9 4448.5 4405.1 4361.7 4318.3 4274.9 4231.5 4188.1 4144.7 4101.3 4057.9 4014.5 3971.1 3927.7 3884.3 3840.9 3797.5 3754.1 3710.7 3667.3 3623.9 3580.5 3537.1 3493.7 3450.3 3406.9 3363.5 3320.1 3276.7 3233.3 3189.9 3146.5 3103.1 3059.7 3016.3 2972.9 2929.5 2886.1 2842.7 2799.3 2755.9 2712.5 2669.1 2625.7
Y-pos
754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3
Name
COL215 COL214 COL213 COL212 COL211 COL210 COL209 COL208 COL207 COL206 COL205 COL204 COL203 COL202 COL201 COL200 COL199 COL198 COL197 COL196 COL195 COL194 COL193 COL192 COL191 COL190 COL189 COL188 COL187 COL186 COL185 COL184 COL183 COL182 COL181 COL180 COL179 COL178 COL177 COL176 COL175 COL174 COL173 COL172 COL171 COL170 COL169 COL168
Signal
SEG71
Color
X-pos
2582.3 2538.9 2495.5 2452.1 2408.7 2365.3 2321.9 2278.5 2235.1 2191.7 2148.3 2104.9 2061.5 2018.1 1974.7 1931.3 1887.9 1844.5 1801.1 1757.7 1714.3 1670.9 1627.5 1584.1 1540.7 1497.3 1453.9 1410.5 1367.1 1323.7 1280.3 1236.9 1193.5 1150.1 1106.7 1063.3 1019.9 976.5 933.1 889.7 846.3 802.9 759.5 716.1 672.7 629.3 585.9 542.5
Y-pos
754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3
SEG86
SEG70
SEG85
SEG69
SEG84
SEG68
SEG83
SEG67
SEG82
SEG66
SEG81
SEG65
SEG80
SEG64
SEG79
SEG63
SEG78
SEG62
SEG77
SEG61
SEG76
SEG60
SEG75
SEG59
SEG74
SEG58
SEG73
SEG57
SEG72
SEG56
Solomon Systech
2004
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SSD1773 Series
Name
COL167 COL166 COL165 COL164 COL163 COL162 COL161 COL160 COL159 COL158 COL157 COL156 COL155 COL154 COL153 COL152 COL151 COL150 COL149 COL148 COL147 COL146 COL145 COL144 COL143 COL142 COL141 COL140 COL139 COL138 COL137 COL136 COL135 COL134 COL133 COL132 COL131 COL130 COL129 COL128 COL127 COL126 COL125 COL124 COL123 COL122 COL121 COL120
Signal
SEG55
Color
X-pos
499.1 455.7 412.3 368.9 325.5 282.1 238.7 195.3 151.9 108.5 65.1 21.7 -21.7 -65.1 -108.5 -151.9 -195.3 -238.7 -282.1 -325.5 -368.9 -412.3 -455.7 -499.1 -542.5 -585.9 -629.3 -672.7 -716.1 -759.5 -802.9 -846.3 -889.7 -933.1 -976.5 -1019.9 -1063.3 -1106.7 -1150.1 -1193.5 -1236.9 -1280.3 -1323.7 -1367.1 -1410.5 -1453.9 -1497.3 -1540.7
Y-pos
754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3
Name
COL119 COL118 COL117 COL116 COL115 COL114 COL113 COL112 COL111 COL110 COL109 COL108 COL107 COL106 COL105 COL104 COL103 COL102 COL101 COL100 COL99 COL98 COL97 COL96 COL95 COL94 COL93 COL92 COL91 COL90 COL89 COL88 COL87 COL86 COL85 COL84 COL83 COL82 COL81 COL80 COL79 COL78 COL77 COL76 COL75 COL74 COL73 COL72
Signal
SEG39
Color X-pos
-1584.1 -1627.5 -1670.9 -1714.3 -1757.7 -1801.1 -1844.5 -1887.9 -1931.3 -1974.7 -2018.1 -2061.5 -2104.9 -2148.3 -2191.7 -2235.1 -2278.5 -2321.9 -2365.3 -2408.7 -2452.1 -2495.5 -2538.9 -2582.3 -2625.7 -2669.1 -2712.5 -2755.9 -2799.3 -2842.7 -2886.1 -2929.5 -2972.9 -3016.3 -3059.7 -3103.1 -3146.5 -3189.9 -3233.3 -3276.7 -3320.1 -3363.5 -3406.9 -3450.3 -3493.7 -3537.1 -3580.5 -3623.9
Y-pos
754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3
SEG54
SEG38
SEG53
SEG37
SEG52
SEG36
SEG51
SEG35
SEG50
SEG34
SEG49
SEG33
SEG48
SEG32
SEG47
SEG31
SEG46
SEG30
SEG45
SEG29
SEG44
SEG28
SEG43
SEG27
SEG42
SEG26
SEG41
SEG25
SEG40
SEG24
SSD1773 Series
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2004
Solomon Systech
Name
COL71 COL70 COL69 COL68 COL67 COL66 COL65 COL64 COL63 COL62 COL61 COL60 COL59 COL58 COL57 COL56 COL55 COL54 COL53 COL52 COL51 COL50 COL49 COL48 COL47 COL46 COL45 COL44 COL43 COL42 COL41 COL40 COL39 COL38 COL37 COL36 COL35 COL34 COL33 COL32 COL31 COL30 COL29 COL28 COL27 COL26 COL25 COL24
Signal
SEG23
Color
X-pos
-3667.3 -3710.7 -3754.1 -3797.5 -3840.9 -3884.3 -3927.7 -3971.1 -4014.5 -4057.9 -4101.3 -4144.7 -4188.1 -4231.5 -4274.9 -4318.3 -4361.7 -4405.1 -4448.5 -4491.9 -4535.3 -4578.7 -4622.1 -4665.5 -4708.9 -4752.3 -4795.7 -4839.1 -4882.5 -4925.9 -4969.3 -5012.7 -5056.1 -5099.5 -5142.9 -5186.3 -5229.7 -5273.1 -5316.5 -5359.9 -5403.3 -5446.7 -5490.1 -5533.5 -5576.9 -5620.3 -5663.7 -5707.1
Y-pos
754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3
Name
COL23 COL22 COL21 COL20 COL19 COL18 COL17 COL16 COL15 COL14 COL13 COL12 COL11 COL10 COL9 COL8 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0
Signal
SEG7
Color X-pos
-5750.5 -5793.9 -5837.3 -5880.7 -5924.1 -5967.5 -6010.9 -6054.3 -6097.7 -6141.1 -6184.5 -6227.9 -6271.3 -6314.7 -6358.1 -6401.5 -6444.9 -6488.3 -6531.7 -6575.1 -6618.5 -6661.9 -6705.3 -6748.7
Y-pos
754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3 754.3
SEG22
SEG6
SEG21
SEG5
SEG20
SEG4
SEG19
SEG3
SEG18
SEG2
SEG17
SEG1
SEG16
SEG0
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
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Signal Name MUX68/80
VDD) 68mux ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 ROW64 ROW65 ROW66 ROW67 ROW68 ROW69 ROW70 ROW71 ROW72 ROW73 ROW74 ROW75 ROW76 ROW77 ROW78 ROW79 ICON DUMMY DUMMY
Select Signal Select Signal Select Signal Select Signal Select Signal Select Signal
Signal Y-pos MUX68/80 X-pos Vss) 80mux COM40 -6922.3 754.3 COM41 -6965.7 754.3 COM42 -7009.1 754.3 COM43 -7052.5 754.3 COM44 -7095.9 754.3 COM45 -7139.3 754.3 COM46 -7182.7 754.3 COM47 -7226.1 754.3 COM48 -7269.5 754.3 COM49 -7312.9 754.3 COM50 -7356.3 754.3 COM51 -7399.7 754.3 COM52 -7443.1 754.3 COM53 -7486.5 754.3 COM54 -7529.9 754.3 COM55 -7573.3 754.3 754.3 COM56 -7616.7 754.3 COM57 -7660.1 754.3 COM58 -7703.5 754.3 COM59 -7746.9 COM60 -7790.3 754.3 COM61 -7833.7 754.3 754.3 COM62 -7877.1 754.3 COM63 -7920.5 COM64 -7963.9 754.3 COM65 -8007.3 754.3 754.3 COM66 -8050.7 COM67 -8094.1 754.3 754.3 COM68 -8137.5 COM69 -8180.9 754.3 COM70 -8224.3 754.3 COM71 -8267.7 754.3 COM72 -8311.1 754.3 COM73 -8354.5 754.3 COM74 -8397.9 754.3 COM75 -8441.3 754.3 COM76 -8484.7 754.3 COM77 -8528.1 754.3 COM78 -8571.5 754.3 COM79 -8614.9 754.3 ICON -8658.3 754.3 -8701.7 754.3 -8745.1 754.3
COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 ICON
Bump Size PAD# 1-229
[um]
[um]
pitch [um] 76.2 43.4
pitch
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DESCRIPTION
This chip selection input. chip enabled communication only when pulled low.
This reset signal input. Initialization chip started once reset pulled low. minimum pulse width reset sequence 10us.
This Data/Command control pin. When pulled high, input D7-D0 treated display data. When pulled low, input D7-D0 will transferred command register.
This interface input. When 6800 interface mode selected, this will used Read/Write selection input. Read mode will carried when this pulled high write mode when this pulled low. When 8080 interface mode selected, this Write control signal input. Data write operation initiated when this pulled chip selected.
This interface input. When 6800 interface mode selected, this will used Enable signal. Read/ write operation initiated when this pulled high chip selected. When 8080 interface mode selected, this Read control signal input. Data read operation initiated when this pulled chip selected.
These pins interface mode selection input. Different interface selected changing setting these pins.
Interface 8-bit 8080 parallel interface 8-bit 6800 parallel interface 3-lines serial peripheral interface (SPI) bits 4-lines serial peripheral interface (SPI)
Table interface mode selection PS1-PS0 Note1: serial applications, recommended connect VDD. Note2: Read back operation only available parallel mode
MUX68/80
This used select ratio driver. When MUX68/( equal VDD, COM0 ~COM33 mapped ROW0~ROW33 COM46~COM79 mapped ROW34~ROW67 memory. When MUX68/( equal Vss, COM0~COM79 mapped ROW0~ROW79.
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D0-D7
These pins 8-bit bi-directional data parallel interface mode. while LSB. serial mode, serial data input serial clock input SCK.
VLREF
This ground operation amplifier VL5. normal power mode, must connect Vss. power mode, must connect must greater than Please refer Figure detail.
6.10 VHREF
This power supply operation amplifier VL3. must connect VOUT.
6.11 VCIX2
This internal reference pin. must connect VCI.
6.12
This system power supply logic block.
6.13 VDDIO
This system power supply buffer. Please refer page connection example.
6.14
This reference voltage input internal DC-DC converter. DC-DC converter output equal multiple factor (3X, times with respect VSS. maximum output voltage will limit max. VOUT characteristic. Note: Voltage this input must larger than equal VDD. (VCI VDD)
6.15
This ground logic.
6.16 RVSS
This ground VREF where VREF reference voltage internal regulator.
6.17 CVSS
This ground analog.
6.18 VOUT
This most positive voltage supply chip. generated internal voltage regulator. This voltage level used internal referencing only voltage level VOUT used driving external circuitry.
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6.19 VL5, VL4,
driving voltages. They supplied externally generated internal bias divider. They have following relationship: VOUT
bias
(a-1)/a VOUT (a-2)/a VOUT VOUT VOUT
Table VOUT Relationship
6.20 ROW0 ROW79
These pins provide driving signals, COMMON, panel.
6.21 COL0 COL311
These pins provide driving signals, SEGMENT, panel. Red, Green, Blue colors signal sent from SEGMENT output same time. output voltage level these pins during sleep mode standby mode.
6.22 ICON
This provides driving signals, COMMON icon line.
6.23
This system clock I/O. This external clock input device, which enabled using extended command. should left open under normal operation. internal oscillator will used after power reset.
6.24
This used cascade purpose only. should left open under normal operation.
6.25
This used cascade purpose only. should left open under normal operation.
6.26 BUSY
This will high during buffer read/write operation during graphic commands executing. System programmer should read this (low ready, high busy) before sending next buffer related command (e.g. write 5CH; read graphic commands)
6.27 TEST0~TEST17
These pins used internal only should left open, connection allowed.
6.28
connection (NC) should connected signal shorted other pins application. should left open.
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6.29 DUMMY
This floating dummy with internal circuit connection.
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FUNCTIONAL BLOCK DESCRIPTIONS
Microprocessor Interface Logic
Microprocessor Interface unit consists three functional blocks driving 6800-series parallel interface, 8080-series parallel interface, 3-lines serial peripheral interface 4-lines serial peripheral interface. selection different interface done pins. Please refer descriptions page Parallel 6800-series Interface parallel Interface consists bi-directional data pins D0), input high indicates read operation from Graphical Display Data (GDDRAM) status register. input indicates write operation Display Data Internal Command Registers depending status input. input serves data latch signal (clock) when high provided that low. Please refer Figure Parallel Interface Timing Diagram 6800series microprocessors. order match operating frequency GDDRAM with that MCU, some pipeline processing internally performed which requires insertion dummy read before first actual display data read. This shown following diagram.
DATA
dummy read
data read1
data read
data read
write column address
Figure Read Display Data Parallel 8080-series Interface parallel interface consists bi-directional data pins
input serves data read latch signal (clock) when provided that low. Whether reading display data from GDDRAM reading status from status register controlled input serves data write latch signal (clock) when provided that low. Whether writing display data GDDRAM writing command command register controlled dummy read also required before first actual display data read 8080-series interface. 4-lines Serial Peripheral Interface 4-lines serial peripheral Interface consists serial clock SCK, serial data SDA, shifted into 8-bit shift register every rising edge order data data data sampled every eighth clock determine whether data byte shift register written Display Data command register same clock. Please refer Figure serial interface timing.
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3-lines Serial Peripheral Interface operation similar 4-lines serial peripheral interface while used. There altogether 9-bits will shifted into shift register every ninth clock sequence: bit, bit. (first sequential data) will determine following data byte shift register written Display Data command register
6800 series Parallel Interface 8080 series Parallel Interface 3-lines 4-lines Serial peripheral Interface 8-bits
Data Read Data Write Command Read Command Write
8-bits 8-bits Status only
8-bits 8-bits Status only
Table Data selection modes
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Reset Circuit
This block integrated into Microprocessor Interface Logic which includes Power Reset circuitry hardware reset pin, Both these having same reset function. Once receives negative reset pulse, internal circuitry will start initialize. minimum pulse width completing reset sequence 10us. status chip after reset given When input low, chip initialized following: Display ON/OFF: Normal/Inverse Display: Scan Direction: Internal Oscillator: Reference Voltage Generation Circuit: Voltage regulator Voltage Follower: Booster: Bias ratio: Multiplex ratio: Contrast Internal Regulator gain Average temperature gradient: Partial display mode: Start address: address: Area Scroll block address: Bottom block address: Number specified block: Area scroll mode: Scroll start Start block address: Data Scan Direction Normal/inverse display page address: Normal/inverse display column address: Address-scan direction: arrangement: Gray-scale setup: Start Page Address set: Page Address set: Start Column address set: Column address set: Select PWM/FRC Display Normal Display ROW0-ROW79 COM0-COM79 Disable Disable Disable Disable (MUX68/( (MUX68/( 68Mux(MUX68/( 80Mux(MUX68/( (Gain 2.84) TC2(-0.20%/ Disable Whole screen scroll mode Normal Normal Column direction color 5-bit 1-bit mode
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Command Decoder
This module determines whether input data interpreted data command. Data directed this module based upon input pin. high, data written Graphic Display data (GDDRAM). low, input interpreted Command will decoded. decoded command will written corresponding command register.
Graphic Display Data (GDDRAM)
GDDRAM mapped static holding pattern displayed. size 134,784 bits. Figure description GDDRAM address map. mechanical flexibility, re-mapping both Segment Common outputs selected software. Please refer command "Data Output/Scan direction" Figure detail description. Four pages display data form address block stored GDDRAM. Each block will form fundamental units scrolling addresses. Various types area scrolling performed software program according command "Set area Scroll" "Set Scroll Start" Table order ease access red, green blue color data; 8-bits color data (Red: bits, Green: bits, Blue: bits) converted 4-bits data (P10, P11, P12, P13). 4-bits data stored into GDDRAM such that data located appropriate locations according gray scale settings.
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data this cell BLOCK PAGE DATA
COMMON OUTPUT COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 ICON
SEGMENT
COL303 COL304 SEG101 COL305 COL306 COL307 SEG102 COL308 COL309 COL310 SEG103 COL311
SEG0
SEG1
SEG2
COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8
COLUMN
Mapping depends Output scan direction setting
Notes: Page SEGMENT data scan direction depend Data Output Scan Direction Setting. Data Output Scan Directin setting cannot affect Block scan direction.
Figure Graphic Display Data
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Driving Voltage Generator Regulator
This module generates voltage needed display output. takes single supply input generates necessary bias voltages. consists DC-DC voltage converter Bias Divider output op-amp buffer option Power Control Register command enabled, this circuit block will divide regulator output (VOUT) give driving levels (VL2 VL5). divider does require external capacitors reduce external hardware counts, power configuration op-amp shown Figure Contrast Control -Software control voltage levels voltage. Bias Ratio Selection circuitry -Software control 1/10 bias ratio match characteristic panel. Self adjust temperature compensation circuitry Provide different compensation grade selections satisfy various liquid crystal temperature grades. grading selected software control. Defaulted temperature coefficient (TC) value -0.20%/°C.
VOUT
VHREF VCIX2 VLREF
SSD1773
Normal Power Mode Recommended capacitance value: 2.2uF 2.2uF 4.7uF
VOUT
VHREF VCIX2 VLREF
Power Mode Power Mode, must
SSD1773
Recommended capacitance value: 2.2uF 2.2uF 4.7uF
Figure SSD1773 Hardware configurations
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Oscillator Circuit
This module On-Chip power oscillator circuitry (Figure oscillator generates clock DC-DC voltage converter. This clock also used Display Timing Generator.
Oscillator enable
enable Oscillation Circuit
enable Buffer
(CL)
Internal resistor
OSC1 OSC2
Figure Oscillator structural block diagram
Display Data Latch
This block series latches carrying display signal information. These latches hold data, which will Buffer Cell Level Selector output required voltage level.
Buffer Cell (Level Shifter)
This block embedded Segment/Common Driver Circuits. Buffer Cell works level shifter, which translates voltage output signal required driving voltage. output shifted with reference internal clock, which comes from Display Timing Generator. voltage levels given level selector, which synchronized with internal signal.
Level Selector
This block embedded Segment/Common Driver circuits. Level Selector control display synchronization. Display voltage levels separated into sets used with different cycles. Synchronization important since selects required voltage level Buffer Cell, which turn outputs waveform.
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COMMAND TABLE
Table Command Table E=1( unless specific setting stated)
Command Column Address Description start column address 0X6X5X4X3X2X1X0 column address 0Y6Y5Y4Y3Y2Y1Y0 Column address 00000000b (POR) color mode, column address range 0~103. color mode, column address range 0~51. start page address 0X6X5X4X3X2X1X0 page address 0Y6Y5Y4Y3Y2Y1Y0. Page address 00000000b (POR) Page address range 0~79 MUX68
ROW0.ROW33 ROW34.ROW39 ROW40.ROW45 ROW46.ROW79 COM0->COM33 COM34->COM39 COM40->COM45 COM46->COM79 (POR) COM0->COM33 COM34->COM39 COM79<-COM64 COM63<-COM40 COM39<-COM6 COM5<-COM0 COM40->COM45 COM46->COM79 COM39<-COM6 COM5<-COM0 COM79<-COM64 COM63<-COM40
Page Address
Output Scan Direction
MUX68
ROW0.ROW33 ROW34.ROW39 ROW40.ROW45 COM0->COM33 SELECT OUTPUT COM0->COM33 SELECT OUTPUT COM33<-COM0 SELECT OUTPUT COM33<-COM0 SELECT OUTPUT ROW46.ROW79 COM34->COM67 (POR) COM67<-COM34 COM34->COM67 COM67<-COM34
Output Normal Reverse page/column/scan directions Scan Direction page address normal display (POR) page address inverse display column address normal rotation (POR) column address inverse rotation scan direction column scan (POR) scan direction page scan Please refer Figure respectively detail description column/page scan direction modes color arrangement P22, P21, P20: control bits used setting (RGB) color arrangement segment output. value. Please refer Table detail mapping segment output. Gray scale selection. Please refer Table 16-bit/pixel mode (RRRRRGGG GGGBBBBB) 8-bit/pixel mode 12-bit/pixel mode (POR) reserved Disable Gamma correction (POR) Enable Gamma correction Gamma curve selection gamma curve 1.4] (POR) gamma curve 1.7]
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Command Display Control
Description
Driver duty selection Select driver duty from 1/80. Y5Y4Y3Y2Y1Y0 increased from 00001b 10011b (MUX6880=VSS) from 00001b 10000 (MUX6880=VDD), number display lines, increased same rating. specify Y1Y0. dummy byte should sent before command byte After command byte sent, additional dummy byte should sent device order finish whole command. Block Address X5X4X3X2X1X0 used specify block address block lines) scrolling area. block address 00000b (POR) Bottom Block Address Y5Y4Y3Y2Y1Y0 used specify block address block lines) bottom scrolling area. Bottom block address 00000b (POR) Number specified Blocks number specified blocks Number (Top fixed area Scroll area) blocks bottom scroll whole screen scroll mode chosen, number specified blocks Z5~Z0 Number specified blocks 00000b (POR) Area Scroll Mode There four types area scroll. Types Area Scroll Center Screen Scroll Screen Scroll Bottom Screen Scroll Whole Screen Scroll Type area scroll Whole Screen Scroll (POR)
Area Scroll
Scroll Start
X5X4X3X2X1X0 specify start block address block lines) area scrolling. Start block address 00000b (POR)
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Command Power Control Register
Description X0=0: turns reference voltage generator (POR) X0=1: turns reference voltage generator X1=0: turns internal regulator voltage follower (POR) X1=1: turns internal regulator voltage follower Select booster level
Contrast Level Internal Regulator Resistor Ratio
Boost level (POR)
Select contrast level from contrast steps Contrast increases X5X4X3X2X1X0 increased from 000000b 111111b. X5X4X3X2X1X0 000000b (POR) internal regulator gain (1+R2/R1) VOUT increases Y2Y1Y0 increased from 000b 111b. factor, 1+R2/R1, given Y2Y1Y0 000: 2.84 (POR) Y2Y1Y0 001: 3.71 Y2Y1Y0 010: 4.57 Y2Y1Y0 011: 5.44 Y2Y1Y0 100: 6.30 Y2Y1Y0 101: 7.16 Y2Y1Y0 110: 8.03 Y2Y1Y0 111: 8.89
X0=0: contrast voltage regulator Increment Decrement incremented contrast X0=1: contrast voltage regulator decremented Normal/Inverse Display Enter partial Display Exit partial Display Display On/Off Enter/Exit sleep mode Enable/disable internal oscillator X0=0: normal display (POR) X0=1: inverse display X6X5X4X3X2X1X0: Start Address 000000b (POR) Y6Y5Y4Y3Y2Y1Y0: Address 000000b (POR) Exit "partial display mode" executing command 10101001b (POR) X0=0: turns panel (POR) X0=1: turns panel X0=0: exit sleep mode. X0=1: enter sleep mode. (POR) Internal oscillator status (POR)
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Command
Description
Temperature compensation coefficient
Average temperature gradients Average Temperature Gradient -0.10 -0.15 -0.20(POR) -0.25 X6X5X4X3X2X1X0 specify ROW0 ROW79 which first display line (COM0) mapped Command result Operation command should issued after execution Status Read command Enter "write display data mode executing command 01011100b. following byte used specify data byte written GDDRAM directly. should stated logic during display data written GDDRAM.
First Display
Write display data
Read display data
Enter "read display data mode executing command 01011100b. next byte dummy data. GDDRAM data will read form second byte. GDDRAM column address pointer will increased automatically after each data read (256 color mode) after each 3-bytes data read. color mode) after each 2-bytes data read (65K color mode).
Remarks: when read
Remark: denote DON'T CARE
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Graphic command table
Command Draw Line Description Enter "Draw line mode" executing command 10000011. following four bytes used specify start coordinates address, start coordinates address, coordinates address coordinates address. remaining bytes used specify color. Remarks: 103; 103;
16-bit color 8/12-bit color
Fill Enable/Disable
Enter "Fill Enable/Disable mode" executing command 10010010. A0=0: Filled color option disabled (POR) A0=1: Filled color option enabled Enter "Draw rectangle mode" executing command 10000100. following four bytes used specify start coordinates address, start coordinates address, coordinates address coordinates address. next bytes used specify color. last bytes used specify fill color.
Remarks: 103; 103;
Draw Rectangle
16-bit color
8/12-bit color
Copy
Enter "Copy mode" executing command. following four bytes used specify start coordinates address, start coordinates address, coordinates address coordinates address. remaining bytes used specify location coordinates coordinates.
Remarks: 103;
Window
Enter "Dim Window mode" executing command 10001100. following four bytes used specify start coordinates address, start coordinates address, coordinates address coordinates address. selected window area will dimmed white black according command
Remarks: 103;
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Command Clear Window
Description Enter "Clear Window mode" executing command 10001110. following four bytes used specify start coordinates address, start coordinates address, coordinates address coordinates address. pixels contrast will Remarks: 103;
Remark:
denote DON'T CARE After executed graphic command, waiting time required update GDDRAM content. (When VDD=2.4~3.0V, waiting time 340ns/pixel; When VDD=3.0~3.6V, waiting time 270ns/pixel)
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Extended command table
Command Description biasing ratio Allow user bias from 1/10 B2B1B0 Bias ratio bias bias bias bias (POR, 68Mux) bias (POR, 80Mux) bias 1/10 bias
This command uses change frame frequency Frame frequency N-line inversion. (MUX68/ line Inversion F3F2F1F0 (MUX68/ VSS) (MUX68/ VDD) 111.5Hz 113Hz 103Hz 105Hz 98Hz 99.5Hz 92Hz 93.5Hz 89.5 90.5Hz 85.5Hz 82Hz (POR) 78.5Hz (POR) 77.5Hz 77.5Hz 74Hz 71.5Hz 69Hz 67Hz 65Hz 63.5 63Hz 61.5 61Hz N3N2N1N0 sets n-line inversion register from lines reduce display crosstalk. Register values from 00001b 11111b mapped lines lines respectively. Value 00000b disables N-line inversion. 00110 value. avoid polarity some lines, should noted that total number should multiple lines inversion (n). reset n-line counter frame (POR) will reset n-line counter frame
Select PWM/FRC
Driving scheme selection X1X0 bits (POR) Reserved Reserved Reserved
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Command sequence
Description
MUX68
ROW0-79 COM0-79 (POR) COM0-15, 32-55, 16-31, 56-79 COM1,3,5.79 (odd) COM0,2,4.78 (even) COM0,2,4.78 (even) COM1,3,5.79 (odd) ROW0-33 ROW46-79 COM0-33 COM34-67(POR) COM0-15, 32-49 16-31, 50-67 COM1,3,5.67 (odd) COM0,2,4.66 (even) COM0,2,4.66 (even) COM1,3,5.67 (even)
MUX68
setting
programming
This command offset value contrast X4X3X2X1X0 00000 original contrast 00001 original contrast step 00010 original contrast steps 00011 original contrast steps 00100 original contrast steps 00101 original contrast steps 00110 original contrast steps 00111 original contrast steps 01000 original contrast steps 01001 original contrast steps 01010 original contrast steps 01011 original contrast steps 01100 original contrast steps 01101 original contrast steps 01110 original contrast steps 01111 original contrast steps 10000 original contrast steps 10001 original contrast steps 10010 original contrast steps 10011 original contrast steps 10100 original contrast steps 10101 original contrast steps 10110 original contrast steps 10111 original contrast steps 11000 original contrast steps 11001 original contrast steps 11010 original contrast steps 11011 original contrast steps 11100 original contrast steps 11101 original contrast steps 11110 original contrast steps 11111 original contrast step This command starts program driver with offset value. Each programmed once.
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Table Read Command Table
Command Status Register Read Description D7D6 Center Screen Scroll Mode D7D6 Screen Scroll Mode D7D6 Bottom Screen Scroll Mode D7D6 Whole Screen Scroll Mode
Scan Direction column direction Scan Direction page direction Display Display Sleep Mode disabled Sleep Mode enabled Display Inverse Display Normal Partial display disabled Partial display enabled
Note: Command patterns other than that given Command Table prohibited. Otherwise, unexpected result will occur. Remarks: denote DON'T CARE
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Data Read Write
read data from GDDRAM, command should executed then input High 6800-series parallel mode. High 8080-series parallel mode. data read provided serial mode. normal mode, GDDRAM column address pointer will increased automatically after each data read 8-levels gray scale mode after each 3-bytes data read 16-levels gray scale mode after 2-bytes data read 64-levels gray scale mode. Also, dummy read required before first data read. Figure Functional Description. write data GDDRAM, input High 6800-series parallel mode. serial interface, will always write mode. GDDRAM column address pointer will increased automatically after each data write 8-levels gray scale mode each 3-bytes data write 16-levels scale mode after 2-bytes data read 64-levels gray scale mode. address will reset next data read/write operation executed when column address.
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COMMAND DESCRIPTIONS
Column Address
This command specifies 8-bit column address display data RAM. start column address specified this command. driver supports columns. addresses incremented from start column column column direction scan, page address incremented column address then returned start column. column address will increased each data access after preset MCU. Start column column must maintained.
Alignment using 8-levels gray scale mode Column Read Color Direction Data Page BLOCK ICON ICON
COMMON OUTPUTS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 ICON
COL306
COL307
COL308
COL309
COL310
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
SEGMENT OUTPUTS
Table arrangements 8-levels gray scale mode
SSD1773 Series
COL9
COL311
COL10
COL11
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Alignment using 16-levels gray scale mode Column Color Data Page
COL0 COL1 COL2 COL3 COL4 COL5
Color Data
BLOCK
Page ICON ICON
COMMON OUTPUTS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 ICON COL306 COL307 COL308 COL309 COL310 COL311
Read Direction
COL10
SEGMENT OUTPUTS
Table arrangements 16-levels gray scale mode
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COL11
COL6
COL7
COL8
COL9
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Read Direction
Color
BLOCK
Page ICON ICON
Data
Alignment using 64-levels gray scale mode Column
COL306
COMMON OUTPUTS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 ICON
COL307
COL308
COL309
COL310
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
SEGMENT OUTPUTS
Table arrangements 64-levels gray scale mode
SSD1773 Series
COL9
COL311
COL10
COL11
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Page Address
This command enters page address from page register read/write operations. driver supports lines. addresses incremented from start page page page direction scan, column address incremented page address then returned start page. Start page page must maintained.
Output Scan Direction
This command sets scan direction output allowing layout flexibility module assembly. Please refer COMMAND TABLE detail mapping. addition, display will have immediate effect once this command issued. That this command sent during normal display, graphic display will have vertical flipping effect.
Data Output Scan Direction
This command sets DDRAM such that operates display data internal RAM. Normal Inverse page/column/scan directions Data Scan direction either normal inverse display page column address scan direction. column page direction illustrated following figure.
MUX68 Column Direction P11=0 P11=1 P10=0 P10=1 Page Direction P11=0 P11=1 P10=0 P10=1
Figure column page scan direction
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parameters following command data output scan direction specifies arrangement selection various gray-scale modes. Please find information arrangement gray scale mode following section. arrangement mode arrangement mode selected according following table. Three selection bits will give eight combinations arrangements. Each combination will specify Red, Green Blue segment output arrangement even page.
P22, P21, (POR) LINE COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7
COL311
Even page page
Table Arrangement modes
Gray scale mode Gray scale selection corresponding data arrangement different interface mode illustrated following table.
Gray Scale selection interface mode (select PS2PS0, Table Data arrangement (D7.D0) mode denote don't care
P31,
Note
16-bit pixel 8-bit pixel 12-bit pixel
RRRRRGGG (byte GGGBBBBB (byte RRRGGGBB RRRRGGGG (byte BBBBRRRR (byte GGGGBBBB (byte
byte/ pixel byte pixel byte pixels
Table Data arrangement different pixel mode
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Display Control
This command used select duty ratio available driving duty selected using this command. driving duty changed from 1/80.
Area Scroll
This command specifies portion screen scrolling. command sets starting block address, finishing block address, number specific blocks area scroll mode area scrolling. Please noted that starting block address should smaller than finishing block address. block address increment direction started block such that GDDRAM address corresponds fixed area. Similarly, block address decrement direction started block such that GDDRAM address corresponds bottom fixed area. remaining block address excluding bottom fixed areas assigned scroll plus background areas. area scroll function divided into four parts. Part -Specify block address scroll background areas. Specify block screen scroll whole screen scroll. scroll start block address also this block address until scroll start command executed. Part Specify bottom address scroll background areas. Specify block bottom whole screen scroll. Part Specify number scrolled blocks number (Top fixed area scroll area) blocks When bottom scroll whole screen scroll chosen, resulted value identical value stated part Part Specify area scroll type. Altogether there four types area scroll. Please refer Table detail.
Types Area Scroll Center Screen Scroll Screen Scroll Bottom Screen Scroll Whole Screen Scroll
Table Area scrolling selection modes
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Center Screen
Screen
Bottom Screen
Whole Screen Scroll
Fixed Area
Scroll Area
Figure Area scrolling selection modes
area scroll function executed prompt area scroll command following changing start block address scroll start command. Figure illustrates operation model scrolling function.
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Example: Center screen scroll 1/64 duty (display range: lines blocks) Description Command Area Scroll lines (block block specified fixed area Block Address Number fixed area =8/4 lines (block block specified bottom fixed area lines (block block specified background area Specified Bottom Block Address Bottom Block Address Number Background area (11Hex) lines (block block specified scroll area Number Specified Block fixed area Scroll Area (0DHex) area scroll mode Center screen mode
Data
Scroll start (Scroll range form 11H)
DDRAM:
panel
blocks line
Fixed area Display area Scroll area Background area
Figure GDDRAM updates area scrolling
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Block Line GDDRAM Content Area
lines Panel COM0
Scroll Area
Background Area Bottom Area
Scroll Start Scroll Start
Scroll Start
COM63 COM0
Example Program Specified Center Scroll mode. Void center_scroll(void) //Set 1/64 Duty Comm_out (0xCA);
Data_out (0x00);
Data_out (0x0F); Data_out(0x00); //Set Area Scroll
COM63 COM0
Comm_out(0xAA);
Data_out(0x02); Block Address Data_out(0x11); Specified Bottom Block Address Data_out(0x0D); //Number Specified Block Data_out(0x00); //Center Screen Mode //Set Scroll Start (I=0x02; I<=0x11; I++) Comm_out(0xAB); //set scroll start Data_out(I); Delay (200); //delay 200ms Scroll Start
COM0 COM63
COM63
Figure Example Specified Center Scroll Mode
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Scroll Start
This command specifies starting block address area scrolling then executes area scroll changing start block address dynamically. Start block block must maintained. Please noted that scroll start command should executed after area scroll command.
Power Control Register
This command turns on/off various power circuits associated with chip. There three power subcircuits (reference voltage generator, internal regulator voltage follower) could turned on/off this command. addition, configuration internal primary booster (4X/5X/6X/7X) selected this command.
Contrast Level Internal Regulator Resistor Ratio
This command adjusts contrast panel changing driving voltage, VOUT, provided On-Chip power circuits. VOUT with steps (6-bit) contrast control register compound commands. Please refer Figure contrast control process flow diagram.
Contrast Control Register Contrast Level Data Changes Complete?
Figure Contrast Control Flow Segment Re-map
This command also sets feedback gain internal regulator. There altogether internal regulator gains, which used adjustment VOUT level. This command enable eight internal resistor (IRS) settings different regulator gains when using internal regulator resistor network. Contrast Control Voltage Range curves referred following formula:
Vout *Vcon
Vcon Vref
Remarks: -0.20%/
where Vref 1.7V
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Contrast Curve
Vout[V] Contrast[0~63]
Figure Contrast Control Voltage Range Curve
9.10 Increment/Decrement contrast (D6/D7
This command increase contrast step decrease contrast step most convenient change contrast display programming.
9.11 Normal/Inverse Display (A6/A7
normally white display panel, after execution Normal Display command, image data 000(RGB) indicates black pixel image data FFF(RGB) indicate white pixel. normally black display panel, after execution Inverse Display command, image data 000(RGB) indicates Black pixel image data FFF(RGB) indicate white pixel.
Example: normal White display panel (Set Normal Display: A6Hex): Content Color White Black Green Blue normal Black display panel (Set Normal Display: A7Hex): Content Color White Black Green Blue
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9.12 Enter Partial Display
This command following parameters specify display area partial display mode. following figure shows display non-display area when partial display mode executed.
Display area
(Partial Display Area) Non-display area
Figure Partial display mode
9.13 Exit Partial Display
This command exits partial display mode.
9.14 Display On/Off (AF/AE
This command used turn display When display issued with entire display power save mode will entered.
9.15 Enter/Exit sleep mode (95/94
This command enter exit sleep mode.
9.16 Enable/Disable internal oscillator (D1/D2
This command enables disables internal oscillator. internal oscillator turned after hardware software reset.
9.17 Temperature compensation coefficient
This command sets average temperature gradients. Four sets average temperature gradients selected. Please refer command table detail description average temperature gradients. default value temperature gradient -0.20
9.18 First Display
This command first display data ROW0 ROW79.
9.19
command causing chip takes Operation.
9.20 Write display data mode
This command used execute write display data mode. display data byte directly written GDDRAM. Please noted that signal should high during display data written GDDRAM.
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9.21 Read display data mode
This command used execute read display data mode. display data byte directly read from GDDRAM. Please noted that signal should high during display data from GDDRAM.
Graphic Command
9.22 Draw Line
Given starting point (X1, ending point (X2, Y2), line will drawn with color specified.
following example illustrates line drawing procedure. Enter "draw line mode" execute command starting X-coordinates, E.g., 00H. starting Y-coordinates, E.g., 00H. finishing X-coordinates, E.g., finishing Y-coordinates, E.g., color (0,1,0) e.g., followed Result: green line will drawn between coordinates (0,0) (1,1) Remark: 103; 103;
9.23 Fill Enable/Disable
This command allows fill color option enabled disabled. This command applicable Draw Rectangle feature. When selection "0", fill color option disabled. When selection "1", fill color option enabled.
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9.24 Draw rectangle
Given starting point (X1, ending point (X2, Y2), specify width height rectangle that will drawn with color specified. Remarks: fill color option disabled, enclosed area will filled.
following example illustrates rectangle drawing procedure. Enter "draw rectangle mode" execute command starting X-coordinates, E.g., 00H. starting Y-coordinates, E.g., 00H. finishing X-coordinates, E.g., finishing Y-coordinates, E.g., color (1,0,0) e.g., following filled color (0,1,0) e.g., following Result: rectangle will drawn (0,0) (2,2), filled green with border Remark: 103;
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9.25 Copy
Copy rectangular region defined starting point (X1, ending point (X2, location (X3, Y3). There possible results with command copy executed depending setting start point coordinates point coordinates. following example illustrates copy procedure. Case overlap region will superimpose. Enter "copy mode" execute command starting X-coordinates, E.g., 00H. starting Y-coordinates, E.g., 00H. finishing X-coordinates, E.g., finishing Y-coordinates, E.g., X-coordinates, E.g., Y-coordinates, E.g.,
Case original content remains unchanged
Enter "copy mode" execute command starting X-coordinates, E.g., 00H. starting Y-coordinates, E.g., 00H. finishing X-coordinates, E.g., finishing Y-coordinates, E.g., X-coordinates, E.g., Y-coordinates, E.g., Remark: 103;
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9.26 Window
This command will window area specify starting point (X1, ending point (X2, Y2). After execution this command, selected window area will dimmed white. Additional execution this command over same window area will change data content. Remark: 103;
9.27
Clear Window
This command sets window area specify starting point (X1, ending point (X2, clear window display. GDDRAM content window will zero. Remark: 103;
Extended Command
9.28 biasing ratio
This command selects suitable bias ratio (1/4 1/10) required driving particular panel use.
9.29 Frame Frequency
This command specifies frame frequency minimize flickering main frequency. frequency after POR.
9.30 N-line inversion
Number line inversion this command reducing crosstalk noise. 32-line inversion operations could selected. POR, this operation 0110b lines). should noted that total number (including icon line) should multiple inversion number (n). else, some lines will change their polarity during frame change.
9.31 Select PWM/FRC
This command Pulse Width Modulation, Frame Rate Control FRC.
9.32 setting
(One Time Programming) method adjust VOUT. order eliminate variations module term contrast level, used achieve best contrast every modules. Each programmed time. setting programming should include major steps. Find offset programming following,
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Step Find offset Hardware Reset (sending active reset pulse pin) Send original initialization routines display test patterns Adjust contrast value (C:0x81, D:0x00~0x3F, 0x00 0x07) until there best visual contrast setting steps Contrast value best visual contrast Contrast value original initialization
Example Contrast value original initialization 0x20 Contrast value best original initialization 0x24 offset value 0x24 0x20 setting command should 0xF6, 0x12, 0x0A) Example Contrast value original initialization 0x20 Contrast value best original initialization 0x1B setting 0x1B 0x20 setting command should (C:0xF6, 0x1D, 0x2A) Step programming Hardware Reset (sending active reset pulse pin) Enable Oscillator 0xD1) Exit Sleep Mode 0x94) Connect external VOUT (see diagram below) Send setting commands that find step 0xF6, 0x10~0x1F, 0x0A/2A) (10)Send programming command 0xF8) (11)Wait least seconds (12)Hardware Reset (13)Verify result repeating step
SSD1773
(12)
VOUT
14.5-15.5V
Note: 4.7u
Figure programming circuitry
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Start Step Step
Hardware reset Send original initialization routines iii) display test patterns
Hardware reset Enable oscillator
Adjust contrast level best visual level
Connect external voltage (14.5~15.5V) VOUT pins
Accept contrast level panel?
Send setting commands Send programming command iii) Wait Hardware reset
setting steps Adjusted contrast value Original contrast value
Send original initialization routines display test patterns iii) Inspect contrast
Figure Flow chart programming Procedure
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Example program Find offset:
Hardware reset sending active reset pulse COMMAND(0XD1) COMMAND(0X94) COMMAND(0X20) DATA(0X0B) COMMAND(0XCA) DATA(0X10) COMMAND(0XF7) COMMAND(0XFB) DATA(0X03) COMMAND(0X81) DATA(0X14) DATA(0X05) Duty ratio 68Mux ([68 16(decimal) 10(Hex)) PWM/FRC Biasing ratio \\Set target gain contrast. contrast gain 7.16 \\Enable oscillator; exit sleep mode; turn reference voltage generator, internal regulator voltage follower; Select booster level.
target display contents COMMAND(0X15) DATA(0x00) DATA(0X67) COMMAND(0X75) DATA(0X00) DATA(0X43) COMMAND(0X5C) DATA(.) COMMAND(0xAF) display column address start column address column address page address start page address page address write target content GDDRAM
offset calculation. target offset value Hardware reset sending active reset pulse COMMAND(0XD1) COMMAND(0x94) Enable Oscillator Exit Sleep Mode
programming:
Connect external VOUT (14.5V~15.5V) COMMAND(0XF6) DATA(0X11) DATA(0x2A) offset value (X4X3X2X1X0 00011) 0001 X4X3X2X1 00X00 1010, where X4X3X2X1X0 offset value Send programming command.
COMMAND(0XF8)
Wait least seconds programming wait time.
Verify result:
After programming, procedure repeated inspection contrast panel.
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Read Status Command
9.33 Status register read
following parameters monitored status read register. Various area scroll mode Column scan direction Page scan direction Display ON/OFF Sleep mode ON/OFF Display Normal/Inverse Partial display mode ON/OFF
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MAXIMUM RATINGS
Table Maximum Ratings (Voltage Referenced VSS)
Symbol VOUT Parameter Value -0.3 +4.0 -0.3 VSS-0.3 Unit
Supply Voltage Input Voltage Current Drain Excluding Operating Temperature Storage Temperature Input Resistance
Tstg
+150 1000
Maximum ratings those values beyond which damages device occur. Functional operation should restricted limits Electrical Characteristics tables Description section This device contains circuitry protect inputs against damage high static voltages electric fields; however, advised that normal precautions taken avoid application voltage higher than maximum rated voltages this high impedance circuit. proper operation recommended that Vout constrained range VOUT. Reliability operation enhanced unused input connected appropriate logic voltage level (e.g., either VDD). Unused outputs must left open. This device light sensitive. Caution should taken avoid exposure this device light source during normal operation. This device radiation protected.
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CHARACTERISTICS
Table Characteristics (Unless otherwise specified, Voltage Referenced VSS, 3.6V, 85°C)
Symbol
VDDIO
Parameter System power supply pins logic block Range
IDP2
ISLEEP
VOUT VREF
Test Condition Recommend Operating Voltage Possible Operating Voltage Recommend Operating Voltage Power supply pins Possible Operating Voltage Booster Reference Supply Recommend Operating Voltage Voltage Range Possible Operating Voltage 2.7V, Voltage Generator DC-DC 16-bit 8080 parallel Access Mode Supply Current writing AAAA HTcyc =3MHz, Typ. Drain (VDD Pins) Osc. Freq., Display panel attached. 2.7V, VOUT 10V, Voltage Generator DC-DC Display Mode Supply Current Converter Enabled, R/W(WR) Halt, Drain (VDD Pins) Typ. Osc. Freq., Display panel attached. Sleep Mode Supply Current 2.7V, Driving Waveform Drain (VDD Pins) Off, Oscillator Off, R/W(WR) halt. Display Voltage Generator Enabled, DC-DC Converter Driving Voltage Generator Enabled, Typ. Osc. Freq., Output (Vout Pin) Regulator Enabled, Divider Enabled. -0.10%/ Internal Reference Voltage -0.15%/ -0.20%/ (POR) -0.25%/
Unit
1000
1.63 1.64 1.65 1.66 1.65 1.80 1.50 0.9* VDDIO 0.8* VDDIO
1.68 1.69 1.70 1.71 1.70 1.85 1.55
13.5 1.73 1.74 1.75 1.76 1.75 1.91 1.59 VDDIO 0.1*VD
Reference Voltage Reference Voltage Reference Voltage VOH1 VOL1 VIH1 VIL1 IIL/IIH Vout Logic High Output Voltage Logic Output Voltage Logic High Input voltage Logic Input voltage
Iout=-100µA Iout=100µA
VDDIO 0.2* VDDIO
Logic High Output Current Vout VDDio-0.4V Source Logic Output Current Drain Vout 0.4V Logic Output Tri-state Current Drain Source Logic Input Current Logic Pins Input Capacitance Regulator Enabled, Internal Variation Vout Output (VDD Contrast Control Enabled, fixed) Contrast Control Register
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Symbol
Parameter Test Condition Average Temperature Gradient Flat Temperature Coefficient Temperature Coefficient Voltage Regulator Enabled Temperature Coefficient (POR) Temperature Coefficient
Unit
-0.12 -0.17 -0.22
-0.10 -0.15 -0.20 -0.25
-0.12 -0.17 -0.22 -0.27
*The formula temperature coefficient
TC(%) Vref Vref Vref
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CHARACTERISTICS
Table Characteristics (Unless otherwise specified, Voltage Referenced VSS, 2.7V,
Symbol Fosc Parameter Oscillation Frequency Display Timing Generator for: Mode Icon disabled Test Condition Internal Oscillator Enabled (default), 2.7V 584.8 Unit
615.6
FFRM
Frame Frequency for: Mode Icon disabled
Graphic Display Mode, Display Internal Oscillator Enabled
Remarks:
Fosc stands frequency value internal oscillator
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Table Parallel 6800-series Timing Characteristics
85°C, 2.4V 3.6V, VDDIO 2.4V VDD)
Symbol tcycle tcycle tDSW tDHW tACC Parameter Clock Cycle Time (write cycle) Control Pulse Width Control Pulse High Width Clock Cycle Time (read cycle) Control Pulse Width (read cycle) Control Pulse High Width (read cycle) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time 166.6 Unit
tcycle
tDHW
tDSW D0~D7(WRITE) tACC D0~D7(READ) Valid Data
timing reference rising falling edge pin. tDSW tDHW timing reference rising falling edge pin.
Valid Data tDHR
Figure Parallel 6800-series Interface Timing Characteristics (PS0
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Table Parallel 8080-series Timing Characteristics
85°C, 2.4V 3.6V, VDDIO 2.4V VDD)
Symbol tcycle tcycle tDSW tDHW tACC Parameter Clock Cycle Time (write cycle) Control Pulse Width Control Pulse High Width Clock Cycle Time (read cycle) Control Pulse Width (read cycle) Control Pulse High Width (read cycle) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time 166.6 Unit
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Write Cycle
tcycle
tDSW
tDHW
D0-D7(WRITE)
Valid Data
timing reference rising falling edge pin. tDSW tDHW timing reference rising falling edge pin.
Read Cycle
tcycle
tACC tDHR Valid Data
D0-D7(READ)
timing reference rising falling edge pin. tDSW tDHW timing reference rising falling edge pin.
Figure Parallel 8080-series Interface Timing Characteristics (PS0
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Table 4-wires Serial Timing Characteristics
85°C, 2.4V 3.6V, VDDIO 2.4V VDD)
Symbol tcycle Parameter Clock Cycle Time Serial Clock Cycle Time Clock tolerance Register select Setup Time Register select Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Time Clock High Time 66.6 Unit
fCLK tCSS tCSH tDSW tOHW tCLKL tCLKH
33.3 33.3
tCSH tcycle
tCSS
tCLKL
tCLKH
SCK(D6)
tDSW tDHW
SDA(D7)
Valid Data
SCK(D6)
SDA(D7)
Figure Serial 4-wires Timing Characteristics (PS0
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Table 3-Wires Serial Timing Characteristics
85°C, 2.4V 3.6V, VDDIO 2.4V VDD)
Symbol tcycle Parameter Clock Cycle Time Serial Clock Cycle Time Clock tolerance Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Time Clock High Time Unit
fCLK tCSS tCSH tDSW tOHW tCLKL tCLKH
tCSS tcycle
tCSH
tCLKL
tCLKH
SCK(D6)
tDSW tDHW
SDA(D7)
Valid Data
SCK(D6)
SDA(D7)
Figure 3-Wires Serial Timing Characteristics (PS0
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Figure Initial Sequence power up/down
Power 2.4~3.6 VDD~3.6 VDDIO
Hardware Reset Active 10us
III) Initial Code Refer example program reference Need charge-up VOUT 11.7V
Normal Operation
Enter Power saving Mode Display Enter Sleep mode Disable Oscillator
Return Normal Mode Enable oscillator Exit Sleep mode VOUT need charge-up 11.7V Display
VII) Power Display Enter Sleep mode Disable Oscillator Disconnect VDD, VDDIO supply
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Table Power Up/Down Timing Characteristics 85°C, 2.4V 3.6V, VDDIO 2.4V VDD)
Symbol tSTABLE tRES tREADY Parameter Power rise time Power delay time Chip stable time Reset pulse Chip need time after hardware reset Unit
VDDIO tSTABLE tREADY tRES
D0~D7
Figure Power
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Symbol tCHARGE tPDOWN
Parameter VOUT Charge wait time (charge 11.7V) Power Hold time
Unit
D0~D7
tCHARGE
Figure Initial Code Timing Chart
VCI/VDD/VDDIO
tPHOLD
tCHARGE
D0~D7
After enable Booster Regulator circuitry, there 200ms mask period that used provide wait time charge VOUT capacitor. Within mask period, doesn't have output waveform.
Enter power save mode
Exit power save mode return normal mode
Power
Figure Power save power power timing chart
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APPLICATION EXAMPLES
DISPLAY PANEL SIZE 104RGB ICON LINE
COM40 COM41 COM78 COM79
ICON COM0 COM1 COM38 COM39
SEG103-B SEG103-G SEG103-R SEG102-B SEG102-G SEG102-R SEG1-B SEG1-G SEG1-R SEG0-B SEG0-G SEG0-R
Output scan command [command: BBH, Data:01H] ROW79 ROW40
COL0 .COL311ROW39 .ICON
SSD1773 (DIE FACE
VDDIO
VOUT
~2uF; 2.2uF 4.7uF. Logic connections specified above: Pins connected VDD: ;D0~D5 Pins connected VSS: PS0; PS1; RVSS; CVSS; MUX68/( Pins connected VCI: VLREF; VCIX2 Pins connected VOUT: VHREF
,where 2.775V;
Figure Application Example (4-wires mode)
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DISPLAY PANEL SIZE 104RGB ICON LINE
COM40 COM41 COM78 COM79
ICON COM0 COM1 COM38 COM39
SEG103-B SEG103-G SEG103-R SEG102-B SEG102-G SEG102-R SEG1-B SEG1-G SEG1-R SEG0-B SEG0-G SEG0-R
Output scan command [command: BBH, Data:01H] ROW79 ROW40
COL0 .COL311ROW39 .ICON
SSD1773 (DIE FACE
VDDIO
VOUT
,where 2.775V;
2.2uF 2.2uF 4.7uF.
Logic connections specified above: Pins connected VDD: PS0; PS1; Pins connected VSS: RVSS; CVSS; MUX68/( Pins connected VCI: VLREF; VCIX2 Pins connected VOUT: VHREF
Figure Application Example (6800 mode)
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2.775V
2.775V
2.775V
/RES D0~D7
VDDIO VCIX2
VOUT VHREF
SSD1773
CVSS RVSS VLREF
Normal Application
2.4V
2.775V 2.4V /RES D0~D7
2.4V
2.775V
VDDIO VCIX2
VOUT VHREF
SSD1773
CVSS RVSS VLREF
Voltage
Figure VDD, VDDIO, connection example
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PACKAGE INFORMATION
14.1 TRAY DIMENSIONS
Spec
(mil)
+0.2 +0.2
76.0 68.0
(2992) (2677) (158) (55) (703) (82) (29)
1.40 17.85 2.07 0.73
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Solomon Systech reserves right make changes without further notice products herein. Solomon Systech makes warranty, representation guarantee regarding suitability products particular purpose, does Solomon Systech assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Solomon Systech does convey license under patent rights rights others. Solomon Systech products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Solomon Systech product could create situation where personal injury death occur. Should Buyer purchase Solomon Systech products such unintended unauthorized application, Buyer shall indemnify hold Solomon Systech offices, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Solomon Systech negligent regarding design manufacture part
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