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SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Members Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Process Operating Range 5.5-V Distributed Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes Layout Latch-Up Performance Exceeds JESD Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54AHC16240 PACKAGE SN74AHC16240 DGG, DGV, PACKAGE (TOP VIEW)
description
'AHC16240 devices 16-bit buffers line drivers designed specifically improve performance density 3-state memory address drivers, clock drivers, bus-oriented receivers transmitters. These devices used four 4-bit buffers, 8-bit buffers, 16-bit buffer. They provide inverting outputs symmetrical active-low output-enable (OE) inputs.
ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. SN54AHC16240 characterized operation over full military temperature range -55°C 125°C. SN74AHC16240 characterized operation from -40°C 85°C.
FUNCTION TABLE (each 4-bit buffer/driver) INPUTS OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC Widebus trademarks Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
Copyright 2000, Texas Instruments Incorporated
DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
logic symbol
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
logic diagram (positive logic)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Output voltage range, (see Note -0.5 Input clamp current, Output clamp current, VCC) Continuous output current, VCC) Continuous current through each Package thermal impedance, (see Note package 70°C/W package 58°C/W package 63°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD
POST OFFICE 655303
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SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54AHC16240 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current 3.85 1.65 SN74AHC16240 3.85 1.65 UNIT
ns/V
Input transition rise fall rate
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS GND, (OE) GND, 2.58 3.94 0.36 0.36 ±0.1 ±0.25 25°C SN54AHC16240 2.48 ±2.5 SN74AHC16240 2.48 0.44 0.44 ±2.5 UNIT
products compliant MIL-PRF-38535, this parameter production tested
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
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SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(o) FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 5.3* 5.3* 6.6* 6.6* 7.8* 7.8* 10.3 10.3 8.4* 8.4* 10.6* 10.6* 11.5* 11.5* 11.9* 11.9 14.1 14.1 1.5** SN54AHC16240 12.5* 12.5* 12.5* 12.5* 13.5 13.5 SN74AHC16240 12.5 12.5 12.5 12.5 13.5 13.5 UNIT
products compliant MIL-PRF-38535, this parameter production tested. products compliant MIL-PRF-38535, this parameter does apply.
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(o) FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 3.6* 3.6* 4.7* 4.7* 5.2* 5.2* 7.3* 7.3* 7.2* 7.2* SN54AHC16240 8.5* 8.5* 8.5* 8.5* 10.5 10.5 10.5 10.5 SN74AHC16240 10.5 10.5 10.5 10.5 UNIT
products compliant MIL-PRF-38535, this parameter production tested. products compliant MIL-PRF-38535, this parameter does apply.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
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SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
noise characteristics, 25°C (see Note
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic Quiet output, minimum dynamic Quiet output, minimum dynamic High-level dynamic input voltage SN74AHC16240 -0.6 UNIT
VIL(D) Low-level dynamic input voltage NOTE Characteristics surface-mount packages only.
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS load, UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
Open
From Output Under Test (see Note
Test Point
From Output Under Test (see Note
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
Open
LOAD CIRCUIT TOTEM-POLE OUTPUTS
LOAD CIRCUIT 3-STATE OPEN-DRAIN OUTPUTS Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES tPZL tPZH Output Waveform (see Note tPLZ tPHZ
Input
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
tPHL
Output Control
tPLH
Output Waveform (see Note
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
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Copyright 2000, Texas Instruments Incorporated

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