PEEL22CV10A-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logi

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PEEL22CV10A-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logi

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Commercial/ Industrial
PEEL22CV10A-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device
High Speed/Low Power Speeds ranging from 25ns Power 30mA 25MHz Electrically Erasable Technology Superior factory testing Reprogrammable plastic package Reduces retrofit development cost
Architectural Flexibility product term input array inputs outputs configurations macrocell Synchronous preset, asynchronous clear Independent output enables 24-pin DIP/SOIC/TSSOP 28-pin PLCC Application Versatility Replaces random logic JEDEC compatible with 22V10 Enhanced Architecture fits more logic than ordinary
Development/Programmer Support Third party software programmers PLACE Development Software
General Description
PEELTM22CV10A Programmable Electrically Erasable Logic (PEELTM) device providing attractive alternative ordinary PLDs. PEELTM22CV10A offers performance, flexibility, ease design production practicality needed logic designers today. PEELTM22CV10A available 24-pin DIP, SOIC, TSSOP 28-pin PLCC packages (see Figure with speeds ranging from 25ns with power consumption 30mA. EE-reprogrammability provides convenience instant reprogramming development reusable production inventory, minimizing impact programming changes errors. EE-reprogrammability also improves factory testability, thus ensuring highest quality possible. PEELTM22CV10A JEDEC file compatible with standard 22V10 PLDs. Eight additional configurations macrocell total also available using software/programming option (i.e., 22CV10A+). additional macrocell configurations allow more logic into every design. Programming development support PEELTM22CV10A provided popular third-party programmers development software. also offers free PLACE development software.
Figure Configuration
I/CLK
Figure Block Diagram
TSSOP
PLCC
*Optional extra ground -7/I-7 speed grade.
SOIC
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ASYNCHRONOUS CLEAR MACROCELLS)
MACRO CELL
I/CLK
MACRO CELL
MACRO CELL
MACRO CELL
MACRO CELL
MACRO CELL
MACRO CELL
MACRO CELL
MACRO CELL
MACRO CELL
SYNCHRONOUS PRESET MACROCELLS)
Figure PEELTM22CV10A Logic Array Diagram
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Function Description
PEELTM22CV10A implements logic functions sumof-products expressions programmable-AND/ fixed-OR logic array. User-defined functions created programming connections input signals into array. Userconfigurable output structures form macrocells further increase logic flexibility. programming selected connections array. (Note that PEELdevice programmers automatically program connections unused product terms that they will have effect output function.)
Variable Product Term Distribution
PEELTM22CV10A provides product terms drive functions. These product terms distributed among outputs groups form logical sums (see Figure This distribution allows optimum device re-sources.
Architecture Overview
PEELTM22CV10A architecture illustrated block diagram Figure Twelve dedicated inputs I/Os provide inputs outputs creation logic functions. core device programmable electrically-erasable array which drives fixed array. With this structure, PEELTM22CV10A implement sum-of-products logic expressions. Associated with each functions macrocell which independently programmed different configurations. programmable macrocells allow each create sequential combinatorial logic functions with either active-high active-low polarity.
Programmable Macrocell
output macrocell provides complete control over architecture each output. ability configure each output independently permits users tailor configuration PEELTM22CV10A precise requirements their designs.
Macrocell Architecture
Each macrocell, shown Figure consists Dtype flip-flop signal-select multiplexers. configuration each macrocell determined EEPROM bits controlling these multiplexers (refer Table These bits determine output polarity output type (registered non-registered). Equivalent circuits four macro-cell configurations illustrated Figure
AND/OR Logic Array
programmable array PEELTM22CV10A (shown Figure formed input lines intersecting product terms. input lines product terms used follows: Input Lines: input lines carry true complement signals applied input pins additional lines carry true complement values feedback input signals from I/Os product terms: product terms (arranged groups used form logical sums output enable terms (one each I/O) global synchronous present term global asynchronous clear term each input-line/product-term intersection there EEPROM memory cell which determines whether there logical connection that intersection. Each product term essentially 44-input gate. product term which connected both true complement input signal will always FALSE, thus will affect function that drives. When connections product term opened, "don't care" state exists that term will always TRUE. When programming PEELTM22CV10A, device programmer first performs bulk erase remove previous pattern. erase cycle opens every logical connection array. device then configured perform user-defined function
Output Type
signal from array directly output (combinatorial function) latched D-type flipflop (registered function). D-type flip-flop latches data rising edge clock controlled global preset clear terms. When synchronous preset term satisfied, output register will HIGH next rising edge clock input. Satisfying asynchronous clear term will LOW, regardless clock state. both terms satisfied simultaneously, clear will override preset.
Output Polarity
Each macrocell configured implement active-high active-low logic. Programmable polarity eliminates need external inverters.
Output Enable
output each macrocell enabled disabled under control associated programmable output enable product term. When logical conditions programmed output enable term satisfied, output signal propagated pin. Otherwise, output buffer driven into high-impedance state. Under control output enable term, function dedicated input, dedicated output, bidirectional I/O. Opening every connection output 04-02-009F
PEEL22CV10A
enable term will permanently enable output buffer yield dedicated output. Conversely, every connection intact, enable term will always logically false will function dedicated input.
Design Security
PEELTM22CV10A provides special EEPROM security that prevents unauthorized reading copying designs programmed into device. security programmer, either conclusion programming cycle separate step after device been programmed. Once security set, impossible verify (read) program PEELuntil entire device first been erased with bulk-erase function.
Input/Feedback Select
When configuring macrocell implement registered function (configurations Figure output flip-flop drives feedback term. When configuring macrocell implement combinatorial function (configurations Figure feedback signal taken from pin. this case, used dedicated input bi-directional I/O. (Refer also Table
Signature Word
signature word feature allows 24-bit code programmed into PEELTM22CV10A PEELTM22CV10A+ software option used. code read back even after security been set. signature word used identify pattern programmed into device record design revision, etc.
Additional Macro Cell ConfigurationBesides standard four-configuration macrocell shown Figure each PEELTM22CV10A provides additional eight configurations that used increase design flexibility. configurations same provided PEELTM18CV8 PEELTM22CV10AZ. However, maintain JEDEC file compatibility with standard 22V10 PLDs additional configurations only utilized specifying PEELTM22CV10A+ logic assembly programming. reference these additional configurations please refer PEELTM22CV10A+ specifications this data sheet.
Figure Block Diagram PEEL22CV10A Macrocell.
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Figure Four Configurations PEELTM22CV10A Macrocell Table PEEL22CV10A Macrocell Configuration Bits Configuration
Input/Feedback Select
Register Feedback
Output Select
Active Register Active High Active
Bi-Directional
Combinatorial Active High
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Additional Macrocell ConfigurationBesides standard four-configuration macrocells, each PEELTM22CV10A provides additional eight configurations (twelve total) that used increase design flexibility (see Figure Table logic assembly twelve configurations, specify PEELTM22CV10A+. Also, select PEELTM22CV10A+ programming.
Figure Twelve Configurations PEELTM22CV10A+ Macrocell Table PEEL22CV10A+ Macrocell Configuration Bits Configuration Input/Feedback Select Output Select
Register Feedback Combinatorial Combinatorial Feedback Combinatorial Bi-Directional Combinatorial Register Active Active High Active Active High Active Active High Active Active High Active Active High Active Active High
Register
Register
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This device been designed tested recommended operating conditions. Proper operation outside these levels guaranteed. Exposure absolute maximum ratings cause permanent damage.
Table Absolute Maximum Ratings Symbol
Parameter
Supply Voltage Voltage Applied Pin2 Output Current Storage Temperature Lead Temperature
ConditionRelative Ground Relative Ground1 (IOL, IOH)
Rating-0.5 -0.5
Unit
Soldering second
+300
Table Operating Ranges Symbol
Parameter
Supply Voltage
ConditionCommercial Industrial Commercial
4.75
5.25
Unit
TRVCC
Ambient Temperature Industrial Clock Rise Time Clock Fall Time Rise Time Note Note Note
Table D.C. Electrical Characteristics over recommended operating conditions Symbol
VOHC VOLC
Parameter
Output HIGH Voltage Output HIGH Voltage CMOS13 Output Voltage Output Voltage CMOS13 Input HIGH Level Input Level Input Leakage Current Output Leakage Current
ConditionVCC Min, -4.0mA Min, -10µA Min, 16mA Min, -10µA
Unit
0.15 -0.3 -7/I-7 90/100 90/100 135/145 30/40
Max, High-Z, 25MHz outputs disabled4
ICC10
Current (See CR-1 typical ICC)
-10/I-10 -15/I-15 -25/I-25
CIN7 COUT7
Input Capacitance Output Capacitance
25°C, 5.0V
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Table A.C. Electrical Characteristics Over Operating Range8,11
Symbol
tCO1 tCO2 tCL, fMAX1 fMAX2 fMAX3 tRESET
I-10
90.9
I-15
76.9 62.5 83.3
I-25
41.6 33.3 38.4
Parameter
Input5 non-registered output Input5 output enable6 Input5 output disable6 Clock Output Clock comb. output delay internal registered feedback Clock Feedback Input5 Feedback Setup Clock Input5 Hold After Clock Clock Time, Click High Time8 Clock Period (tSC tCO1) Internal Feedback (1tSC tCF)12 External Feedback (1/tCP)12 Feedback (1/tCL tCH)12 Asynchronous Reset Pulse Width Input Asynchronous Reset Asynch. Reset recovery time Power-on Reset Time registers Clear State
Unit
Switching WaveformInputs, I/O, Registered Feedback, Synchronous Preset Clock Asynchronous Reset Registered Outputs Combinatorial OutputNote1. Minimum input -0.5V, however inputs undershoot -2.0V periods less than 20ns. specified program/verify operation. Test points Clock referenced levels. pins "Input" refers Input signal. measured from input transition VREF 0.1V, measured from input transition -0.1V +0.1V; VREF test loads Section Data Book. Capacitances tested sample basis. Test conditions assume: signal transition times less from points, timing reference levels 1.5V (unless otherwise specified). Test output time duration less than 1sec. typical application: This parameter tested with device programmed 8-bit Counter. PEELDevice test loads specified Section this Data Book. Parameters 100% tested. Specifications based initial characterization tested after design process modification which affect operational frequency. Available only 22CV10A -15/I-15/-25/I-25 grades.
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Table Ordering Information Part Number
PEEL22CV10AP-7 7.5ns PEEL22CV10API-7 PEEL 22CV10AJ-7 7.5ns PEEL 22CV10AJI-7 PEEL 22CV10AS-7 7.5ns PEEL 22CV10ASI-7 PEEL 22CV10AT-7 7.5ns PEEL 22CV10ATI-7 PEEL 22CV10AP-10 10ns PEEL 22CV10API-10 PEEL 22CV10AJ-10 10ns PEEL 22CV10AJI-10 PEEL 22CV10AS-10 10ns PEEL 22CV10ASI-10 PEEL 22CV10AT-10 10ns PEEL 22CV10ATI-10 PEEL 22CV10AP-15 15ns PEEL 22CV10API-15 PEEL 22CV10AJ-15 15ns PEEL 22CV10AJI-15 PEEL 22CV10AS-15 15ns PEEL 22CV10ASI-15 PEEL 22CV10AT-15 15ns PEEL 22CV10ATI-15 PEEL 22CV10AP-25 25ns PEEL 22CV10API-25 PEEL 22CV10AT-25 25ns PEEL 22CV10ATI-25 PEEL 22CV10AJ-25 25ns PEEL 22CV10AJI-25 PEEL 22CV10AS-25 25ns PEEL 22CV10ASI-25
Speed
Temperature
Package
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Part Number
Device
Suffix
PEEL22CV10A PI-25
Package
Plastic 300mil Plastic Leaded Chip Carrier (PLCC) SOIC TSSOP
Speed
7.5ns 10ns 15ns 25ns
Temperature Range Power Option(Blank) Commercial 70°C Industrial +85°C
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PEEL22CV10A-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logi

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