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9080 Data Book
Version 1.06
Website: http://www.plxtech.com Email: apps@plxtech.com Phone: 774-9060 759-3735 Fax: 774-2169
2000 Technology, Inc. rights reserved. Technology, Inc. retains right make changes this product time, without notice. Products have minor variations this publication, known errata. assumes liability whatsoever, including infringement patent copyright, sale products. Technology logo registered trademarks Technology, Inc. Other brands names property their respective owners. Order Number: 9080-SIL-DB-P1-1.06 Printed USA,
CONTENTS
FIGURES TABLES XIII
TIMING DIAGRAMS XVII PREFACE
REVISION HISTORY XXIII FEATURES GENERAL DESCRIPTION COMPANY PRODUCT BACKGROUND 9080 APPLICATIONS
1.2.1 1.2.2
Adapter Cards Embedded Systems
MAJOR FEATURES COMPATIBILITY WITH 9060, 9060ES, 9060SD.4
1.4.1 1.4.2
Compatibility.4 Register Compatibility
COMPARISON 9060, 9060ES, 9060SD, 9080
OPERATION CYCLES
2.1.1 2.1.2
2.1.2.1 2.1.2.2
Target Command Codes Master Command Codes
Master Command Codes Direct Local-to-PCI Command Codes
2.1.3
Arbitration
LOCAL CYCLES
2.2.1 2.2.2 2.2.3
2.2.3.1
Local Arbitration Local Direct Master Local Direct Slave
Ready/Wait State Control.8 Wait State-Local Wait State-PCI Bus.9
2.2.3.1.1 2.2.3.1.2 2.2.3.2
Burst Mode Continuous Burst Mode (Bterm "Burst Terminate" Mode).9 Burst Mode.9 Continuous Burst Mode (Bterm "Burst Terminate" Mode).10 Partial Lword Accesses.10
2.2.3.2.1 2.2.3.2.2 2.2.3.2.3
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Contents
2.2.3.3 2.2.3.4 2.2.3.5 2.2.3.6 2.2.3.7 2.2.3.8 Recovery States.10 Local Read Accesses Local Write Accesses.10 Direct Slave Write Accesses-8- 16-Bit Buses Local Data Parity.10 Local Big/Little Endian 32-Bit Local Bus-Big Endian Mode 16-Bit Local Bus-Big Endian Mode 8-Bit Local Bus-Big Endian Mode
2.2.3.8.1 2.2.3.8.2 2.2.3.8.3
FUNCTIONAL DESCRIPTION RESET
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5
Input RST# Software Reset LRESETo#.13 Local Input LRESETi#.13 Local Output LRESETo#.13 Software Reset.13
9080 INITIALIZATION.13
3.2.1 3.2.2
Serial EEPROM Initialization.14 Local Initialization
SERIAL EEPROM
3.3.1 3.3.2 3.3.3 3.3.4 3.3.5
Short Serial EEPROM Load Long Serial EEPROM Load.15 Extra Long Serial EEPROM Load Recommended Serial EEPROMs Programming Serial EEPROM
INTERNAL REGISTER ACCESS
3.4.1 3.4.2
Access Internal Registers Local Access Internal Registers.18
RESPONSE FULL EMPTY FIFOS DIRECT DATA TRANSFER MODES
3.6.1
3.6.1.1 3.6.1.2 3.6.1.3 3.6.1.4 3.6.1.5
Direct Master Operation (Local Master Target)
Decode.20 FIFOs Memory Access IO/CFG Access
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Contents
3.6.1.6 3.6.1.7 3.6.1.8 3.6.1.9 (PCI Configuration Type Type Cycles) Direct Master Lock Master/Target Abort Write Invalidate Write Invalidate Direct Master Write Invalidate
3.6.1.9.1 3.6.1.9.2
3.6.2
3.6.2.1 3.6.2.2
Direct Slave Operation (PCI Master Local Access)
Mode PCI-to-Local Address Mapping Byte Enables.27 Local Initialization Software Initialization Software
3.6.2.2.1 3.6.2.2.2 3.6.2.2.3 3.6.2.3
Deadlock BREQo Backoff.30 Software/Hardware Solution Systems without Backoff Capability.30 Software Solutions Deadlock
3.6.2.3.1 3.6.2.3.2 3.6.2.3.3 3.6.2.4
Direct Slave Lock
3.6.3
Direct Slave Priority.31
OPERATION
3.7.1 3.7.2 3.7.3
3.7.3.1 3.7.3.2 3.7.3.3
Non-Chaining Mode Chaining Mode Data Transfers.34
Local-to-PCI Transfer.35 PCI-to-Local Transfer.35 Unaligned Transfers.36
3.7.4 3.7.5 3.7.6
3.7.6.1 3.7.6.2 3.7.6.3
Demand Mode DMA.36 Priority Arbitration
Transfer (EOT0# EOT1#) Input Abort Local Latency Pause Timers
3.10 3.11 3.12
VENDOR DEVICE REGISTERS.37 DOORBELL REGISTERS MAILBOX REGISTERS.37 USER INPUT OUTPUT INTERRUPTS
3.12.1
Interrupts (INTA#).38
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Contents
3.12.1.1 3.12.1.2 Local Interrupt Input Master/Target Abort Interrupt.38
3.12.2
Local interrupts (LINTo#).39
Local-to-PCI Doorbell Interrupt PCI-to-Local Doorbell Interrupt Built-In Self Test Interrupt (BIST) Channel Interrupts.40
3.12.2.1 3.12.2.2 3.12.2.3 3.12.2.4
3.12.3 3.12.4
3.13
SERR# (PCI NMI) Local LSERR# (Local NMI)
COMPATIBLE MESSAGE UNIT
3.13.1 3.13.2 3.13.3 3.13.4 3.13.5 3.13.6 3.13.7 3.13.8 3.13.9
Inbound Messages Outbound Messages Pointer Management Inbound Free List FIFO Inbound Post List FIFO Outbound Post List FIFO.44 Outbound Post Queue.44 Inbound Free Queue Outbound Free List FIFO
3.13.10 Enable Sequence
REGISTERS.47 REGISTER DEFINITIONS SUMMARY
4.1.1
Register Differences between 9080 9060, 9060ES, 9060SD.48
REGISTER ADDRESS MAPPING CONFIGURATION REGISTERS LOCAL CONFIGURATION REGISTERS.66 RUNTIME REGISTERS REGISTERS MESSAGING QUEUE REGISTERS
DESCRIPTION.89 SUMMARY COMMON MODES MODE MODE MODE OUT.98
viii
ELECTRICAL SPECIFICATIONS .101
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Contents
GENERAL SPECIFICATIONS .101 LOCAL INPUTS.103 LOCAL OUTPUTS .104
PACKAGE, SIGNAL, SPECS.107 PACKAGE MECHANICAL DIMENSIONS.107 TYPICAL MASTER ADAPTER .108 9080 .109
TIMING DIAGRAMS .111 INITIALIZATION .111 MODE .115
8.2.1 8.2.2 8.2.3
Mode Direct Slave .115 Mode Direct Master .137 Mode .159
MODE .170
8.3.1 8.3.2 8.3.3
Mode Direct Slave .170 Mode Direct Master .177 Mode DMA.180
MODE.184
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FIGURES
Typical Adapter Block Diagram 9080 Internal Block Diagram Figure 2-1. Wait States.8 Figure 2-2. Big/Little Endian-32-Bit Local Figure 2-3. Big/Little Endian-16-Bit Local Figure 2-4. Big/Little Endian-8-Bit Local Figure 3-1. Reset Initialization Process.13 Figure 3-2. 9080 Internal Register Access Figure 3-3. Dual Address Decode Mode Figure 3-4. Direct Master, Direct Slave, Figure 3-5. Mailbox/Doorbell Message Passing.19 Figure 3-6. Direct Master Write Figure 3-7. Direct Master Read Figure 3-8. Local Master Direct Master Access Figure 3-9. Specification v2.1 Delayed Reads Figure 3-10. 9080 Read Ahead Mode Figure 3-11. Direct Slave Write Figure 3-12. Direct Slave Read Figure 3-13. Direct Slave Access Local Figure 3-14. Non-Chaining Initialization Figure 3-15. DMA, PCI-to-Local Figure 3-16. DMA, Local-to-PCI Figure 3-17. Chaining Initialization Figure 3-18. Chaining Mode from PCI-to-Local Figure 3-19. Local-to-PCI Data Transfer Operation.35 Figure 3-20. PCI-to-Local Data Transfer Operation.35 Figure 3-21. Interrupt Error Sources Figure 3-22. System Architecture Figure 3-23. Software Architecture.41 Figure 3-24. Circular FIFO Operation.43 Figure 6-1. 9080 Local Input Setup Hold Waveform .103 Figure 6-2. 9080 Local Output Delay .104 Figure 6-3. Operation.105
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Figures
Figure 7-1. Package Mechanical Dimensions .107 Figure 7-2. Typical Master Adapter.108 Figure 7-3. 9080 (All Modes).109
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
TABLES
Table 1-1. Programmable Local Modes Table 1-2. Compatibility.4 Table 1-3. Comparison 9060, 9060ES, 9060SD, 9080.5 Table 2-1. Target Command Codes.7 Table 2-2. Master Command Codes Table 2-3. Local-to-PCI Memory Access.7 Table 2-4. Local-to-PCI Access.7 Table 2-5. Local-to-PCI Configuration Access Table 2-6. Local Processor Types Table 2-7. Burst Bterm Local Table 2-8. Burst Mode Table 2-9. Partial Lword Accesses.10 Table 2-10. Big/Little Endian Program Mode Table 2-11. Upper Lword Lane Transfer Table 2-12. Upper Word Lane Transfer Table 2-13. Lower Word Lane Transfer Table 2-14. Upper Byte Lane Transfer.12 Table 2-15. Lower Byte Lane Transfer.12 Table 3-1. Serial EEPROM Guidelines Table 3-2. Short Serial EEPROM Load Registers.15 Table 3-3. Long Serial EEPROM Load Registers Table 3-4. Extra Long Serial EEPROM Load Registers.17 Table 3-5. Recommended Serial EEPROM Loads Table 3-6. Response Full Empty FIFOs Table 3-7. Queue Starting Address.41 Table 3-8. Circular FIFO Summary Table 4-1. Registers Definitions Summary.47 Table 4-2. Register Differences between 9080 9060.48 Table 4-3. Register Differences between 9080 9060ES Table 4-4. Register Differences between 9080 9060SD.52 Table 4-5. Configuration Registers.54 Table 4-6. Local Configuration Registers Table 4-7. Runtime Registers.56 Table 4-8. Registers
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Tables
Table 4-9. Messaging Queue Registers.58 Table 4-10. (PCIIDR; PCI:00h, LOC:00h) Configuration Register Table 4-11. (PCICR; PCI:04h, LOC:04h) Command Register Table 4-12. (PCISR; PCI:06h, LOC:06h) Status Register.60 Table 4-13. (PCIREV; PCI:08h, LOC:08h) Revision Register Table 4-14. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) Class Code Register Table 4-15. (PCICLSR; PCI:0Ch, LOC:0Ch) Cache Line Size Register.61 Table 4-16. (PCILTR; PCI:0Dh, LOC:0Dh) Latency Timer Register Table 4-17. (PCIHTR; PCI:0Eh, LOC:0Eh) Header Type Register.61 Table 4-18. (PCIBISTR; PCI:0Fh, LOC:0Fh) Built-In Self Test (BIST) Register.61 Table 4-19. (PCIBAR0; PCI:10h, LOC:10h) Base Address Register Memory Accesses Local, Runtime, Registers.62 Table 4-20. (PCIBAR1; PCI:14h, LOC:14h) Base Address Register Accesses Local, Runtime, Registers.62 Table 4-21. (PCIBAR2; PCI:18h, LOC:18h) Base Address Register Memory Accesses Local Address Space Table 4-22. (PCIBAR3; PCI:1Ch, LOC:1Ch) Base Address Register Memory Accesses Local Address Space Table 4-23. (PCIBAR4; PCI:20h, LOC:20h) Base Address Register Table 4-24. (PCIBAR5; PCI:24h, LOC:24h) Base Address Register Table 4-25. (PCICIS; PCI:28h, LOC:28h) Cardbus Pointer Register.64 Table 4-26. (PCISVID; PCI:2Ch, LOC:2Ch) Subsystem Vendor Register Table 4-27. (PCISID; PCI:2Eh, LOC:2Eh) Subsystem Register Table 4-28. (PCIERBAR; PCI:30h, LOC:30h) Expansion Base Register.64 Table 4-29. (PCIILR; PCI:3Ch, LOC:3Ch) Interrupt Line Register.64 Table 4-30. (PCIIPR; PCI:3Dh, LOC:3Dh) Interrupt Register Table 4-31. (PCIMGR; PCI:3Eh, LOC:3Eh) Min_Gnt Register Table 4-32. (PCIMLR; PCI:3Fh, LOC:3Fh) Max_Lat Register Table 4-33. (LAS0RR; PCI:00h, LOC:80h) Local Address Space Range Register PCI-to-Local Table 4-34. (LAS0BA; PCI:04h, LOC:84h) Local Address Space Local Base Address (Remap) Register.66 Table 4-35. (MARBR; PCI:08h ACh, LOC:88h 12Ch) Mode/Arbitration Register Table 4-36. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register Table 4-37. (EROMRR; PCI:10h, LOC:90h) Expansion Range Register.69 Table 4-38. (EROMBA; PCI:14h, LOC:94h) Expansion Local Base Address (Remap) Register BREQo Control Table 4-39. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion Region Descriptor Register Table 4-40. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register Direct Master PCI.71
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Tables
Table 4-41. (DMLBAM; PCI:20h, LOC:A0h) Local Base Address Register Direct Master Memory.71 Table 4-42. (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register Direct Master IO/CFG.71 Table 4-43. (DMPBAM; PCI:28h, LOC:A8h) Base Address (Remap) Register Direct Master Memory Table 4-44. (DMCFGA; PCI:2Ch, LOC:ACh) Configuration Address Register Direct Master IO/CFG Table 4-45. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space Range Register PCI-to-Local Table 4-46. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space Local Base Address (Remap) Register Table 4-47. (LBRD1; PCI:F8h, LOC:178h) Local Address Space Region Descriptor Register.74 Table 4-48. (MBOX0; PCI:40h 78h, LOC:C0h) Mailbox Register Table 4-49. (MBOX1; PCI:44h 7Ch, LOC:C4h) Mailbox Register Table 4-50. (MBOX2; PCI:48h, LOC:C8h) Mailbox Register Table 4-51. (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register Table 4-52. (MBOX4; PCI:50h, LOC:D0h) Mailbox Register Table 4-53. (MBOX5; PCI:54h, LOC:D4h) Mailbox Register Table 4-54. (MBOX6; PCI:58h, LOC:D8h) Mailbox Register Table 4-55. (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register Table 4-56. (P2LDBELL; PCI:60h, LOC:E0h) PCI-to-Local Doorbell Register Table 4-57. (L2PDBELL; PCI:64h, LOC:E4h) Local-to-PCI Doorbell Register Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register.77 Table 4-59. (CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, Command Codes, User Control, Init Control Register Table 4-60. (PCIHIDR; PCI:70h, LOC:F0h) Permanent Configuration Register Table 4-61. (PCIHREV; PCI:74h, LOC:F4h) Permanent Revision Register Table 4-62. (DMAMODE0; PCI:80h, LOC:100h) Channel Mode Register Table 4-63. (DMAPADR0; PCI:84h, LOC:104h) Channel Address Register Table 4-64. (DMALADR0; PCI:88h, LOC:108h) Channel Local Address Register.81 Table 4-65. (DMASIZ0; PCI:8Ch, LOC:10Ch) Channel Transfer Size (Bytes) Register Table 4-66. (DMADPR0; PCI:90h, LOC:110h) Channel Descriptor Pointer Register.81 Table 4-67. (DMAMODE1; PCI:94h, LOC:114h) Channel Mode Register Table 4-68. (DMAPADR1; PCI:98h, LOC:118h) Channel Address Register Table 4-69. (DMALADR1; PCI:9Ch, LOC:11Ch) Channel Local Address Register Table 4-70. (DMASIZ1; PCI:A0h, LOC:120h) Channel Transfer Size (Bytes) Register Table 4-71. (DMADPR1; PCI:A4h, LOC:124h) Channel Descriptor Pointer Register Table 4-72. (DMACSR0; PCI:A8h, LOC:128h) Channel Command/Status Register Table 4-73. (DMACSR1; PCI:A9h, LOC:129h) Channel Command/Status Register Table 4-74. (DMAARB; PCI:ACh, LOC:12Ch) Arbitration Register Table 4-75. (DMATHR; PCI:B0h, LOC:130h) Threshold Register
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Tables
Table 4-76. (OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register.85 Table 4-77. (OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register Table 4-78. (IQP; PCI:40h) Inbound Queue Port Register.85 Table 4-79. (OQP; PCI:44h) Outbound Queue Port Register Table 4-80. (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register Table 4-81. (QBAR; PCI:C4h, LOC:144h) Queue Base Address Register.86 Table 4-82. (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register.86 Table 4-83. (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register.86 Table 4-84. (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register.87 Table 4-85. (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register Table 4-86. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register Table 4-87. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register Table 4-88. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register Table 4-89. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register.88 Table 4-90. (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register Table 5-1. Type Abbreviations Table 5-2. Power Ground Description.90 Table 5-3. Serial EEPROM Interface Description Table 5-4. System Interface Description.91 Table 5-5. Local Mode Processor Independent Interface Description.92 Table 5-6. Mode Interface Description Table 5-7. Mode Interface Description Table 5-8. Mode Interface Description Table 6-1. Absolute Maximum Ratings .101 Table 6-2. Operating Ranges .101 Table 6-3. Capacitance (sample tested only).101 Table 6-4. Electrical Characteristics Estimated over Operating Range .102 Table 6-5. Electrical Characteristics (Local Inputs) Estimated over Operating Range .103 Table 6-6. Electrical Characteristics (Local Outputs) Estimated over Operating Range .104 Table 6-7. Operation.105
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
TIMING DIAGRAMS
Timing Diagram 8-1. Modes) RST# Asserting Local Output LRESETo# .111 Timing Diagram 8-2. Mode) Phase Clock Synchronization Using LRESETo#.111 Timing Diagram 8-3. 9080 Local Arbitration.112 Timing Diagram 8-4. 9080 Serial EEPROM Initialization.113 Timing Diagram 8-5. Local Interrupt (LINTi#) Input Asserting Output INTA# .114 Timing Diagram 8-6. Mode) Configuration Write 9080 Configuration Register.115 Timing Diagram 8-7. Mode) Configuration Read 9080 Configuration Register .115 Timing Diagram 8-8. Mode) Memory Write 9080 Local Configuration Register .116 Timing Diagram 8-9. Mode) Memory Read 9080 Local Configuration Register Timing Diagram 8-10. Mode) Direct Slave Single Cycle Read (32-Bit Local Bus).117 Timing Diagram 8-11. Mode) Direct Slave Single Cycle Write.118 Timing Diagram 8-12. Mode) 9080 Direct Slave Burst Read from Local Bus, Wait States, Bterm Enabled .119 Timing Diagram 8-13. Mode) Direct Slave 9080 Burst Write Local Bus, Bterm Enabled .120 Timing Diagram 8-14. Mode) Direct Slave PCI-to-Local Burst Read, Bterm Disabled .121 Timing Diagram 8-15. Mode) 9080 Direct Slave Burst Write, Bterm Disabled .122 Timing Diagram 8-16. Mode) Direct Slave Read with Prefetch Counter .123 Timing Diagram 8-17. Mode) Direct Slave Burst Write 32-Bit Local Suspended BREQ Input .124 Timing Diagram 8-18. Mode) Direct Slave Burst Read Five Lwords with Wait State.125 Timing Diagram 8-19. Mode) Direct Slave Burst Write Five Lwords with Wait State.126 Timing Diagram 8-20. Mode) Direct Slave Read Spec .127 Timing Diagram 8-21. Mode) Direct Slave Read Flush Mode (Read Ahead Mode).128 Timing Diagram 8-22. Mode) Direct Slave Read Lwords from 8-Bit .129 Timing Diagram 8-23. Mode) 9080 Direct Slave Lword Burst Write 8-Bit Local Bus, Wait States, Bterm Enabled .130 Timing Diagram 8-24. Mode) Direct Slave Read Lwords from 16-Bit .131 Timing Diagram 8-25. Mode) 9080 Direct Slave Lword Burst Write 16-Bit Local Bus, Wait States, Bterm Enabled .132 Timing Diagram 8-26. Mode) Direct Slave Read Lwords from 8-Bit Local Bus, Burst Disabled .133 Timing Diagram 8-27. Mode) Direct Slave Write Lwords 8-Bit Local Bus, Burst Disabled.134 Timing Diagram 8-28. Mode) Direct Slave BIGEND Local with BIGEND# Input Internal Register Setting .135 Timing Diagram 8-29. Mode) Locked Direct Slave Read Followed Write Release (LLOCKo#).136 Timing Diagram 8-30. Mode) Local Read from 9080 Registers .137 Timing Diagram 8-31. Mode) Local Write 9080 Registers .138 Timing Diagram 8-32. Mode) Local Direct Master Single Memory Read.139
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Timing DIagrams
Timing Diagram 8-33. Mode) Local Direct Master Single Memory Write Cycle.140 Timing Diagram 8-34. Mode) 9080 Direct Master Memory Read, Lword Burst .141 Timing Diagram 8-35. Mode) 9080 Direct Master Memory Write Lwords .142 Timing Diagram 8-36. Mode) 9080 Direct Master Memory Read with WAITI# .143 Timing Diagram 8-37. Mode) 9080 Direct Master Memory Write with WAITI# .144 Timing Diagram 8-38. Mode) 9080 Direct Master Configuration Read-Type Type .145 Timing Diagram 8-39. Mode) 9080 Direct Master Configuration Write-Type Type .146 Timing Diagram 8-40. Mode) Local Direct Master Read from I/O.147 Timing Diagram 8-41. Mode) Direct Master Write .148 Timing Diagram 8-42. Mode) 9080 Direct Master Memory Read-Keep .149 Timing Diagram 8-43. Mode) 9080 Direct Master Memory Read-Drop Bus.150 Timing Diagram 8-44. Mode) Request (REQ#) Delay During Direct Master Write Clock Delay) .151 Timing Diagram 8-45. Mode) Direct Master Memory Read, Prefetch .152 Timing Diagram 8-46. Mode) Direct Master Memory Write Invalidate (MWI)-Cache Line Size .153 Timing Diagram 8-47. Mode) Direct Master BIGEND Local with BIGEND# Input Interrupt.154 Timing Diagram 8-48. Mode) Direct Master Burst, Memory Read Cycles (Changing LBE[3:0]#) .155 Timing Diagram 8-49. Mode) Direct Master Five Lword Burst Write (Changing LBE[3:0]#) .156 Timing Diagram 8-50. Mode) Direct Master Locked Read Followed Write Release (LLOCK# LOCK#).157 Timing Diagram 8-51. Mode) BREQo Deadlock .158 Timing Diagram 8-52. Mode) Aligned Address Aligned Local Address, Bterm Disabled.159 Timing Diagram 8-53. Mode) Aligned Local Address Aligned Address, Burst Enabled, Bterm Enabled.160 Timing Diagram 8-54. Mode) Aligned Address Aligned Local Address (External Generation Wait States) .161 Timing Diagram 8-55. Mode) Read Chaining Parameters from Local Buses .162 Timing Diagram 8-56. Mode) 9080 Read Chaining Parameters from Local Bus, Wait States.163 Timing Diagram 8-57. Mode) Read Chaining Parameters from (Local-to-PCI Transfer).164 Timing Diagram 8-58. Mode) Single Cycle Demand Mode PCI-to-Local.165 Timing Diagram 8-59. Mode) Multiple Cycle (Burst) Demand Mode PCI-to-Local, Wait States .165 Timing Diagram 8-60. Mode) Demand Mode Terminated with BLAST# (Local-to-PCI) .166 Timing Diagram 8-61. Mode) Local-to-PCI, Terminated with EOT[1:0]# .167 Timing Diagram 8-62. Mode) PCI-to-Local, Terminated with EOT[1:0]# .168 Timing Diagram 8-63. Mode) PCI-to-Local with Local Pause Timer Local Latency Timer .169 Timing Diagram 8-64. Mode) 9080 Direct Slave Burst Read from Local Bus, Wait States, Bterm Enabled.170 Timing Diagram 8-65. Mode) 9080 Direct Slave Burst Write Local Bus, Wait States, Bterm Enabled .171 Timing Diagram 8-66. Mode) 9080 Direct Slave Burst Write Local Bus, Wait States, Bterm Disabled.172
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Timing DIagrams
Timing Diagram 8-67. Mode) Direct Slave BIGEND Local with BIGEND# Input Internal Register Setting .173 Timing Diagram 8-68. Mode) Direct Slave Read v2.1 Spec .174 Timing Diagram 8-69. Mode) Direct Slave Read Flush Mode (Read Ahead Mode), Prefetch Mode Enabled .175 Timing Diagram 8-70. Mode) Local Read from 9080 Registers.176 Timing Diagram 8-71. Mode) Local Write 9080 Registers .176 Timing Diagram 8-72. Mode) Direct Master Read Access from (Keep Read FIFO Full Mode), Disconnects.177 Timing Diagram 8-73. Mode) Local Direct Master Burst Write Access Bus, Continuous Same Clock Rate Disconnects .178 Timing Diagram 8-74. Mode) Local Direct Master Lock Memory Read Access from Followed Write Release .179 Timing Diagram 8-75. Mode) 9080 Local-to-PCI, Wait States, Bterm Enabled .180 Timing Diagram 8-76. Mode) 9080 PCI-to-Local Bus, Wait States, Bterm Enabled .181 Timing Diagram 8-77. Mode) Read Chaining Parameters, Wait States.182 Timing Diagram 8-78. Mode) 9080 Write Local BREQ Asserted.183 Timing Diagram 8-79. Mode) 9080 Direct Slave Lword Burst Write 16-Bit Local Bus, Wait States, Bterm Enabled .184 Timing Diagram 8-80. Mode) Local Read from 9080 Registers .185 Timing Diagram 8-81. Mode) Local Write 9080 Registers.186
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9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
PREFACE
information contained this document should considered preliminary. Although effort been made keep information accurate, there misleading even incorrect statements made herein. document being written parallel with actual chip development and, such, subject change. This description intended living document, updated throughout 9080 design effort. provides broad technical overview 9080. following list additional documentation provide reader with further information about 9080 related subjects:
Local Specification, Revision Special Interest Group 5200 N.E. Elam Young Parkway, Hillsboro, 97124-6497 503-696-2000, http://www.pcisig.com Hot-Plug Specification, Revision Special Interest Group 5200 N.E. Elam Young Parkway, Hillsboro, 97124-6497 503-696-2000, http://www.pcisig.com Power Management Interface Specification, Revision 1.0, June 1997 Special Interest Group 5200 N.E. Elam Young Parkway, Hillsboro, 97124-6497 503-696-2000, http://www.pcisig.com PICMG 2.0, CompactPCI (registered) Specification, Revision greater Industrial Computer Manufacturers Group (PICMG) Edgewater Place, Suite 220, Wakefield, 01880, Tel: 781-224-1100, Fax: 617-224-1239, http://www.picmg.org Intelligent (I2O) Architecture Specification, Revision Special Interest Group Balboa Street, Francisco, 94118 Tel: 415-750-8352, Fax: 415-751-4829, http://www.i2osig.com
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9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
REVISION HISTORY
Date 07/3/1997 Revision 07/10/1997 1.01 07/24/1997 1.02 08/19/1997 1.03 01/26/1998 1.04 Initial release. Release timing diagrams. Corrected typos matched spec. Changed Changed LARBR (Local/Arbitration Register) MARBR (Mode/Arbitration Register). hold output timings Change mechanical package dimension. Complete electrical tables Section Correct timing diagrams. Matched spec. Changed title Section Added READYo# value Table 6-6. Removed signals from corrected signal LA[31:0] reference Timing Diagram 8-20. Corrected titles Timing Diagrams 8-20 8-68. Corrected titles Sections 8.3.3 8.4.3. Corrected Bterm mode reference Section 2.2.3.2. Corrected reference Note Table 4-7. Corrected information bits [23:20] Table 4-75. Corrected package mechanical dimension 30.6 30.6 Figure 7-1. Corrected LBE[3:0]# signal information Timing Diagram 8-15. Corrected signal LA[31:0] reference Timing Diagram 8-21. Corrected "Bterm enabled" "Bterm disabled" references "BTERM# enabled" "BTERM# disabled" affected timing diagrams Section Applied general editing register tables. Corrected values Table 3-5. Corrected direction DEVSEL#, TRDY# signal Figure 3-16. Corrected name Figure "Typical Adapter Block Diagram" Table 6-3. Changed values include both CMOS values Table 6-4. Significantly revised Table Table 6-6. Updated timing diagrams. Reversed "BTERM# enabled/disabled" changes made v1.03 back "Bterm enabled/disabled." Corrected text DMATHR [31:28, 15:12] reads ".before requesting reads" bits [27:24, 11:8] reads ".before requesting writes." Comment
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xxiii
REVISION HISTORY
Date 09/01/1999 Revision 1.05 01/2000 1.06 Comment Changed document title from "Data Sheet" "Data Book." Added company background information. Corrected register number section 3.7.6.1. Corrected Serial EEPROM Writable capability Register Table 4-5. Corrected Bterm information Table 4-39. Revised Channel number full entries (delete divide operation) Table 4-75. Updated timing diagrams. Added Operation section after Electrical Specification page 101, Section Added values Table 6-1. Revised operating range temperature values Table 6-2. Added values Table VOH3, VOL3, VIH3, VIL3. Revised values Table 6-6. Revised timing diagrams 8-10, 8-17, 8-30, 8-31, 8-70, 8-71. Cosmetic changes (capitalizations specific terms, etc.).
Applied minor format changes. Changed copyright date 2000. Added primary title page, number, disclaimer trademarks, part number, list Figures, Tables, Timing Diagrams. Changed "negate" "de-assert." Added Local information FIgure 3-5.
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9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
9080
Accelerator
January 2000 VERSION 1.06
Compatible Master Interface Chip Adapters Embedded Systems
Local Data transfers MB/sec Programmable Local supports nonmultiplexed 32-bit address/data, multiplexed 16-bit, Slave accesses 32-, 16-, 8-bit Local devices Local runs asynchronously Eight 32-bit Mailbox 32-bit Doorbell registers Performs Endian/Little Endian conversion Upward compatibility with 9060, 9060ES, 9060SD
FEATURES
Specification (v2.1) compliant Master Interface chip adapters embedded systems Compatible Messaging Unit volt signaling, volt core, low-power CMOS 208-pin PQFP independent channels Local memory from Host Data transfers Eight programmable FIFOs zero wait state burst operation
Boot
Local Memory
Device (LAN, Disk, Video, etc.)
Local
9080
Local Interface
FIFOs Control:
Unaligned Transfer
Registers Serial EEPROM
Local Runtime
Interface
Typical Adapter Block Diagram
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Features
Internal Registers
Config. Local Config. Run-Time Messaging
Serial EEPROM Initialization
State Machines
Initiator (for Direct Master Xfers) Target (for Direct Slave Xfers)
FIFOs
Dir. Master Write Dir. Master Read Dir. Slave Write Dir. Slave Read DMA1 PCI/Loc DMA1 Loc/PCI DMA0 PCI/Loc DMA0 Loc/PCI
Local State Machines
Local Slave (for Direct Master Xfers) Local Master (for Direct Slave Xfers) Local Master (For Xfers)
Local Interface: Select Width 8,16, Endian Conversion Select Muxed non-Muxed Addr/Data
Interface
Initiator (For Xfers)
Initiator (For Xfers)
Local Master (For Xfers)
Control Logic
Messaging
Chaining
Unaligned Xfer
9080 Internal Block Diagram
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GENERAL DESCRIPTION
Company Product Background
Technology, Inc., world leader PCI-to-Local accelerator chips, supports more than customers wide variety applications. Customer applications include workstations servers, add-in boards, embedded communication systems such routers switches, industrial implementations such CompactPCI, PMC, Passive Backplane PCI. Technology, Inc., active participant industry standard committees, including SIG® SIG®, PICMG maintains active developer technology cross-marketing partnerships with industry leaders, such Intel, IBM, Hewlett-Packard, Motorola, Integrated Systems, WindRiver others. Focused providing complete solutions implementations, provides design assistance customers form Reference Design Software Development kits. Depending upon application, these kits include reference boards, libraries, software debug tools, sample device drivers with source, enabling customers quickly bring designs production. tools, application notes, FAQs, information updates constantly added website convenience customers. expertise total solutions interface allow customers focus adding value their designs without worrying about complexities implementing PCI, I2O, CompactPCI.
management pointers that used message passing under protocol custom protocol.
1.2.2 Embedded Systems
Another application 9080 embedded systems, such network hubs routers, printer engines, industrial equipment. this configuration, four above-mentioned Data Transfer modes used. addition, 9080 supports Type Type Configuration cycles, which allows embedded embedded system host configure other devices system.
Major Features
Compliant. 9080 compliant with aspects Specification v2.1. Messaging Unit. 9080 incorporates messaging unit. This enables adapter embedded system communicate with other I2O-supported devices. messaging unit fully compatible with extension specification v1.5. Dual Independent Programmable Controllers with Programmable FIFOs. 9080 provides independently programmable controllers with programmable FIFOs each channel. Each channel supports Non-chaining Chaining modes, Demand mode DMA, Transfer (EOT) mode. Direct Master. 9080 supports MemoryMapped bursts, Transfer accesses, I/O-Mapped Single-Transfer accesses from Local Master. 9080 also supports Interlock (LOCK#) cycles. Read Write FIFOs enable high-performance bursting. Host Capability. Direct Master mode, 9080 generate Type Type Configuration cycles. Direct Slave. 9080 supports Burst MemoryMapped single I/O-Mapped accesses Local Bus. Read Write FIFOs enable highperformance bursting. Programmable Local Modes. 9080 Master interface chip that connects three Local types, selected through mode pins. 9080 connected Local with similar design with little glue logic. Table lists three modes.
9080 Applications 1.2.1 Adapter Cards
Major adapter card applications 9080 include high performance communications, networking, disk control, multimedia, video adapters. 9080 moves data between host adapter Local several ways. First, local host processor program controller 9080 move data between adapter memory host Bus. Second, 9080 perform Direct Master Transfers, whereby local controller accesses directly through Master transfer. 9080 also supports Slave transfers which another device Master. Finally, 9080 contains complete messaging unit with mailbox registers, doorbell registers, queue
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Section General Description
Table 1-1. Programmable Local Modes
Mode Description 32-bit address/32-bit data, nonmultiplexed 32-bit address/32-bit data, multiplexed 32-bit address/16-bit data, multiplexed
Compatibility with 9060, 9060ES, 9060SD
Bus. Address must subsequent previous address 32-bit aligned (next address current address Programmable Wait States. 9080 programmed keep generating wait state(s), thereby de-asserting TRDY#, Write FIFO becomes full. 9080 also programmed keep Local Bus. LHOLD asserted Direct Slave Write FIFO becomes empty Direct Slave Read FIFO becomes full. Local dropped either case when Local Latency Timer enabled expires.
Interrupt Generator. 9080 generate Local interrupts from several sources. Clock. 9080 Local interface runs from local clock generates necessary internal clocks. This clock runs asynchronously clock. There buffered clock (BPCLKo) Local use. BPCLKo connected LCLK. Volt Volt Operation. 9080 core requires Vcc. 9080 provides 3.3V signaling Bus. Local operates signaling level. Serial EEPROM Interface. 9080 contains optional serial EEPROM interface that used load configuration information. This useful loading information unique particular adapter (such Network Vendor ID). Mailbox registers. 9080 contains eight 32-bit mailbox registers that accessed from Local Bus. Doorbell registers. 9080 includes 32-bit doorbell registers. generates interrupts from Local Bus. other generates interrupts from Local Bus. Unaligned Transfer Support. 9080 transfer data byte boundary. Big/Little Endian Conversion. 9080 supports dynamic switching between Endian Little Endian operations Direct Slave, Direct Master, DMA, Internal register accesses Local Bus. 9080 supports on-the-fly Endian conversion Space Space Expansion space. Local Big/Little Endian using BIGEND# input programmable internal register configuration. When BIGEND# asserted, overrides internal register configuration.
Compatibility with 9060, 9060ES, 9060SD
9080 upward compatible with 9060, 9060ES 9060SD, except noted Table Section 4.1, "New Register Definitions Summary."
1.4.1 Compatibility
When upgrading from 9060, 9060ES 9060SD, observe following definitions listed Table 1-2. Table 1-2. Compatibility
9060/9060ES/9060SD Name CLKSEL Description Serial EEPROM Clock Select Optional Serial EEPROM Clock Source Name 9080 Description
EE1MC
EESEL
Serial EEPROM Select 1=93CS46 bit) 0=93CS56 bit)
1.4.2 Register Compatibility
registers implemented 9060, 9060ES, 9060SD implemented 9080. There limited number definitions several registers. Refer Section 4.1, "New Register Definitions Summary."
Note:
always Little Endian.
Read Ahead Mode. 9080 supports Read Ahead mode, where prefetched data read from 9080 internal FIFO instead from Local
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Comparison 9060, 9060ES, 9060SD, 9080 Comparison 9060, 9060ES, 9060SD, 9080
Table 1-3. Comparison 9060, 9060ES, 9060SD, 9080
Feature Number Channel(s) Local Address Spaces Direct Master Mode Mailbox Registers Doorbell Registers FIFOs FIFO Depth-Direct Slave Write, Direct Master Write, Read Write FIFO Depth-Direct Slave Read, Direct Master Read, Read Write LLOCKo# Lock Cycles WAITI# Wait State Generation BPCLKo Pin; Buffered Clock DREQ# DACK# Pins Demand Mode Support Register Addresses 9060 Eight 32-bit 32-bit Lwords bytes) Lwords bytes) 9060ES Four 32-bit 8-bit Lwords bytes) Lwords bytes) Identical except 9060ES registers Tables were added Signals deleted: DREQ0# (pin DACK0# (pin Input signals added: WAITI# (pin BIGEND# (pin Output signals added: BPCLKo (pin 168) LLOCKo# (pin 9060SD Four 32-bit 8-bit Lwords bytes) Lwords bytes) (Channel only)
Section General Description
9080 Eight 32-bit 32-bit Lwords (128 bytes) Lwords bytes) Identical except 9080 additional related registers 30h, 34h, 40h, were remapped Input signal added: EOT1# (pin 163) Signal changed: EESEL (pin 175)
Identical, except 9060SD register Tables 4-29 4-30 were added Signals deleted: BREQ (pin DMPAF# (pin DREQ0# (pin DACK0# (pin BTERMo# (pin Input signals added: WAITI# (pin BIGEND# (pin EOT0# (pin mode, modes) Output signals added: BPCLKo (pin 168) LLOCKo# (pin
Note: 9080 includes changes made 9060, 9060ES, 9060SD.
Big/Little Endian Conversion Specification v2.1 Deferred Reads Programmable Prefetch Counter Write Invalidate Cycle Additional Device Vendor Register Messaging Unit 3.3V Signaling
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OPERATION
Cycles
9080 compliant with Specification v2.1. Refer spec specific features Bus.
2.1.2.1 Master Command Codes
controllers 9080 generate Memory cycles listed Table 2-2. Table 2-2. Master Command Codes
Command Type Memory Read Code (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1100 (Ch) 1110 (Eh) 1111 (Fh)
2.1.1 Target Command Codes
Target, 9080 allows access Internal registers Local Bus, using commands listed Table 2-1. Table 2-1. Target Command Codes
Command Type Read Write Memory Read Memory Write Memory Read Multiple Memory Read Line Memory Write Invalidate Configuration Read Configuration Write Code (C/BE[3:0]#) 0010 (2h) 0011 (3h) 0110 (6h) 0111 (7h) 1100 (Ch) 1110 (Eh) 1111 (Fh) 1010 (Ah) 1011 (Bh)
Memory Write Memory Read Multiple Memory Read Line Memory Write Invalidate
2.1.2.2 Direct Local-to-PCI Command Codes
direct Local-to-PCI accesses, 9080 generates cycles listed Table through Table 2-5. Table 2-3. Local-to-PCI Memory Access
Command Type Memory Read Memory Write Memory Read Multiple Memory Read Line Code (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1100 (Ch) 1110 (Eh)
Read Write accesses 9080 Byte, Word, Longword (Lword) accesses. memory commands aliased basic memory commands. accesses 9080 decoded Lword boundary. byte enables used determine which bytes read written. access with illegal byte enable combinations terminated with Target Abort.
Table 2-4. Local-to-PCI Access
Command Type Read Write Code (C/BE[3:0]#) 0010 (2h) 0011 (3h)
Table 2-5. Local-to-PCI Configuration Access
Command Type Code (C/BE[3:0]#) 1010 (Ah) 1011 (Bh) Configuration Memory Read Configuration Memory Write
2.1.2 Master Command Codes
9080 access perform transfers Direct Master Local-to-PCI transfers. During Direct Master transfer, command code assigned 9080 Internal register location, (CNTRL[15:0], used command code. Table through Table lists various Master Command codes.
2.1.3 Arbitration
9080 asserts output REQ# request Bus. 9080 programmed using MARBR[23] de-assert REQ# when asserts FRAME# during Master cycle, keep REQ# asserted entire Master cycle. 9080 always deasserts REQ# minimum clocks between Master ownership that includes Target disconnect.
Notes: Programmable Internal registers determine command codes when 9080 Master. cannot perform Configuration accesses.
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Section Operation
Direct Master Write Delay bits (DMPBAM[15:14]) programmed delay assertion 9080 REQ# signal during Direct Master Write cycle. This register programmed wait clocks after 9080 received first Write data from Local Master ready begin Write transaction. This feature useful applications where Local Master bursting Local clock slower than clock. This allows Write data accumulate Direct Master Write FIFO 9080, which provides better utilization Bus.
Local Cycles 2.2.2 Local Direct Master
Local cycles Continuous Single Burst cycles (programmable 9080 Internal registers). Local Target, 9080 allows access Internal registers Bus. modes, Local Direct Master accesses 9080 must 32-bit nonpipelined bus. mode, Local Direct Master accesses 9080 must 16-bit nonpipelined bus.
2.2.3 Local Direct Slave Local Cycles
9080 connects Host several Local processor types, listed Table 2-6. operates three modes, selected through mode pins corresponding three types-C, Table 2-6. Local Processor Types
Mode Reserved Type 32-bit nonmultiplexed 32-bit multiplexed 16-bit multiplexed
Master Read/Write Local (the 9080 Target Local Master).
2.2.3.1 Ready/Wait State Control
Accessing 9080 from Accessing 9080 from Local
9080 de-asserts TRDY# when waiting Local de-asserts IRDY# simply cycle when it's ready 9080 Accessing 9080 programmed de-assert IRDY# when FIFOs Direct Master Read de-asserts TRDY# when it's ready
9080 generates READYo# when data valid following clock edge Local Processor generates wait states with WAITI# 9080 Accessing Local
9080
2.2.1 Local Arbitration
When 9080 owns Local Bus, both LHOLD output LHOLDA input asserted. When 9080 samples that BREQ asserted during transfer Direct Slave Write transfer, gives Local within Lword transfers de-asserting LHOLD floating Local outputs BREQ gated disabled; Gating enabled Local Latency Timer expires
9080 generates wait states with WAITO# (programmable) Local respond 9080 requests with READYi#
Figure 2-1. Wait States
Note: figure represents sequence cycles.
READYi# input disabled, external READYi# input effect wait states local access. Wait states between Data cycles generated internally wait state counter. Wait state counter initialized with Configuration register value start each data access. READYi# enabled, READYi# effect until wait state counter READYi# then controls number additional wait states. BTERM# input sampled until wait state counter BTERM# overrides READYi# when BTERM# asserted.
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Local Arbiter grant Local another Local Master. After 9080 samples that LHOLDA de-asserted Local Pause Timer zero, re-asserts LHOLD request Local Bus. When 9080 receives LHOLDA, drives continues from where left off.
Local Cycles 2.2.3.1.1 Wait State-Local
With Direct Master mode accessing 9080 registers (PCI 9080 local Slave): 9080 generates wait states with READYo# Local processor generates wait states with WAITI#
Section Operation
BTERM# input valid only when 9080 Master Local (Direct Slave modes). BTERM# generated external logic. input 9080 (and i960) used tell 9080 (and i960) break Burst cycle. BTERM# used, example, signal that Memory access crossing page boundary.
With Direct Slave modes (PCI 9080 Local Master): 9080 generates wait states with WAITO# Local processor generates wait states with READYi# LBRD0[21:18, 5:2], DMAMODE0[5:2], DMAMODE1[5:2] program number wait states
Bus, burst always enabled.
Notes: Bterm disabled, 9080 performs following:
32-bit Local Bus-Burst four Lwords 16-bit Local Bus-Burst Lwords 8-bit Local Bus-Burst Lword
2.2.3.1.2 Wait State-PCI
When wait state occurs Bus, Master throttles IRDY# Slave throttles TRDY#.
every case, performs four transactions. following sections, Bterm refers 9080 Internal register bit. BTERM# refers 9080 external signal.
2.2.3.2 Burst Mode Continuous Burst Mode (Bterm "Burst Terminate" Mode)
Table 2-7. Burst Bterm Local
Mode Single Cycle Single Cycle Burst-4 Burst Forever Burst Bterm Result ADS# data (default) Still ADS# data ADS# four data (use this mode i960) ADS# BTERM#
2.2.3.2.1 Burst Mode
bursting enabled BTERM# input enabled, bursting start boundary continue address boundary, described Table 2-8. After data boundary transferred, 9080 generates Address cycle (ADS#). Table 2-8. Burst Mode
Mode Burst 32-bit bus-Four Lwords quad Lword boundary (LA3, 16-bit bus-Four words quad word boundary (LA2, 8-bit bus-Four bytes quad byte boundary (LA1, 16-bit bus-Eight words quad Lword boundary (LA3,
Local Bus, BLAST# BTERM# perform following: burst enabled (LBRD0[26,24] non-DMA, DMAMODE0[8] DMAMODE1[8] DMA), Bterm mode disabled (LBRD0[7], DMAMODE0[7] DMAMODE1[7]), then 9080 bursts four Lwords. BLAST# generated fourth Lword (LA[3:2]=11), ADS# first Lword (LA[3:2]=00) next burst. BTERM# sampling enabled BTERM# low, 9080 forces ADS#, does generate BLAST# signal.
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Section Operation 2.2.3.2.2 Continuous Burst Mode (Bterm "Burst Terminate" Mode)
Bterm mode enables 9080 perform long bursts devices that accept longer than four Lword bursts. 9080 generates Address cycle continues burst data. device requires Address cycle after certain address boundary, assert BTERM# input cause 9080 generate Address cycle. BTERM# input acknowledges current Data transfer requests that Address cycle generated (ADS#). This address used next Data transfer. Bterm mode enabled, 9080 asserts BLAST# only FIFOs become full empty, transfer complete.
Local Cycles 2.2.3.4 Local Read Accesses
Single Cycle Local Read accesses, 9080 reads only bytes corresponding byte enables requested initiator. Burst Cycle Read accesses, 9080 reads only Lwords.
2.2.3.5 Local Write Accesses
Local writes, only bytes specified Master 9080 controller written. Access 16-bit results Lword being broken into multiple Local transfers. each transfer, byte enables encoded 80960C provide Local Address bits LA[1:0].
Note: BTERM# asserted, BLAST# does assert until previously described conditions met.
2.2.3.2.3 Partial Lword Accesses
Lword accesses which byte enables asserted broken into Single Address Data cycles, listed Table 2-9. Table 2-9. Partial Lword Accesses
Register Value LBRD0 Burst Enable Bterm Enable Result (Number Transfers) Single Cycle (Default) Single Cycle Burst four Lwords time Continuous Burst Mode
2.2.3.6 Direct Slave Write Accesses-8- 16-Bit Buses
Direct access 16-bit results Lword being broken into multiple Local transfers. each transfer, byte enables encoded 80960C provide Local Address bits LA[1:0].
2.2.3.7 Local Data Parity
There data parity each byte lane 9080 data (DP[3:0]). Even data parity generated each lane during Local reads from 9080 during 9080 Master writes Local Bus. Even data parity checked during Local writes 9080 during 9080 reads from Local Bus. Parity checked each byte lane with asserted byte enable. PCHK# asserted Clock cycle following data being checked parity error detected. Generation Local data parity optional. Signals data parity pins affect operation 9080. parity checking generation independent Local parity checking generation.
2.2.3.3 Recovery States
modes, 9080 inserts recovery state between last Data transfer next Address cycle. 9080 does support 80960J feature using READYi# input recovery states. additional recovery states added READYi# input remains asserted during last Data cycle.
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Local Cycles 2.2.3.8 Local Big/Little Endian
Little Endian (that data Lword aligned lowermost byte lane). Byte (address appears AD[7:0], Byte appears AD[15:8], Byte appears AD[23:16] Byte appears AD[31:24]. 9080 Local programmed operate Little Endian mode, listed Table 2-10.
Section Operation
BYTE Little Endian BYTE BYTE BYTE
Table 2-10. Big/Little Endian Program Mode
BIGEND# Register 1=Big, 0=Little Endian
BYTE BYTE BYTE BYTE
Endian
Little
Figure 2-2. Big/Little Endian-32-Bit Local
2.2.3.8.2 16-Bit Local Bus-Big Endian Mode
16-bit Local Bus, 9080 programmed upper lower word lane. Byte lanes burst order listed Table 2-12 Table 2-13 illustrated Figure 2-3. Table 2-12. Upper Word Lane Transfer
Burst Order Byte Lane Byte appears Local Data [31:24] Byte appears Local Data [23:16] Second Transfer Byte appears Local Data [31:24] Byte appears Local Data [23:16] First Transfer
Configuration cycles, refer BIGEND[0]. Direct Master, Memory, cycles, refer BIGEND[1]. Direct Slave cycles, refer BIGEND[2], Space BIGEND[3], Expansion ROM. Endian mode, 9080 transposes data byte lanes. Data transferred listed Table 2-11 through Table 2-15.
2.2.3.8.1 32-Bit Local Bus-Big Endian Mode
Data Lword aligned uppermost byte lane. Byte lanes burst orders listed Table 2-11 illustrated Figure 2-2. Table 2-11. Upper Lword Lane Transfer
Burst Order First Transfer Byte Lane Byte appears Local Data [31:24] Byte appears Local Data [23:16] Byte appears Local Data [15:8] Byte appears Local Data [7:0]
Table 2-13. Lower Word Lane Transfer
Burst Order First Transfer Byte Lane Byte appears Local Data [15:8] Byte appears Local Data [7:0] Second Transfer Byte appears Local Data [15:8] Byte appears Local Data [7:0]
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Section Operation
BYTE Little Endian BYTE BYTE
First Cycle
Local Cycles
BYTE
BYTE
Little Endian BYTE BYTE BYTE
First Cycle
Second Cycle
BYTE
BYTE
Second Cycle Third Cycle
BYTE
BYTE
BYTE
BYTE
Endian
Fourth Cycle
BYTE
Endian
BYTE
Endian
Figure 2-3. Big/Little Endian-16-Bit Local Figure 2-4. Big/Little Endian-8-Bit Local
2.2.3.8.3 8-Bit Local Bus-Big Endian Mode
8-bit Local Bus, 9080 programmed upper lower byte lane. Byte lanes burst order listed Table 2-14 Table 2-15 illustrated Figure 2-4. Table 2-14. Upper Byte Lane Transfer
Burst Order First transfer Second transfer Third transfer Fourth transfer Byte Lane Byte appears Local Data [31:24] Byte appears Local Data [31:24] Byte appears Local Data [31:24] Byte appears Local Data [31:24]
each following transfer types, 9080 Local independently programmed operate Little Endian Endian mode: Local accesses 9080 Configuration registers Direct Slave accesses Local Address Space Direct Slave accesses Local Address Space Direct Slave accesses Expansion Channel accesses Local Channel accesses Local Direct Master accesses
Table 2-15. Lower Byte Lane Transfer
Burst Order First Transfer Second Transfer Third Transfer Fourth Transfer Byte Lane Byte appears Local Data [7:0] Byte appears Local Data [7:0] Byte appears Local Data [7:0] Byte appears Local Data [7:0]
Local Configuration accesses, input used dynamically change Endian mode.
Notes: always Little Endian mode. Only byte lanes swapped, individual bits.
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FUNCTIONAL DESCRIPTION
Functional operation described changed modified, depending register configuration.
3.1.3 Local Input LRESETi#
When asserted, LRESETi# input resets Local portion 9080, clears local configuration registers causes LRESETo# output asserted.
Reset 3.1.1 Input RST#
RST# input Host reset. causes outputs float, resets entire 9080 causes local reset output, LRESETo#, asserted. have Host (PCICR[2:0]), Master Enable, Memory Space, Space programmed host after initialization complete (CNTRL[31]=1). (Refer Figure 3-1.)
3.1.4 Local Output LRESETo#
LRESETo# asserted when RST# input asserted, LRESETi# input asserted, Software Reset Init Control register
3.1.5 Software Reset
host software Software Reset Init Control register reset 9080 assert LRESETo# output. Local Configuration registers reset. Configuration registers reset. When Software Reset set, 9080 responds accesses, Local accesses. 9080 remains this reset condition until Host clears bit.
Reset
Serial EEPROM Initialization
Local Processor Sets CNTRL[3] Local Init Done
Note: Local cannot clear this reset because Local reset state.
9080 Initialization
Local Processor Configures 9080 Host Configures 9080
9080 Configuration registers programmed optional serial EEPROM and/or Local processor, listed Table 3-1. serial EEPROM reloaded setting CNTRL[29]. general, 9080 retries cycles until Local Init Done until low.
Figure 3-1. Reset Initialization Process
3.1.2 Software Reset LRESETo#
When asserted, LRESETo# Software Reset CNTRL[30] resets 9080 Local Configuration Local registers. However, does reset Configuration Shared Runtime registers. When set, 9080 responds accesses, local accesses. 9080 remains this condition until Host clears bit. serial EEPROM reloaded CNTRL[29] set.
Note: Host processor also access internal Configuration register after power-on.
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Section Functional Description
Table 3-1. Serial EEPROM Guidelines
Serial EEPROM Programmed Blank High System Boot Condition Boot with 9080 default values. Boot with serial EEPROM values. recommended (uses default values). Local processor programs 9080 registers, then sets Local Init Status (CNTRL[31] done).
Serial EEPROM Serial EEPROM
After reset, 9080 attempts read serial EEPROM determine presence. active start indicates serial EEPROM present (the 9080 supports 93CS46 (1K) 93CS56 (2K), selectable EESEL pin). (Refer manufacturer's data sheet particular serial EEPROM being used.) first word then checked verify serial EEPROM programmed. first word bit) ones, blank serial EEPROM 9080 uses default values instead. serial EEPROM clock (EESK, 173) derived from clock. 9080 generates serial EEPROM clock internally dividing clock serial EEPROM read programmed from Local Bus. Bits [27:24] Serial EEPROM Control register (CNTRL[27:24]) control 9080 pins that enable reading writing serial EEPROM data bits. (Refer manufacturer's data sheet particular serial EEPROM being used.) 9080 three serial EEPROM load options: Short Load Mode-SHORT# input pulled down 9080 loads five Lwords from serial EEPROM Long Load Mode-SHORT# input pulled Local Region Descriptor Register 9080 loads Lwords from serial EEPROM (LBRDO[25]) Extra Long Load Mode-SHORT# input pulled Local Region Descriptor Register during Long Load from serial EEPROM, 9080 loads Lwords from serial EEPROM (LBRDO[25])
Note: Some systems hang Direct Slave reads writes take long (during initialization, Host also performs Direct Slave accesses). Value Target Retry Delay Clocks (LBRD0[31:28]) resolve this problem.
Programmed Load serial EEPROM, Local processor reprogram 9080. Load serial EEPROM (default values), Local processor reprogram 9080. system boot.
Blank
Note: serial EEPROM programmed through 9080 after system boots this condition.
3.2.1 Serial EEPROM Initialization
During serial EEPROM initialization, 9080 response Target accesses Retry. During serial EEPROM initialization, 9080 response Local processor hold READYo#.
3.2.2 Local Initialization
9080 issues Retry accesses until Local Init Done Init Control register set. Init Done programmable through Local Configuration accesses. this going Local processor, then input should tied low. Holding input externally forces Local Init Done 9080 default values used serial EEPROM present Local Init Status holding input Local processor.
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Serial EEPROM 3.3.1 Short Serial EEPROM Load
registers listed Table loaded from serial EEPROM after reset de-asserted SHORT# low. serial EEPROM organized 16-bit words. 9080 first loads (Most Significant Word; bits [31:16]), starting from most significant [31]. 9080 then loads (Least Significant Word; bits [15:0]), starting again from most significant [15]. Therefore, 9080 loads Device Vendor class code, forth. five 32-bit words stored sequentially serial EEPROM. Table 3-2. Short Serial EEPROM Load Registers
Serial EEPROM Offset Description Sample Serial EEPROM Value 9080 10B5 0680 0002 0000 0100 xxxx xxxx xxxx xxxx
Section Functional Description 3.3.2 Long Serial EEPROM Load
registers listed LBRD0 loaded from serial EEPROM after reset de-asserted SHORT# high. serial EEPROM organized 16-bit words. 9080 first loads (Most Significant Word; bits [31:16]), starting from most significant [31]. 9080 then loads (Least Significant Word; bits [15:0]), starting again from most significant [15]. Therefore, 9080 loads Device Vendor class code, forth. serial EEPROM value entered into DATA programmer order shown below. values shown examples must modified each particular application. 16-bit words listed table stored sequentially serial EEPROM.
Device Vendor Class Code Class Code, Revision Maximum Latency, Minimum Grant Interrupt Pin, Interrupt Line Routing Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined)
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Section Functional Description
Table 3-3. Long Serial EEPROM Load Registers
Serial EEPROM Offset Description Device Vendor Class Code Class Code, Revision Maximum Latency, Minimum Grant Interrupt Pin, Interrupt Line Routing Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Range PCI-to-Local Address Space Range PCI-to-Local Address Space Local Base Address (Remap) PCI-to-Local Address Space Local Base Address (Remap) PCI-to-Local Address Space Local Arbitration Register Local Arbitration Register Local Big/Little Endian Descriptor Register Local Big/Little Endian Descriptor Register Range PCI-to-Local Expansion Range PCI-to-Local Expansion Local Base Address (Remap) PCI-to-Local Expansion Local Base Address (Remap) PCI-to-Local Expansion Region Descriptors PCI-to-Local Accesses Region Descriptors PCI-to-Local Accesses range Direct Master range Direct Master Local Base Address Direct Master Memory Local Base Address Direct Master Memory Local Address Direct Master IO/CFG Local Address Direct Master IO/CFG Base Address (Remap) Direct Master Base Address (Remap) Direct Master Configuration Address Register Direct Master IO/CFG Configuration Address Register Direct Master IO/CFG
Serial EEPROM
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Internal Register Access 3.3.3 Extra Long Serial EEPROM Load
Extra Long Load mode provided 9080 (LBRDO) load additional five Lwords from serial EEPROM. Local Region Descriptor register (LBRDO), following five Lword registers loaded addition normal Long Load process (refer Section 3.3.2, "Long Serial EEPROM Load"). must during Long Load Process. (Refer Table 3-4.) Table 3-4. Extra Long Serial EEPROM Load Registers
Serial EEPROM Offset Description
Section Functional Description
Note: 9080 does support serial EEPROMs that support sequential read write (such NM93C46 NM93C56).
3.3.5 Programming Serial EEPROM
serial EEPROM written read, using bits [28:24] Serial EEPROM Control register (CNTRL[28:24]).
Internal Register Access
9080 chip provides several Internal registers, allowing maximum flexibility interface design performance. register types accessible from both Local Buses, including following: Configuration registers Local Configuration registers Mailbox registers Doorbell registers registers Messaging queue registers (I2O)
Subsystem Subsystem Vendor Range PCI-to-Local Address Space Range PCI-to-Local Address Space Local Base Address (Remap) PCI-to-Local Address Space Local Base Address (Remap) PCI-to-Local Address Space Region Descriptors (Space PCI-to-Local accesses Region Descriptors (Space PCI-to-Local accesses Base Address Local Expansion Base Address Local Expansion
Figure illustrates these registers accessed.
Master Local Master
9080
Configuration Registers Local Configuration Registers Registers Mailbox Registers
3.3.4 Recommended Serial EEPROMs
1K-bit (National NM93CS46 compatible) 2K-bit (National NM93CS56 compatible) device used. Table lists recommended serial EEPROM loads. Refer also Table Section "Pin Description." Table 3-5. Recommended Serial EEPROM Loads
Load Short Long Extra Long Unused Bytes CS46 bit) Unused Bytes CS56 bit)
Interrupt
Clear
PCI-to-Local Doorbell Register LocalPCI -toDoorbell Register Messaging Queue Registers
Clear
Figure 3-2. 9080 Internal Register Access
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Local Interrupt
Section Functional Description 3.4.1 Access Internal Registers
9080 Configuration registers accessed from with Type Configuration cycle. 9080 Internal registers accessed Memory cycle, with address that matches base address specified Base Address Memory-Mapped Configuration register 9080. They also accessed cycle, with address matching base address specified Base Address I/O-Mapped Configuration register 9080. Read Write accesses 9080 registers Byte, Word, Lword accesses. Memory accesses 9080 registers Burst Non-burst. 9080 responds with Disconnect Burst accesses 9080 registers.
Internal Register Access
Local Read Write accesses 9080 registers Byte, Word, Lword accesses. Local accesses 9080 registers Burst Non-burst. modes, accesses must 32-bit nonpipelined bus. 9080 READYo# indicates Data transfer complete. mode, accesses must 16-bit nonpipelined bus. 9080 READYo# indicates Data transfer complete.
Address Decode Mode
LA31 LA30 LA29
9080
compare
9080
(PCI 9080 Chip Select)
3.4.2 Local Access Internal Registers
Local processor access Internal registers 9080 through either internal external address decode logic. 9080 provides Address Decode Mode (ADMODE) that selects whether internal address decode logic used designer supplies external chip select from external address decoder. Figure illustrates dual address decode logic works. Address Decode Mode internal 9080 address decode logic enabled. this mode, 9080 Internal registers selected when Local Address bits LA[31:29] match input address select pins S[2:0]. Address Decode Mode 9080 responds Local access when asserted through external chip select logic.
9080 Internal Register Chip Select 9080 Internal Register Chip Select
Figure 3-3. Dual Address Decode Mode
Notes: must decoded while ADS# low. ADMODE LA[31:29], specify Local Memory space allocated accessing Internal registers.
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Response Full Empty FIFOs Response Full Empty FIFOs
Table lists response 9080 full empty FIFOs. Table 3-6. Response Full Empty FIFOs
Mode Direct Master Write Direction Local-to-PCI FIFO Full Empty Direct Master Read Direct Slave Write PCI-to-Local PCI-to-Local Full Empty Full Empty Direct Slave Read Local-to-PCI Full Empty Local-to-PCI PCI-to-Local Full Empty Full Empty action De-assert REQ# (off Bus) De-assert REQ# throttle IRDY# action Disconnect throttle TRDY# action action Throttle TRDY# action De-assert REQ# De-assert REQ# action
Section Functional Description
Local De-assert READYo# action action De-assert READYo# action De-assert LHOLD, assert BLAST# (see Note) De-assert LHOLD, assert BLAST# (see Note) action De-assert LHOLD, assert BLAST# action action De-assert LHOLD, assert BLAST#
Note:
De-assertion LHOLD depends MARBR[21].
Direct Data Transfer Modes
Figure Figure illustrate direct Data Transfer modes. Refer also Table responses full empty FIFOs.
Host System Chipset
Address Translation DMA, Memory, Cycles Interrupts Software Protocol
Local
Local
Mailbox registers read and/or written from both sides Mailbox Mailbox
Doorbell registers clear interrupts
Clear
PCI-to-Local
Clear
Physical System Memory
Local-to-PCI
Mailbox Mailbox Mailbox Mailbox Mailbox Mailbox
Used Passing Commands Pointers Status
Local Memory
Local
Figure 3-5. Mailbox/Doorbell Message Passing
Host accesses Local Memory Direct Slave read/write Local accesses System Memory Direct Master read/write 9080 read/write from System Memory write/read Local memory read/write
Figure 3-4. Direct Master, Direct Slave,
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Section Functional Description 3.6.1 Direct Master Operation (Local Master Target)
9080 supports direct access Local processor intelligent controller. Master mode must enabled Command register. Five registers used define Local-to-PCI access: Range Local Base Address Direct Master Memory Register Local Base Address Direct Master IO/CFG Register Configuration Address Register Direct Master IO/CFG Base Address
Slave Slave
Direct Data Transfer Modes
Master Slave Master
ADS#, LBE#, LW/R#, BLAST# READYo# REQ#
GNT# FRAME#, C/BE# (addr) IRDY# DEVSEL#, TRDY# (data)
9080
Figure 3-6. Direct Master Write
3.6.1.1 Decode
Range register specifies Local Address bits decoding Local-to-PCI access. Local processor perform only Memory cycles. Therefore, Local Base Address Direct Master Memory register used decode access memory space. Local Base Address Direct Master IO/CFG register used decode access space Configuration cycle access.
Master
Slave
ADS#, LW/R#
Master
REQ# GNT#
IRDY# DEVSEL#, TRDY#, (data)
9080
READYo# BLAST#
3.6.1.2 FIFOs
Direct Master Memory access Bus, 9080 32-Lword (128 byte) Write FIFO 16-Lword byte) Read FIFO. FIFOs enable Local operate independently allows high-performance bursting Local Buses. Direct Master Write, Local processor (Master) writes data (Slave). Direct Master Read, Local processor (Master) reads data from (Slave). Figure Figure illustrate FIFOs during Direct Master Write Read.
Figure 3-7. Direct Master Read
Note: figures represent sequence cycles.
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Local
FRAME#, C/BE#, (addr)
Local
Direct Data Transfer Modes 3.6.1.3 Memory Access
Local processor read write memory. 9080 converts Local Read/Write access. Local Address space starts from Direct Master Local Base Address range. Remap (PCI Base Address) defines starting address. Writes-The 9080 continues accept writes returns READYo# until Write FIFO full. then holds READYo# until space becomes available Write FIFO. programmable Direct Master FIFO "almost full" status output provided (DMPAF#). Reads-The 9080 holds READYo# while gathering Lword from Bus. Programmable Prefetch modes available prefetch enabled: prefetch, continuous until Direct Master cycle ends. Read cycle terminated when Local BLAST# input asserted. Unused Read data then flushed from FIFO. 9080 does prefetch Read data Single Cycle Direct Master reads (Local BLAST# input asserted during first Data phase). this case, 9080 reads single Lword. Direct Master Single Cycle reads, 9080 asserts same byte enables asserted Local Bus. Multiple Cycle reads, 9080 reads entire Lwords (all byte enables asserted), regardless local byte enables. Prefetch Limit DMPBAM[11] enabled, 9080 does prefetch past boundary. Also, Local must cross boundary during Burst read. 9080 never prefetches beyond region specified Direct Master accesses.
Section Functional Description 3.6.1.5
Configuration Enable clear, single access made Bus. Local Address, remapped decode address bits local byte enables encoded provide address output with Read Write command during Address cycle. writes, data loaded into Write FIFO READYo# returned Local Bus. reads, 9080 holds READYo# while gathering Lword from Bus. When Remap Select value these Address bits [31:16] forced value (DMPBAM[13]).
3.6.1.6 (PCI Configuration Type Type Cycles)
Configuration Enable set, access made Bus. addition enabling Configuration DMCFGA[31], user must provide register information. register number (bits [7:2]) device number (bits [15:11]) must modified Read/Write cycle must performed before other registers devices accessed. Configuration Address register selects Type command, bits [10:0] from register copied address bits [10:0]. Bits [15:11] (device number) translated into single being Address bits [31:11]. Address bits [31:11] used device select. Type command, bits [23:0] copied from register bits [23:0] Address. Address bits [31:24] Configuration Read Write command code output with address during Address cycle (DMCFGA). writes, Local data loaded into Write FIFO READYo# returned. reads, 9080 holds READYo# while gathering Lword from Bus.
3.6.1.4 IO/CFG Access
When Local Direct Master access made, Configuration Enable Configuration Address register determines Configuration access made Bus. Local Burst accesses broken into Single Address/Data cycles. 9080 does prefetch Read data reads. Direct Master Configuration cycles, 9080 asserts same byte enables asserted Local Bus.
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Section Functional Description
Example 1-To perform Type Configuration cycle device AD[21]: 9080 must configured allow Direct Master access Bus. 9080 must also respond Space accesses. PCICR[2,0] follows: Space Master Enable
Direct Data Transfer Modes
Register Number (bits [7:2]) Device Number (bits [15:11]) must modified Read/Write cycle must performed before other registers devices accessed.
3.6.1.7 Direct Master Lock
9080 supports direct Local-to-PCI exclusive accesses (locked atomic operations). locked operation must start with Local input LLOCK# being asserted during Direct Master Read cycle. Refer timing Section "Timing Diagrams."
board designer selects Direct Master range. this example, range 000FFFFFh
3.6.1.8 Master/Target Abort
9080 Master/Target abort logic enables Local Master perform Direct Master poll devices determine whether devices exist (typically when Local performs Configuration cycles Bus). Master, Target Abort, Retry Time-out encountered during transfer, 9080 asserts LSERR# enabled (INTCSR[1:0]) (can used NMI). Local Master waiting READYo#, asserted along with BTERMo#. Local Master's interrupt handler take appropriate application specific action. then clear Abort bits Status Configuration register (PCISR) clear LSERR# interrupt re-enable Direct Master transfers. Local Master attempting Burst read from nonresponding device (Master/Target abort), receives READYo# BTERMo# first cycle only. Local processor cannot terminate Burst cycle, cause Local processor hang. Local must then reset from local watchdog timer asserting RESETi#. Local Master cannot terminate cycle with BTERMo#, should perform Burst cycles when attempting determine whether device exists.
value program into range register inverse 000FFFFFh, which FFF00000h: DMRR FFF00000h
board designer determines local Base Address Direct Master IO/CFG. this example, 40000000h: DMLBAI 40000000h
Address (Remap) Direct Master Memory register must enable Direct Master access. DMPBAM[1] follows: Direct Master Access Enable
must know which device Configuration register Configuration cycle accessing. this example, access device AD[21], well PCIBAR0, Base Address Memory-Mapped Configuration register (the fourth register, counting from 0-use Table 4-5, "PCI Configuration Registers," reference). DMCFGA[31, 23:0] follows: Bits Configuration Type Bits Register Number fourth register, therefore must program into this bit, beginning with 000100b Bits 10:8 Function Number 000b Bits 15:11 Device Number n-11, where value AD[n]=21-11 01010b Bits 23:16 Number 00000000b Configuration Enable
3.6.1.9 Write Invalidate
9080 programmed perform Write Invalidate cycles Direct Master transfers. 9080 supports Write Invalidate transfers cache line sizes Lwords. size specified Cache Line Size register. size other than specified, 9080 performs Write transfers rather than Write Invalidate transfers.
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Direct Data Transfer Modes 3.6.1.9.1 Write Invalidate
Write Invalidate transfers enabled when Write Invalidate Enable controller Mode register Memory Write Invalidate Enable Command register. Write Invalidate mode, 9080 waits until number Lwords required specified cache line size have been read from Local before starting access. This ensures that complete cache line write completed ownership. Target disconnects before cache line completed, 9080 completes remainder that cache line using normal writes before resuming Write Invalidate transfers. Write Invalidate cycle progress, 9080 continues burst another cache line been read from Local before cycle completes. Otherwise, 9080 terminates burst waits next cache line read from Local Bus. final transfer complete cache line, 9080 completes transfer, using normal writes.
Section Functional Description 3.6.1.9.2 Direct Master Write Invalidate
Direct Master Write Invalidate transfers enabled when Invalidate Enable Base Address (Remap) register Direct Master Memory Memory Write Invalidate Enable Command register (PCICR). Write Invalidate mode, start address Direct Master transfer cache line boundary, 9080 waits until number Lwords required specified cache line size have been written from Local before starting Write Invalidate access. This ensures that complete cache line write completed ownership. start address cache line boundary, 9080 starts normal Write access. 9080 terminates cycle cache line boundary performing normal write performing Write Invalidate cycle another cache line data available. entire cache line available time 9080 regains Bus, 9080 resumes Write Invalidate cycles. Otherwise, continues with normal write. Target disconnects before cache line completed, 9080 completes remainder that cache line using normal writes.
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Section Functional Description
Direct Data Transfer Modes
Master
Local Processor
Initialize Local Direct Master Access Registers
Local Range Direct Master Local Base Address Direct Master Memory Base Address (Remap) Direct Master
Local Base Address Direct Master IO/CFG Address Register Direct Master IO/CFG Command Register
Type Enabled
Access
FIFOs
Deep Write Deep Read Local Access
Local Base Address Direct Master Memory Space LA[31:16] Memory Command
Local Memory
Local Base Address Direct Master Memory Space
Range
Local Base Address Direct Master IO/CFG
Base Address
Command
Range
Address Space
Address Register
Command Type
Figure 3-8. Local Master Direct Master Access
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Direct Data Transfer Modes 3.6.2 Direct Slave Operation (PCI Master Local Access)
9080 supports both Burst Memory-Mapped Transfer accesses I/O-Mapped, Single-Transfer accesses Local from Bus. Base Address registers provided location adapter memory space. addition, local mapping registers allow address translation from Address space Local Address Space. Three spaces available: Space Space Expansion space
Section Functional Description 3.6.2.1 Mode
9080 programmed through Local Arbitration Mode register perform delayed reads, specified Specification v2.1.
Read request 9080 tells Host "Retry" Read cycle later free perform other cycles during this time host returns fetch Read data again Read data ready Host Spec v2.1 mode Internal registers 9080 requests Read data from Local Local memory returns requested data 9080
Local
Data stored Lword Internal FIFO
Expansion space intended support bootable device host. Each Local space programmed operate 32-bit Local width. 9080 internal wait state generator external wait state input, READYi#, which disabled enabled with Internal Configuration register. Local Bus, independent Bus, can: Burst long data available Continuous Burst (mode) Burst four Lwords time Perform continuous single cycle, with without wait state(s)
9080 returns prefetched data immediately
Figure 3-9. Specification v2.1 Delayed Reads
Note: figure represents sequence cycles.
addition delayed read, 9080 supports following Specification v2.1 features: write while read pending (Retry reads) Write flush pending read
Single Cycle Direct Slave reads, 9080 reads single Local Lword partial Lword. 9080 disconnects after transfer Direct Slave accesses. highest Data transfer rate, 9080 supports posted writes programmed prefetch data during Burst reads. prefetch size, when enabled, from Lwords, until stops requesting. 9080 prefetches, enabled, drops Local after Prefetch Counter reached. Continuous Prefetch mode, 9080 prefetches long FIFO space available terminates prefetch when terminates request. Read prefetching disabled, 9080 disconnects after Read transfer.
9080 also supports Read Ahead mode (refer Figure 3-10), where prefetched data read from internal 9080 FIFO instead from Local Bus. address must subsequent previous address must 32-bit aligned (next address current address
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Section Functional Description
Local
Master
FRAME#, C/BE#, (addr) IRDY#, (data)
Direct Data Transfer Modes
Slave Master Slave
9080
Read request Read Ahead mode Internal register 9080 prefetches data from Local device
Read data Master read returns with "Sequential Address" Prefetched data stored Internal FIFO 9080 returns prefetched data immediately from Internal FIFO without reading again from Local
9080
LHOLD LHOLDA ADS#, LW/R# BLAST# READYi#
9080 prefetches more data FIFO space available
Read data
9080 prefetches more data from Local memory
Figure 3-11. Direct Slave Write Figure 3-10. 9080 Read Ahead Mode
Master
FRAME#, C/BE#, (addr) IRDY#
Slave
Master
Slave
Note: figure represents sequence cycles.
9080 programmed keep generating wait state(s), thereby de-asserting TRDY#, Write FIFO becomes full. 9080 also programmed keep Local Bus, thereby asserting LHOLD, Direct Slave Write FIFO becomes empty Direct Slave Read FIFO becomes full. Local dropped either case when Local Latency Timer enabled expires. (Refer Figure 3-11 Figure 3-12.) Direct Slave writes, (Master) writes data Local (Slave). Direct Slave "Command from Host," which highest priority. Direct Slave Direct Master pre-empts DMA; however, Direct Slave does pre-empt Direct Master (refer Section 3.6.2.3.1, "Backoff").
9080
TRDY#, (data)
LHOLD LHOLDA ADS#, LW/R#, BLAST# READYi#,
Figure 3-12. Direct Slave Read
Note: figures represent sequence cycles.
Direct Slave reads, (Master) reads data from Local (Slave). 9080 supports on-the-fly Endian conversion Space Space Expansion space. Local Big/Little Endian either using BIGEND# input programmable internal register configuration. When BIGEND# asserted, overrides internal register configuration.
Note:
always Little Endian.
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Local
DEVSEL#
Local
DEVSEL#, TRDY#
Direct Data Transfer Modes 3.6.2.2 PCI-to-Local Address Mapping
Note: applicable mode.
Three Local Address spaces-Space Space Expansion ROM-are accessible from Bus. Each defined three registers: Local Address Range Local Base Address Base Address
Section Functional Description
8-Bit Bus-For 8-bit bus, BE1# BE0# encoded provide LA0, respectively. BE3# used BE2# used BE1# Address (LA1) BE0# Address (LA0)
Each PCI-to-Local Address space defined part reset initialization described next section.
fourth register, Region Descriptor PCI-to-Local Accesses, defines Local characteristics both regions (refer Figure 3-13).
3.6.2.2.2 Local Initialization Software
Range-Specifies which Address bits decoding access Local space. Each Prefetch Limit corresponds Address bit. corresponds Address Write bits that must included decode others. Remap PCI-to-Local Addresses into Local Address Space-Bits this register remap (replace) Address bits used decode Local Address bits. Local Region Descriptor-Specifies Local characteristics.
3.6.2.2.1 Byte Enables
LBE[3:0]# (pins 139-142) encoded based configured width, follows: 32-Bit Bus-For 32-bit bus, four byte enables indicate which four bytes active during Data cycle. BE3# Byte Enable 3-LD[31:24] BE2# Byte Enable 2-LD[23:16] BE1# Byte Enable 1-LD[15:8] BE0# Byte Enable 0-LD[7:0]
3.6.2.2.3 Initialization Software
reset software determines much address space required writing value ones Base Address register then reading back value. 9080 return zeroes Don't Care Address bits, effectively specifying address space required. software then maps Local Address space into Address space programming Base Address register. (Refer Figure 3-13.)
16-Bit Bus-For 16-bit bus, BE3#, BE1# BE0# encoded provide BHE#, LA1, BLE#, respectively. BE3# Byte High Enable (BHE#)-LD[15:8] BE2# used BE1# Address (LA1) BE0# Byte Enable (BLE#)- LD[7:0]
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Section Functional Description
Master
Direct Data Transfer Modes
Local Processor
Initialize Local Direct Access Registers
Initialize Base Address Registers
Range PCI-to-Local Address Space
Local Base Address (Remap) PCI-to-Local Address Space
Region Descriptors PCI-to-Local Accesses
Range PCI-to-Local Expansion
Local Base Address (Remap) PCI-to-Local Expansion
Region Descriptors PCI-to-Local Accesses
Local Hardware Characteristics
Base Address Local Address Space Base Address Local Expansion
Access
FIFOs
Deep Write Deep Read Local Access
Address Space
Base Address Local Base Address
Local Memory
Range
Figure 3-13. Direct Slave Access Local
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Direct Data Transfer Modes
Example Local Address Space 12300000h through 123FFFFFh accessible from Addresses 78900000h through 789FFFFFh. Local initialization software sets Range Local Base Address registers, follows: Range-FFF00000h decode upper Address bits) Local Base Address (remap)-123XXXXXh (Local Base Address PCI-to-Local accesses) (bit Space Enable bit, must recognized Host)
Section Functional Description 3.6.2.3 Deadlock BREQo
Deadlock occur when Master wants access 9080 Local same time Master 9080 Local requires access Bus. types deadlock situations occur: Partial Deadlock-Master Local performing direct Master access device other than device concurrently trying access Local Bus. Full Deadlock-Master Local performing direct Master access same device concurrently trying access Local Bus.
Initialization software writes ones Base Address, then reads back again. 9080 returns value FFF00000h. software then writes Base Address register Base Address-789XXXXXh (PCI Base Address access Local Address Space)
This applies only Direct ("pass through") Master Slave accesses through 9080. Deadlock does occur transfers through 9080 controller mailboxes. partial deadlock, access Local times (the Target Retry Timer, which programmable through Local Region Descriptor register PCI-to-Local accesses) 9080 responds with Retry. specification requires that Master release request (de-asserts REQ#) minimum clocks after receiving Retry. This allows arbiter grant 9080 that complete Direct Master access free Local Bus. Possible solutions described below cases which arbiter does function described (PCI architecture dependent), waiting time-out undesirable, full deadlock condition exists. full deadlock, only solution back Local Master.
direct access Local Bus, 9080 32-Lword (128 byte) Write FIFO 16-Lword byte) Read FIFO. FIFOs enable Local operate independently Bus. 9080 programmed return Retry response throttle TRDY# transaction attempting write 9080 Local when FIFO full. Read transactions from 9080 Local Bus, 9080 holds TRDY# while gathering Local Lword returned. Read accesses mapped memory space, 9080 prefetches Lwords (has Continuous Prefetch mode) from Local Bus. Unused Read data flushed from FIFO. Read accesses mapped space, 9080 does prefetch Read data. Rather, breaks each read Burst cycle into Single Address/Data cycle Local Bus. period time 9080 holds TRDY# programmed (the Target Retry Timer) Local Region Descriptor register (LBRD0). 9080 issues Retry transaction Master when programmed time period expires. This occurs when 9080 cannot gain control Local return TRDY# within programmed time period.
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Section Functional Description 3.6.2.3.1 Backoff
9080 contains (BREQo) that indicates possible deadlock condition exists. 9080 starts BREQo timer (programmable through registers) when detects following conditions: Master trying access memory device Local gaining access (for example, LHOLDA received). Master Local performing direct Master Read access Master Local performing direct Master Write access 9080 Direct Master Write FIFO cannot accept another Write cycle.
Direct Data Transfer Modes 3.6.2.3.2 Software/Hardware Solution Systems without Backoff Capability
adapters that support Backoff, possible deadlock solution follows. Host software, external Local hardware, general purpose output USERO general purpose input (USERI) used Host software prevent deadlock. USERO request that external arbiter grant Local Master except 9080. status output from local arbiter connected general-purpose input USERI indicate that Local Master owns Local Bus. Host determine that Local Master currently owns Local read input. Host then perform Direct Slave access. When host done, clears USERO. devices that support pre-empt, USERO used pre-empt current Master device. current Local Master device completes current cycle gives Local (de-asserts LHOLD).
timer expires 9080 received LHOLDA signal, 9080 asserts BREQo. External logic this signal perform Backoff. Backoff cycle device/bus architecture dependent. External logic (arbiter) assert necessary signals cause Local Master release Local (Backoff). After backing Local Master, grant 9080 asserting LHOLDA). Once BREQo asserted, READYo# current Data cycle never asserted (the Local Master must perform Backoff). When 9080 detects LHOLDA, proceeds with Master Local access. When this access complete 9080 releases Local Bus, external logic release Backoff Local Master resume cycle interrupted Backoff cycle. Write FIFO 9080 retains data acknowledged (that last data which READYo# asserted). After Backoff condition ends, Local Master restarts last cycle with ADS#. writes, data following this ADS# should data that acknowledged 9080 prior Backoff cycle (for instance, last data which there READYo# asserted). Read cycle completed when Local backed off, Local Master receives that data Local Master restarts same last cycle (data read twice). read performed, resumed Local cycle same backed-off cycle.
3.6.2.3.3 Software Solutions Deadlock
Host software Local software combination mailbox registers, doorbell registers, interrupts, direct Local-to-PCI accesses direct PCI-to-Local accesses avoid deadlock.
3.6.2.4 Direct Slave Lock
9080 supports direct PCI-to-Local exclusive accesses (locked atomic operations). locked operation Local results entire address Space Space Expansion space being locked until they released Master. 9080 asserts LLOCKo# during first clock atomic operation (Address cycle) deasserts minimum clock, following last access atomic operation. LLOCKo# deasserted after 9080 detects FRAME# LOCK# de-asserted same time. Refer timing diagrams Section "Timing Diagrams." Locked operations enabled disabled with Local Region Descriptor register PCI-to-Local accesses. responsibility external arbitration logic monitor LLOCKo# enforce meaning atomic operation. example, Local Master initiates locked operation, local arbiter choose grant Local other Masters until locked operation complete.
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Operation 3.6.3 Direct Slave Priority
Direct Slave accesses have higher priority than accesses. Direct Slave accesses pre-empt transfers. When 9080 controller owns Local Bus, LHOLD output LHOLDA input asserted LDSHOLD output de-asserted. When Direct Slave access occurs, 9080 gives Local within Lword transfers de-asserting LHOLD floating Local outputs. After 9080 samples LHOLDA input de-asserted, requests Local Direct Slave transfer asserting LHOLD LDSHOLD. When 9080 receives LHOLDA, drives performs Direct Slave transfer. Upon completion Direct Slave transfer, 9080 gives Local de-asserting both LHOLD LDSHOLD floating Local outputs. After 9080 samples LHOLDA deasserted local pause timer zero, requests Local transfer re-asserting LHOLD. When receives LHOLDA, drives continues with transfer.
Section Functional Description Operation
9080 supports independent channels capable transferring data from Local from Local Bus. Each channel consists controller programmable FIFO. Both channels support Chaining Non-chaining transfers, Demand mode DMA, Transfer (EOT) pins. Master mode must enabled Command register.
3.7.1 Non-Chaining Mode
host processor Local processor sets Local Address, Address, transfer count transfer direction. host Local processor then sets control initiate transfer. 9080 arbitrates Local Buses transfer data. Once transfer complete, 9080 sets Channel Done value generates interrupt Local processor Host (programmable). Done internal register pooled indicate status transfer. registers accessible from Local Bus. (Refer Figure 3-14.)
Mode Non-Chaining
Mode Register
Host Memory
Transfer Parameters
Address Register Local Address Register Transfer Size (byte count) Register Descriptor Pointer Register (set direction only)
Memory Block Transfer
Local Memory
Command/Status Register
Memory Block Transfer
Enable bits Command/Status Register Initiate Transfer
Figure 3-14. Non-Chaining Initialization
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Section Functional Description
Local processor requires DMA. 9080 Master both Local Buses. Direct Slave Direct Master pre-empts DMA. 9080 releases following occurs (refer Figure 3-15): FIFO full Terminal count reached Latency Timer (PCILTR[7:0]) expires- normally programmed Host BIOS- GNT# de-asserts Host asserts STOP Direct Master request pending
Operation
9080 releases Local following occurs (refer Figure 3-16): FIFO empty Terminal count reached Local Latency Timer (MARBR[7:0]) expires BREQ# input asserted Direct Slave request pending
Slave
Start
Master
Master
Start LHOLD LHOLDA
Slave
Slave
Start REQ# GNT# FRAME#, C/BE#, (addr) IRDY#
Master
Master
Slave
ADS#, LW/R#
Start
REQ# GNT# IRDY# DEVSEL#, TRDY# (addr data)
9080
DEVSEL#, TRDY# (data)
9080
LHOLD LHOLDA ADS#, LW/R#, BLAST# READYi#
Local
Figure 3-16. DMA, Local-to-PCI
Figure 3-15. DMA, PCI-to-Local
Note: figures represent sequence cycles.
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Local
Operation 3.7.2 Chaining Mode
Chaining mode DMA, Host Processor Local Processor sets descriptor blocks local host memory that composed Address, Local Address, transfer count, transfer direction, address next descriptor block (refer Figure 3-18). Host Local Processor then sets address initial descriptor block Descriptor Pointer register 9080 initiates transfer setting control bit. 9080 loads first descriptor block initiates Data transfer. 9080 continues load descriptor blocks transfer data until detects Chain Next Descriptor Pointer register. 9080 programmed interrupt Local processor setting Interrupt after Terminal Count Host upon completion each
Section Functional Description
block transfer after block transfers complete (done) (refer Figure 3-17). chaining descriptors located Local memory, controller programmed clear transfer size completion each (DMAMODE0[16] DMAMODE1[16]).
Notes: Chaining mode DMA, descriptor includes Address, Local Address, Transfer Size Next Descriptor Pointer (DMAPADR0-DMADPR0). Descriptor Pointer register contains Chain bit, Direction Transfer, Next Descriptor Address, Next Descriptor Location. descriptor Local memory, both (first descriptor Local memory, second descriptor memory).
Mode Chaining
Local Host Memory
First Address First Local Address
Mode Register
First Descriptor Pointer Register (First only requires Descriptor Pointer) Descriptor Pointer Register
First Transfer Size (byte count) Next Descriptor Pointer
Host Memory
Address Local Address Transfer Size (byte count) Next Descriptor Pointer Command/Status Register Enable bits Command/Status Register Initiate Transfer
First Memory Block Transfer
Chain Specification
Next Memory Block Transfer
First Memory Block Transfer
Next Memory Block Transfer
Figure 3-17. Chaining Initialization
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Section Functional Description
Setup chains PCI-to-Local 9080 retrieves chaining information from Local memory 9080 writes data Local
Operation 3.7.3 Data Transfers
9080 controller programmed transfer data from Local side side from side Local side. Refer Figure 3-19 Figure 3-20 description operation.
9080 initiates read from 9080 initiates read from
9080
9080 writes data Local 9080 retrieves chaining information from Local memory 9080 writes data Local 9080 writes data Local
9080 initiates read from 9080 initiates read from
Read Write Cycles continue.
Figure 3-18. Chaining Mode from PCI-to-Local
Note: figure represents sequence cycles.
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Operation 3.7.3.1 Local-to-PCI Transfer
Interrupt Generation (Programmable)
Section Functional Description
Local Interrupt Generation (Programmable)
Done Chaining: Terminal Count Current Descriptor
Unload FIFO with Write Cycles
FIFO
Arbitration Local Arbitration
Load FIFO with Local Read Cycles
Done Chaining: Terminal Count Current Descriptor
Chaining Mode Descriptors: start each block transfer-in Chaining mode only-loads registers reading four Lwords from address specified Next Descriptor Pointer register. Arbitration: Releases control whenever FIFO becomes empty, latency timer expires GRANT de-asserts, Disconnect received, Direct Local-to-PCI request pending. Rearbitrates control when preprogrammed number entries FIFO become available, after clocks disconnect received.
Chaining Mode Descriptors: start each block transfer- Chaining mode only-loads registers reading four Lwords from address specified Next Descriptor Pointer register.
GNT#
REQ# LHOLDA LHOLD
Local Arbitration: Releases control Local whenever FIFO becomes full, terminal count reached, Local latency timer expires, BREQ input asserted, Direct PCI-to-Local request pending. Rearbitrates control Local when preprogrammed number empty entries FIFO become available. Local latency timer expired, waits until pause timer expires.
Figure 3-19. Local-to-PCI Data Transfer Operation
3.7.3.2 PCI-to-Local Transfer
Interrupt Generation (Programmable) Local Interrupt Generation (Programmable)
Done Chaining: Terminal Count Current Descriptor
Load FIFO with Read Cycles
FIFO
Arbitration Local Arbitration
Unload FIFO with Local Write Cycles
Done Chaining: Terminal Count Current Descriptor
Chaining Mode Descriptors: start each block transfer-in Chaining mode only-loads registers reading four Lwords from address specified Next Descriptor Pointer register. Arbitration: Releases control whenever FIFO becomes full, terminal count reached, latency timer expires GRANT de-asserts, Disconnect received, Direct Local-to-PCI request pending. Rearbitrates control when preprogrammed number empty entries FIFO become available, after clocks disconnect received.
Chaining Mode Descriptors: start each block transferin Chaining mode only-loads registers reading four Lwords from address specified Next Descriptor Pointer register.
GNT#
REQ# LHOLDA LHOLD
Local Arbitration: Releases control Local whenever FIFO becomes empty, Local latency timer expires, BREQ input asserted, Direct PCI-to-Local request pending. Rearbitrates control Local when preprogrammed number entries become available FIFO terminal count reached. Local latency timer expired, waits until pause timer expires.
Figure 3-20. PCI-to-Local Data Transfer Operation
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Section Functional Description 3.7.3.3 Unaligned Transfers
unaligned Local-to-PCI transfers, 9080 reads partial Lword from Local Bus. continues read Lwords from Local Bus. Lwords assembled, aligned address loaded into FIFO. PCI-to-Local transfers, Lwords read from loaded into FIFO. Local Bus, Lwords assembled from FIFO, aligned Local address written Local Bus. both Local Buses, byte enables writes determine LA[1:0] start transfer. last transfer, byte enables specify bytes written. reads Lwords.
Operation 3.7.5 Priority
Channel priority, Channel priority, rotating priority specified Arbitration register.
3.7.6 Arbitration
9080 controller releases control Local (de-asserts LHOLD) when following occurs: FIFOs full Local-to-PCI transfer FIFOs empty PCI-to-Local transfer Local Latency Timer expires enabled) BREQ input asserted (BREQ enabled disabled, gated with latency timer before 9080 gives Local Bus) Direct Slave access pending input received enabled)
3.7.4 Demand Mode
Mode register (BLAST mode Demand mode DMA), determines number Lwords transferred after controllers DREQ[1:0]# input de-asserted. BLAST# output required last Lword transfer (bit controller releases data after receives external READYi# internal wait state counter decrements value current Lword. controller currently bursting data, which last Data phase burst, BLAST# output asserted. BLAST# output required last Lword transfer (bit controller transfers Lwords. DREQ[1:0]# de-asserted during Address phase first transfer 9080 Local ownership (ADS#, LHOLDA asserted), controller completes current Lword. DREQ[1:0]# de-asserted during phase other than Address phase first transfer 9080 Local ownership, controller completes current Lword, additional Lword (this allows BLAST# output asserted during final Lword). FIFO full empty after Data phase which DREQ[1:0]# de-asserted, second Lword transferred. DREQ[1:0]# controls only number Lword transfers. 8-bit bus, 9080 gives after last byte Lword transferred. 16-bit bus, 9080 gives after last word Lword transferred.
controller releases control when following occurs: FIFOs full empty Latency Timer expires loses GNT# signal Target Disconnect response received
controller de-asserts request (REQ#) minimum clocks.
3.7.6.1 Transfer (EOT0# EOT1#) Input
Mode register (BLAST mode EOT), determines number Lwords transferred after controller EOT[1:0]# input asserted. BLAST# output required last Lword transfer (bit controller releases data terminates after receives external READYi# internal wait state counter decrements value current Lword. controller currently bursting data, which last Data phase burst, BLAST# output asserted.
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Vendor Device Registers
BLAST# output required last Lword transfer (bit controller transfers Lwords. EOT[1:0]# asserted, controller completes current Lword, additional Lword (this allows BLAST# output asserted during final Lword). FIFO full empty after Data phase which EOT[1:0]# asserted, second Lword transferred. controller terminates transfer Lword boundary after EOT[1:0]# asserted. 8-bit bus, 9080 terminates after last byte Lword transferred. 16-bit bus, 9080 terminates after last word Lword transferred.
Section Functional Description Vendor Device Registers
Three Vendor Device registers supported: PCIIDR, which contains normal Device Vendor IDs. This register loaded from serial EEPROM from Local processors. PCISVID, which contains Subsystem Subvendor IDs. This register loaded from serial EEPROM from Local processors. PCIHIDR, which contains hardcoded Vendor Device IDs.
Doorbell Registers 3.7.6.2 Abort
transfer aborted. abort process follows: Channel must enabled (DMACSR0[0]=1). Channel must started (DMACSR0[1]=1). Wait Channel Done zero (DMACSR0[4]=0). Disable Channel (DMACSR0[0] =0). Abort programming Channel Abort (DMACSR0[2]=1). Wait until Channel Done (DMACSR0[4]=1). There 32-bit doorbell interrupt/status registers 9080. assigned interface other assigned Local interface. Local processor generate interrupt writing number other than zeroes PCIto-Local Doorbell register (P2LDBELL). Host generate Local interrupt writing number other than zeroes Local-toPCI Doorbell register (L2PDBELL).
3.10 Mailbox Registers
There eight 32-bit mailbox registers 9080 that written read from both buses. These registers used pass command status information directly between Local devices. Local interrupt generated, enabled, when Host writes first four mailbox registers.
Note: Data transfers occur after Abort set. Aborting when cycles progress causes next abort.
3.7.6.3 Local Latency Pause Timers
Local Latency Timer Local Pause Timer programmable with Arbitration register. Local Latency Timer expires, 9080 completes current Lword transfer releases LHOLD. After programmable Pause Timer expires, reasserts LHOLD. When receives LHOLDA, continues transfer. transfer continues until FIFO empty Local-to-PCI transfer until full PCI-to-Local transfer.
3.11 User Input Output
9080 supports user input output pins, USERI[31] USERO[27], respectively. User output data logged writing CNTRL[16]. User input data read from CNTRL[17].
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Section Functional Description 3.12 Interrupts
Parity Error Master Abort Retrys Target Abort Messaging Queue
[12]
Interrupts
Done Terminal Count Doorbells
LSERR#
[17]
Mailboxes Done Terminal Count Doorbells Master Abort Retrys Target Abort LINTi#
[12] [10]
[16]
LINTo#
BIST
[23]
Messaging Queue
Done Terminal Count
[11]
INTA#
represent register (LOC [E8h]) Bits [7:6] register (LOC [168h]) register (LOC [100h]) register (LOC [E110h]) register (LOC [E8h]) register (LOC [100h]) Bits [5:4] register (LOC [168h]) register (LOC [114h]) register (LOC [124h]) register (LOC [E8h]) register (LOC [114h]) register (LOC [B0h]) register (LOC [B4h])
Messaging Queue Done Terminal Count
17='0', then LINTo# generated 17='1', then INTA# generated.
Figure 3-21. Interrupt Error Sources
3.12.1 Interrupts (INTA#)
9080 Interrupt (INTA#) generated following: Local-to-PCI Doorbell register Local interrupt input Master/Target abort status condition 0/Ch Done 0/Ch Terminal Count reached Messaging Outbound Post Queue empty
3.12.1.1 Local Interrupt Input
Asserting Local input LINTi# generate interrupt. Host processor read 9080 Interrupt Control/Status register determine that interrupt pending LINTi# being asserted. interrupt remains asserted long LINTi# asserted Local interrupt input enabled. Adapter specific action taken Host processor cause Local release LINTi#.
INTA#, individual sources interrupt, enabled disabled with 9080 Interrupt Control/Status register (INTCSR). This register also provides interrupt status each interrupt source. 9080 interrupt level output. Disabling Interrupt Enable clearing cause(s) interrupt clear interrupt.
3.12.1.2 Master/Target Abort Interrupt
9080 sets Master Abort Target Abort Status Configuration register when detects Master Target abort. These status bits cause INTA# asserted interrupts enabled. interrupt remains asserted long Master Target Abort bits remain Status
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
Interrupts
Configuration register (PCISR) Master/Target Abort Interrupt enabled. Type Configuration access Local access clear Master Abort Target Abort Interrupt bits Status Configuration register. Interrupt Control/Status register Bits (INTCSR[26:24]) latched time Target abort interrupt Master abort interrupt. They provide information Master when abort occurred. 9080 updates these bits whenever abort occurs.
Section Functional Description
prevent race conditions when accessing Doorbell register Configuration register), 9080 automatically de-asserts READYo# prevent Local accesses.
3.12.2.2 PCI-to-Local Doorbell Interrupt
Master generate Local interrupt writing PCI-to-Local Doorbell register (P2LDBELL). Local processor then read 9080 Interrupt Control/Status register (INTCSR) determine that doorbell interrupt pending. then read 9080 PCI-to-Local Doorbell register. Each PCI-to-Local Doorbell register individually controlled. only bits Doorbell register. From Bus, writing position sets that writing position effect. Bits PCI-to-Local Doorbell register only cleared from Local Bus. From Local Bus, writing position clears that writing position effect.
3.12.2 Local interrupts (LINTo#)
9080 Local interrupt (LINTo#) generated following: PCI-to-Local Doorbell/Mailboxes Register access BIST interrupt, done interrupt terminal count reached abort interrupt Messaging Outbound Post Queue empty
LINTo#, individual sources interrupt, enabled disabled with 9080 Interrupt Control/Status register (INTCSR). Interrupt Control/Status register also provides interrupt status each source interrupt. 9080 Local interrupt level output. interrupt cleared disabling Interrupt Enable source clearing cause interrupt.
Note: Local cannot clear Doorbell Interrupt, PCI-to-Local Doorbell register.
interrupt remains asserted long PCI-to-Local Doorbell register bits Local Doorbell Interrupt enabled. prevent race conditions when Local accessing Doorbell register Configuration register), 9080 automatically issues Retry Bus.
3.12.2.1 Local-to-PCI Doorbell Interrupt
Local Master generate interrupt writing Local-to-PCI Doorbell register (L2PDBELL). Host processor then read 9080 Interrupt Control/Status register (INTCSR) determine that doorbell interrupt pending. then read 9080 Local-to-PCI Doorbell register. Each Local-to-PCI Doorbell register individually controlled. Local only bits Doorbell register. From Local Bus, writing position sets that writing position effect. Bits Local-to-PCI Doorbell register only cleared from Bus. From Bus, writing position clears that writing position effect. interrupt remains asserted long Local-to-PCI Doorbell register bits Doorbell Interrupt enabled.
9080 Data Book v1.06 ©PLX Technology, Inc. rights reserved
3.12.2.3 Built-In Self Test Interrupt (BIST)
Master generate Local interrupt performing Type Configuration write BIST register. Local processor then read 9080 Interrupt Control/Status register (INTCSR) determine that BIST interrupt pending. interrupt remains asserted long BIST interrupt enabled. Local then resets when BIST complete. Host software fail device reset after seconds.
Note:
9080 does have internal BIST.
Section Functional Description 3.12.2.4 Channel Interrupts
channel generate Local interrupt when done (transfer complete) after transfer complete descriptor Chaining mode. mode register determines whether generate Local interrupt. local processor then read 9080 Interrupt Control/Status register (INTCSR) determine whether channel interrupt pending. Done Status Control/Status register used determine whether interrupt done interrupt result transfer descriptor chain that complete
Compatible Message Unit
parity error checking enabled Command register, 9080 sets Master Detected Parity Error Status Status Configuration register (PCISR) detects following: Parity error during 9080 Master Read signal PERR# being asserted during 9080 Master Write
9080 sets Parity Error Status Configuration register (PCISR) detects following: Data parity error during 9080 Master Read Data parity error during Slave Write access 9080 Address parity error
mode register channel enables Done Interrupt. Chaining mode, Next Descriptor Pointer register channel (loaded from Local memory) specifies whether generate interrupt transfer current descriptor. channel interrupt cleared writing Clear Interrupt Command/Status register (DMACSR0[3] DMACSR1[3]).
9080 Interrupt Control/Status register (INTCSR) used individually enable disable LSERR# abort parity error. LSERR# level output that remains asserted long Abort Parity Error Status bits set.
3.13 Compatible Message Unit
Messaging Unit supplies paths messages, inbound FIFOs receive messages from primary outbound FIFOs pass messages primary Bus. Refer Architecture Specification v1.5 details. Figure 3-22 Figure 3-23 illustrate information about architecture.
Message Frames
hardware changes required host side
3.12.3 SERR# (PCI NMI)
9080 generates SERR# pulse parity checking enabled Command register detects address parity error Generate SERR# Interrupt Control/Status register (INTCSR) written. SERR# output enabled disabled with Command register.
Host
Physical System Memory
3.12.4 Local LSERR# (Local NMI)
LSERR# interrupt output asserted following occurs: Target Abort Master Abort Status Status Configuration register Parity Error Statu
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