Short Form Datasheet Single-Slot ACPI CardBus Controller ACPI-PCI
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OZ6912
Short Form Datasheet Single-Slot ACPI CardBus Controller
ACPI-PCI Power Management Interface Specification Compliant Supports OnNow wakeup, OnNow Ring Indicate, CLKRUN#, PME#, CardBus CCLKRUN# Compliant with specification v2.2, 2000 Card Standard YentaPCI PCMCIA CardBus Bridge register compatible ExCA (Exchangeable Card Architecture) compatible registers mappable memory space Intel 82365SL PCIC Register Compatible Supports PCMCIA_ATA Specification Supports 5V/3.3V Cards 3.3V CardBus cards Supports single Card CardBus slot with insertion removal Supports multiple FIFOs PCI/CardBus data transfer Supports Direct Memory Access PC/PCI PCI/Way Card socket Programmable interrupt protocol: PCI, PCI+ISA, PCI/Way, PC/PCI interrupt signaling modes Supports parallel serial interface socket power control including devices from O2Micro (OZ2211 OZ2206), Micrel Zoomed Video Support; Zoomed video buffer enable pins D3cold state PME# wakeup support 3.3Vaux Power Support Subsystem Vendor support, with auto lock Activity Pins
specification defined PCMCIA release 2.1. CardBus intended support "temporal" add-in functions Cards, such Memory cards, Network interfaces, FAX/Modems other wireless communication cards, etc. high performance capability CardBus interface will enable development many functions applications. OZ6912 CardBus controller compliant with latest ACPI-PCI Power Management Interface Specification. supports four power states PME# function maximum power savings ACPI compliance. Additional compliance OnNow Power Management includes D3cold state support, paving sleep state power consumption minimized resume times. allow host software reduce power consumption further, OZ6912 provides power-down mode which internal clock distribution Card socket clocks stopped. advanced CMOS process also used minimize system power consumption. OZ6912 single PCMCIA socket supports match 3.3V/5V 8/16-bit Card card 32-bit CardBus card. card support compatible with Intel 82365SL PCIC controller, card support fully compliant with 2000 Card Standard CardBus specification. OZ6912 stand-alone device, which means that does require additional buffer chip Card socket interface. addition, OZ6912 supports dynamic Card insertion removal, with auto configuration capabilities. OZ6912 fully compliant with 33Mhz specification, v2.2. supports master device with internal CardBus direct data transfer. OZ6912 implements FIFO data buffer architecture between CardBus socket interface enhance data transfers CardBus devices. bi-directional FIFO buffer permits OZ6912 accept data from target (PCI CardBus interface) while simultaneously transferring data. This architecture only speeds data transfers also prevents system deadlocks. OZ6912 PCMCIA R2/CardBus controller, providing most advanced design flexibility Cards that interface with advanced notebook designs.
ORDERING INFORMATION
OZ6912T LQFP OZ6912B Mini-BGA
GENERAL DESCRIPTION
OZ6912 ACPI compliant "Designed Microsoft Windows" logo certified, high performance, single slot Card controller with synchronous 32-bit master/target interface. This Card bridge host controller compliant with 2000 Card Standard. This standard incorporates 32-bit CardBus while retaining 16-bit Card
10/08/02 Copyright 2000 O2Micro
OZ6912-SF-2.0 Rights Reserved
Page Patent Pending
OZ6912
Functional Block Diagram
Interface
Configuration/ Function Control Registers Function Control Configuration/ Registers
Arbite Arbiter
ACPI/ OnNow Power Management PC99
Power Switch Power Control Contro Switch
CardBu CardBus FIFO Data FIFO DatasBuffering Buffering
Interrupt Interrup Subsystem Subsyste
8/16-Bit 16PC Card Machin Card Machine
CardBus Card Machine Arbiter
Powe Power Switc Switch Interface
Single Card Interface Card Interface
OZ6912-SF-2.0
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OZ6912
SYSTEM BLOCK DIAGRAM
following diagram typical system block diagram utilizing OZ6912 ACPI CardBus controller with other related chipsets.
North Bridge
Memory
OZ6912 CardBus Controller
South Bridge
Card
OZ6912-SF-2.0
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OZ6912
DIAGRAM LQFP
REQ# GNT# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL CORE_VCC AD23 AD22 AD21 PCI_VCC AD20 RST# PCI_CLK AD19 AD18 AD17 AD16 C/BE2# FRAME# IRDY# PCI_VCC TRDY# DEVSEL# STOP# PERR# SERR#
A22/CTRDY# A15/CIRDY# A23/CFRAME# A12/CCBE2# A24/CAD17 A7/CAD18 A25/CAD19 VS2/CVS2 A6/CAD20 RESET/CRST# A5/CAD21 A4/CAD22 CORE_VCC INPACK#/CREQ# A3/CAD23 REG#/CCBE3# SOCKET_VCC A2/CAD24 A1/CAD25 A0/CAD26 VS1/CVS1 RDY/IREQ#/CINT# WAIT#/CSERR# BVD2/SPKR#/LED/CAUDIO BVD1/STSCHG#/RI#/CSTSCHG WP/IOIS16/CCLKRUN# CD2/CCD2# CORE_VCC D0/CAD27 D8/CAD28 D1/CAD29 D9/CAD30 D2/RFU D10/CAD31
0108 9107 Micro OZ6912 A16/CCLK A21/CDEVSEL# WE#/CGNT# A20/CSTOP# A14/CPERR# A19/CBLOCK# CORE_VCC A13/CPAR A18/RFU A8/CCBE1# A17/CAD16 A9/CAD14 IOW#/CAD15 A11/CAD12 IORD#/CAD13 OE#/CAD11 CE2#/CAD10 SOCKET_VCC A10/CAD9 CE1#/CCBE0# D15/CAD8 CORE_VCC D7/CAD7 D14/RFU D6/CAD5 D13/CAD6 D5/CAD3 D12/CAD4 D4/CAD1 D11/CAD2 D3/CAD0 CD1/CCD1# VCCD1#/SCLK VCCD0#/SDATA
VPPD1 VPPD0/SLATCH SUSPEND# GLOBAL_RST# AUX_VCC SPKR_OUT# RI_OUT/PME# PCI_VCC C/BE0# AD10 PCI_VCC AD11 AD12 AD13 AD14 AD15 C/BE1#
OZ6912-SF-2.0
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OZ6912
List
Bold Text Normal Default Name
Interface Pins
Name AD[31:0] Description Address/Data: These pins connect signals AD[31:0]. transaction consists address phase followed more data phases. Number LQFP 3-5, 7-11, 15C2, 23-26, 38-41, 45F2, 51-57 Input Type Power Rail PCI_Vcc Drive Spec
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
PERR#
SERR#
Command/Byte Enable: command signaling byte enables multiplexed same pins. During address phase transaction, C/BE[3:0]# interpreted commands. During data phase, C/BE[3:0]# interpreted byte enables. byte enables valid entirety each data phase, they indicate which bytes 32-bit data path carry meaningful data current data phase. Cycle Frame: This signal indicates OZ6912 that transaction beginning. While FRAME# asserted, data transfers continue. When FRAME# de-asserted, transaction final phase. Initiator Ready: This signal indicates initiating agent's ability complete current data phase transaction. IRDY# used conjunction with TRDY#. Target Ready: This signal indicates target Agent's OZ6912's ability complete current data phase transaction. TRDY# used conjunction with IRDY#. Stop: This signal indicates current target requesting master stop current transaction. Initialization Device Select: This input used chip select during configuration read write transactions. This point-to-point signal. IDSEL used chip select during configuration read write transactions. Device Select: This signal driven active when address recognized supported, thereby acting target current cycle. Target must respond before timeout occurs cycle will terminate. Parity Error: output driven active when data parity error detected during write phase. System Error: This output driven active indicate address parity error.
PCI_Vcc
Spec
PCI_Vcc
Spec
PCI_Vcc
Spec
PCI_Vcc
Spec
PCI_Vcc
Spec Spec
PCI_Vcc
PCI_Vcc
Spec
PCI_Vcc
Spec Spec
PCI_Vcc
OZ6912-SF-2.0
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OZ6912
Name Description Parity: This generates parity ensures even parity across AD[31:0] C/BE[3:0]#. During address phase, valid after clock. With data phases, stable clock after write read transaction. Clock: This input provides timing transactions from OZ6912. signals, except RST#, sampled driven rising edge PCI_CLK. This input operated frequencies from MHz. Device Reset: This input used initialize registers internal logic their reset states place most OZ6912 pins HIGHimpedance state. Grant: This signal indicates that access been granted. Request: This signal indicates arbiter that OZ6912 requests bus. Number LQFP Input Type Power Rail PCI_Vcc Drive Spec
PCI_CLK
PCI_Vcc
RST#
AUX_Vcc
GNT# REQ#
PCI_Vcc PCI_Vcc
Spec Spec
Power Control General Interface Pins
Name RI_OUT/ PME# Description Ring Indicate Out: This Ring Indicate when following occurs while Mode Control Register (index 2Eh) Power Control (Index+02h) Interrupt General Control (Index+03h) O2Micro Control (Offset: D4h) Power Management Event: power management event process which OZ6912 request change power consumption state. Usually, occurs during request change from power saving state fully operational state. Speaker Output: This output used support Card audio output. Mode Register (Index 3Eh), Multifunction Terminal [6:0]: Multifunction Register (Offset:08h). Suspend: This signal used protect internal registers from clearing when RST# signal asserted. When low, this signal used mask RESET during suspend. This used during suspend prevent controller reset. Global_Reset#: This signal connected either reset ACPI reset depending system implementation. cold state implemented, this signal should connected ACPI reset, otherwise, connect reset. This signal reset content under cold state AUX_VCC provided. Number LQFP Input Type Power Rail Aux_Vcc Drive
SPKR_OUT#
Aux_Vcc
MF[6:0]
60-61, 64-65, 67-69
SUSPEND#
N10, L10, N11,
Aux_Vcc
Aux_Vcc
G_RST#
Aux_Vcc
OZ6912-SF-2.0
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OZ6912
Name VPPD0/ SLATCH Description VPPD0: This power input used with parallel power control chip SLATCH: This output controls serial interface power control chip. VPPD1: This power input used parallel power interface chip. VCCD0#: Rail power inputs with parallel power control chip. Serial Data: This serves output DATA when used with serial interface serial power control chip. VCCD1#: Rail power inputs with parallel power control chip. Serial Clock: input used reference clock (10-100kHz, usually 32kHz) control serial power control chips. setting O2Micro Control register (Offset: D4h) SCLK output. Default input mode. Number LQFP Input Type Power Rail Aux_Vcc Drive
VPPD1 VCCD0#/ SDATA
Aux_Vcc Aux_Vcc
VCCD1#/ SCLK
Aux_Vcc
OZ6912-SF-2.0
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OZ6912
Card Socket Interface Pins
Refer Interface descriptions details CardBus function. EXCEPTIONS: CCD[2:1]#, CAUDIO, CSTSCHG, CVS[2:1]
Name REG#/ CCBE3# Description Register Access: During Card memory cycles, this output chooses between Attribute Common Memory. During cycles non-DMA transfers, this signal active (low). During mode, this signal always inactive. cycles OZ6912 DMA-capable card, REG# becomes DACK PCMCIA card. CardBus Command Byte Enable: CardBus mode, this CCBE3#. Address: Card socket address 25:24 outputs. CardBus Address/Data: CardBus mode, these pins bits Address: Card socket address output. CardBus Frame: CardBus mode, this CFRAME# signal. Address: Card socket address output. CardBus Target Ready: CardBus mode, this CTRDY# signal. Address: Card socket address output. CardBus Device Select: CardBus mode, this CDEVSEL# signal. Address: Card socket address output. CardBus Stop: CardBus mode, this CSTOP# signal. Address: Card socket address output. CardBus Lock: CardBus mode, this signal CBLOCK# signal used locked transactions. Address: Card socket address output. Reserved: CardBus mode, this reserved future use. Address: Card socket address output. CardBus Address/Data: CardBus mode, this Address: Card socket address output. CardBus Clock: CardBus mode, this supplies clock inserted card. Number LQFP Input Type Power Rail Socket _Vcc Drive CardBus spec.
A[25:24]/ CAD[19, A23/ CFRAME# A22/ CTRDY# A21/ CDEVSEL# A20/ CSTOP# A19/ CBLOCK# A18/ A17/ CAD16 A16/ CCLK#
116,
A10,
Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc Socket _Vcc
CardBus spec. CardBus spec. CardBus spec. CardBus spec. CardBus spec. CardBus spec. CardBus spec. CardBus spec. CardBus spec.
I/O-PU
I/O-PU
I/O-PU
I/O-PU
OZ6912-SF-2.0
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OZ6912
Name A15/ CIRDY# Description Address: Card socket address output. CardBus Initiator Ready: CardBus mode, this CIRDY# signal. Address: Card socket address output. CardBus Parity Error: CardBus mode, this CPERR# signal. Address: Card socket address output. CardBus Parity: CardBus mode, this CPAR signal. Address: Card socket address output. CardBus Command/Byte Enable: CardBus mode, this CCBE2# signal. Address: Card socket address 11:9 output. CardBus Address/Data: CardBus mode, these pins bits Address: Card socket address output. CardBus Command/Byte Enable: CardBus mode, this CCBE1# signal. Address: Card socket address outputs. CardBus Address/Data: CardBus mode, these pins bits 20:26. Data: Card socket data CardBus Address/Data: CardBus mode, this Data: Card socket data Reserved: CardBus mode, this reserved future use. Data: Card socket data Ibits 13:3. CardBus Address/Data: CardBus mode, this respectively. Data: Card socket data Reserved: CardBus mode, this reserved future use. Data: Card socket data bits 1:0. CardBus Address/Data: CardBus mode, these pins bits respectively. Output Enable: This output goes active (low) indicate memory read from OZ6912 Card. CardBus Address/Data: CardBus mode, this Write Enable: This output goes active (low) indicate memory write from OZ6912 Card socket. CardBus Grant: CardBus mode, this CGNT# signal. Number LQFP Input Type I/O-PU Power Rail Socket _Vcc Drive CardBus spec.
A14/ CPERR#
I/O-PU
Socket _Vcc
CardBus spec.
A13/ CPAR
Socket _Vcc
CardBus spec.
A12/ CCBE2#
Socket _Vcc
CardBus spec.
A[11:9]/ [12,9,14] CCBE1#
F11, G12,
Socket _Vcc
CardBus spec.
Socket _Vcc
CardBus spec.
A[7:0]/ CAD[18] [20:26] D15/ CAD8
115, 118, 120, 121, 124, 127, 128,
B10,
Socket _Vcc
CardBus spec.
Socket _Vcc
CardBus spec.
D14/
Socket _Vcc
CardBus spec.
D[13:3]/ CAD[6,
144, 142, 140,
J11, K13, K10, H10, J12, J10, K12,
Socket _Vcc
CardBus spec.
Socket _Vcc
CardBus spec.
D[1:0]/ CAD[29,27]
141,
Socket _Vcc
CardBus spec.
OE#/ CAD11
Socket _Vcc
CardBus spec.
WE#/ CGNT#
Socket _Vcc
CardBus spec.
OZ6912-SF-2.0
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OZ6912
Name IORD#/ CAD13 Description Read: This output goes active (low) reads from OZ6912 socket. CardBus Address/Data: CardBus mode, this Write: This output goes active (low) writes from OZ6912 socket. CardBus Address/Data: CardBus mode, this Write Protect/ 16-Bit: Memory mode, this input indicates status write protect switch Card. mode, this input indicates size current data transfer Card. CardBus Clock Run: CardBus mode, this CCLKRUN# signal, which starts stops CardBus CCLK. enable CLKRUN# signal, ExCA register bit[3:2] must enabled. Input Acknowledge: INPACK# function applicable environments. This provided Legacy card compatibility. CardBus Request: CardBus mode, this CREQ# signal. Ready/Interrupt Request: Memory mode, this input indicates that card ready busy. mode, this input indicates card interrupt request. CardBus Interrupt: CardBus mode, this CINT# signal. This signal active-low level-sensitive. Wait: This driven Card delay completion current cycle. CardBus System Error: CardBus mode, this CSERR# signal. Card Detect: These inputs indicate card present socket. They internally pulled high AUX_VCC. CardBus Card Detect: CardBus mode, these inputs used with CVS[2:1] detect presence type card. Card Enable This driven control byte/word card access. CE2# enables oddnumbered address bytes. CardBus Address/Data: CardBus mode, this Card Enable This driven control byte/word card access. CE1# enables evennumbered address bytes. When configured 8bit cards, CE1# active used indicate access odd- even-numbered bytes. CardBus Command/Byte Enable: CardBus mode, this CCBE0# signal. Number LQFP Input Type Power Rail Socket _Vcc Drive CardBus spec.
IOW#/ CAD15
Socket _Vcc
CardBus spec.
IOIS16#/ CCLKRUN#
I/O-PU
Socket _Vcc
CardBus spec.
INPACK#/ CREQ#
I-PU
Socket _Vcc
CardBus spec.
RDY/IREQ#/ CINT#
I-PU
Socket _Vcc
CardBus spec.
WAIT#/ CSERR#
I-PU
Socket _Vcc
CardBus spec.
CD[2:1]/ CCD[2:1]#
137,
I-PUSchmitt
Aux_Vcc
CardBus spec.
CE2#/ CAD10
Socket _Vcc
CardBus spec.
CE1#/ CCBE0#
Socket _Vcc
CardBus spec.
OZ6912-SF-2.0
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OZ6912
Name RESET/ CRST# Description Reset: This active high output resets card. prevent reset glitches, this signal highimpedance unless card seated socket, card power applied, card's interface signals enabled. CardBus Reset: CardBus mode, this CRST# output. Battery Voltage Detect 2/Speaker/LED: Memory mode, this input serves BVD2 (battery warning status) input. mode, this input configured card's SPKR# audio input drive-active input. CardBus Audio: CardBus mode, this CAUDIO input. Battery Voltage Detect 1/Status Change/ Ring Indicate: Memory mode, this BVD1 (battery-dead status) input. mode, this STSCHG# input indicating that card's internal status changed, ring indicates input wakeup-on-ring system power management support. Interrupt General Control register (03h). CardBus Status Change: CardBus mode, this CSTSCHG. This used generate PME#. Voltage Sense: These pins used conjunction with CD[2:1] determine type voltage card. These pins internally pulled high AUX_VCC. Table CardBus Voltage Sense: CardBus mode, these pins CVS[2:1] pins. Socket Power: These pins power rail input socket interface control logic. These pins 3.3, socket interface outputs will operate voltage applied these pins. Number LQFP Input Type Power Rail Socket _Vcc Drive CardBus spec.
BVD2/SPKR#/ LED/CAUDIO
I-PU
Socket _Vcc
BVD1/ STSCHG#/RI# /CSTSCHG
I-PU
Socket _Vcc
VS[2:1]/ CVS[2:1]
117,
I/O-PU
Aux_Vcc
CardBus spec.
SOCKET_VCC
G13,
OZ6912-SF-2.0
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OZ6912
Power, Ground, Reserved Pins
Name AUX_VCC CORE_VCC Description Auxiliary VCC: This must connected system's 3.3-volt supply. CORE_VCC: This provides power core circuitry OZ6912. must connected 3.3-volt power supply. VCC: These pins must connected 3.3-volt power supply. interface will operate voltage applied these pins, independent voltage applied other OZ6912 groups. System Ground Number LQFP 102, 122, H11, D12, Input Type Power Rail Drive
PCI_VCC
114,
K11, F12, C10,
Legend
Type I-PU I-PU Schmitt TO-PU OD-PU Description Input Input with internal pull-up Input with internal pull-up Schmitt trigger Output Open-drain Tri-state output Tri-state output with internal pull-up Open-drain output with internal pull-up Power Power Rail Source Output's Power AUX_VCC: outputs powered from AUX_VCC SOCKET_VCC: outputs powered from socket PCI_VCC: outputs powered from power supply CORE_VCC: outputs powered from CORE_VCC
OZ6912-SF-2.0
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OZ6912
Package Information LQFP
0.08(0.003)
MILLIMETER SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
INCH
GAGE PLANE
0.05
0.10
0.15
0.002
0.004
0.006
1.35
1.40
1.45
0.053
0.055
0.057
0.25
0.17
0.22
0.27
0.007
0.009
0.011
0.090
0.200
0.004
0.008
20.00
0.787
20.00
0.787
0.50
0.020
22.00
0.866
22.00
0.866
0.45
0.60
0.75
0.018
0.024
0.030
1.00
0.039
0.08
0.003
OZ6912-SF-2.0
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OZ6912
Mini
NOTES: DIMENSIONING TOLERANCING ASME Y14.5M-1994. REPRESENTS SOLDER BALL GRID PITCH. REPRESENTS MAXIMUM NUMBER SOLDER BALLS MATRIX SIZE DIMENSION MEASURED MAXIMUM SOLDER BALL DIAMETER AFTER REFLOW PARALLEL PRIMARY DATUM ORIGINAL SOLDER BALL DIAMETER 0.45 PRIMARY DATUM SEATING PLANE DEFINED SPHERICAL CROWNS SOLDER BALLS. CORNER MUST IDENTIFIED MARK, METALLIZED MARKINGS, IDENTATION OTHER FEATURE PACKAGE BODY, INTEGRAL HEATSLUG, SURFACE PACKAGE. SOLDER BALL DEPOPULATION ALLOWED. DEPOPULATION OMISSION BALLS FROM FULL MATRIX M2). BALL CORNER INDICATOR (NC) SOLDER BALL
OZ6912-SF-2.0
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OZ6912
IMPORTANT NOTICE
portion O2Micro specifications/datasheets subparts reproduced form, means, without prior written permission from O2Micro. O2Micro subsidiaries reserve right make changes their datasheets and/or products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. O2Micro warrants performance products specifications applicable time sale accordance with O2Micro's standard warranty. Testing other quality control techniques utilized extent O2Micro deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customer acknowledges that O2Micro products designed, manufactured intended incorporation into systems products intended connection with life support other hazardous activities environments which failure O2Micro products could lead death, bodily injury, property environmental damage ("High Risk Activities"). O2Micro hereby disclaims warranties, O2Micro will have liability Customer third party, relating O2Micro products connection with High Risk Activities. support, assistance, recommendation information (collectively, "Support") that O2Micro provide (including, without limitation, regarding design, development debugging your circuit board other application) provided IS." O2Micro does make, hereby disclaims, warranties regarding such Support, including, without limitation, warranties merchantability fitness particular purpose, warranty that such Support will accurate error free that your circuit board other application will operational functional. O2Micro will have liability under legal theory connection with your reliance such Support. COPYRIGHT 2002, O2Micro International Limited
OZ6912-SF-2.0
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