NetPHY-1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver w
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Am79C873
NetPHY-1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support DISTINCTIVE CHARACTERISTICS
100BASE-FX direct interface industry standard electrical/optical transceivers 10/100BASE-TX physical-layer, single-chip transceiver Compliant with IEEE 802.3u 100BASE-TX standard Compliant with ANSI X3T12 TP-PMD 1995 standard Compliant with IEEE 802.3u AutoNegotiation protocol automatic link type selection Supports with serial management interface Supports Full Duplex operation Mbps Mbps High performance Mbps clock generator data recovery circuitry Adaptive equalization circuitry Mbps receiver Controlled output edge rates Mbps Supports 10BASE-T interface without need external filter Provides Loopback mode system diagnostics Includes flexible configuration capability Digital clock recovery circuit using advanced digital algorithm reduce jitter Low-power, high-performance CMOS process Available 100-pin PQFP package
GENERAL DESCRIPTION
NetPHY-1 device physical-layer, single-chip, low-power transceiver 100BASE-TX, 100BASE-FX, 10BASE-T operations. media side, provides direct interface Fiber Media 100BASE-FX Fast Ethernet, Unshielded Twisted Pair Category Cable (UTP5) 100BASE-TX Fast Ethernet, UTP5/UTP3 Cable 10BASE-T Ethernet. Through IEEE 802.3u Media Independent Interface (MII), NetPHY-1 device connects Medium Access Control (MAC) layer, ensuring high interoperability among products from different vendors. NetPHY-1 device uses low-power, high-performance CMOS process. contains entire physical layer functions 100BASE-FX 100BASE-TX defined IEEE 802.3u standard, including Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), 100BASE-TX Twisted Pair Physical Medium Dependent (TP-PMD) sublayer, 10BASE-T Encoder/Decoder (ENDEC). NetPHY-1 device provides strong support Auto-Negotiation function utilizing automatic media speed protocol selection. NetPHY-1 device incorporates internal wave-shaping filter control rise/fall time, eliminating need external filtering 10/100 Mbps signals.
This document contains information product under development Advanced Micro Devices. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
Publication# 22164 Rev: Amendment/+2 Issue Date: February 1999
Refer AMD's Website (www.amd.com) latest information.
BLOCK DIAGRAM
OSCI
LED1-4
Driver PECL Driver FXTD±
4B/5B Encoder
Scrambler
Parallel Serial
NRZI
NRZI MLT-3
MLT-3 Driver
100TXD±
Rise/Fall Time 125M Signals Interface/ Control
4B/5B Decoder
Codegroup Alignment
Descrambler
Serial Parallel
NRZI
MLT-3 NRZI
Adaptive
RXI±
Digital Logic
PECL Receiver
FXRD± FXSD+ RXI± 10TXD±
10BASE-T Module
Register
Collision Detection
Carrier Sense
AutoNegotiation
22164A-1
Am79C873
CONNECTION DIAGRAM
RPTR/NODE
OPMODE3
10BTSER
BPALIGN
PHYAD4
PHYAD3
PHYAD1
PHYAD0
BP4B5B
BPSCR
TESTMODE
OPMODE2
OPMODE1
OPMODE0
PHYAD2
DGND
DVcc
AVcc FXSDFXSD+ FXRDFXRD+ AGND AVcc AVcc RXIRXI+ AGND AGND 10TXO10TXO+ AVcc AVcc AGND AGND FXTDFXTD+ AVcc AVcc AGND AGND 100TXO100TXO+ AVcc AVcc OSCI/X1
RESET
AGND
AGND
RX_EN RX_ER/RXD4 RX_DV RX_CLK DVcc DGND RXD0 RXD1 RXD2 RXD3 DVcc DGND MDIO TX_CLK TX_EN DVcc DGND TXD0 TXD1 TXD2 TXD3 TX_ER/TXD4 TXLED RXLED LINKLED DGND COLLED
Am79C873/KC NetPHY-1
RX_LOCK
SPEED10
OSC/XTL
LINKSTS
CLK25M
FDXLED
TRIDRV
BGREF
BGRET
AVcc
DGND
DGND
DGND
DGND
DVcc
AGND
AGND
DVcc
22164A-2
Am79C873
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination elements below. Am79C873
ALTERNATE PACKAGING OPTION Trimmed formed tray TEMPERATURE RANGE Commercial (0°C +70°C) PACKAGE TYPE Plastic Quad Flat Pack (PQR100) SPEED OPTION Applicable DEVICE NUMBER/DESCRIPTION Am79C873 NetPHY-110/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support Valid Combinations Valid Combinations Am79C873 KC\W Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C873
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Am79C873
CONTENTS
DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM ORDERING INFORMATION Standard Products RELATED PRODUCTS DESCRIPTIONS Interface Media Interface Interface Device Configuration/Control/Status Interface Clock Interface Address Interface Miscellaneous Power Ground Pins FUNCTIONAL DESCRIPTION Interface 100BASE Operation 100BASE Transmit 4B5B Encoder. Scrambler. Parallel-to-Serial Converter NRZ-to-NRZI Converter PECL Driver 100BASE-FX MLT-3 Converter. MLT-3 Driver. 100BASE Receiver 100BASE-TX Signal Detect. 100BASE-FX Signal Detect. Adaptive Equalization PECL Receiver MLT-3-to-NRZI Decoder. Clock Recovery Module. NRZI-to-NRZ Decoder. Serial-to-Parallel Converter Descrambler Code Group Alignment 4B5B Decoder 10BASE-T Operation Collision Detection. Carrier Sense Auto-Negotiation Serial Management Serial Management Interface Register Description Default Basic Mode Control Register (BMCR) Register Basic Mode Status Register (BMSR) Register Identifier Register (PHYIDR1) Register Identifier Register (PHYIDR2) Register Auto-Negotiation Advertisement Register(ANAR) Register Auto-Negotiation Link Partner Ability Register (ANLPAR) Register Auto-Negotiation Expansion Register (ANER) Register Specified Configuration Register (DSCR) Register Specified Configuration Status Register (DSCSR) Register 10BASE-T Configuration/Status (10BTCSRSCR) Register
Am79C873
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Commercial Devices Power Consumption. ELECTRICAL CHARACTERISTICS Electrical Characteristics 100BASE-TX Transmit Timing 100BASE-TX Transmit Timing Parameters (Half Duplex) 100BASE-TX Receive Timing MII-100BASE-TX Receive Timing Parameter (Half Duplex) Auto-Negotiation Fast Link Pulse Timing Auto-Negotiation Fast Link Pulse Timing Parameters 10BASE-T Nibble Transmit Timing. MII-10BASE-T Nibble Transmit Timing Parameters. 10BASE-T Receive Nibble Timing Diagram. MII-10BASE-T Receive Nibble Timing Parameters 10BASE-T (Heartbeat) Timing 10BASE-T (Heartbeat) Timing Parameters 10BASE-T Unjab Timing 10BASE-T Unjab Timing Parameters MDIO Timing when OUTPUT MDIO Timing when OUTPUT NetPHY-1 Device Timing Parameters MAGNETICS SELECTION GUIDE CRYSTAL SELECTION GUIDE NETPHY-1 EXAMPLE SCHEMATIC. PHYSICAL DIMENSIONS
Am79C873
DESCRIPTIONS Interface TX_ER/TXD4
Transmit Error Input Mbps mode, this signal asserted high TX_EN active, HALT symbol substituted actual data nibble. Mbps mode, this input ignored. bypass modes (BP4B5B BPALIGN), TX_ER becomes TXD4 pin, fifth data bit.
RXD[3:0]
Receive Data Output/Z1 Nibble wide receive data (synchronous RX_CLK 100BASE-TX mode, 10BASE-T nibble mode). Data driven falling edge RX_CLK. Mbps serial mode, RXD0 used data output pin. RXD[3:1] ignored.
RX_CLK
Receive Clock Output/Z1 Provides recovered receive clock different modes operation: nibble clock Mbps mode nibble clock Mbps nibble mode receive clock Mbps serial mode
TXD[3:0]
Transmit Data Input These transmit data input pins nibble data from Mbps Mbps nibble mode Mbps mode, Mbps nibble mode). Mbps serial mode, TXD0 used serial data input pin. TXD[3:1] ignored.
Carrier Sense Output/Z1 This asserted high indicate presence carrier receive transmit activities 10BASET 100BASE-TX Half Duplex modes. Repeater, when Full Duplex Loopback mode logic indicates presence carrier only receive activity.
TX_EN
Transmit Enable Input Active high input indicates presence valid nibble data TXD[3:0] both Mbps Mbps nibble mode. Mbps serial mode, active high indicates presence valid Mbps data TXD0.
Collision Detect Output/Z1 This asserted high indicate detection collision conditions Mbps Mbps Half Duplexmodes. 10BASE-T Half Duplex mode with Heartbeat active (bit register 18h), also asserted duration approximately transmission indicate heartbeat. Full Duplex mode, this signal always logic There heartbeat function Full Duplex mode.
TX_CLK
Transmit Clock Output/Z1 This provides transmit clock output from NetPHY-1 deviceas follows: nibble transmit clock derived from transmit Phase Locked Loop PLL) 100BASE-TX mode transmit clock 10BASE-T nibble mode transmit clock 10BASE-T serial mode
RX_DV
Receive Data Valid Output/Z1 This asserted high indicate that valid data present RXD[3:0].
Management Data Clock Input This synchronous clock MDIO management data input/output serial interface which asynchronous transmit receive clocks. maximum clock rate MHz.
RX_ER/RXD4
Receive Error Output/Z1 This asserted high indicate that invalid symbol been detected inside received packet Mbps mode. bypass mode (BP4B5B BPALIGN modes), RX_ER becomes RXD4, fifth data symbols.
MDIO
Management Data Input/Output This bidirectional management instruction/ data signal that driven station management entity PHY. This requires pullup resistor.
Goes high impedance.
Am79C873
RX_EN
Receive Enable Input This active high enabled receive signals RXD[3:0], RX_CLK, RX_DV RX_ER. this input tri-states these output pins. normal operation NODE application, this should pulled high.
function will change indicate Polarity status Mbps operation. polarity inverted, POLLED will
COLLED
Collision Output This indicates presence collision activity Mbps Mbps operation. This meaning Mbps Mbps Full Duplex operation (Active low).
Media Interface RXI±
100/10 Mbps-TX/T Twisted Pair Differential Input Pair Input These pins differential receive input 10BASE-T 100BASE-TX. They capable receiving 100BASE-TX MLT-3 10BASE-T Manchester encoded data.
LINKLED (TRAFFIC LED)
Link Output This indicates Good Link status Mbps Mbps operation (Active low). functions TRAFFIC when register TRAFFIC mode, always when link TRAFFIC flashes when transmitting receiving.
FXRD±
100BASE-FX PECL Differential Input Pair Input These pins differential receive input 100BASE-FX.
RXLED
Receive Output Drain This indicates presence receive activity Mbps Mbps operation (Active low). NetPHY-1 device incorporates "monostable" function RXLED output. This ensures that even minimal receive activity will generate adequate time.
FXSD±
100BASE-FX PECL Signal Detect Input These input signals from FX-PMD transceiver indicate detection receive signal from Fiber Media.
10TXO±
10BASE-T Differential Output Pair Output This output pair provides controlled rise fall times designed filter transmitters output.
TXLED
Transmit Output Drain This indicates presence transmit activity Mbps Mbps operation (Active low). NetPHY-1 device incorporates "monostable" function TXLED output. This ensures that even minimal transmit activity will generate adequate time.
100TXO±
100BASE-TX Twisted Pair Differential Output Pair Output This output pair drives MLT-3 encoded data twisted pair cable provides controlled rise fall times designed filter transmitters output, reducing associated EMI.
Device Configuration/Control/Status Interface
Cable Indication Output This Cable Indication. When UTP=1, indicates that cable being used.
FXTD±
100BASE-FX PECL Differential Output PairOutput These pins differential transmit output 100BASE-FX. They capable transmitting 100BASE-FX
SPEED10
Speed Mbps Output When high, this indicates Mbps operation, when Mbps operation. This drive current indicate that Mbps operation selected.
Interface
These outputs directly drive LEDs provide status information network management device.
FDXLED (POLLED)
Polarity/Full Duplex Output This indicates Full Duplex mode status Mbps Mbps operation (Active low). Register (FDXLED_MODE) set, FDXLED
RX_LOCK
Lock Clock/Data Recovery Output When this high, indicates that receiver recovery logic locked input data stream.
Am79C873
LNKSTS
Link Status Register Output This reflects status register
RTPR/NODE
Repeater/Node Mode Input When high, this selects REPEATER mode; when low, selects NODE. REPEATER mode NODE mode with Full Duplex configured, Carrier Sense (CRS) output from NetPHY-1 device will asserted only during receive activity. NODE mode mode configured Full Duplex operation, will asserted during receive transmit activity. power-up/reset, value this latched into Register
OPMODE0-OPMODE3
OPMODE0-OPMODE3 Input These pins used control forced advertised operating mode NetPHY-1 device (see table below). value latched into NetPHY-1 device registers power-up/rese.
OPOPOPOPMODE3 MODE2 MODE1 MODE0 Function Auto-Negotiation enable with capabilities with Flow Control Auto-Negotiation enable without capabilities without Flow Control Auto-Negotiation 100TX with Flow Control only Auto-Negotiation 100TX FDX/HDX without Flow Control Auto-Negotiation 10TP with Flow Control only Auto-Negotiation 10TX FDX/HDX without Flow Control Manual select 100TX Manual select 100TX Manual select 10TX Manual select 10TX Manual select 100FX Manual select 100FX Auto-Negotiation 10/100TX. only
BPALIGN
Bypass Alignment Input This allows Mbps transmit receive data streams bypass transmit receive operations when high. power-up/reset, value this latched into Register
BP4B5B
Bypass 4B5B Encoder/Decoder Input This allows Mbps transmit receive data streams bypass encoder decoder circuits when high. power-up/reset, value this latched into Register
BPSCR
Bypass Scrambler/Descrambler Input This allows Mbps transmit receive data streams bypass scrambler descrambler circuits when high. power-up/reset, value this latched into Register
10BTSER
Serial/Nibble Select Mbps Serial Operation: Input
When high, this input selects serial data transfer mode. Manchester encoded transmit receive data exchanged serially with clock rate least significant bits nibble-wide data buses, TXD[0] RXD[0] respectively. This mode intended with NetPHY-1 device connected device (MAC Repeater) that Mbps serial interface. Serial operation supported Mbps mode. Mbps, this input ignored. Mbps Nibble Operation: When low, this input selects compliant nibble data transfer mode. Transmit receive data exchanged nibbles TXD[3:0] RXD[3:0] pins respectively. power-up/reset, value this latched into Register
Am79C873
Clock Interface OSCI/X1
Crystal Oscillator Input Input This should connected (±50 ppm) crystal OSC/XTL=0 (±50 ppm) external oscillator input, OSC/XTLB=1.
PHYAD4
Address Input This provides address multiple address applications. status this latched into Register during power up/reset.
Crystal Oscillator Output Output external (±50 ppm) crystal should connected this OSC/XTL=0, left unconnected OSC/XTL=1.
Miscellaneous
Connect These pins left unconnected (floating).
BGREF
Bandgap Voltage Reference Input Connect 6.01K resistor between this BGRET provide accurate current reference NetPHY-1 device.
OSC/XTL
Crystal Oscillator Selector Output OSC/XTL=0: external (±50ppm) crystal should connected pins. OSC/XTL=1: external (±50ppm) oscillator should connected should left unconnected.
BGRET
Bandgap Voltage Reference Return Input This return 6.01K resistor connection.
CLK25M
Clock Output Output/Z This clock derived directly from crystal circuit.
TRIDRV
Tri-State Digital Output Input When high, digital output pins high impedance state, pins, input mode.
Address Interface
PHYAD[4:0] pins provide unique addresses. address selection zeros (00000) will result isolation condition. isolate description BMCR, address
RESET
Reset Input This active input that initializes NetPHY1 device. should remain after stabilized (nominal) before transitions high.
PHYAD0
Address Input This provides address multiple address applications. status this latched into Register during power up/reset.
TESTMODE
Test Mode Control TESTMODE=0: Normal operating mode. TESTMODE=1: Enable test mode. Input
PHYAD1
Address Input This provides address multiple address applications. status this latched into Register during power up/reset.
Power Ground Pins
power (VCC) ground (GND) pins NetPHY-1 device grouped pairs categories Digital Circuitry Power/Ground Pairs Analog Circuitry Power/Ground Pair.
PHYAD2
Address Input This provides address multiple address applications. status this latched into Register during power up/reset.
DGND
Digital Logic Ground These pins digital supply pairs. Power
DVCC
Digital Logic Power Supply These pins digital supply pairs. Power
PHYAD3
Address Input This provides address multiple address applications. status this latched into Register during power up/reset.
AGND
Analog Circuit Ground Power These pins analog circuit supply pairs.
AVCC
Analog Circuit Power Supply Power These pins analog circuit supply pairs. Am79C873
FUNCTIONAL DESCRIPTION
NetPHY-1 Fast Ethernet single-chip transceiver, provides functionality specified IEEE 802.3u standard, integrates complete 100BASE-FX, 100BASE-TX modules complete 10BASE-T module. NetPHY-1 device provides Media Independent Interface (MII) defined IEEE 802.3u standard (Clause 22).
NetPHY-1 device performs Physical Coding Sublayer (PCS), Physical Media Access (PMA), Twisted Pair Physical Medium Dependent (TP-PMD) sublayer, 10BASE-T Encoder/Decoder, Twisted Pair Media Access Unit (TPMAU) functions. Figure shows major functional blocks implemented NetPHY-1 device.
100Base Transmitter
100Base Receiver
Interface
10Base-T Tranceiver
Carrier Sense
Collision Detection
Auto Negotiation
Serial Management Interface
22164A-3
Figure
Functional Block Diagram
Interface
purpose interface provide simple, easy implement connection between Reconciliation layer PHY. designed make differences between various media transparent sublayer. consists nibble wide receive data bus, nibble wide transmit data bus, control signals facilitate data transfers between Reconciliation layer. (transmit data) nibble bits) data that driven reconciliation sublayer synchronously with respect TX_CLK. each TX_CLK period which TX_EN asserted, (3:0) accepted transmission PHY. TX_CLK (transmit clock) output reconciliation sublayer continuous clock that provides timing reference transfer TX_EN, TXD, TX_ER signals.
TX_EN (transmit enable) input from reconciliation sublayer indicate nibbles being presented transmission physical medium. TX_ER (transmit coding error) transitions synchronously with respect TX_CLK. TX_ER asserted more clock periods, TX_EN asserted, will emit more symbols that part valid data delimiter somewhere frame being transmitted. (receive data) nibble bits) data that sampled reconciliation sublayer synchronously with respect RX_CLK. each RX_CLK period which RX_DV asserted, (3:0) transferred from reconciliation sublayer. RX_CLK (receive clock) output reconciliation sublayer continuous clock that provides timing reference transfer RX_DV, RXD, RX_ER signals.
Am79C873
RX_DV (receive data valid) input from indicate presenting recovered decoded nibbles reconciliation sublayer. interpret receive frame correctly reconciliation sublayer, RX_DV must encompass frame starting later than Start-of-Frame delimiter excluding End-Stream delimiter. RX_ER (receive error) transitions synchronously with respect RX_CLK. RX_ER will asserted reconciliation sublayer that error detected somewhere frame being transmitted from reconciliation sublayer. (carrier sense) asserted when either transmit receive medium non-idle deasserted when transmit receive medium idle. Figure depicts behavior during 10BASE-T 100BASE-TX transmission.
IDLE
Preamble
Data
IDLE
100Base-TX
Preamble
Data
10Base-T
22164A-4
Figure Carrier Sense during 10BASE-T 100BASE-TX Transmission
100BASE Operation
100BASE transmitter receives 4-bit nibble data clocked outputs scrambled 5-bit encoded MLT-3 signal media Mbps. on-chip clock circuit converts clock into clock internal use. IEEE 802.3u specification defines Media Independent Interface. interface specification defines dedicated receive data dedicated transmit data bus.
These busses include various controls signal indications that facilitate data transfers between NetPHY-1 device Reconciliation layer. 100BASE Transmit 100BASE transmitter consists functional blocks shown Figure 100BASE transmit section converts 4-bit synchronous data provided scrambled MLT-3 million symbols second serial data stream.
Am79C873
OSCI
LED1-4#
Driver PECL Driver FXTD±
4B/5B Encoder
Scrambler
Parallel Serial
NRZI
NRZI MLT-3
MLT-3 Driver
100TXD±
Rise/Fall Time
Signals
Interface/ Control
10BASE-T Module
RXI± 10TXD±
Register
Collision Detection
Carrier Sense
AutoNegotiation
22164A-5
Figure 100BASE Transmitter Functional Block Diagram
block diagram Figure provides overview functional blocks contained transmit section. transmitter section contains following functional blocks: 4B5B Encoder Scrambler Parallel-to-Serial Converter NRZ-to-NRZI Converter PECL Driver (For Operation) NRZI MLT-3 (For Operation) MLT-3 Driver (For Operation)
combined code groups. 4B5B encoder substitutes first bits preamble with code-group pair (11000 10001) upon transmit. 4B5B encoder continues replace subsequent preamble data nibbles with corresponding code-groups. transmit packet, upon deassertion Transmit Enable signal from Reconciliation layer, 4B5B encoder injects code-group pair (01101 00111) indicating frame. After code-group pair, 4B5B encoder continuously injects IDLEs into transmit data stream until Transmit Enable asserted next transmit packet detected. NetPHY-1 device includes Bypass 4B5B conversion option within 100BASE-TX transmitter support applications like Mbps repeaters which require 4B5B conversion.
4B5B Encoder
4B5B encoder converts 4-bit (4B) nibble data generated Reconciliation Layer into 5-bit (5B) code group transmission (see Table This conversion required control packet data
Am79C873
Table
Symbol
4B5B Code Group
code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 undefined 0101 0101 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001
Meaning Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Idle Error Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
twisted pair cable 100BASE-TX operation. scrambling data, total energy presented cable randomly distributed over wide frequency range. Without scrambler, energy levels cable could peak beyond limitations frequencies related repeated sequences like continuous transmission IDLE symbols. scrambler output combined with data from code-group encoder logic function. result scrambled data stream with sufficient randomization decrease radiated emissions critical frequencies. Since concern fiber application, scrambler bypassed 100BASE-FX.
Parallel-to-Serial Converter
Parallel-to-Serial Converter receives parallel scrambled data from scrambler serializes (i.e., converts from parallel serial data stream). serialized data stream then presented NRZ-to-NRZI Encoder block
NRZ-to-NRZI Converter
After transmit data stream been scrambled serialized, data must NRZI encoded compatibility with TP-PMD standard 100BASE-TX transmission over Category-5 unshielded twisted pair cable.
PECL Driver 100BASE-FX
PECL driver accepts NRZI coded data converts PECL signal levels transmission over fiber media. output pair differential pseudo (PECL) interface designed connect directly standard fiber optic PMD. differential driver FXTD± current mode designed drive resistive termination complementary mode. FXTD± pins incapable sourcing current, this implies that must ratios Thevenin termination resistors each lines. RIOH pull-up resistor connected from FXTD± output VCC. RIOL pulldown resistor connected from FXTD± output ground. RIOH RIOL electrically parallel from standpoint. target impedance needed transmission line impedance. value RIOH value RIOL will yield Thevenin equivalent characteristic impedance 49.7 value VCC-.88 volts, compatible with PECL circuits. required VDD-1.81 greater. sink current milli-amps (mA) would achieve this through output termination resistors.
MLT-3 Converter
MLT-3 conversion accomplished converting data stream output from NRZI encoder into binary data streams with alternately phased logic events.
Scrambler
scrambler required control radiated emissions (EMI) spreading transmit energy across frequency spectrum media connector
Am79C873
MLT-3 Driver
binary data streams created MLT-3 converter twisted pair output driver which converts these streams current sources alternately drives either side transmit transformer primary winding resulting minimal current MLT-3 signal. Refer Figure block diagram MLT-3 converter.
Signal Detect Adaptive Equalization MLT-3-to-Binary Decoder Clock Recovery Module NRZI -o-NRZ Decoder Serial-to-Parallel Converter Descrambler Code Group Alignment 4B5B Decoder 100BASE-TX Signal Detect signal detect function meets specifications mandated ANSI XT12 TP-PMD 100BASE-TX standards both voltage thresholds timing parameters.
100BASE Receiver
100BASE receiver contains several function blocks that convert scrambled Mbps serial data synchronous 4-bit nibble data that then provided MII. receive section contains following functional blocks:
Binary
Binary plus
Binary minus
Common Driver
MLT-3
Binary MLT-3
22164A-6
Figure MLT-3 Converter Block Diagram
100BASE-FX Signal Detect NetPHY-1 device accepts signal detect information FXSD PECL signal levels from Optical Module. Adaptive Equalization When transmitting data high speeds over copper twisted pair cable, attenuation based frequency becomes concern. high speed twisted pair signaling, frequency content transmitted signal vary greatly during normal operation based randomness scrambled data stream. This variation
signal attenuation caused frequency variations must compensated ensure integrity received data. order ensure quality transmission when employing MLT-3 encoding, compensation must able adapt various cable lengths cable types depending installed environment. selection long cable lengths given implementation, requires significant compensation which will over-kill situation that includes shorter, less attenuating cable lengths. Conversely, selection short intermediate cable lengths requiring less compensation will
Am79C873
cause serious under-compensation longer length cables. Therefore, compensation equalization must adaptive ensure proper conditioning received signal independent cable length. PECL Receiver PECL receiver accepts PECL signal-level data from Optical Module presents Clock Recovery Module. MLT-3-to-NRZI Decoder NetPHY-1 device decodes MLT-3 information from Digital Adaptive Equalizer into NRZI data. relationship between NRZI MLT-3 data shown Figure Clock Recovery Module Clock Recovery Module accepts NRZI data from MLT-3-to-NRZI decoder PECL Receiver. Clock Recovery Module locks onto data stream extracts reference clock. extracted synchronized clock data presented NRZI-to-NRZ Decoder. NRZI-to-NRZ Decoder transmit data stream required NRZI encoded compatibility with 100BASE transmission over. This conversion process must reversed receive end. NRZI-to-NRZ decoder, receives NRZI data stream from Clock Recovery Module converts data stream presented Serial Parallel conversion block. Serial-to-Parallel Converter Serial-to-Parallel Converter receives serial data stream from NRZI-to-NRZ converter, converts data stream parallel data presented descrambler. Descrambler Because scrambling process required control radiated emissions transmit data streams, receiver must descramble receive data streams. descrambler receives scrambled parallel data streams from Serial Parallel converter, descrambles data streams, presents data streams Code Group alignment block. 4B5B Decoder 4B5B Decoder functions look-up table that translates incoming code groups into (Nibble) data. When receiving frame, first 5-bit code groups received start-of-frame delimiter (J/K symbols). symbol pair stripped nibbles preamble pattern substituted. last code groups end-of-frame delimiter (T/R symbols).The symbol pair also stripped from nibble presented Reconciliation layer.
10BASE-T Operation
10BASE-T transceiver IEEE 802.3u compliant. When NetPHY-1 device operating 10BASE-T mode, coding scheme Manchester. Data processed transmit presented interface nibble format, converted serial stream, then Manchester encoded. When receiving, Manchester encoded stream decoded converted into nibble format presentation interface. Collision Detection Half Duplex operation, collision detected when transmit receive channels active simultaneously. When collision been detected, will reported signal interface. Collision detection disabled Full Duplex operation. Carrier Sense Carrier Sense (CRS) asserted Half Duplex operation during transmission reception data. During Full Duplex mode, asser only during receive operations. Auto-Negotiation objective Auto-Negotiation provide means exchange information between segment linked devices automatically configure both devices take maximum advantage their abilities. important note that Auto-Negotiation does test link segment characteristics. Auto-Negotiation function provides means device advertise supported modes operation remote link partner, acknowledge receipt understanding common modes operation, reject un-shared modes operation. This allows devices both ends segment establish link best common mode operation. more than common mode exists between devices, mechanism provided allow devices resolve single mode operation using predetermined priority resolution function. Auto-Negotiation also provides parallel detection function devices that support Auto-Negotiation feature. During Parallel detection there exchange configuration information, instead, receive signal examined. discovered that signal matches technology that receiving device
Note: scrambler bypassed 100BASE-FX operation.
Code Group Alignment Code Group Alignment block receives unaligned data from descrambler converts into code group data. Code Group Alignment occurs after detected, subsequent data aligned fixed boundary.
Am79C873
supports, connection will automatically established using that technology. This allows devices that support Auto-Negotiation support common mode operation establish link. Serial Management serial management interface consists data interface, basic register set, serial management interface register set. Through this interface possible control configure multiple devices, status error information, determine type capabilities attached device(s). NetPHY-1 devices management functions correspond specification IEEE 802.3u-1995 (Clause registers through with vendor-specific registers 16,17, read/write operation, management data frame 64-bits long starts with contiguous logic bits (preamble) synchronization clock cycles MDC. Start Frame Delimiter (SFD) indicated <01> pattern followed operation code (OP):<10> indicates Read operation <01> indicates Write operation. read operation, 2-bit turnaround (TA) filing between Register Address field Data field provided MDIO avoid contention. Following turnaround time, 16-bit data read from written onto management registers. Serial Management Interface serial control interface uses simple two-wired serial interface obtain control status physical layer through interface. serial control interface consists Management Data Clock (MDC), Management Data Input/Output (MDI/O) signals. MDIO bidirectional shared devices.
MDIO Read "1"s Idle Preamble Data Read Idle
Code Write
Address
Register Address
Turn Around
22164A-7
Figure Management Interface Read Frame Structure
MDIO Write "1"s Idle Preamble Code
Address
Register Address Write
Turn Around
Data
Idle
22164A-8
Figure Management Interface Write Frame Structure
Am79C873
Register Description
Register Address Others Register Name BMCR BMSR PHYIDR1 PHYIDR2 ANAR ANLPAR ANER DSCR DSCSR 10BTCSR Reserved Basic Mode Control Register Basic Mode Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Specified Configuration Register Specified Configuration/Status Register 10BASE-T Configuration/Status Register Reserved Future Use-Do Read/Write These Registers Description
Default register description that follows, default column takes form: <Reset Value>, <Access Type> <Attribute(s)> Where <Reset Value>:
(Pin No.) logic logic zero default value Value latched from number reset
<Access Type>: Read only Read/Write <Attribute (s)>: Self clearing Value permanently Latching Latching high
Am79C873
Basic Mode Control Register (BMCR) Register
Name Default Reset: 1=Software reset 0=Normal operation 0.15 Reset RW/SC When this configures status control registers their default states. This will return value until reset process complete. Description
Loopback: Loopback control register 1=Loopback enabled 0.14 Loopback 0=Normal operation When 100M operation selected, setting this will cause descrambler lose synchronization. 720ms "dead time" will occur before valid data appears receive outputs.
Speed Select: 1=100 Mbps 0=10 Mbps 0.13 Speed Selection Link speed selected either this Auto-Negotiation this register set. When Auto-Negotiation enabled, this will return Auto-Negotiation link speed.
Auto-Negotiation Enable: Auto-Negotiation enabled: 0.12 Auto-Negotiation Enable Auto-Negotiation disabled: When auto-Negotiation enabled bits will contain AutoNegotiation results. When Auto-Negotiation disabled bits will determine duplex mode link speed.
Power Down: 1=Power Down 0.11 Power Down 0=Normal Operation Setting this will power down NetPHY-1 device with exception crystal oscillator circuit.
Isolate: Isolate Normal Operation (PHYAD= 0.10 Isolate 00000), When this data path will isolated from interface. TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], will placed high impedance state. management interface effected this bit. When Address 00000 isolate will upon power-up/reset.
Am79C873
Basic Mode Control Register (BMCR) Register (Continued)
Name Default Restart Auto-Negotiation: Restart Auto-Negotiation. Normal Operation Restart AutoNegotiation RW/SC When this Auto-Negotiation process re-initiated. When Auto-Negotiation disabled (bit this register cleared), this function should cleared. This self-clearing will return value until Auto-Negotiation initiated. operation AutoNegotiation process will affected management entity that clears this bit. Duplex Mode: Full Duplex operation. Duplex Mode Normal operation Auto-Negotiation disabled, setting this will cause NetPHY-1 device operate Full Duplex mode. When Auto-Negotiation enabled, this reflects duplex selected Auto-Negotiation. Collision Test: Collision Test enabled. Collision Test Normal Operation When set, this will cause signal asserted response assertion TX_EN. Reserved Reserved: Write ignore read. Description
Am79C873
Basic Mode Status Register (BMSR) Register
Name Default 100BASE-T4 Capable: 1.15 100BASE-T4 0,RO/P 1=NetPHY-1 device able perform 100BASE-T4 mode. 0=NetPHY-1 device able perform 100BASE-T4 mode. 100BASE-TX Full Duplex Capable: 1.14 100BASE-TX Full Duplex 1,RO/P 1=NetPHY-1 device able perform 100BASE-TX Full Duplex mode. 0=NetPHY-1 device able perform 100BASE-TX Full Duplex mode. 100BASE-TX Half Duplex Capable: 1.13 100BASE-TX Half Duplex 1,RO/P 1=NetPHY-1 device able perform 100BASE-TX Half Duplex mode. 0=NetPHY-1 device able perform 100BASE-TX Half Duplex mode. 10BASE-T Full Duplex Capable: 1,RO/P 1=NetPHY-1 device able perform 10BASE-T Full Duplex mode. 0=NetPHY-1 device able perform 10BASE-T Full Duplex mode. 10BASE-T Half Duplex Capable: 1,RO/P 1=NetPHY-1 device able perform 10BASE-T Half Duplex mode. 0=NetPHY-1 device able perform 10BASE-T Half Duplex mode. 0,RO Reserved: Write ignore read. Frame Preamble Suppression: Preamble Suppression 0,RO 1=PHY will accept management frames with preamble suppressed. 0=PHY will accept management frames with preamble suppressed. Auto-Negotiation Complete Auto-Negotiation Complete: 0,RO 1=Auto-Negotiation process completed. 0=Auto-Negotiation process completed. Remote Fault: Remote Fault RO/LH Remote fault condition detected (cleared read chip reset). Fault criteria detection method NetPHY-1 device implementation specific. This will after ANLPAR (bit register address set. remote fault condition detected. Auto-Negotiation Ability Auto Configuration Ability: 1,RO/P 1=NetPHY-1 device able perform Auto-Negotiation. 0=NetPHY-1 device able perform Auto-Negotiation. Link Status: 1=Valid link established (for either Mbps Mbps operation). 0=Link established. Link Status 0,RO/LL link status implemented with latching function, that occurrence link failure condition causes Link Status cleared remain cleared until read management interface. Description
1.12
10BASE-T Full Duplex
1.11
10BASE-T Half Duplex
1.10-1.7
Reserved
Am79C873
Basic Mode Status Register (BMSR) Register
Name Default Description Jabber Detect: 1=Jabber condition detected. Jabber Detect RO/LH 0=No jabber condition detected. This implemented with latching function. Once Jabber conditions detected this will remain until read operation completed through management interface NetPHY-1 device reset. This works only Mbps mode. Extended Capability: Extended Capability 1,RO/P 1=Extended register capable. 0=Basic register capable only.
Identifier Register (PHYIDR1) Register
Identifier Registers work together single identifier NetPHY-1 device. Identifier consists concatenation Organizationally
Name Default
Unique Identifier (OUI), vendor's model number, model revision number. IEEE assigned 00606E.
Description Most Significant Bits:
2.15-2.0
OUI_MSB
<0181H>
This register stores bits (00606E) bits this register, respectively. most significant bits ignored (the IEEE standard refers these
Identifier Register (PHYIDR2) Register
3.15-3.10 Name OUI_LSB Default Least Significant Bits: <101110>,RO/P Bits (00606E) mapped bits this register, respectively. Vendor Model Number: 3.9-3.4 VNDR_MDL <000000>,RO/P bits vendor model number mapped bits (most significant Model Revision Number: 3.3-3.0 MDL_REV <0001>,RO/P Four bits vendor model revision number mapped bits (most significant Description
Am79C873
Auto-Negotiation Advertisement Register(ANAR) Register
This register contains advertised abilities NetPHY-1 device they will transmitted link partners during Auto-Negotiation.
Name Default Next Page Indication: 0=No next page available 4.15 0,RO/P 1=Next page available NetPHY-1 device does support next page function. This permanently Acknowledge: 1=Link partner ability data reception acknowledged. 0=Not acknowledged. 4.14 0,RO NetPHY-1 device's Auto-Negotiation state machine will automatically control this outgoing bursts appropriate time during Auto-Negotiation process. Software should attempt write this bit. Remote Fault: 4.13 1=Local Device senses fault condition. 0=No fault detected. 4.12-4.11 Reserved Reserved: Write ignore read. Flow Control Support: 4.10 1=Controller chip supports flow control ability. 0=Controller chip does support flow control ability. 100BASE-T4 Support: 1=100BASE-T4 supported local device. RO/P 0=100BASE-T4 supported. NetPHY-1 device does support 100BASE-T4 this permanently 100BASE-TX Full Duplex Support: TX_FDX 1=100BASE-TX Full Duplex supported local device. 0=100BASE-TX Full Duplex supported. 100BASE-TX Support: TX_HDX 1=100BASE-TX supported local device. 0=100BASE-TX supported. 10BASE-T Full Duplex Support: 10_FDX 1=10BASE-T Full Duplex supported local device. 0=10BASE-T Full Duplex supported. 10BASE-T Support: 10_HDX 1=10BASE-T supported local device. 0=10BASE-T supported. Protocol Selection Bits: 4.4-4.0 Selector <00001>, These bits contain binary encoded protocol selector supported this node. <00001> indicates that this device supports IEEE 802.3 CSMA/CD. Description
Am79C873
Auto-Negotiation Link Partner Ability Register (ANLPAR) Register
This register contains advertised abilities link partner they received during Auto-Negotiation.
Name Default Next Page Indication: 5.15 Link partner, next page available. Link partner, next page available. Acknowledge: 1=Link partner ability data reception acknowledged. 5.14 0=Not acknowledged. NetPHY-1 device's Auto-Negotiation state machine will automatically control this from incoming bursts. Software should attempt write this bit. Remote Fault: 5.13 1=Remote fault indicated link partner. 0=No remote fault indicated link partner. 5.12-5.10 Reserved Reserved: Write ignore read. 100BASE-T4 Support: 1=100BASE-T4 supported link partner. 0=100BASE-T4 supported link partner. 100BASE-TX Full Duplex Support: TX_FDX 1=100BASE-TX Full Duplex supported link partner. 100BASE-TX Full Duplex supported link partner. 100BASE-TX Support: TX_HDX 1=100BASE-TX Half Duplex supported link partner. 0=100BASE-TX Half Duplex supported link partne.r 10BASE-T Full Duplex Support: 10_FDX 1=10BASE-T Full Duplex supported link partner. 0=10BASE-T Full Duplex supported link partner. 10BASE-T Support: 10_HDX 1=10BASE-T Half Duplex supported link partner. 0=10BASE-T Half Duplex supported link partner. 5.4-5.0 Selector <00000>, Protocol Selection Bits: Link partners binary encoded protocol selector. Description
Am79C873
Auto-Negotiation Expansion Register (ANER) Register
6.15-6.5 Name Reserved Default Reserved: Write ignore read. Local Device Parallel Detection Fault: RO/LH PDF=1: fault detected parallel detection function. PDF=0: fault detected parallel detection function. Link Partner Next Page Able: LP_NP_ABLE LP_NP_ABLE=1: Link partner, next page available. LP_NP_ABLE=0: Link partner, next page. Local Device Next Page Able: NP_ABLE 0,RO/P NP_ABLE=1: NetPHY-1 device, next page available. NP_ABLE=0: NetPHY-1 device, next page. NetPHY-1 device does support this function, this always Page Received: PAGE_RX RO/LH link code word page received. This will automatically cleared when register (Register read management. Link Partner Auto-Negotiation Able: LP_AN_ABLE LP_AN_ABLE=1 indicates that link partner supports AutoNegotiation. Description
Am79C873
Specified Configuration Register (DSCR) Register
Name Default Description Bypass 4B5B Encoding 5B4B Decoding: 16.15 BP_4B5B 1=4B5B encoder 5B4B decoder function bypassed. 0=Normal 4B5B 5B4B operation value latched into this power-up/reset. Bypass Scrambler/Descrambler Function: 16.14 BP_SCR 1=Scrambler descrambler function bypassed. 0=Normal scrambler descrambler operation. value input latched into this power-up/reset. Bypass Symbol Alignment Function: Receive functions (descrambler, symbol alignment symbol decoding functions) bypassed. Transmit functions (symbol encoder scrambler) bypassed. Normal operation. value BPALIGN input latched into this power-up/ reset. 16.12 Reserved Reserved: This must Repeater/Node Mode: 1=Repeater mode. 0=Node mode. 16.11 REPEATER Repeater mode, Carrier Sense (CRS) output from NetPHY-1 device will asserted only receive activity. NODE mode, mode configured Full Duplex operation, will asserted either receive transmit activity. value RPTR/NODE input latched into this power-up reset. 100BASE-TX Mode Control: 16.10 1=100BASE-TX operation. 0=100BASE-FX operation. 16.9 Cable Control: 1=The media cable, 0=STP. CLK25M Disable: 1=CLK25M output clock signal tri-stated. 16.8 CLK25MDIS 0=CLK25M enabled. This should disable output reduce ground bounce power consumption. applications requiring CLK25M output, this Force Good Link Mbps: 16.7 F_LINK_100 1=Normal Mbps operation. 0=Force Mbps good link status. This useful diagnostic purposes. Reserved: 16.6 Reserved This must written
16.13
BP_ALIGN
Am79C873
Specified Configuration Register (DSCR) Register
Name Default LINKLED Mode Select: Link output configured indicate link status only. 16.5 LINKLED_CTL Link output configured indicate traffic status: When link status will When chip transmitting receiving, flashes. FDXLED Mode Select: 16.4 FDXLED_MODE FDXLED output configured indicate polarity 10BASE-T mode. FDXLED output configured indicate Full DuplexFull Duplex mode status Mbps Mbps operation. Reset State Machine: 16.3 SMRST When this state internal machines will reset. This will clear after reset completed. Preamble Suppression Control: 16.2 MFPSC preamble suppression preamble suppression off. frame preamble suppression control bi.t Sleep Mode: 16.1 SLEEP Writing this will cause NetPHY-1 device enter Sleep mode power down circuits except oscillator clock generator circuit. exit Sleep mode, write this position. prior configuration will retained when sleep state terminated, state machine will reset. Remote Loopout Control: 16.0 RLOUT When this received data will loop transmit channel. This useful error rate testing. Description
Am79C873
Specified Configuration Status Register (DSCSR) Register
Name Default Description Full Duplex Operation: 17.15 100FDX After Auto-Negotiation completed, results will written this bit. this position indicates Full Duplex operation. software read bits [15:12] determine which mode selected after AutoNegotiation. This invalid when Auto-Negotiation disabled. Half Duplex Operation: 17.14 100HDX After Auto-Negotiation completed, results will written this bit. this position indicates Half Duplex operation. software read bits [15:12] determine which mode selected after AutoNegotiation. This invalid when Auto-Negotiation disabled. Full Duplex Operation: 17.13 10FDX After Auto-Negotiation completed, results will written this bit. this position indicates Full Duplex operation. software read bits [15:12] determine which mode selected after AutoNegotiation. This invalid when Auto-Negotiation disabled. Half Duplex Operation: 17.12 10HDX After Auto-Negotiation completed, results will written this bit. this position indicates Half Duplex operation. software read bits [15:12] determine which mode selected after AutoNegotiation. This invalid when Auto-Negotiation disabled. Reserved: Write ignore read. Address 4:0: values PHYAD[4:0] pins latched this register powerup/reset. first address transmitted received (bit station management entity connected multiple entities must know appropriate address each PHY. address <00000> will cause isolate BMCR (bit Register Address set.
17.1117.10
Reserved
17.8-17.4
PHYAD[4:0]
(PHYAD),
17.3-17.0
Name ANMB[3:0]
Default
Description Auto-Negotiation Monitor Bits: These bits debug only. Auto-Negotiation status will written these bits. IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detect signal_link_ready Parallel detect signal_link_ready fail Auto-Negotiation completed successfully
Am79C873
10BASE-T Configuration/Status (10BTCSRSCR) Register
18.15 Name Reserved Default Reserved: Write ignore read. Link Pulse Enable: 18.14 LP_EN 1=Transmission link pulses enabled. 0=Link pulses disabled, good link condition forced. This valid only Mbps operation. Heartbeat Enable: 1=Heartbeat function enabled. 18.13 Inverse 0=Heartbeat function disabled. When NetPHY-1 device configured Full Duplex operation, this will ignored (the collision/heartbeat function invalid Full Duplex mode). initial state this inverse value RPTR/NODE input power reset. Reserved: Write ignore read. Jabber Enable: Jabber function enabled. 18.11 JABEN Jabber function disabled. Enables disables Jabber function when NetPHY-1 device 10BASE-T Full Duplex 10BASE-T Transceiver Loop-back mode. 10BASE-T Serial Mode: 1=10BASE-T serial mode selected. 18.10 10BT_SER 0=10BASE-T nibble mode selected. value 10BTSER input latched into this power-up/ rese.t Serial mode supported Mbps operation. 18.9-18.1 Reserved Reserved: Write ignore read. Polarity Reversed: 18.0 POLR When this indicates that cable polarity reversed. This cleared 10BASE-T module automatically. Description
18.12
Reserved
Am79C873
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied. -0°C +70°C Supply Voltage with Respect Ground -4.75 +5.25 Input Voltage (VIN) -0.5 +0.5 Output Voltage (VOUT) .-0.5 +0.5
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free Air. .0°C +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
Power Consumption 100BASE-TX Full Duplex
(Measured using Unscrambled IDLE transmission looped back RXIN, includes external termination circuitry)
10BASE-T Full Duplex
(Measured using Maximum packet size, minimum I.P.G. transmission looped back RXIN, includes external termination circuitry)
Auto-Negotiation
(Measured during Parallel Detect until link established)
Idle
(Measured with link established)
Power Down Mode
(Measured while Register true)
ELECTRICAL CHARACTERISTICS (VCC VDC, ±5%, unless specified otherwise)
Symbol I100TX Parameter Supply Current 100BASE 100BASE-TX active Supply Current 10BASE-TX active I10TTP (Random data, Random Random size) Supply Current 10BASE-TX active I10TWC IPDM IRST (Max. Packet size, Min. Worst case data pattern) Supply Current Power Down Mode Supply Current during Auto-Negotiation Supply Current during Reset. Conditions Typical Unit
Inputs (TXD0-TXD3, TX_CLK, MDIO, TX_EN, TX_DV, TX_ER, TESTMODE, PHYAD0-4, OPMODE0-4, RPTR, BPALIGN, BP4B5B, BPSCR, 10BTSER, RESET) Input Voltage Input High Voltage Input Current Input High Current -400 -200
Am79C873
ELECTRICAL CHARACTERISTICS (VCC VDC, ±5%, unless specified otherwise) (Continued)
Symbol Parameter Conditions Typical Unit Outputs (RXD0-3, RX_EN, RX_DV, RX_ER, CRS, COL, MDIO) Output Voltage Output High Voltage
Non-MII Outputs (TXLED, RXLED, LINKLED, COLLED, FDXLED, RX_LOCK) VICM Output Voltage Output High Voltage RXI+/RXI- Input Common-Mode Voltage -0.1
Termination Across
Twisted Pair Transmitter
ITD100
100TX+± 100BASE-TX Mode Differential Output Current 10TX± 10BASE-T Differential Output Current
ITD10
PECL Receiver PECL Receiver Voltage High PECL Receiver Voltage PECL Signal Detect PECL Signal Detect Voltage High PECL Signal Detect Voltage PECL Transmitter PECL Output Voltage High PECL Output Voltage -1.05 -1.85 -0.88 -1.60 -1.16 -1.81 -0.90 -1.48 -1.16 -1.81 -0.90 -1.48
ELECTRICAL CHARACTERISTICS (Over full range operating conditions unless specified otherwise)
Symbol Transmitter tTR/F ttTDC tT/T XOST 100TXO+/- Differential Rise/Fall Time 100TXO+/- Differential Rise/Fall Time Mismatch 100TXO+/- Differential Output Duty Cycle Distortion 100TXO+/- Differential Output Peak-toPeak Jitter 100TXO+/- Differential Voltage Overshoot -0.5 -0.5 Parameter Conditions Typical Unit
Am79C873
ELECTRICAL CHARACTERISTICS (Over full range operating conditions unless specified otherwise) (Continued)
Symbol Parameter Conditions Typical Unit PECL Transmitter Transmit Interface) ptTR/F ptptTDC ptPPJ ptDDJ 100FXTD+/- Differential Rise/Fall Time 100FXTD+/- Differential Rise/Fall Time Mismatch 100FXTD+/- Differential Output Duty Cycle Distortion 100FXTD+/- Differential Output Peakto-Peak Jitter 100FXTD+/- Differential Output Data Dependent Jitter -0.5 -0.5
Clock Specifications XNTOL XBTOL tPWH
tPWL
Input Clock Frequency Tolerance Output Clock Frequency Tolerance Pulse Width High Pulse Width RX_CLK Pulse Width High RX_CLK Pulse Width
Frequency Frequency -100 +100
tRPWH tRPWL
Am79C873
100BASE-TX Transmit Timing
TX_CLK tTXs [0:3], TX_EN, TX_ER 100TX± tTXpd tTXr/f tTXh
22164A-9
Figure 100BASE-TX Transmit Timing Diagram
100BASE-TX Transmit Timing Parameters (Half Duplex)
Symbol tTXs tTXh tTXpd tTXr/f Parameter TXD[0:3], TX_EN, TX_ER Setup TX_CLK High TXD[0:3], TX_EN, TX_ER Hold From TX_CLK High TX_EN Sampled Asserted TX_EN Sampled De-asserted TX_EN Sampled Latency) 100TX Driver Rise/Fall Time 10%, Into Differential Conditions Typical (Note Unit
Note: Typical values design only; guaranteed subject production testing.
Am79C873
100BASE-TX Receive Timing
RX_CLK
tTXpd
[0:3], RX_DV, RX_ER
tRXS tRXh
RXI±
22164A-10
Figure 100BASE-TX Receive Timing Diagram
MII-100BASE-TX Receive Timing Parameter (Half Duplex)
Symbol tRXs tRXh tRXpd Parameter RXD[0:3), RX_DV, RX_ER Setup RX_CLK High RXD[0:3], RX_DV, RX_ER Hold From RX_CLK High RXD[0:3] Latency) Asserted RXD[0:3], RX_DV, RX_ER De-asserted RXD[0:3], RX_DV, RX_ER Asserted Quiet De-asserted De-asserted Conditions Typical (Note Unit
Note: Typical values design only; guaranteed subject production testing.
Am79C873
Auto-Negotiation Fast Link Pulse Timing
Clock Pulse Data Pulse Clock Pulse
Fast Link Pulses
Burst
Burst
10TX0±
22164A-11
Figure Auto-Negotiation Fast Link Pulse Timing Diagram
Auto-Negotiation Fast Link Pulse Timing Parameters
Symbol Parameter Clock/Data Pulse Width Clock Pulse Data Pulse Period Clock Pulse Clock Pulse Period Burst Width Burst Burst Period Clock/Data Pulses Burst DATA Conditions Typical 62.5 13.93 Unit
10BASE-T Nibble Transmit Timing
TX_CLK tTXS [0:3], TX_EN, TX_ER tTXpd 10TX± tTXh
22164A-12
Figure 10BASE-T Nibble Transmit Timing Diagram
MII-10BASE-T Nibble Transmit Timing Parameters
Symbol tTXs tTXh tTXpd Parameter TXD[0:3), TX_EN, TX_ER Setup TX_CLK High TXD[0:3], TX_EN, TX_ER Hold From TX_CLK High TX_EN Sampled Asserted TX_EN Sampled De-asserted TX_EN Sampled 10TXO Latency) Conditions Typical Unit
Am79C873
10BASE-T Receive Nibble Timing Diagram
RX_CLK tTXpd [0:3], RX_DV, RX_ER RXI± tRXS tRXh
22164A-13
Figure 10BASE-T Receive Nibble Timing Diagram
MII-10BASE-T Receive Nibble Timing Parameters
Symbol tRXs tRXh tRXpd Parameter RXD[0:3), RX_DV, RX_ER Setup RX_CLK High RXD[0:3], RX_DV, RX_ER Hold From RX_CLK High RXD[0:3] Latency) Asserted RXD[0:3], RX_DV, RX_ER De-asserted RXD[0:3], RX_DV, RX_ER Asserted Quiet De-asserted Conditions Typical Unit
Am79C873
10BASE-T (Heartbeat) Timing
TX_CLK TX_EN
22164A-14
Figure 10BASE-T (Heartbeat) Timing Diagram
10BASE-T (Heartbeat) Timing Parameters
Symbol Parameter (SQE) Delay After TX_EN (SQE) Pulse Duration Conditions 0.65 Typical Unit
10BASE-T Unjab Timing
TX_EN
22164A-15
Figure 10BASE-T Unjab Timing Diagram
10BASE-T Unjab Timing Parameters Symbol Parameter Maximum Transmit Time Unjab Time Conditions Typical 1500 Unit
Am79C873
MDIO Timing when OUTPUT
(Min) MDIO (Min)
22164A-16
Figure MDIO Timing when OUTPUT Timing Diagram
MDIO Timing when OUTPUT NetPHY-1 Device
MDIO
22164A-17
Figure MDIO Timing when OUTPUT NetPHY-1 Timing Diagram
Timing Parameters
Symbol Parameter MDIO Setup Before MDIO Hold After MDIO Output Delay Conditions When OUTPUT When OUTPUT When OUTPTU NetPHY-1 device Typical Unit
Am79C873
MAGNETICS SELECTION GUIDE
NetPHY-1 device requires ratio both receive transmit transformers. Refer Table transformer requirements. Transformers meeting these requirements available from variety magnetic manufacturers. Designers should test qualify magnetics before using them application. transformers listed Table electrical equivalent, pin-to-pin equivalent.
CRYSTAL SELECTION GUIDE
crystal used generate reference clock instead crystal oscillator. M-TRON crystal, part number 00301-00169, MP-1 Fund, 25.000000 MHz, equivalent used. crystal must fundamental type, parallel resonant. Connect shunt each crystal lead ground with 18pf capacitor (see Figure 16).
Table
Transformer Requirements
Part Number S558-5999-01 LF8200, LF8221 Single Port TG22-3506ND, TD223506G1, TG22-S010ND, OSC/XTLB OSCGND
Manufacturer Fuse Delta
AGND
HALO Electronics, Inc.
TG22-S012ND, TG110-S050N2 Quad Port TG110-6506NX, TG110S450NX, TG110-S452NX
AGND AGND
22164A-18
Nano Pulse Inc.
6181-37, 6120-30, 6120-37 6170-30 PE-68517, PE-68515, H1019, H1012 -Single Port
Figure
Crystal Circuit Diagram
Pulse Engineering
H1027, H1028 Dual Port PE-69037, H1001, H1036, H1044 Quad Port
Valor
ST6114, ST6118 20PMT04, 20PMT05
Am79C873
Table Part List Example Design
Item D1,D2,D3,D4 L1,L2 OSC1 Q2,Q1 R1,R2 R7,R8,R14,R15 R10,R11,R12,R13 R17,R16 R17,R18,R21 R19,R21 R22,R23,R26 R24,R25 Reference Number Part Description Capacitor, Decoupling, Capacitor, LED, General Purpose Connector, RJ45 Ferrite, Panasonic EXCCL4532U Oscillator, Crystal, MHz, Transistor, NNP, General Purpose, 2N2222 Resistor, 470, Resistor, 820, Resistor, Resistor, 510, Resistor, 6.01K, Resistor, 49.9, Resistor, 1.5K, Resistor, Resistor, 10K, NetPHY-1 device, PHY/Transceiver, Magnetics, Pulse Engineering, PE68515 Resistor Resistor Resistor 130, Resistor 300,
Am79C873
NetPHY-1 Example Schematic
RXER RXDV RXCLK RXD0 RXD1 RXD2 RXD3 1.5K MDIO TXCLK TXEN TXD0 TXD1 TXD2 TXD3 TXER TXLED RXLED LILED COLLED#
RXER
RXDV
RXD0
RXD1
RXD2
RXD3
DGND
DGND
RXCLK
TXCLK
TXEN
DGND
MDIO
COLLED#
RX_EN
TXER
RXLED
LINKLED
DVCC
TXD1
TXD3
TXD0
TXD2
TXLED
DVCC
SPST TMODE PHAD0 PHAD1 PHAD2 PHAD3 PHAD4 OPMD0 OPMD1 OPMD2 OPMD3 NODEB BPAGN BP45B BPSCR 10SER XTLB RXLOCK SPEED SIGOK FDXLED CLK25M
RESET# TESTMODE PHYAD0 PHYAD1 PHYAD2 DGND DVCC PHYAD3 PHYAD4 OPMODE0 OPMODE1 OPMODE2 OPMODE3 RPTR/NODE# BPALIGN BP4B5B BPSCR 10BTSER AGND AGND
FDXLED# DVCC CLK25M LINKSTS DGND RX_LOCK SPEED10
Am79C873 NetPHY-1
TRIDRV DVCC DGND DGND DGND BGRET BGRES AGND AVCC OSC/XTL# AGND
100TXO10TXO+ 10TXOFXRD+ FXSD+ FXRDFXSDAGND AGND AGND AGND AGND AGND AGND AVCC AVCC AVCC AVCC AVCC AVCC AVCC FXTD FXTD RXI+ RXI-
100TXO+
OSCI/X
AVCC
AVCC
DM9101F
FXRD+
FXSD+
FXRD-
FXSD-
FXTD-
TXOM
TXOM
TXOP
TXOP
RXIM
RXIP
FXSDVCC
FXTD+
49.9 49.9
C16,
Load these components OSC1+ R12. TP15 TP16
FXSD+ FXRD+
FXRDC26
FXSD D300
HFBR5103T
TP19
TP17 TP18
FXSD
FXTD+ FXTDVCC_T VCC_R FXSD FXRDFXRD+
Am79C873
NetPHY-1 Example Schematic (Continued)
TXLED RXLED LILED COLLED FDXLED CLK25M RXLOCK SPEED SIGOK TXD0 TXD3 Digital Power Ground Area Locate near U1's Ground Pins Physically place caps SOLDER SIDE. (SPEED) 100M TP10 TXD1 TXD2 RJ45 RXD1 RXD0 RXDV RXCLK RXER TXEN TXCLK TXER RXD3 RXD2 MDIO
BYPASS CAPACITOR
.1u/1KV 2N2222 (BGRET) (BGRES) 5.76K POWER/GROUND AREA traces power near this area TP11 TP13 RXIM RXIP TXOM TXOP TP12 TP14
POWER/GROUND AREA
PE68515 Place caps close possible pins. (SOLDER SIDE) .01u
DIP-8 PHAD0 PHAD1 PHAD2 PHAD3 PHAD4 TMODE XTLB
RP7_1K
.01u
(AGND) OSC1 Place caps close pins shown number each cap. Physically place SOLDER SIDE. #100 VCC_R VCC_T Advanced Micro Devices Title NetPHY-1 Evaluation Board Size Document Number netphy1_ev_0 Date: Monday, 1998 Sheet .01u DIP-8
10SER BPSCR BP45B BPAGN NODEB OPMD3 OPMD2 OPMD1 OPMD0
+VDD
Load
RP9_1K
Am79C873
PHYSICAL DIMENSIONS* PQR100
Detail Seating Plane
Detail
*For Reference Only
Symbol
Trademarks Copyright 1998 Advanced Micro Devices, Inc. rights reserved.
Notes:
Dimensions 3.30 Max. 0.10 Min. 2.85 ±0.13 0.31 +0.10 -0.05 0.15 +0.10 -0.05 14.00 ±0.13 20.00 ±0.13 0.65 ±0.15 18.85 NOM. 17.60 NOM. 23.60 NOM. 18.80 ±0.31 24.79 ±0.31 1.19 ±0.20 2.41 ±0.20 0.15 Max.
Dimensions Inches 0.130 Max. 0.004 Min. 0.1120.005 0.012 +0.004 -0.002 0.006 +0.004 -0.002 0.551 ±0.005 0.787 ±0.005 0.026 ±0.006 0.742 NOM. 0.693 NOM. 0.929 NOM. 0.740 ±0.012 0.976 ±0.012 0.047 ±0.008 0.095 ±0.008 0.004 Max.
Dimension include resin fins. Dimension Board surface mount pitch design reference only. dimensions based metric system.
AMD, logo, combinations thereof trademarks Advanced Micro Devices, Inc. NetPHY PCnet trademarks Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
Am79C873
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