Version Order Number: 100108-05 October 1999 Copyright 1999
|
|
|
Top Searches for this datasheet
MXT3010
Version
Order Number: 100108-05
October 1999 Copyright 1999 Maker Communications, Inc. rights reserved. Printed United States America. information this document believed correct, however, information change without notice. Maker Communications, Inc. disclaims responsibility consequences resulting from information contained this document. hardware, software, related documentation provided with RESTRICTED RIGHTS. Use, duplication, disclosure U.S. Government subject restrictions forth subparagraph (c)(1) (ii) Rights Technical Data Computer Program Product clause DFARS 252.227-7013 subparagraphs (c)(1) Commercial Computer SoftwareRestricted Rights 52.227-19, applicable. Contractor/manufacturer Maker Communications, Inc. Mount Wayte Avenue, Framingham, 01702 CellMaker BridgeMaker registered trademarks Maker Communications, Inc. AccessMaker, High-Intensity Communications Processor, High-Intensity Communications Processing, PortMaker, Octave, SimMaker trademarks Maker Communications, Inc. other trademarks owned their respective companies. This manual supercedes obsoletes following Maker Communications publications: 100108-03 MXT3010 Reference Manual, dated June 1999 100108-04 MXT3010 Reference Manual, dated October 1999
CONTENTS
Preface
Maker Products Using this manual xxiii Contacting Maker Support Services xxiv Changes Installed This Version Manual
Section
CHAPTER
Subsystems
Introduction
MXT3010 features MXT3010 subsystems What information this manual
CHAPTER
SWAN Processor
SWAN advantage
SWAN's instructions address spaces
MXT3010
Instruction execution Instruction space organization Instruction cache
SWAN processor instruction classes
Arithmetic Logic Unit (ALU) instructions Branch instructions
Registers
Flag registers
generation check circuit
CHAPTER
Cell Scheduling System
Cell Scheduling System works Data transmission servicing scheduling
Servicing Scheduling
Pacing transmission rate cells Programming Cell Scheduling System Guaranteeing availability location Connection table PUSHC/POPC instruction buffer POPC, PUSHC, POPF, PUSHF instruction operation
POPC PUSHC timing POPF PUSHF timing Connection table Scoreboard addressing
Initializing Scoreboard Selecting Scoreboard size Supporting multiple Scoreboard sections
CHAPTER
Fast Memory Interface
Loading Storing
SWAN processor accesses Fast Memory
Cell Scheduling System accesses Fast Memory SWAN executable fetches from Fast Memory Fast Memory configurations
Memory sizes supported selection configuration
MXT3010
Mode operation Mode operation contention avoidance
Fast Memory sequence diagrams
CHAPTER
Cell Buffer
Internal cell storage Cell Buffer Cell Buffer memory construction Cell Buffer access
CHAPTER
UTOPIA port
Features Operating modes UTOPIA cell formats
UTOPIA port interface overview
Receive cell flow Transmit cell flow
UTOPIA receiver counters UTOPIA transmitter counters TXBUSY counter TXFULL counter CRC10 generation checking support
Multi-PHY support Receive Header Reduction hardware UTOPIA port configuration summary UTOPIA port sequence diagrams
CHAPTER
Port1 Port2 Interfaces
Port interface overview Port command queues
Port1 Port2 command queues Testing Controller queues with bits
Port Controller features
Cyclical Redundancy Check generator Port1 Cyclical Redundancy Check operation acceleration Silent transfers
MXT3010
Post-increment option operations Data alignment Byte manipulations Port1 Post-DMA Operation Directives (PODs)
Burst non-burst operation (Port2) Port Operations
Port1 basic protocol Port1 control state machine Communication register transfers Port2 basic protocol Port2 control state machine Port2 non-burst-mode read transfers Port2 non-burst-mode write transfers
Additional Port1 Port2 Design Information
Arbitrating access Port1 Simplified Port2 interfaces driving, turnaround, parking Data Alignment
Transfer complete
Byte Count zero External cycle abort (P1ABORT_)
Endian-ness Port1 Port2 Reference Designs
P1MemMaker P2MemMaker
CHAPTER
Communications
COMMIN/COMMOUT register Interchip communications
Section
Register Instruction Reference
Registers Instructions
Instruction description notations
MXT3010
CHAPTER
Registers
Register types
Software registers Hardware registers Specifying registers SWAN instructions Initializing software hardware registers
R36-write R37-R39 R40-R41 R42-read R42-write R43-read R43-read R43-write R44-R47 R48-R51 R54-R55 R57-read R57-write
General Purpose 0000 General Purpose FFFF General Purpose FF00 General Purpose 0040 Bucket register General Purpose registers Host Communication registers External State Signals (ESS) register Mode Configuration register Fast Memory Swap register (R42w[8]=0) Special Features register (R42w[8]=1) UTOPIA Control FIFO register CRC32PRX CRC32PRY registers Local Address registers (rla) Alternate Byte Count/ID register Instruction Base Address register Programmable Interval Timer registers Fast Memory Data register Sparse Event/ICS register Sparse Event/ICS register (Set/Clear) Fast Memory Shadow register Branch register Cell Scheduling System (CSS) Configuration register R61-read Scheduled Address register UTOPIA Configuration register System register
CHAPTER
Arithmetic Logic Unit Instructions
Addressing modes
MXT3010
Triadic register Immediate
Overflow flag Instruction options
Modulo arithmetic Automatic memory updates branching
Registers Register Immediate Registers Register Immediate Compare Registers Compare Register Immediate Compare Registers with Previous Compare Register Immediate with Previous Find Last LIMD Load Immediate Maximum Registers MAXI Maximum Register Immediate Minimum Registers MINI Minimum Register Immediate Registers Register Immediate Shift Signed Amount SFTA Shift Right Arithmetic SFTAI Shift Right Arithmetic Immediate SFTC Shift Left Circular SFTCI Shift Circular Immediate SFTRI/SFTLI Shift Right Left Immediate Subtract Registers SUBI Subtract Register Immediate Registers XORI Register Immediate
ADDI ANDI CMPI CMPP CMPPI
CHAPTER
Branch Instructions
General Branch instruction information
viii
MXT3010
Introduction Target address Condition code (ESS Field) logical state identifier (S-Bit) Committed slot instructions Conditional operator (C-bit) Subroutine linking Counter system operation
Branch Fast Memory Shadow Register Branch Fast Memory Shadow Register Link Branch Immediate Branch Immediate Link Branch Register Branch Register Link
CHAPTER
Cell Scheduling Instructions
Cell Scheduling System target address POPC Service Schedule POPF Fast PUSHC Schedule PUSHF Push Fast
CHAPTER
Direct Memory Access Instructions
General instruction information
Introduction codes instructions increment (i-bit) Byte Count instruction field option (BC) Control instruction field option
DMA1R DMA1W DMA2R DMA2W
Direct Memory Operation Port1 Read Direct Memory Operation Port1 Write Direct Memory Operation Port2 Read Direct Memory Operation Port2 Write
MXT3010
CHAPTER
Load Store Fast Memory Instructions
General information Load Store Fast Memory instructions
Introduction Transfer size (the field) Fast Memory address (the fields) Address masking (the Z-bit) Destination register (the field) Linking (the bit)
Instructions accelerating operations
Alternate address (the field) Hardware register (reg field) Least significant bits (the lsbs field)
LMFM SHFM
Load Multiple from Fast Memory Store Halfword Fast Memory Store Register Halfword
CHAPTER
Load Store Internal Instructions
General information Load Store internal instructions
Introduction Register load address (rla field) index field (IDX)
Byte swap support
Swap field
Load Register Load Double Register Store Register Store Double Register
CHAPTER
Swan Instruction Reference Examples
Subtract examples Branch examples Load Store Fast Memory examples
MXT3010
Load Store Internal examples Logical examples Shift examples Miscellaneous examples
Section
Signal Descriptions Electrical Characteristics
Timing
CHAPTER
MXT3010EP timing general information
Definition switching levels Input clock details
MXT3010EP Fast Memory interface timing MXT3010EP UTOPIA interface timing MXT3010EP Port1 timing MXT3010EP Port2 timing MXT3010EP miscellaneous control signal timing
MXT3010EP Reset timing
MXT3010EP Fast Memory interface operation MXT3010EP JTAG operation
CHAPTER
Information
MXT3010EP pinout MXT3010EP signal descriptions MXT3010EP JTAG/PLL termination MXT3010EP listing
reference
CHAPTER
Electrical Parameters
MXT3010EP maximum ratings operating conditions
electrical characteristics electrical characteristics
MXT3010EP power sequencing
MXT3010
Overview Damage metal latch-up Overview decoupling General decoupling Reference clock jitter Circuit design goals
MXT3010EP considerations
CHAPTER
Mechanical Thermal Information
MXT3010EP mechanical/thermal information
APPENDIX APPENDIX
Acronyms Device Initialization
Initializing MXT3010EP Downloading firmware
system determines boot path application uses output pins code structured boot Limitations size boot code
Initializing Mode Configuration register
Restrictions starting addresses
APPENDIX
Quick Reference
Hardware register summary instruction field summary Shift amount summary Branch instruction field summary instruction field summary Instruction summary
MXT3010
List Figures
FIGURE MXT3010 surrounding system devices FIGURE SWAN processor address spaces access instructions FIGURE SWAN instruction space FIGURE Formation page offset instruction FIGURE Target address format Fast Memory FIGURE Pipeline feedback FIGURE Connection entries FIGURE Servicing scheduling FIGURE Scoreboard operation FIGURE Connection table address generation FIGURE Scoreboard address generation FIGURE Load Fast Memory instruction FIGURE Store Fast Memory instruction FIGURE Fast Memory SRAM options FIGURE Mode design example FIGURE Mode design example FIGURE Fast Memory read operations single bank FIGURE Fast Memory write operations single bank FIGURE Fast Memory reads writes back-to-back dual bank FIGURE Cell Buffer organization FIGURE Cell fields defined FIGURE Receive cell organization: 52-byte 56-byte cells FIGURE Gather method accesses FIGURE Cell Buffer access FIGURE UTOPIA port: 16-bit modes FIGURE Clock phases RX/TX Internal Clock FIGURE Clock phases RX/TX Internal Clock FIGURE UTOPIA 8-bit 16-bit cell formats FIGURE HEC-enabled 52-byte mode FIGURE HEC-disabled 52-byte mode FIGURE HEC-enabled 56-byte mode FIGURE HEC-disabled 56-byte mode FIGURE RXBUSY counter FIGURE RXFULL counter FIGURE TXBUSY counter
MXT3010 Reference Manual xiii
FIGURE TXFULL counter FIGURE Level configurations FIGURE Mixed Level Level configuration FIGURE UTOPIA Port receive timing single PHY, 8-bit mode FIGURE UTOPIA Port transmit timing single PHY, 8-bit mode FIGURE UTOPIA Port receive full timing single PHY, 8-bit mode FIGURE UTOPIA Port transmit full timing single PHY, 8-bit mode FIGURE command queues MXT3010EP FIGURE Diagram Port1 instruction bits FIGURE Port1 Read transfer with Wait state FIGURE Port1 Read transfer without Wait state FIGURE Port1 Write transfer with Wait state FIGURE Port1 Write transfer without Wait state FIGURE Cut-and-Paste Version Port1 Read FIGURE Cut-and-Paste Version Port1 Write FIGURE COMMIN write followed COMMOUT read FIGURE Diagram Port2 burst instruction bits FIGURE Diagram Port2 non-burst instruction bits FIGURE Port2 burst-mode Read transfer with Wait state FIGURE Port2 burst-mode Read transfer without Wait state FIGURE Port2 burst-mode write transfer with Wait state FIGURE Port2 burst-mode write transfer without Wait state FIGURE Port2 non-burst-mode Read transfer. FIGURE Port2 non-burst-mode Write transfer. FIGURE System example Port1 bus. FIGURE Read transfer with standard END_ signal FIGURE Read transfer with Early FIGURE Read transfer terminated P1ABORT_ FIGURE Most Significant Byte Lowest Address ("Big-endian") FIGURE Least Significant Byte Lowest Address ("Little-endian") FIGURE Hardware Byte-swapping Circuit FIGURE Word Access FIGURE 16-bit xxx0 Access FIGURE 16-bit xxx2 Access FIGURE Byte Access FIGURE Port1 MemMaker FPGA FIGURE Data Path Connections Shared Memory
MXT3010
FIGURE Data Path Connections Shared Memory MXT3010 FIGURE Port2 MemMaker FPGA FIGURE Data Path Connections Shared Memory FIGURE Data Path Connections Shared Memory MXT3010 FIGURE Timing CIN_BUSY COUT_RDY FIGURE Triadic register operation FIGURE Triadic instruction format FIGURE Immediate 10-bit instruction format FIGURE Immediate 6-bit instruction format FIGURE Branch instruction format (simplified) FIGURE Target address format Fast Memory FIGURE instruction format (simplified) FIGURE Control field format) FIGURE Z-bit usage example FIGURE Simplified Channel Descriptors FIGURE Channel Descriptor LMFM example FIGURE operation between FIGURE Gather method accesses FIGURE Switching level voltages FIGURE Input clock waveform (pin FIGURE Timing Fast Memory reads FIGURE Timing Fast Memory writes FIGURE half-speed RX_CLK/TX_CLK FIGURE quarter-speed RX_CLK/TX_CLK FIGURE UTOPIA port receive timing FIGURE UTOPIA port transmit timing FIGURE Port1 read timing FIGURE 100.Port1 write timing FIGURE 101.COMMIN register write, COMMOUT register read timing FIGURE 102.Port2 read timing FIGURE 103.Port2 write timing FIGURE 104.Timing CIN_BUSY COUT_RDY FIGURE 105.MXT3010EP reset timing FIGURE 106.Reset trailing edge timing FIGURE 107.Reset timing circuit FIGURE 108.MXT3010EP package/pin diagram FIGURE 109.Generating quiet
MXT3010
FIGURE 110.MXT3010EP decoupling capacitor location FIGURE 111.MXT3010EP package/pin diagram view FIGURE 112.MXT3010EP package/pin diagram side view
MXT3010
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table SWAN processor instruction classes Methods specifying branch target field Hardware registers requiring instruction delay Hardware registers requiring instruction delays Scoreboard sectioning control Connection table address bits Scoreboard address bits Comparison Mode Mode operation UTOPIA Configuration control Cell Buffer Cell field functions UTOPIA port data width selection UTOPIA port utilization 16-bit mode Cell length control UTOPIA port clock selection assignments multi-PHY operation Receive Header Reduction control Receive Header Reduction enable UTOPIA configuration information Characteristics Port1 Port2 Bits Controller status Example Controller status utilization Specification CRCX/CRCY instruction field option Valid invalid first, mid-cell, last transfers. Port instruction mapping Signals control Port1 transfers State table Port1 burst read state machine State table Port1 burst write state machine State table Port1 communication state machine Port2 burst instruction mapping Another view Port2 burst instruction mapping Port2 non-burst instruction mapping Another view Port2 non-burst instruction mapping Signals control Port2 transfers State table Port2 burst-mode read state machine State table Port2 burst write state machine State table Port2 non-burst-mode read state machine State table Port2 non-burst-mode write state machine Comparison Big-endian Little-endian Read Operations Accesses With Hardware Software Swaps, 32-bit Accesses With Hardware Software Swaps, 32-bit 16-bit
MXT3010
xvii
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Accesses With Hardware Software Swaps, 32-bit, 16-bit, 8-bit Definitions CIN_BUSY COUT_RDY ICSI pins ICSO pins Hardware registers Alphabetical list instructions Abbreviations used SWAN instructions Field abbreviations Hardware registers Signal utilization 1-PHY 2-PHY modes Modulo arithmetic options Branch Conditions instructions except Compare Min/Max instructions Branch Conditions Compare Min/Max instructions Methods specifying Branch target field External State Signals register (R42) bits S-bit Conditional Nullify operators Example conditional branch, condition satisfied Example conditional branch, condition Example unconditional branch Example conditional operator, conditional branch, condition satisfied Example conditional operator, conditional branch, condition satisfied Example Branch with link, return field codes instructions Timing chart accessing after field Control byte Load Fast Memory instruction format Store Fast Memory instruction format fields Z-bit Limits when linking Memory alignment requirements field field Restrictions access registers after LMFM Load internal instruction format Store internal instruction format field Byte-swapping Load instructions
xviii
MXT3010
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Byte-swapping Store instructions Input clock timing parameters Fast Memory timing Maker MXT3010EP UTOPIA timing Maker MXT3010EP Delay UTOPIA clocks relative MXT3010EP internal clock (CLK) Port1 timing table Port2 timing table Miscellaneous control signal timing MXT3010EP reset timing MXT3010EP RESET_ timing parameters MXT3010EP Port1 signal descriptions MXT3010EP Port2 signal descriptions UTOPIA port signal description MXT3010EP Fast Memory controller signal description MXT3010EP inter-chip communication registers signal description MXT3010EP miscellaneous clock, control, test signal descriptions Power ground descriptions MXT3010EP terminations MXT3010EP listing types Absolute maximum ratings (VSS Recommended operating conditions Electrical characteristics MXT3010EP package summary Selecting boot mode with ISCO_A ICSO_B User code set's four fields Bootstrap starting addresses Fast Memory mode Hardware registers MODx fields fields field field Shift amount chart SFT, SFTLI, SFTRI Shift amount chart SFTC SFTCI Shift amount chart SFTA Shift amount chart SFTAI field field (condition codes) S-bit field C-bit field I-bit field Control byte
MXT3010
Table
Instruction summary
MXT3010
Preface
Maker Products
Integrated Circuits Maker Communications delivers wide range Asolutions based MXT3010 cell processing engine MXT3020 circuit interface coprocessor. MXT3010 high-performance programmable cell processor engine specifically designed handle Acell manipulation transmission data rates Mb/s. MXT3020 Acircuit interface coprocessor MXT3010 cell processor. provides flexible interworking between Time Division Multiplexed (TDM) links Anetwork. MXT3010 MXT3020 complemented with series software applications that provide standard cell processing functionality. CellMaker®-155 CellMaker®-622 execute MXT3010 provide AAdaptation Layer (AAL5) Segmentation Reassembly (SAR) data rates Mb/s Mb/s, respectively. AccessMakerexecutes MXT3010 with four attached MXT3020 coprocessors.
Software Solutions
MXT3010
Version
provides cell processing functions both packet circuit interworking support multiple services concurrently including AAL1, AAL5, IMA, cell relay. Development Tools Maker Communications offers full suite development tools MXT3010 Cell Processor including Verilog models chips, WASM assembler, CellMaker Simulator (CSIM), Graphical CellMaker Simulator (GCSIM). CSIM Verilog-based simulator that provides tightly controlled fully observable environment execute debug both processor applications external host programs before running them target hardware. Maker also provides development boards. CSIM complemented with graphical post processor, GCSIM. MXT3016 32-bit, bus-based development board used test 622Mb/s applications. MXT3025 32bit, bus-based evaluation board used test OC-3 A(MXT3010) (MXT3020) applications.
xxii
Version
MXT3010
Using this manual
Using this manual
This section provides information conventions used within this manual. Typographical conventions This document uses following typographical conventions when describing features hardware software, usermachine interactions, variables. Commands appear mixed case, example Write_Channel_Map. Instruction mnemonics appear uppercase, example SUBBI instruction. User input appears bold monospace font. System output code examples appear monospace font. Variables, such user-definable names, appear italics. Instruction syntax instructions following syntax:
Required values appear between (parentheses). Optional values appear between [square brackets]. Optional descriptions appear lowercase. Literal descriptions appear UPPERCASE. Numbers denoted pound signs, string options from which only choose appear follows: [option1 option2 option3]
string options from which choose options appear follows: [option1] [option2] [option3] Bits which should written zeroes ignored reads appear Reserved
MXT3010
Version
xxiii
Terminology
Common acronyms abbreviations defined "Acronyms" page text. addition, this manual uses following term defined: Packets refer Local Area Network (LAN) information frames refer circuit information.
Contacting Maker Support Services
Maker Communications, Inc. following forums communicating ideas, questions, reporting problems: Sales customer support 508-628-0622 Product support Product inquires Facsimile support@maker.com info@maker.com 508-628-0256 www.maker.com
xxiv
Version
MXT3010
Changes Installed This Version Manual
Changes Installed This Version Manual
Change Bars Change bars provided indicate revisions made since previous publication manual.
Changes
Additional text been added "Register access rules" page paragraph before that, concerning between accesses registers. Cross references this warning have been added "Avoiding stale values" page 315, Load Register" page 321, "LDD Load Double Register" page 322, hardware register descriptions CHAPTER "Registers" page 189. Figure half-speed RX_CLK/TX_CLK," page Figure quarter-speed RX_CLK/ TX_CLK," page have been added show relationship UTOPIA clocks Figure "Receive cell organization: 52-byte 56-byte cells," page been modified correctly identify User Header bytes 56-byte cell format. description "LIMD Load Immediate" page been corrected indicate that immediate loaded into register register rsa. Table "Abbreviations used SWAN instructions," page been modified generalize definition usi. caption Figure page been corrected indicate that applies rather than typographic error ("3020" "3010") description out-of-bag floor life "MXT3010EP mechanical/thermal information" page been corrected. note that explains enabling/disabling "R54-R55 Programmable Interval Timer registers" page been changed.
MXT3010
Version
xxvi
Version
MXT3010
Section
Subsystems
This section composed eight chapters. provides overview MXT3010 Acell processing engine major functional subsystems.
MXT3010
Version
Version
MXT3010
CHAPTER
Introduction
MXT3010 Maker Communication's innovative, programmable Acell processing engine. MXT3010 built around Maker Communication's SWAN processor specifically designed high-speed Acell-processing applications. MXT3010 delivers throughput hard-wired speeds while maintaining benefits programmable approaches.
MXT3010
Version
Introduction
MXT3010 features
MXT3010-based systems insulated against changes Astandards because firmware modifications accommodate these changes. MXT3010 can: Scale across both performance application ranges. speeds ranging from Mb/s Mb/s. Handle AForum's Traffic Management Available Rate (ABR) service specification. Operate self-contained device managing concurrent Constant Rate (CBR), Variable Rate (VBR), connections, which frees host processing resources other tasks. Support rate-based Quantum Flow Control-based services with algorithmic implementation traffic shaping. Perform Alayer processing applications. MXT3010 high speed glueless interface Fast Memory (SRAM) storage instructions control structures, high-performance data interfaces, UTOPIA Level compliant interface. MXT3010 device, packaged 240-pin plastic quad flat package, available three speed grades, MHz, MHz. Full electrical mechanical details provided Section this manual. Figure shows MXT3010's internal subsystems their relationship devices found typical Aapplication.
Version
MXT3010
MXT3010 subsystems
FIGURE MXT3010 surrounding system devices
Application specific devices switch fabric
16-bit Multi-purpose (Port2) UTOPIA Port
32-bit
Main Memory Message buffers other information
Cell Buffer
High Performance (Port1)
Instruction Cache Fast Memory Host Processor Inter-chip Signalling
SWANProcessor
Fast Memory Controller Cell Scheduling System
Instructions data structures
MXT3010
MXT3010 subsystems
While SWAN processor heart MXT3010, device also uses series subsystems hardware agents created handle ATM-specific tasks. only these subsystems off-load many time-critical functions from SWAN processor, they also operate simultaneously with SWAN processor with each other, achieving high degree parallelism. subsystems include: Cell Scheduling System (CSS), hardware-based traffic-shaping subsystem that allows concurrent shaping dissimilar traffic types. Fast Memory port that provides latency access external Channel Descriptors, program code, traffic shaping memory, look tables used Available Cell Rate calculations. Cell Buffer that buffers cells both transmit receive directions.
MXT3010 Reference Manual Version
Introduction
UTOPIA port that provides connection Anetwork UTOPIA Level Multi-PHY interface. Port1 Port2 interfaces: Port1 high performance 32-bit host system interface Port2 general purpose 16-bit interface. subsystems work together Cell Scheduling System, Fast Memory port, Cell Buffer RAM, port interfaces utilize "dispatched" instructions that operate outside such that SWAN processor does stall while instruction being executed. only dispatched instructions interfere with SWAN, those associated with different subsystems interfere with each other, thus permitting simultaneous operation several dispatched instructions within independent subsystems. Although Cell Scheduling System relies SWAN processor direction required traffic patterns, manages traffic-shaping functions Atask. This function provides benefits algorithmic traffic shaping without decreasing overall performance.
What information this manual
This reference manual includes three sections: "Subsystems", "Register Instruction Reference," "Signal Descriptions Electrical Characteristics." Also included Appendix "Acronyms," Appendix "Device Initialization," Appendix "Quick Reference."
Version
MXT3010
What information this manual
"Subsystems" section includes information SWAN processor Cell Scheduling System Fast Memory port Cell Buffer UTOPIA port Port1 Port2 interfaces Interchip communications "Register Instruction Reference" section describes software hardware registers within SWAN processor, includes assignments functions hardware registers. "Register Instruction Reference" section also describes instructions functional groups provides alphabetical list instructions within each group. "Signal Descriptions Electrical Characteristics" section includes information Timing information listing Signal descriptions Electrical parameters details Thermal characteristics Mechanical information
MXT3010
Version
Introduction
Version
MXT3010
CHAPTER
SWAN Processor
Data Stream Cell Stream
Multi-purpose (Port2) Cell Buffer UTOPIA Port High Performance (Port1) Data Stream
Instruction Cache Control Memory SRAM
Inter-chip Signalling
SWANProcessor
Fast Memory Controller Cell Scheduling System
SWAN processor used network protocol processing applications. This chapter describes SWAN processor functions provides functional descriptions Arithmetic Logic Unit (ALU) Branch instructions SWAN processor.
MXT3010
Version
SWAN Processor
SWAN advantage
SWAN processor designed using Reduced Instruction Computer (RISC) Complex Instruction Computer (CISC) design techniques. combining high pipeline speeds RISC processor with instruction power CISC processor, SWAN processor attains level performance required process Mb/s Acell stream.
SWAN's instructions address spaces
addition utilizing advanced RISC/CISC design, SWAN processor employs highly efficient instructions address spaces optimized Aapplications. Instruction features instructions include memory update feature that write results operation back into memory location linked destination register. instructions include integral branching capability that perform branch within instruction cycle results operation meet selected criteria. instructions perform modulo arithmetic operations, selectable from bits (full width). Branch instructions test status more than dozen internal hardware points external pins. Branch instructions branching facilities programmed eliminate performance penalties normally exacted branch failures pipeline architectures. Cell Scheduling System provides powerful cell scheduling instructions.
Version
MXT3010
SWAN advantage
operations dispatched with single instruction, those Port1 include flexible capabilities. Load Store instructions include indexing byteswapping capability. Address spaces architecture SWAN processor, big-endian design, provides several independent address spaces. processor accesses each space with instructions specifically designed optimal performance. Figure shows these address spaces instructions which access them. circled numbers figure correspond explanatory paragraphs which follow.
FIGURE SWAN processor address spaces access instructions
Application specific devices switch fabric DMA2W Port2 DMA2R UTOPIA Port DMA1W Port1 DMA1R Main Memory Message buffers other information
Cell Buffer
Instruction Cache LMFM Host Processor Inter-chip Signalling
Instruction Fetches
SWANProcessor PUSH
Register file LD/ST
Fast Cntl SHFM
Fast Memory Instructions data structures
Cell Scheduling System Scoreboard
Instruction Space 128K Words SWAN processor executes instructions stored Fast Memory. Fast Memory instructions prefetched optionally cached direct mapped on-chip cache accelerate execution. 17-bit Program Counter (allowing 128K instructions) identifies current instruction.
MXT3010
Version
SWAN Processor
processor executes instructions four stage instruction pipeline. four stages Fetch, Decode, Execute Store utilize scoreboarding feedback ensure proper operation, minimize stalls, safeguard against illegal instruction sequences. Decode stage pipeline current Program Counter value.
Control Memory Space 1MByte (includes instruction space) Fast Memory also provides latency store control structures such descriptors applications objects descriptors, packet descriptors). SWAN register tightly coupled this control memory space through special purpose instructions Load Multiple from Fast Memory (LMFM) Store Halfword Fast Memory (SHFM). "Load Store Fast Memory Instructions" page 293. powerful extension operations, linking, dynamically associates Fast Memory with register set. These instructions virtually eliminate context switching overhead that limits performance off-the-shelf processors Asystems. "Automatic memory updates" page 228.
On-Chip Cell Buffer 1Kbytes Cell Buffer MXT3010 provides SWAN processor with latency access cells Adata flow control information from host. flexible Load/Store instruction paradigm provides efficient memory-register manipulation mechanism. addition byte swapping, extended load/store operations include indexing method facilitate control structure parsing. "Load Store Internal Instructions" page 313. This multi-port accessible UTOPIA, Port1 Port2 engine well
Version
MXT3010
SWAN advantage
SWAN. Since truly multi-ported, provides very latency access arbiters. "Direct Memory Access Instructions" page 283.
On-Chip Cell Scheduling System Scoreboard 2Kbytes Cell Scheduling System uses on-chip accelerate cell scheduling operations. When used CSS, this accessible SWAN processor through Load/Store instructions used general purpose memory. "The Cell Scheduling System" page
Instruction execution
SWAN instructions, except dispatched instructions, execute single clock cycle. Dispatched instructions include Load Multiple Fast Memory (LMFM), cell scheduling instructions (PUSHC, POPC), instructions (DMA1, DMA2), load store double instructions (LDD, STD). Dispatched instructions require more than cycle complete, their execution occurs outside such that processor accomplish other tasks while dispatched instructions execute. Since input clock doubled frequency on-chip PLL, SWAN processor executes instructions twice frequency input clock. Like other high performance RISC processors, SWAN utilizes multi-stage pipeline. Delayed branching techniques ensure that Branch instructions also operate effective rate instruction cycle preventing pipeline delays.
MXT3010
Version
SWAN Processor
Instruction space organization
SWAN supports instruction space 128K 32-bit instructions, which must 4-byte aligned. instruction space spans Segments instructions each. Figure shows SWAN instruction space.
FIGURE SWAN instruction space Segment Page Page Segment Page Page Segment Page Page Segment Page Page 120K Segment Page Page 124K Segment Page Page 128K Notes: numbers wrap every instructions Page size defined instruction cache size. Therefore, MXT3010 sixty-four pages.
Segments defined branching range instruction set. Since Branch instruction instruction address range, jump anywhere within segment. "Target field" page
Version
MXT3010
SWAN advantage
Instruction cache
internal Instruction Cache 2048 instructions. cache direct-mapped cache, with each 32-bit entry having independent 4-bit tag. There separate valid bits cache entries. device initialization time, cache tags written 0xF. After micro-boot routine downloads firmware, SWAN processor jumps specified starting address. address must onto cache 0xF, these fetches would cause incorrect cache hits. simplicity's sake, consider code space instructions executable space instructions with instructions inaccessible execution. Cache organization mapping line size MXT3010 cache (i.e. amount cache replaced cache miss) instruction. Each entry cache therefore single instruction. Each entry instruction cache 'tagged' with value that represents cache page. shown Figure page each instruction segment contains cache pages. (No-Cache) Instruction Base Address register (R53) disables cache. this (one), SWAN fetches instructions from Fast Memory, these instructions stored on-chip cache. Since Fast Memory interface runs processor speed, delivers instruction every other cycle. Therefore, while running Fast Memory, SWAN will stall, minimum, every other cycle. While clear (zero), cache enabled. When SWAN fetches instruction, cache entry page offset instruction compared with instruction address. Figure details formation page offset instruction tag.
MXT3010 Reference Manual Version
SWAN Processor
FIGURE Formation page offset instruction bits) Instruction bits)
Cache 2047 4-bit Page offset Program counter (17-bits) Segment Instruction offset
Note: Instruction Offset word offset, opposed byte offset. byte instruction address Fast Memory will ((Segment_ID 14)+ (Instruction Offset
instruction matches corresponding cache tag, cache been achieved cache returns instruction within single cycle. processor continues execution without stalling. However, does match, cache miss occurred instruction must fetched from Fast Memory. This will cause processor stall awaits instruction. Once Fast Memory returns instruction, stored cache updated. Because cache line size single instruction, only single instruction replaced cache cache miss. Subsequent cache misses replace other instructions cache. With empty cache, such when exiting bootstrap, every instruction must fetched from Fast Memory. Therefore, every other cycle will stall cache cold filled. firmware designer controls which segments cacheable. Instruction Base Address register (R53) controls cache typically modified firmware when code path jumps current segment. firmware must ensure that each cache value (0x0-0xE), only single
Version
MXT3010
SWAN advantage
cache page made cacheable. Otherwise, stale cache entries prevent proper operation. SWAN's bootstrap program preloads into cache entries initialization. recommended that cacheable code placed location with 0xF. Using Cache Code that always executed, referred 'fast path', should placed cacheable space, preferably within single cache page. Infrequently executed code (slow path) performance insensitive code (for example, initialization code) should located non-cacheable segments. Maker's development tools provide code location features. Many applications require more than instructions. this case, application located single cache page. entire page will mapped into cache. Obviously, this will provide optimal level performance. However, requirement, program easily jump segment using following instruction sequence:
LIMD new-segment offset_in_new_segment
Instruction prefetch SWAN architecture highly pipelined. hardware prefetch instructions from Fast Memory anticipation execution. These prefetches cached. However, changes program flow (branches) prevent instructions from being executed. This behavior expected does cause improper operation. Prefetches mentioned here alert user that fetches from Fast Memory correlate exactly sequence Program Counter.
MXT3010
Version
SWAN Processor
Observing cached program flow When processor executing cache, does need access Fast Memory. However, Fast Memory being used, MXT3010 presents program counter address Fast Memory address lines. This helps monitor code execution from cache.
SWAN processor instruction classes
SWAN processor includes powerful 32-bit instructions functional areas classes. Descriptions each class instruction divided into sections which describes subsystem that uses that instruction which describes utilization format each instruction. These descriptions appear chapters listed Table
TABLE SWAN processor instruction classes Subsystem Description Instruction Description "The SWAN Processor" (this chapter) "The SWAN Processor" (this chapter) "The Cell Scheduling System" page "The Port1 Port2 Interfaces" page "Arithmetic Logic Unit Instructions" page "Branch Instructions" page "Cell Scheduling Instructions" page "Direct Memory Access Instructions" page "Load Store Internal Instructions" page "Load Store Fast Memory Instructions" page
Functional Area Arithmetic Logic Unit Instructions Branch Instructions Cell Scheduling Instructions Direct Memory Access Instructions
Load Store Inter- "The Cell Buffer RAM" page Instructions Load Store Fast Memory Instructions "The Fast Memory Interface" page
Version
MXT3010
SWAN processor instruction classes
Arithmetic Logic Unit (ALU) instructions
Basic instructions SWAN processor instruction includes complete suite arithmetic, logical, shifting instructions implemented high performance ALU. format typical instruction shown below: (rsa, rsb) [MODx][abc][AE][UM] example shown, input data stored rsb, while result delivered register notations shown square brackets represent special features that optimize SWAN Acell processing. These features, referred instruction field options (IFOs), include modulo field (MODx), branch condition field (abc), always execute (AE), update memory feature (UM). more information "Arithmetic Logic Unit Instructions" page 223.
Branch instructions
SWAN processor includes basic branch control mechanisms: suite instructions that includes conditional branching capabilities. "Arithmetic Logic Unit Instructions" page 223. suite three basic branch instructions, each which available with return address linking version. Basic Branch instructions format typical Branch instruction (Branch Fast Memory) shown below: [ESS#/(0|1)[/C]][cso][N]
MXT3010
Version
SWAN Processor
Branch instructions allow programmer specify conditional branching decisions which will alter instruction execution sequence. branching decisions based state MXT3010 subsystems, indicated External State Signals (ESS) register. point tested specified field (ESS#). branch taken when point tested ESS# followed branch taken when point tested ESS# followed Branch instructions also used manipulate UTOPIA port's control counters counter system operation (cso) field. options optimize performance Branch instructions special circumstances. Descriptions these options appear "The Conditional operator (C-bit)" page 265. Complete information Branch instructions appears "Branch Instructions" page 261. Target address branch target address address which execution continues specified branch condition satisfied. full branch target address within Fast Memory formed from Segment Instruction Base Address register (R53) branch target field. Figure shows format target address.
FIGURE Target address format Fast Memory
Segment
Branch Target Field
Target field
branch target field 12-bit field that specifies absolute word address within current code segment (4096 words) which execution continue. three basic branch instructions differ only their method specifying branch target address field. Table summarizes methods used.
Version
MXT3010
Registers
TABLE Instruction
Methods specifying branch target field Method specifying branch target field bits [11:0] instruction bits [11:0] Fast Memory Shadow register (R58). (Note bits [11:0] Branch register (R59)
Branch Immediate (BI) Branch Fast Memory Shadow Register (BF) Branch Register (BR)
Note 1:The Fast Memory shadow register loaded with first halfword returned from memory during Fast Memory read operation that specifies Instruction Field Option.
complete description three basic branch instructions versions which include return address linking, "Branch Instructions" page 261.
Registers
Register types SWAN processor contains software-visible registers types, general-purpose control/status. general-purpose registers classified software registers because their usage content firmware dependent. registers that control functions provide status information classified hardware registers. SWAN processor general-purpose software registers, R0-R31, each 16-bits wide. SWAN also control status hardware registers, R32-R63. Pipeline feedback SWAN processor includes pipeline feedback features. feedback paths takes results from execution stage instruction pipeline delivers those results decode stage. second feedback path takes results from storage stage pipeline also delivers those results decode stage. Figure shows general concept:
MXT3010
Version
SWAN Processor
FIGURE Pipeline feedback
Fetch Stage Decode Stage Register File Storage Stage
Cache
Execution Stage Feedback
Other Logic
Execution Stage
Using execution stage feedback facility, instruction that modifies register followed immediately another instruction that accesses that same register. Using storage stage feedback facility, other instructions that modify register followed, after intervening instruction, instruction that accesses same register. This intervening instruction must hardware register. Register access rules perform load (LD, LDD) hardware register immediately between instruction that accesses register (R48R51, GA-GD) instruction that stores that register. number processor cycles which must intervene between instruction that alters register instruction which uses data altered register depends upon factors: instruction used When POPC issued, destination register, does contain requested data until eight cycles after POPC instruction decoded.
Version
MXT3010
Storage Stage Feedback
Registers
When Load (LD) instruction issued, destination register, does contain requested data until cycle after instruction decoded. When Load Double (LDD) instruction issued, second destination register, does contain requested data until cycles after instruction decoded. When Load Multiple Fast Memory (LMFM) instruction issued, destination registers updated after delays described "LMFM Load Multiple from Fast Memory" page 308. register accessed write software register, R0-R31, immediately followed instruction that uses data that register. Writes following hardware registers should followed least other instruction before information register used load, store, branch instructions. This restriction does apply their instructions.:
TABLE Location R44-R47 R57-write Hardware registers requiring instruction delay Name CRCX/CRCY (when used general purpose registers) Address register Address register Address register Address register Sparse Event/ICS register Fast Memory Shadow register Branch register Read/Write Set/Clear
MXT3010
Version
SWAN Processor
Writes following hardware registers should followed least other instructions before information register used:
TABLE Location R42-write R43-read Hardware registers requiring instruction delays Name Mode Configuration register Fast Memory Swap register Configuration register UTOPIA Configuration register System register Read/Write Set/Clear
Flag registers
Flag registers include Assigned Cell Flag register Overflow Flag register. These registers internal state bits; programs manipulate them directly, status flags modify program flow. Assigned Cell flag register Cell Scheduling System manipulates this register conclusion POPC operation. state Scoreboard targeted POPC operation copied into this register, which connected ESS4 tested Conditional Branch instructions. Subtract instructions that cause arithmetic overflow this register. Conditional Branch instructions test this register. complete description registers within SWAN processor, please "Registers" page 189.
Overflow flag register
more information
Version
MXT3010
generation check circuit
generation check circuit
MXT3010 provides generation checking methods:
generation checking provided UTOPIA port. "Receive cell flow" page applications which UTOPIA port, generation checking provided SWAN processor.
SWAN operation
Mode Configuration Register (R42) enables generation mode SWAN processor changes definition General Purpose register R33. normal operation, read/write register initialized 0xFFFF. HECenabled mode, redefined include output from generation circuitry therefore longer available simple read/write register constant value. Additionally, circuitry uses source data generation. This register read/write initialized 0x0000. When used purposes, continue function 16-bit read/write register. generation logic takes 16-bit data values produces 8-bit result. normal Acell processing, first data value would first bytes Acell header. second data value would second bytes Acell header, 8-bit result that second operation would inserted checked) current cell. circuitry initializes 8-bit seed value when data written R32. subsequent write completes input data circuit. After appropriate pipeline delays, resultant available right justified R33. following code segment illustrates this.
MXT3010
Version
SWAN Processor
LIMD #first_two_bytes
;load first half cell header ;this also resets SEED value
LIMD #second_two_bytes r33,
;load second half cell header ;execute stage ;store stage ;HEC processing ;HEC returned byte
result used directly transmitted cell, compared fifth byte received cell. instructions replaced with useful operations, result valid until fourth instruction after data written R33.
Version
MXT3010
CHAPTER
Cell Scheduling System
Data Stream Cell Stream
Multi-purpose (Port2) Cell Buffer UTOPIA Port High Performance (Port1) Data Stream
Instruction Cache Control Memory SRAM
Inter-chip Signalling
SWANProcessor
Fast Memory Controller Cell Scheduling System
Cell Scheduling System (CSS) traffic-shaping system that operates combination algorithmic- hardwareassisted functions. SWAN processor implements algorithmic-assisted portion scheduling function, cell scheduler performs hardware-assisted portion. implement-
MXT3010
Version
Cell Scheduling System
traffic shaping combination algorithmic- hardware-assisted functions, programmer complete control over traffic-shaping algorithms used. This chapter includes following information: Cell Scheduling System works Data transmission servicing scheduling Pacing transmission rate cells Programming Cell Scheduling System
Cell Scheduling System works
Cell Scheduling System works dividing Acell payload capacity transmission link into periodic containers cells. boundary periodic containers relative transmission convergence framing structure arbitrary. schedule cell usage within containers, MXT3010 creates Scoreboard (schedule) on-chip Connection table Fast Memory. Scoreboard contain eight sections, each which represents independent periodic container separate physical link priority level. Each location within periodic container corresponds single Scoreboard section single entry corresponding Connection table. Bits [13:12] Cell Scheduling System (CSS) Configuration register (R60) control number sections Scoreboard.
Version
MXT3010
Cell Scheduling System works
TABLE Bits 13:12
Scoreboard sectioning control Description Scoreboard Section Size 2,048 bits/entries section; sections 4,096 bits/entries section; sections 8,192 bits/entries section; sections 16,384 bits/entries section; section
Name
clarify discussion which follows, will assumed that Scoreboard contains only single section 16,384 bits/ entries. Scoreboard Connection table maintained SWAN processor working with specialized control circuit referred cell scheduler. cell scheduler modifies Scoreboard Connection table response servicing cell scheduling requests issued SWAN processor. Successive bits Scoreboard locations Connection table represent successive cell time slots transmission link. transmission link fully loaded with traffic, only some entries table have virtual circuit (VC) assigned them, indicated Scoreboard. Others labeled Available, indicated Scoreboard that zero. Figure shows example Connection table entries.
MXT3010
Version
Cell Scheduling System
FIGURE Connection entries
Connection Available Connection
Scoreboard Note Connection Table MXT3010 accommodates Scoreboards 2,048 through 16,384 bits Connection tables 2,048 through 16,384 16-bit halfwords.
During cell-scheduling process, status bits Scoreboard table summarize assigned available status each Connection table entry. Since Scoreboard represents status 16-bit entry Connection table, Scoreboard only 1/16th size Connection table. This compaction table status accelerates cell scheduler task searching available time slots. searching task further accelerated proprietary algorithm that guarantees identify available cell-time slot from anywhere within Scoreboard write Connection into that slot within processor cycles. High-speed searching especially important high-speed Alinks and/or those links that carry large number VCs, larger Connection tables used such systems.
Under ideal conditions (Fast Memory write pipe empty), this number could highly likely that write pipe entry will need displaced, raising number
Version
MXT3010
Data transmission servicing scheduling
Data transmission servicing scheduling
data transmission process consists major steps:
Servicing Connection table find entries representing assigned time slots that scheduled transmission established virtual circuit. Scheduling time slots existing virtual circuits establishing placing entries into Connection table locations that ensure proper service quality that
Servicing
SWAN processor services Connection table Scoreboard linearly services that have reserved various locations. SWAN processor determines which reserved time slot examining corresponding Connection table entry. SWAN processor reads Connection table entry executing POPC instruction. When POPC executes, cell scheduler returns addressed Connection table entry, copies value Scoreboard corresponding entry into Assigned Cell flag External State Signals register (R42, clears Scoreboard bit. processor maintains pointer into Connection table that represents current cell time slot. normal application, processor increments this pointer each time issues POPC instruction. Because Scoreboard Connection table represent periodic containers, SWAN processor responsible manipulating Connection table pointer modulo container size. multiple Scoreboards Connection tables used, SWAN responsible manipulating multiple Connection table pointers, each modulo respective container size.
MXT3010
Version
Cell Scheduling System
POPC instruction dispatched instruction operating outside such that SWAN processor does stall while cell scheduler executes POPC instruction. SWAN processor determine when POPC operation complete testing state External States Signals register (R42). ESS5 while cell scheduling operation progress. Alternatively, SWAN processor determine when POPC operation complete accessing destination register, although this method result processor stall. Register scoreboarding guarantees that processor will stall processor tries access destination register (rd) before cell scheduler written POPC result that register. However, instruction immediately following POPC register scoreboarded should access register When POPC instruction executed, Assigned Cell Flag indicates that selected time slot assigned Connection table entry, program read destination register POPC instruction obtain pointer Channel Descriptor associated with that time slot. Channel Descriptor contains application-defined state information needed process cell transmission event associated This data normally includes pointer data transmitted plus rate flow control information used scheduling future activity Assigned Cell Flag indicates that selected time slot unassigned, program must employ measures ensure that appropriate transmission rate maintained. "Pacing transmission rate cells" page
Scheduling
SWAN processor schedules when adding connection when servicing existing SWAN processor initiates scheduling operation executing PUSHC instruc32 Version MXT3010
Data transmission servicing scheduling
tion. PUSHC specifies 16-bit Connection target location within periodic container (Scoreboard). cell scheduler responds PUSHC scanning Scoreboard looking first available location after targeted location. available location found time last Scoreboard reached, cell scheduler loops back beginning Scoreboard continue search. When cell scheduler finds available location, sets Scoreboard writes Connection into corresponding Connection table entry. general, Connection identifies Fast Memory address Channel Descriptor Like POPC, PUSHC dispatched instruction operating outside such that SWAN processor does stall while cell scheduler executes PUSHC instruction. SWAN processor determines when PUSHC operation complete testing state External Signal Status register (R42). ESS5 while cell scheduling operation progress. When scheduling operation complete, processor reads scheduled address Cell Scheduling System Scheduled Address register (R61). This address differs from target address target address previously scheduled. Software cannot depend upon state register until PUSH/PUSHF instruction complete, register scoreboarding mechanism protects access this register during PUSH/PUSHF instruction operation. example, Figure shows SWAN processor servicing third location Connection table scheduling time slot Connection
MXT3010
Version
Cell Scheduling System
FIGURE Servicing scheduling
Connection Available Connection
Pointer representing current time slot
Scoreboard
Connection Connection Available
Ideal next transmission time slot First available transmission time slot nearest ideal time slot
Connection Table
example shown Figure requested location entries away from entry being serviced. However, that location assigned, nearest available location eight entries away. cell scheduler reserves available location reports location SWAN processor Cell Scheduling System Scheduled Address register (R61). This report-back feature important when creating controlled delay connections, enables program determine whether chosen location meets cell delay variation (CDV) requirements. requirements met, SWAN processor make another scheduling attempt otherwise reschedule reject connection. Calculating target time slots SWAN processor uses Channel Descriptor information calculate, algorithm, target time slot location next transmission serve variety methods employed.
Version
MXT3010
Data transmission servicing scheduling
Using GCRA calculate time slots
scheduling cells per-connection basis completely implementation dependent. example, implementation Generic Cell Rate Algorithm1 defined Increment Limit ((GCRA(I,L)) schedule cells Increment represents minimum inter-cell emission interval scheduling algorithm calculates target time slots various types connection follows: Available Rate (ABR) connection, inter-cell emission interval based feedback from network (flow control information Channel Descriptor) equal 1/ACR. implementation calculate Increment connections accordance with AForum's rate-based service specification, other methods used. Variable Rate (VBR) connection, target time slot calculation algorithm that allows burst transmission specified number cells (Maximum Burst Size) peak cell rate (Peak Cell Rate), exceed sustained cell rate (Sustained Cell Rate) over time. this case, Increment depends upon above three parameters. Unspecified Rate (UBR) connection, target time slot calculation based information Channel Descriptor without regard flow control, with effort reliable transport. connection, algorithm schedule required time slots Scoreboard when connection initially established. quantity spacing these time slots depends bandwidth Cell Delay Variation (CDV) requirements associated with connection. Therefore, when target time slot calculation created
Consult AForum's Traffic Management GCRA information.
MXT3010
Version
Cell Scheduling System
established connection, target time slot current time slot. Maintaining currently assigned time slots ensures consistent connection performance. connections, inter-cell emission interval time varying equal 1/Peak Cell Rate (PCR). with dynamically allocated time slots, such VCs, single time slot exist Connection Table/Scoreboard each that permanent reservation bandwidth, such VCs, have multiple time slots. information required calculate inter-cell emission intervals stored Fast Memory. Inter-cell emission intervals stored fractional integers support high connection rates. program store inter-cell interval fractional integer maintain remainder. SWAN processor then schedule cells using integer portion result, saving remainder next scheduling event that SWAN processor recover bandwidth lost cell scheduling collisions scheduling connections calculated Theoretical Arrival Time minus Limit. copy scheduled time must stored Channel Descriptor each scheduled this fashion proper operation GCRA.
Version
MXT3010
Pacing transmission rate cells
Pacing transmission rate cells
MXT3010 pace transmission rate cells either ways: Back pressure through UTOPIA port external clock Back pressure method When back pressure method used, Cell Scheduling System self-pacing system-no external clock required. Back pressure from transmission link through UTOPIA port limits rate which SWAN processor queue cells transmission. Therefore, processor must maintain continuously scheduled cell stream UTOPIA port. processor maintains this cell stream issuing idle unassigned cells when active scheduled. indicated "Servicing" page SWAN processor determines time slot assigned unassigned testing state Assigned Cell flag register following POPC instruction. Assigned Cell flag time slot unassigned unassigned cell must queued maintain necessary back pressure. queuing unassigned cells guarantees that inter-cell emission intervals transmission link remain synchronous with intervals programmed into schedule. External clock method When external clock method used, Cell Scheduling System longer self-pacing system, external clock required indicate cell transmission opportunities. there cells sent, cells presented PHY. Only user data cells presented UTOPIA Port transmission; idle cells sent.
Either Programmable Interval Timers (PIT0 PIT1) used. "R54-R55 Programmable Interval Timer registers" page 211.
MXT3010
Version
Cell Scheduling System
Advantages each method
back pressure method preferable when transmitting cells over Atransmission link, Atransmission link must kept full, transmission idle cells required. external clock method preferable when MXT3010 connected switch fabric, saves switch overhead dealing with idle cells.
Programming Cell Scheduling System
Cell Scheduling System example Figure shows SWAN processor maintaining pointer that represents present transmission time slot, such service address, this example halfword address third location Connection table.
FIGURE Scoreboard operation
Connection Available Connection
Pointer representing current time slot
Scoreboard before POPC/PUSHC Ideal next transmission time slot
Connection Connection Available
First available transmission time slot nearest ideal time slot
Connection Table
Scoreboard after POPC
Scoreboard after PUSHC
Version
MXT3010
Programming Cell Scheduling System
following instructions represent typical cell scheduling operation:
POPC UTOPIA Port Transmit queue full, SWAN processor executes POPC requesting that cell scheduler access Connection table entry that references (location 02), place that Connection into R10. cell scheduler copies Scoreboard associated with this Connection table entry into Assigned Cell Flag register, then clears Scoreboard (see "Scoreboard after POPC" Figure Because relevant Scoreboard time that POPC executed, Assigned Cell Flag register SWAN processor first tests completion POPC instruction (bit External Signals State (ESS) register) using Branch Immediate (BI) instruction. instruction specifies branch location $RDY point tested (ESS5) indicating scheduling operation longer progress. SWAN processor then tests Assigned Cell Flag register (bit External Signals State (ESS) register) using Branch Immediate (BI) instruction. instruction specifies branch location $SAC point tested (ESS4) Since time slot assigned, SWAN processor uses connection returned retrieve Fast Memory-based Channel Descriptor that reserved time slot. Load Multiple Fast Memory (LMFM) instruction used copy halfwords beginning Fast Memory Address specified into SWAN registers starting with register R16. ensure that changes Fast Memory locations automatically copied into entries stored R16-R31, Link (LNK) instruction field option invoked.
$RDY ESS5/0
$RDY
$SAC ESS4/1
$SAC
LMFM @R10/ 16HW
MXT3010
Version
Cell Scheduling System
SWAN processor uses information stored Channel Descriptor build retrieve cell application that uses dynamic scheduling part service routine, SWAN processor determines when service next connection. SWAN processor does this executing scheduling algorithm using parameters stored Channel Descriptor. Channel Descriptor contains parameters necessary determine connection scheduling rate. From information Channel Descriptor, SWAN processor determines next location within Connection table that should scheduled this Then SWAN processor places result into software register, example R22. SWAN processor activates connection executing PUSHC instruction. PUSHC instruction requests that cell scheduler find available time slot after target address specified R22, assign chosen time slot, write Connection from register into Connection table location corresponding that time slot.
PUSHC @R22
cell scheduler translates target address indicated into Scoreboard position searches Scoreboard, beginning that position. example shown Figure cell scheduler discovers that previous connection reserved target location. Therefore, cell scheduler examines Scoreboard until finds available location. This location found cell slots away from target location. cell scheduler reserves location present connection setting Scoreboard (see "Scoreboard after PUSHC" Figure writing Connection provided SWAN processor into selected location. When scheduling operation complete, cell scheduler reports scheduled address Cell Scheduling System Scheduled Address register (R61). SWAN processor read this register determine whether scheduled address meets requirements service being provided.
Version
MXT3010
Guaranteeing availability location Connection table
SWAN processor completes servicing connection incrementing service address contained modulo Connection table size. example, SWAN processor Immediate (ADDI) instruction 0x0002 address contained place result Connection table size 4096 entries, ADDI instruction include 4096 modulo value, limiting incrementation process lowest order twelve bits. This limitation causes incrementation process cycle through table locations.
ADDI 0x0002 MOD4096
Guaranteeing availability location Connection table
Scoreboard full while cell scheduler servicing adding connection, Cell Scheduling System returns error setting R60, Cell Scheduling System Configuration register. Constant checking this error slows down effective operating rate device. Rather than check error setting, either these methods ensure that location available:
connections activate inactive connections only when unassigned slots encountered. Maintain count active scoreboard, being careful adjust connections (such pre-allocated connections) that consume more than slot Scoreboard. admit connection that exceeds capacity Scoreboard.
MXT3010
Version
Cell Scheduling System
PUSHC/POPC instruction buffer
cell scheduler contains two-deep PUSHC/POPC instruction buffer. SWAN processor issue following cell scheduling instructions without entering stall condition: PUSHC PUSHF followed PUSHC PUSHF PUSHC PUSHF followed POPC POPF Execution cell scheduling instruction while buffer full results SWAN processor stall until first operation finishes.
POPC, PUSHC, POPF, PUSHF instruction operation
POPC PUSHC timing
POPC operation completes eight cycles from instruction decode loading register. worst case PUSHC time cycles from instruction decode Fast Memory write acknowledge from write buffer. four-stage write buffer full time PUSHC operation, this cycle count increases that buffer flushed entry, space write information provided.
POPF PUSHF timing
Both POPF (Pop Fast) PUSHF (Push Fast) instructions manipulate internal Scoreboards without accessing Connection table Fast Memory. eliminating unnecessary accesses Fast Memory, memory read/write latencies avoided.
Version MXT3010
POPC, PUSHC, POPF, PUSHF instruction operation
POPF, POPC, Cell Scheduling System translates target address into Scoreboard position. Cell Scheduling System copies state that into Assigned Cell flag (see below), clears location. However, POPF differs from POPC that Cell Scheduling System does access Fast Memory does provide Connection destination register. POPF operation completes five cycles from instruction decode. PUSHF, PUSHC, Cell Scheduling System translates target address into Scoreboard position. Cell Scheduling System searches first available location Scoreboard after that position sets that location reserve However, PUSHF differs from PUSHC that Cell Scheduling System does write Connection into Connection table location corresponding reserved Scoreboard bit. Rather, existing Connection that location scheduled. PUSHF operation completes cycles from instruction decode. This same speed optimum PUSHC that experiences write buffer delays. Unlike PUSHC instruction, PUSHF will never experience write buffer delays, does perform Fast Memory write. When servicing Scoreboard where time slot assignments rarely vary, combination POPF PUSHF used service schedule connections without overhead Fast Memory access.
Connection table Scoreboard addressing
Cell Scheduling System Configuration register specifies bits(18:15) Connection table address. Bits (14:1) Connection table address provided software bits(13:0) register specified POPC PUSHC instructions.
MXT3010
Version
Cell Scheduling System
FIGURE 10.Connection table address generation
TABLE Bits [14:1] [18:15]
Connection table address bits Source Fixed zero Bits [13:0] register POPC PUSHC instruction Bits [11:8] "R60 Cell Scheduling System (CSS) Configuration register" page
Connection table entry generates Scoreboard address corresponding specified Connection table entry follows:
FIGURE 11.Scoreboard address generation
Reserved TABLE Bits 18:11 10:1 Scoreboard address bits Source Reserved. Write zeros; ignore reads Bits [13:4] register POPC PUSHC instruction Fixed zero Note:Bits [3:0] register POPC PUSHC instruction select target within 16-bit Scoreboard entry. (While Cell Scheduling System searches Scoreboard basis 32-bit quantities, SWAN processor addresses Scoreboard 16-bit basis.)
Version
MXT3010
Initializing Scoreboard
Initializing Scoreboard
SWAN processor clears Scoreboard during system initialization routine. SWAN processor initializes Scoreboard executing POPF instructions locations Connection table. Once SWAN processor cleared Scoreboard, execute cell-scheduling instructions. those portions Scoreboard used cell scheduling, program must perform scheduling changes through PUSHC POPC instructions ensure that MXT3010's internal mechanisms remain consistent. However, SWAN processor read Connection table entries time with LMFM instruction, read Scoreboard using instruction, without affecting internal mechanisms.
Selecting Scoreboard size
Cell Scheduling System Configuration register includes desired Scoreboard size, rounded nearest power two. SWAN processor mark certain locations unavailable support Scoreboard sizes other than powers two. example, assume desired Schedule size 2304 bits. program execute series PUSHC operations select 4096 schedule mark bits 2304 4095 unavailable. From that point cell scheduler will reserve those locations response cell scheduling requests. program executes instructions Scoreboard, must return beginning Scoreboard when reaches location 2303. other words, once unwanted locations reserved, program must specify them target address operation. Also, program must calculate PUSHC target addresses modulo 2304 instead modulo 4096.
MXT3010
Version
Cell Scheduling System
Supporting multiple Scoreboard sections
indicated Table "Scoreboard sectioning control," page MXT3010 supports multiple Connection tables/ Scoreboard sections. device supports maximum Eight Connection tables/Scoreboard sections Four Connection tables/Scoreboard sections Connection tables/Scoreboard sections Connection table/Scoreboard section eight schedules used, bits [13:11] register POPC PUSHC instruction select schedule within block eight. four schedules used, bits [13:12] select schedule within block four, PUSHC/POPC register address bit(s) 13:12 13:11
Select(s) which schedule
Version
MXT3010
CHAPTER
Fast Memory Interface
Data Stream Cell Stream
Multi-purpose (Port2) Cell Buffer UTOPIA Port High Performance (Port1) Data Stream
Instruction Cache Control Memory SRAM
Inter-chip Signalling
SWANProcessor
Fast Memory Controller Cell Scheduling System
Fast Memory port provides SWAN processor Cell Scheduling System with latency access external Channel Descriptors, program code, traffic shaping memory, look tables used Available Rate calculations. Fast Mem-
MXT3010
Version
Fast Memory Interface
controller provides glue-less interface synchronous, flow-through, burst-mode cache RAMs. Samsung KM718B90 compatible parts examples suitable RAMs. This chapter describes: SWAN processor accesses Fast Memory Cell Scheduling System accesses Fast Memory SWAN executable fetches from Fast memory Fast Memory configuration
SWAN processor accesses Fast Memory
processor accesses Fast Memory with Load Multiple Fast Memory (LMFM) Store Halfword (SHFM) instructions. specialized Fast Memory access update protocol Fast Memory controller accelerates access update Fast Memory-based data structures.
Loading
software tables data structures stored Fast Memory accessed SWAN processor through LMFM (Load Multiple Fast Memory) instruction. simplified version LMFM instruction shown below.
FIGURE 12.Load Fast Memory instruction
Code
Version
MXT3010
SWAN processor accesses Fast Memory
LMFM @rsa/rsb [LNK] SWAN processor uses field specify number halfwords fetched fields specify Fast Memory byte address which transfer will begin. response LMFM instruction, Fast Memory interface controller will write halfwords returned from memory into SWAN's register file beginning with register continuing with rd+1, rd+2, etc. until designated number halfwords have been transferred. Thus, LMFM instruction allows SWAN processor transfer halfwords1 from Fast Memory into register file single instruction. Memory update protocol instruction field option specified, fast memory interface controller links loaded registers locations Fast Memory from which their contents were read. instructions which modify these registers force modifications written back Fast Memory specifying update memory (UM) option. Thus, function allows SWAN processor update data structure Fast Memory without executing dedicated Store instruction. addition, option causes first halfword read from memory read into Fast Memory Shadow Register (R58), where used BF/BFL instructions. Once linking relationship been LMFM instruction, subsequent LMFM instructions need specify linking option, links remain place. When desired that links changed, LMFM with linking option enabled change links. LMFM used change links does have specify data transfer (#HW zero).
Since number halfwords that transferred range from halfwords, there possible values field. Therefore, field bits wide.
MXT3010
Version
Fast Memory Interface
Additional information option memory updating, including restrictions, appears "Linking (the bit)" page following pages. Further information Further information about LMFM instruction provided "Load Store Fast Memory Instructions" page 293. Examples LMFM instruction usage provided that chapter "Swan Instruction Reference Examples" page 325.
Storing
Fast Memory writes accomplished utilizing memory update function described above utilizing Store Halfword Fast Memory (SHFM) instruction. simplified version SHFM instruction shown below.
FIGURE 13.Store Fast Memory instruction
Code
000000000
SHFM @rsa/rsb Execution SHFM instruction causes Fast Memory interface controller write halfword contained Fast Memory Data register (R56) into halfword addressed byte address contained registers rsb. more powerful store instruction, Store Register Halfword (SRH) also available. instruction especially useful accelerating operations. "Cyclical Redundancy Check operation
Version
MXT3010
Cell Scheduling System accesses Fast Memory
acceleration" page "Instructions accelerating operations" page 305. Further Information Further information about SHFM instructions provided "Load Store Fast Memory Instructions" page 293. Examples SHFM instruction usage provided that chapter "Swan Instruction Reference Examples" page 325.
Cell Scheduling System accesses Fast Memory
Cell Scheduling System maintains more Connection tables Fast Memory. Cell Scheduling System accesses Fast Memory with PUSHC POPC instructions issued SWAN processor. PUSHC instructions cause halfword write Connection table, POPC instructions cause halfword read Connection table. Cell Scheduling System operations lower priority than LMFM burst data reads. Cell Scheduling System operation progress when LMFM issued, Cell Scheduling System operation finishes LMFM serviced before next Cell Scheduling System operation proceeds.
SWAN executable fetches from Fast Memory
SWAN processor fetches instructions from Fast Memory using 32-bit word read accesses. These accesses higher priority than other access Fast Memory. LMFM Cell Scheduling System operation progress when SWAN processor makes Fast Memory read request, LMFM Cell Scheduling System operation finishes read request serviced before next LMFM Cell Scheduling System operation proceeds.
MXT3010
Version
Fast Memory Interface
Fast Memory configurations
This section describes these configuration features: Memory sizes supported selection configuration Mode operation chips with single multiple Chip Enable inputs Mode operation chips with multiple Chip Enable inputs only, allowing 512K banks contention avoidance
Memory sizes supported
Fast Memory interface supports memory sizes from Kbytes Mbyte configurations banks. configurations Fast Memory bits wide.
FIGURE 14.Fast Memory SRAM options
Control Address Data
512K Bytes, Banks with 128Kx16 RAMs) MXT3010
256K Bytes (512KB with 128Kx16RAMs)
128K Bytes
Version
MXT3010
Fast Memory configurations
selection configuration
MXT3010 supports following configurations:
Memory Size 128K Bytes 32Kx32 256K Bytes 64Kx32 512K Bytes 128Kx32 512K Bytes 128Kx32 Byte 256Kx32 32Kx32 64Kx16 64Kx16 128Kx16 128Kx16 Banks Mode
Mode operation
MXT3010 provides operation modes Fast Memory. Table compares modes, which selected modifying target Mode Configuration Register (R42):
TABLE Attribute Types access supported Maximum addressable memory Comparison Mode Mode operation Mode Byte halfword Kbytes Mode Byte halfword Multiple only Mbyte
Device Chip Enable configurations Single multiple
Mode MXT3010 drives address bits four independent byte enables permit direct addressing 32-bit words each memory banks. chip select signals output enable signals provide independent bank selection output drive enable signals memory banks. Address FADRS[18] internally generates select signal active bank. Physical memory appears contiguous 64Kx32 banks starting address space 0x00000, going 0x7FFFF.
MXT3010
Version
Fast Memory Interface
FIGURE 15.Mode design example
FADRS[17:2] FDAT[31:0] Control MXT3010 A[17:2] D[31:16] FCS0_ FOE0_ FWE0_ FWE1_ A15-A0 D15-D0 BW1_ BW0_ A15-A0 D15-D0 BW1_ BW0_ A[17:2] D[31:16] FCS1_ FOE1_ FWE0_ FWE1_ A15-A0 D15-D0 BW1_ BW0_ A15-A0 D15-D0 BW1_ BW0_
A[17:2] D[15:0] FCS0_ FOE0_ FWE2_ FWE3_ Bank
A[17:2] D[15:0] FCS1_ FOE1_ FWE2_ FWE3_ Bank
0x00000-0x3FFFF
0x40000-0x7FFFF
Mode operation
Mode MXT3010 drives address bits four independent byte enables directly address 256K 32-bit words each memory banks. output enable signals provide independent output drive enable signals memory banks. chip enable signals used; address FADRS[19] selects active bank. Physical memory appears contiguous 128Kx32 banks starting address space 0x00000 ending 0xFFFFF. banks always enabled since independent chip enable signals used. single bank configuration, Mode configure only Kbytes Fast Memory using 128Kx16 RAMs. this configuration, physical memory appears single 128Kx32 bank address space from 0x00000 0x7FFFF. Connection table executable code space Segment field Instruction Base Address register) only reside first 512K bytes Fast Memory.
Version
MXT3010
Fast Memory configurations
FIGURE 16.Mode design example
FADRS[19:2] FDAT[31:0] Control MXT3010 A[18:2] D[31:16] A[19] FOE0_ FWE0_ FWE1_ 128K A16-A0 D15-D0 BW1_ BW0_ 128K A16-A0 D15-D0 BW1_ BW0_ A[18:2] D[31:16] A[19] FOE1_ FWE0_ FWE1_ 128K A16-A0 D15-D0 BW1_ BW0_ 128K A16-A0 D15-D0 BW1_ BW0_
A[18:2] D[15:0] A[19] FOE0_ FWE2_ FWE3_
A[18:2] D[15:0] A[19] FOE1_ FWE2_ FWE3_
0x00000-0x7FFFF
0x80000-0xFFFFF
When operating Mode Chip Select pins used Fast Memory Address lines FCS1_ FADRS[19]. FCS0_ FADRS[18]
contention avoidance
timing output enable signals (FOE1_ FOE0_) skewed when addresses consecutive memory accesses cross bank boundaries prevent contention back-to-back read cycles. MXT3010 guarantees window between disabling bank enabling alternate bank. This allows both banks directly wired data without external buffers transceivers.
Please refer "Timing" Section further information.
MXT3010
Version
Fast Memory Interface
Fast Memory sequence diagrams
This section shows sequence diagrams following Fast Memory operations: Read operations, single bank (Figure page Write operations, single bank (Figure page Read write operations, back-to-back operation dual bank (Figure page Set-up times, propagation times, other timing information Fast Memory interface provided "Timing" page 343.
FIGURE 17.Fast Memory read operations single bank
FADRS[17:2] FDATout[31:0] high impedance high impedance
FDATin[31:0] FOE0_ FCS0_ FWE[3:0]_
Version
MXT3010
Fast Memory sequence diagrams
FIGURE 18.Fast Memory write operations single bank
FADRS[17:2] FDATout[31:0]
FDATin[31:0] FOE0_ FCS0_ FWE[3:0]_
FIGURE 19.Fast Memory reads writes back-to-back dual bank
Read Bank Read Bank Read Bank Read Bank Write Bank Read Bank Write Bank
FADRS[17:2]
FDATout[31:0] FDATin[31:0]
Driven Bank
FDATin[31:0]
Driven Bank
FOE0_ FOE1_ FCS0_ FCS1_ FWE[3:0]_
MXT3010
Version
Fast Memory Interface
Version
MXT3010
CHAPTER
Cell Buffer
Data Stream Cell Stream
Multi-purpose (Port2) Cell Buffer UTOPIA Port High Performance (Port1) Data Stream
Instruction Cache Control Memory SRAM
Inter-chip Signalling
SWANProcessor
Fast Memory Controller Cell Scheduling System
MXT3010's internal Cell Buffer buffers cells both transmit receive directions. unit access Cell Buffer through memory access protocols. This chapter describes Cell Buffer memory access protocols.
MXT3010
Version
Cell Buffer
Internal cell storage Cell Buffer
store cells, Cell Buffer configured into number byte blocks referred cell holders. During reception, cells written into cell holders they received from physical layer. During transmission, cells built cell holders before being transmitted physical layer. device initialization, Cell Buffer segmented into sections receive cell storage, transmit cell construction, general purpose scratch use. shown Table bits [6:1] UTOPIA Configuration register(R62) control segmentation Cell Buffer RAM.
TABLE Bits UTOPIA Configuration control Cell Buffer
Description Receive Cell Buffer Size Cell Buffer UTOPIA Port Receiver Reset Mode. outputs tristated. This includes RXDATA bidirectional signal), does include RXCLK. inputs pulled their inactive states MXT3010. Receiver Buffer Size Cell Buffer cells Receiver Buffer Size Cell Buffer cells -110 Receiver Buffer Size Cell Buffer cells Receiver Buffer Size Cell Buffer cells
Transmit Cell Buffer Size Cell Buffer UTOPIA Port Transmitter Reset Mode. outputs tristated except TXCLK. inputs pulled their inactive states MXT3010. Transmitter Buffer Size Cell Buffer cells Transmitter Buffer Size Cell Buffer cells -110 Transmitter Buffer Size Cell Buffer cells Transmitter Buffer Size Cell Buffer cells
Version
MXT3010
Internal cell storage Cell Buffer
minimum allocation receive cell holders two, maximum eight, receiver cell holder addressing begins location 0x0000. minimum allocation transmit cell holders two, maximum eight, transmit cell holder addressing begins location 0x0200. example, Figure shows Cell Buffer organization with eight receive cell holders, four transmit cell holders, remaining space available scratch space.
FIGURE 20.Cell Buffer organization 0x0000 0x0040 0x0080 0x00C0 0x0100 0x0140 0x0180 0x01C0 0x0200 0x0240 0x0280 0x02c0 0x0300 0x0340 0x0380 0x03C0 Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes
MXT3010
Version
Cell Buffer
Cell fields
Independent specific cell format used, certain fields provided) occupy certain positions. Figure shows these fields, Table summarizes their functions.
FIGURE 21.Cell fields defined
bytes bytes byte bytes
User Header AHeader
Present proprietary 56-byte cells only Present cells Optionally present cells Present cells
TABLE Cell field functions Field User Header AHeader Function User Header four-byte field that inserted before Aheader, adding four bytes front cell. AHeader four-byte field specified relevant Astandards consists GFC, VPI, VCI, subfields. generally present proprietary schemes. sub-fields interpreted UTOPIA Receive Header Reduction hardware MXT3010 form Channel Identifier cell. "Receive Header Reduction hardware" page Header Error Control (HEC) one-byte accumulated across AHeader. MXT3010 configured transmit receive cells with without HEC. 48-byte field that present every cell.
Cell formats
format information cell holders function selection 52-byte 56-byte cell operation "R42-write Mode Configuration register" page 201.
State Function Cell Length Control byte cells byte cells
Version
MXT3010
Internal cell storage Cell Buffer
Figure compares 52-byte 56-byte cell formats.
FIGURE 22.Receive cell organization: 52-byte 56-byte cells 52-byte cell Unused Receive Cell Status Word AHeader bytes AHeader bytes bytes bytes bytes bytes bytes 56-byte cell User Header bytes User Header bytes AHeader bytes AHeader bytes bytes bytes bytes bytes bytes
0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010
0x0034 0x0036 0x0038 0x003A 0x003C 0x003E
bytes bytes Unused Unused Unused Unused
bytes bytes Receive Cell Status Word Unused Unused Unused
Figure does show byte, because byte enabled) never written read from Cell Buffer RAM. Rather, generation/insertion transmission checking/removal reception performed UTOPIA port1. result verification available Receive Cell Status Word. Figure "Receive cell flow" page Receive Cell Status location While AHeader bytes bytes fixed with respect cell holder both 52-byte 56-byte mode, location Receive Cell Status Word does change.
MXT3010 also provides generation checking logic devices using UTOPIA port.
MXT3010
Version
Cell Buffer
52-byte mode, precedes AHeader field, while 56byte mode, four-byte User Header precedes AHeader, Receive Cell Status Word follows last byte PDU. placement Receive Cell Status Word beyond last byte 56-byte mode conflicts with concept Cell Buffer memory gathering described "Gather method accesses" page Memory gathering still valid means addressing unused Cell Buffer space, however presence Receive Cell Status Word within each receive cell holder must accommodated.
Cell Buffer memory construction
shown Figure "Cell Buffer organization," page Cell Buffer logically constructed sixteen 64-byte cell holders. shown Figure "Receive cell organization: 52-byte 56-byte cells," page cell occupies more than bytes cell holder. This leaves approximately eight bytes bottom each cell holder location. This space discontinuous therefore difficult use. that regain access this unused memory single linear space, Cell Buffer interface supports both linear access memory gathering protocol. Selecting access method Both controllers access Cell Buffer using either linear gather access methods. uses register Index field (IDX) (Load), (Load Double), (Store), (Store Double) instructions form address Cell Buffer RAM. "Register load address (rla field)" page "The index field (IDX)" page 315. controllers register DMA1 DMA2 instruction form address Cell Buffer RAM. "Direct Memory Access Instructions" page 283.
Version
MXT3010
Cell Buffer memory construction
Whether generated instruction controller, [10] local address selects access method Cell Buffer RAM.
Cell Buffer method selected Linear Gather
Linear method accesses
linear method accesses, Cell Buffer treated simple contiguous memory 1024 bytes length. Bits [9:1] target address select 16-bit halfword within this space. gather method accesses, last eight bytes each 64-byte section appear contiguous 128-byte block memory. first 16-bit halfword this block address 0x0400 gather address method. last 16-bit halfword address 0x047E. Thus, gather access recovers discontinuous regions Cell Buffer memory into continuous address space. This additional space, rather method making small pieces existing space. Figure illustrates this addressing method.
Gather method accesses
MXT3010
Version
Cell Buffer
FIGURE 23.Gather method accesses
0x0000
0x0400 0x0408 0x0410
Cell Store
0x0038 0x0040 0x047E 0x0480
Cell Store
0x0078 0x0080 0x03B8 0x03C0
Cell Store
0x03F8 0x0400
Please note restrictions gather access 56-byte mode (see "Receive Cell Status location" page 63). additional information, please "Cell Buffer accesses" page 317.
Version
MXT3010
Cell Buffer access
Cell Buffer access
MXT3010EP Cell Buffer five independent 16-bit ports, each capable moving data internal clock frequency. arrangement data ports shown Figure
FIGURE 24.Cell Buffer access
Port1 Read UTOPIA Port2 Read Read
Port Port addr write addr
Cell Buffer
Port1/CPU Write Port2/UTOPIA Write
SWAN Processor Load/Store Pipe
device, three read ports deliver data total rate second, write ports accept total second. Making optimum this high performance design requires some programming care, however. While Load Store instructions from SWAN processor guaranteed ordered with respect another, ordering guaranteed between Load/Store instructions operations Port1 Port Consider following example:
R0/R1 @R48 R2/R3 @R49 R4/R5 @R50 DMA1W rsa/rsb
MXT3010
Version
Cell Buffer
Port1 write operation guaranteed values R4/R5. This true because Store Double (STD) instructions retired Cell Buffer half rate they issued SWAN, SWAN does have dedicate write pipe into Cell Buffer RAM. guarantee correct behavior, program must following:
Guarantee that least write ports always available
ensure that from Port1 Port2 never fetch stale data. pipelining operation guarantees that will fetch data before flushed from SWAN Load/Store pipe into Cell Buffer RAM.
Follow stores dummy read prior issuing com-
mand. read ensures that preceding writes flushed pipe. Note that since Load Double (LD) offloaded from host, must followed instruction that uses destination load invoke hardware register scoreboarding mechanism.
successive writes ensure that preceding writes flushed
through pipe into Cell Buffer RAM.
Version
MXT3010
CHAPTER
UTOPIA port
Data Stream Cell Stream
Multi-purpose Cell Buffer UTOPIA Port High Performance Data Stream
Instruction Cache Control Memory SRAM
Inter-chip Signalling
SWANProcessor
Fast Memory Controller Cell Scheduling System
UTOPIA port implements AForum's UTOPIA Level Level protocol interfacing ALayer devices, such MXT3010, Layer devices, such SONET framers. UTOPIA port supports direct attachment single multiple logical devices. addition, UTOPIA port supports direct attachment Level 2-compliant
MXT3010
Version
UTOPIA port
Multi-PHY device with ports. compliance with AForum specification, UTOPIA connection operates Master device. This chapter includes: UTOPIA port interface overview Receive cell flow Transmit cell flow control byte special operations Multi-PHY support Receive Header Reduction hardware UTOPIA port configuration summary
UTOPIA port interface overview
Features
UTOPIA port interface includes following features: modes operation supported, 8-bit bi-directional mode 16-bit unidirectional mode (either transmit receive). UTOPIA port supports physical ports 8-bit bi-directional mode. UTOPIA port complies with AForum's Level Specification Multi-PHY Operations. Cell-level handshaking supported. wait states inserted, wait states expected. 56-byte cell mode over UTOPIA interface supported applications where field prepended Acell. insertion checking enabled.
Version MXT3010
UTOPIA port interface overview
Operating modes
UTOPIA port configured operate bi-directional mode with 8-bit Receive (Rx) data path 8-bit Transmit (Tx) data path, unidirectional mode either 16-bit Transmitter 16-bit Receiver. 16-bit mode supports Mb/s data rates. Selecting 8-bit 16-bit mode UTOPIA Configuration register (R62) controls operating mode.
TABLE UTOPIA port data width selection Description UTOPIA Port Data Width Bits Wide Bits Wide
16-bit transmit mode, TxData pins carry data [7:0]. RxData pins configured outputs carry data [15:8]. 16-bit receive mode, RxData pins carry data [7:0]. TxData pins configured inputs carry data [15:8].
TABLE UTOPIA port utilization 16-bit mode Mode 16-bit transmit 16-bit receive Data Pins Data [7:0] Data (inputs) [15:8] Data Pins Data (outputs) [15:8] Data [7:0]
Resetting transmitter receiver
Bits [6:4] UTOPIA Configuration register (R62) control Transmit Cell Buffer size Cell Buffer RAM, bits [3:1] control Receive Cell Buffer size. Definitions these bits appear Table "UTOPIA Configuration control Cell Buffer RAM," page While these bits primarily affect operation Cell Buffer RAM, buffer size selection cells places corresponding transmit receive UTOPIA interface reset mode. reset mode corresponding output signals placed into their inactive states.
MXT3010
Version
UTOPIA port
Selecting transmit receive mode
Transmit-only operation selected setting bits [3:1] UTOPIA Configuration register (R62) zeroes, thus placing UTOPIA port receiver reset mode. Receive-only operation selected setting bits [6:4] UTOPIA Configuration (R62) zeroes, thus placing UTOPIA port transmitter reset mode. Figure shows UTOPIA port using 8/8- 16-bit modes.
FIGURE 25.The UTOPIA port: 16-bit modes MXT3010 8-bit transmit 8-bit receive Control SONET Framer MXT3010 16-bit transmit Control MXT3010 16-bit receive Control
SONET Framer OC12
Selecting cell length operation
UTOPIA configuration operation uses R42, bits select operation cell length.
TABLE Cell length control Description Control generated (Tx), inserted (Tx), checked (Rx) omitted 52-byte cells 56-byte cells
Cell Length Control
UTOPIA speed select
MXT3010 operate each UTOPIA interface (transmit receive) either input clock frequency one-half that frequency. Since SWAN processor internal clock runs
Version
MXT3010
UTOPIA port interface overview
twice input clock frequency, these selections correspond one-half one-quarter internal clock frequency. MXT3010 generates UTOPIA output clock each transmit receive interfaces based setting clock selection UTOPIA Configuration register (R62). Alayer transfers should controlled from rising edge these clocks.
TABLE UTOPIA port clock selection Description UTOPIA Port operational/output clock selection TXCLK RXCLK operate internal clock frequency. TXCLK RXCLK operate internal clock frequency.
UTOPIA Port clock phases
Figure Figure show relationship between chip input clock, internal clock, TXCLK RXCLK operating internal clock frequency, respectively.
FIGURE 26.Clock phases RX/TX Internal Clock
INPUT INTERNAL
FIGURE 27.Clock phases RX/TX Internal Clock
INPUT INTERNAL
MXT3010
Version
UTOPIA port
UTOPIA cell formats
standard formats cells defined UTOPIA interfaces depending width data use. Additionally, proprietary schemes define arbitrary cell lengths formats long format commonly understood components bus. Figure shows standard cell formats UTOPIA interfaces.
FIGURE 28.UTOPIA 8-bit 16-bit cell formats 8-bit UTOPIA
16-bit UTOPIA
AHeader
AHeader
case cells received through 16-bit UTOPIA port, inserts additional byte after ensure that data structure presented UTOPIA port 16-bit aligned. After been checked UTOPIA port, both extra byte deleted before cell stored Cell Buffer RAM. case cells transmitted through 16-bit UTOPIA port, UTOPIA port inserts additional byte after ensure that data structure presented 16-bit aligned. transmits over SONET interface, discards extra byte. Cell format examples following figures show examples HEC-enabled 52-byte mode, HEC-disabled 52-byte mode, HEC-enabled 56-byte mode, HEC-disabled 56-byte mode.
Version
MXT3010
UTOPIA port interface overview
FIGURE 29.HEC-enabled 52-byte mode 52-byte cell 0x0000 Unused 0x0002 Receive Cell Status Word 0x0004 AHeader bytes 0x0006 AHeader bytes 0x0008 bytes 0x000A bytes 0x000C bytes 0x000E bytes 0x0010 bytes
8-bit UTOPIA
AHeader
16-bit UTOPIA
AHeader
0x0036 0x0038 0x003A 0x003C 0x003E
bytes Unused Unused Unused Unused
FIGURE 30.HEC-disabled 52-byte mode 52-byte cell 0x0000 Unused 0x0002 Receive Cell Status Word 0x0004 AHeader bytes 0x0006 AHeader bytes 0x0008 bytes 0x000A bytes 0x000C bytes 0x000E bytes 0x0010 bytes
8-bit UTOPIA
AHeader
16-bit UTOPIA
AHeader
0x0036 0x0038 0x003A 0x003C 0x003E
bytes Unused Unused Unused Unused Version
MXT3010
UTOPIA port
FIGURE 31.HEC-enabled 56-byte mode 56-byte cell User Header bytes User Header bytes AHeader bytes AHeader bytes bytes bytes bytes bytes bytes
0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010
8-bit UTOPIA
User Header
16-bit UTOPIA
User Header AHeader
AHeader
0x0036 0x0038 0x003A 0x003C 0x003E
bytes Receive Cell Status Word Unused Unused Unused
FIGURE 32.HEC-disabled 56-byte mode 56-byte cell User Header bytes User Header bytes AHeader bytes AHeader bytes bytes bytes bytes bytes bytes
0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010
8-bit UTOPIA
User Header
16-bit UTOPIA
User Header AHeader
AHeader
0x0036 0x0038 0x003A 0x003C 0x003E
bytes Receive Cell Status Word Unused Unused Unused
Version
MXT3010
Receive cell flow
Receive cell flow
UTOPIA Receiver transfers cells from external framing device into Cell Buffer RAM. cells received from physical layer device written into Cell Buffer RAM. insertion checking enabled Mode Configuration Register (R42), validity cell's byte marked Receive Cell Status field. insertion checking disabled, should ignored. Since Header Error Control (HEC) generation checking Layer function1, MXT3010 discards field before copying cell into Cell Buffer RAM. result, cell Cell Buffer consists contiguous bytes with existing between AHeader PDU. UTOPIA port writes receive cells into Cell Buffer beginning location 0x0000. UTOPIA Receiver writes successive cells into successive cell buffers Cell Buffer RAM. During device initialization, programmer specify many cells UTOPIA Receiver use. Receiver buffer size cells, example, Receiver loops around after sixth cell begins writing cells again location 0x0000 Cell Buffer RAM. Receiver buffer size eight cells, receiver loops around after eighth cell begins writing cells again location 0x0000 Cell Buffer RAM.
applications which UTOPIA port, generation checking provided SWAN processor. "HEC generation check circuit" page
MXT3010
Version
UTOPIA port
Receive Cell Status word stored Cell Buffer completion each receive cell. format Receive Cell Status word
Reserved Bits Name
Function
Copy
Addr
Address address from which this cell received. Copy copy Payload Type Indicator field from received cell header. CRC10 Error When (1), this indicates erroneous received. Otherwise, this zero (0). This should ignored when CRC10 use. Error When (1), this indicates erroneous received. Otherwise, this zero (0). This should ignored when use. These bits should ignored reads.
15:10 Reserved
location Receive Cell Status word Cell Buffer dependent configured cell length, bytes. more information, "Receive Cell Status location" page
UTOPIA receiver counters
UTOPIA Receiver contains counters, RXBUSY RXFULL, that track cells received from layer stored Cell Buffer RAM. Figure page Figure page show these counters used reception process. written description follows "The RXBUSY counter" page "The RXFULL counter" page
Version
MXT3010
Receive cell flow
FIGURE 33.The RXBUSY counter
Port1 Done Port2 Done
UTOPIA Cell Received
UTOPIA Cell Received
Decrement
Increment
Decrement
Increment
Receiver Busy Counter (Cells Cell Buffer awaiting servicing)
Receiver Full Counter (Cells Cell Buffer awaiting transfer)
RXCLAV RXENB_ Control Logic
ESS3 Attention ESS9 Busy
RXBUSY counter Function RXBUSY counter tracks arrival cells Cell Buffer awaiting servicing. device initialization process clears RXBUSY counter zero. UTOPIA receiver places last byte cell into receive section Cell Buffer RAM, increments RXBUSY counter. RXBUSY signal RXBUSY counter drives External State Signals (ESS) register (R42). SWAN processor tests ESS9 determine when more cells awaiting processing Cell Buffer RAM: ESS9 cells awaiting processing. ESS9 more cells awaiting processing. ESS9 signal conditionally branch receive cell service routine. example, Branch Immediate
Incrementing
Signals driven
MXT3010
Version
UTOPIA port
instruction ("BI Branch Immediate" page 272) specify conditional branch $RECV_CELL ESS9
$RECV_CELL ESS9/1
addition RXBUSY indication ESS9, receiver attention output RXBUSY counter drives ESS3. This signal indicates that receive buffer almost full: ESS3 Cell Buffer receive buffer contains less than cells. ESS3 Cell Buffer receive buffer contains more cells. Decrementing services newly arrived cell, decrements RXBUSY counter. decrements RXBUSY counter using Counter System Operation feature Branch instructions. example, Branch Immediate (BI) instruction specify unconditional branch $MAIN decrement RXBUSY counter using counter system operation option. "Counter system operation" page 269.
$MAIN DRXBUSY
Version
MXT3010
Receive cell flow
FIGURE 34.The RXFULL counter
Port1 Done Port2 Done
UTOPIA Cell Received
UTOPIA Cell Received
Decrement
Increment
Decrement
Increment
Receiver Busy Counter (Cells Cell Buffer awaiting servicing)
Receiver Full Counter (Cells Cell Buffer awaiting transfer)
RXCLAV Control Logic RXENB_
ESS3 Attention ESS9 Busy
RXFULL counter Function RXFULL counter indicates engines that cells Cell Buffer awaiting transfer. RXFULL counter also drives RXENB_ signal devices. device initialization process: Partitions Cell Buffer RAM. Establishes value number cells that stored Cell Buffer receive section. Clears RXFULL counter zero. Incrementing last byte cell placed into receive section Cell Buffer UTOPIA receiver, increments RXFULL counter. When MXT3010 receives cell, tests RXCLAV signal from device, which signals presence cell ready transfer. UTOPIA Port controller tests availability space Cell Buffer examining count kept
MXT3010
Version
UTOPIA port
RXFULL counter. MXT3010 accept cell cell send, UTOPIA port enables transfer asserting Alayer Receiver Enable (RXENB_) output. Decrementing Port 1/Port controllers decrement RXFULL counter completion data transfer operation command specifies UTOPIA post-DMA operative directive (POD) option memory write operation. further information other instruction options, "The Control instruction field option" page 287. Alternatively, decrement RXFULL counter after received cell been processed. with RXBUSY counter, decrements RXFULL counter specifying Branch instruction with option. example, Branch Immediate (BI) instruction specify unconditional branch $MAIN decrement RXFULL counter using DRXFULL counter system operation option.
$MAIN DRXFULL
Whether RXFULL decremented Branch instruction instruction, must decrement RXBUSY counter whenever finishes handling cell.
Transmit cell flow
UTOPIA transmitter transfers cells from Cell Buffer external framing device. cells transmitted must reside Cell Buffer before transmission. part transmit operation when generation enabled, UTOPIA transmitter inserts valid between last byte AHeader first byte SAR-PDU. 8-bit mode, only 8-bit inserted; 16-bit mode, 8-bit plus 8-bit stuffer inserted.
Version
MXT3010
Transmit cell flow
UTOPIA port transfers cells from Cell Buffer beginning location 0x0200. UTOPIA transmitter reads successive cells from Cell Buffer RAM. During device initialization, programmer specify many cells UTOPIA transmitter should use. transmitter buffer size cells, transmitter loops around after second cell begins reading cells again location 0x0200 Cell Buffer RAM. example, transmitter buffer size cells, transmitter loops around after sixth cell begins reading cells again location 0x0200 Cell Buffer RAM. Each transmit cell buffer associated with 16-bit control word. transmit control word written through FIFO-like internal memory mapped into R43. Writes push control words onto control byte FIFO when transmit operation executed. format transmit control word
Reserved Bits 15:7 Name TXPHY Reserved Function
TXPHY
Select address target multi-PHY system Generate insert CRC10 this cell Insert unassigned cell Programs should write zero these bits.
UTOPIA Control FIFO register recirculates output back input. applications that only transmit type cell, locations loaded initialization time need written again.
MXT3010
Version
UTOPIA port
UTOPIA transmitter counters
UTOPIA transmitter contains counters, TXBUSY TXFULL, that track cells transmit section Cell Buffer RAM. Figure page Figure page show these counters used transmission process. written description follows "The TXBUSY counter" page "The TXFULL counter" page
FIGURE 35.The TXBUSY counter
Port1 Done Port2 Done UTOPIA Cell begins
UTOPIA Cell begins
Decrement
Increment
Decrement
Increment
Transmitter Full Counter
Transmitter Busy Counter (Cells Cell Buffer loaded transfer)
TXCLAV TXENB_ Control Logic
ESS2 Attention ESS10 Full
TXBUSY counter
Function uses TXBUSY counter inform UTOPIA transmitter that cell Cell Buffer ready transmission. When TXBUSY counter non-zero, MXT3010 generates Alayer Transmit Enable (TXENB_) output signal that informs device that MXT3010 ready send cell.
Version
MXT3010
Transmit cell flow
Incrementing
Program execution accelerated controller increments TXBUSY counter after reads data. This technique requires command specify memory read operation with option (see "Post-DMA Operation Directives (PODs)" page 109). example:
DMA1R rsa/rsb, rla[BC/#, CRC{X POD, DMA2R rsa/rsb, rla[BC/#, POD,
Alternatively, increment TXBUSY counter specifying Branch instruction with counter system operation option. example:
$MAIN ITXBUSY
Decrementing
UTOP
Other recent searches
NSL-37V81 - NSL-37V81 NSL-37V81 Datasheet
NFW31S - NFW31S NFW31S Datasheet
NFE31P - NFE31P NFE31P Datasheet
FMM5508ZE - FMM5508ZE FMM5508ZE Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
