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bq2010

Gas Gauge IC

bq2010
Gas Gauge IC
Features
Conservative and repeatable measurement of available charge in rechargeable batteries Designed for battery pack integration
General Description
The bq2010 supports a simple single-line bidirectional serial link to an external processor (common ground). The bq2010 outputs battery information in response to external commands over the serial link. The bq2010 may operate directly from 3 or 4 cells. With the REF output and an external transistor, a simple, inexpensive regulator can be built to provide V CC across a greater number of cells. Internal registers include available charge, temperature, capacity, battery ID, battery status, and programming pin settings. To support subassembly testing, the outputs may also be controlled. The external processor may also overwrite some of the bq2010 gas gauge data registers.
120µA typical standby current Small size enables implementations in as little as 1 2 square inch of PCB
Integrate within a system or as a stand-alone device
Display capacity via singlewire serial communication port or direct drive of LEDs
Pin Connections
Pin Names
LCOM LED common output REF NC DQ EMPTY SB DISP SR VCC VSS Voltage reference output No connect Serial communications input / output Empty battery indicator output Battery sense input Display control input Sense resistor input 3.0-6.5V System ground SEG1 / PROG1 LED segment 1 / program 1 input SEG2 / PROG2 LED segment 2 / program 2 input SEG3 / PROG3 LED segment 3 / program 3 input SEG4 / PROG4 LED segment 4 / program 4 input SEG5 / PROG5 LED segment 5 / program 5 input SEG6 / PROG6 LED segment 6 / program 6 input
LCOM SEG1 / PROG1 SEG2 / PROG2 SEG3 / PROG3 SEG4 / PROG4 SEG5 / PROG5 SEG6 / PROG6 VSS
VCC REF NC DQ EMPTY SB DISP SR
16-Pin Narrow SOIC
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bq2010
Pin Descriptions
bq2010 Functional Description
General Operation
The bq2010 determines battery capacity by monitoring the amount of charge input to or removed from a rechargeable battery. The bq2010 measures discharge and charge currents, estimates self-discharge, monitors the battery for low-battery voltage thresholds, and compensates for temperature and charge / discharge rates. The charge measurement derives from monitoring the voltage across a small-value series sense resistor between the negative battery terminal and ground. The available battery charge is determined by monitoring this voltage over time and correcting the measurement for the environmental and operating conditions. Figure 1 shows a typical battery pack application of the bq2010 using the LED display capability as a chargestate indicator. The bq2010 can be configured to display capacity in either a relative or an absolute display mode. The relative display mode uses the last measured discharge capacity of the battery as the battery "full" reference. The absolute display mode uses the programmed full count (PFC) as the full reference, forcing each segment of the display to represent a fixed amount of charge. A push-button display feature is available for momentarily enabling the LED display. The bq2010 monitors the charge and discharge currents as a voltage across a sense resistor (see RS in Figure 1). A filter between the negative battery terminal and the SR pin may be required if the rate of change of the battery current is too great.
R1 bq2010 Gas Gauge IC
REF Q1 ZVNL110A
LCOM SEG1 / PROG1 SEG2 / PROG2 SEG3 / PROG3 SEG4 / PROG4 SEG5 / PROG5 SEG6 / PROG6
VCC SB
C1 0.1µF VCC
DISP SR
VSS EMPTY DQ
Charger Load
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Figure 1. Battery Pack Application Diagram-LED Display
bq2010
Voltage Thresholds
TMPGG (hex) 0x 1x 2x 3x 4x 5x
EMPTY Output
Layout Considerations
The bq2010 measures the voltage differential between the SR and VSS pins. VOS (the offset voltage at the SR pin) is greatly affected by PC board layout. For optimal results, the PC board layout should follow the strict rule of a single-point ground return. Sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. Additionally:
Reset
The bq2010 recognizes a valid battery whenever VSB is greater than 0.1V typical. VSB rising from below 0.25V or falling from above 2.25V resets the device. Reset can also be accomplished with a command over the serial port as described in the Reset Register section.
Temperature
The capacitors (SB and VCC) should be placed as close as possible to the SB and VCC pins, respectively, and their paths to VSS should be as short as possible. A high-quality ceramic capacitor of 0.1µf is recommended for VCC. The sense resistor capacitor should be placed as close as possible to the SR pin. The sense resistor (RSNS) should be as close as possible to the bq2010.
The bq2010 internally determines the temperature in 10°C steps centered from -35°C to +85°C. The temperature steps are used to adapt charge and discharge rate compensations, self-discharge counting, and available
bq2010
Gas Gauge Operation
Inputs
Charge Current Rate and Temperature Compensation
Discharge Current Rate and Temperature Compensation
Self-Discharge Timer
Temperature Compensation
+ Main Counters and Capacity Reference (LMD)
Nominal Available Charge (NAC)
Last Measured Discharged (LMD)
Discharge Count Qualified Register (DCR) Transfer
Temperature Translation
Temperature Step, Other Data
Outputs
Chip-Controlled Available Charge LED Display
Serial Port
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Figure 2. Operational Overview
bq2010
Table 1. bq2010 Programming
Pin Connection H Z L Note: PROG5 Self-Discharge Rate Disabled
NAC 64
PROG5 and PROG6 states are independent.
Table 2. bq2010 Programmed Full Count mVh Selections
Programmed Full Count (PFC) 49152 45056 40960 36864 33792 30720 27648 25600 22528
VSR equivalent to 2 counts / sec. (nom.)
bq2010
Discharge Counting
Self-Discharge Estimation
The bq2010 continuously decrements NAC and increments DCR for self-discharge based on time and temperature. The self-discharge count rate is programmed to be a nominal 1 64 NAC, 1 47 NAC per day, or disabled as selected by PROG5. This is the rate for a battery whose temperature is between 20°-30°C. The NAC register cannot be decremented below 0.
Count Compensations
The bq2010 determines fast charge when the NAC updates at a rate of 2 counts / sec. Charge and discharge activity is compensated for temperature and charge / discharge rate before updating the NAC and / or DCR. Selfdischarge estimation is compensated for temperature before updating the NAC or DCR.
Charge Compensation
Two charge efficiency compensation factors are used for trickle charge and fast charge. Fast charge is defined as a rate of charge resulting in 2 NAC counts / sec ( 0.15C to 0.32C depending on PFC selections see Table 2). The compensation defaults to the fast charge factor until the actual charge rate is determined. Temperature adapts the charge rate compensation factors over three ranges between nominal, warm, and hot temperatures. The compensation factors are shown below.
Charge Counting
Trickle Charge Compensation 0.80 0.75 0.65
Fast Charge Compensation 0.95 0.90 0.80
Discharge Compensation
Corrections for the rate of discharge are made by adjusting an internal discharge compensation factor. The discharge compensation factor is based on the namically measured VSR.
bq2010
The compensation factors during discharge are: Discharge Compensation Factor 1.00 1.05
Digital Magnitude Filter
Table 4. Typical Digital Filter Settings
DMF 75 100 150 (default) 175 200 DMF Hex. 4B 64 96 AF C8 VSRD (mV) -0.60 -0.45 -0.30 -0.26 -0.23 VSRQ (mV) 0.75 0.56 0.38 0.32 0.28
Error Summary
Capacity Inaccurate
The LMD is susceptible to error on initialization or if no updates occur. On initialization, the LMD value includes the error between the programmed full capacity and the actual capacity. This error is present until a valid discharge occurs and LMD is updated (see the DCR description on page 7). The other cause of LMD error is battery wear-out. As the battery ages, the measured capacity must be adjusted to account for changes in actual battery capacity. A Capacity Inaccurate counter (CPI) is maintained and incremented each time a valid charge occurs (qualified by NAC see the CPI register description) and is reset whenever LMD is updated from the DCR. The counter does not wrap around but stops counting at 255. The capacity inaccurate flag (CI) is set if LMD has not been updated following 64 valid charges.
Self-Discharge Compensation
Table 3. Self-Discharge Compensation
NAC NAC 256 128 64 32 16 8 4 2
NAC 188 94 47 NAC NAC NAC NAC NAC NAC NAC
Current-Sensing Error
Table 5 illustrates the current-sensing error as a function of VSR. A digital filter eliminates charge and discharge counts to the NAC register when VSRO (VSR + VOS) is between VSRQ and VSRD.
NAC NAC NAC
Communicating With the bq2010
The bq2010 includes a simple single-pin (DQ plus return) serial data interface. A host processor uses the interface to access various bq2010 registers. Battery characteristics may be easily monitored by adding a single contact to the battery pack. The open-drain DQ pin on
bq2010
Table 5. bq2010 Current-Sensing Errors
the bq2010 should be pulled up by the host system or may be left floating if the serial interface is not used. The interface uses a command-based protocol, where the host processor sends a command byte to the bq2010. The command directs the bq2010 either to store the next eight bits of data received to a register specified by the command byte or to output the eight bits of data specified by the command byte. The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 333 bits / sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2010 may be sampled using the pulse-width capture timers available on some microcontrollers. Communication is normally initiated by the host processor sending a BREAK command to the bq2010. A BREAK is detected when the DQ pin is driven to a logic-low state for a time, tB or greater. The DQ pin should then be returned to its normal ready-high logic state for a time, tBR. The bq2010 is now ready to receive a command from the host processor. The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2010 taking the DQ pin to a logic-low state for a period, tSTRH, B. The next section is the actual data transmission, where the data should be valid by a period, tDSU, after the negative edge used to start
communication. The data should be held for a period, tDV, to allow the host or bq2010 to sample the data bit. The final section is used to stop the transmission by returning the DQ pin to a logic-high state by at least a period, tSSU, after the negative edge used to start communication. The final logic-high state should be held until a period, tSV, to allow time to ensure that the bit transmission was stopped properly. The timings for data and break communication are given in the serial communication timing specification and illustration sections. Communication with the bq2010 is always performed with the least-significant bit being transmitted first. Figure 3 shows an example of a communication sequence to read the bq2010 NAC register.
bq2010 Registers
The bq2010 command and status registers are listed in Table 6 and described below.
Command Register (CMDR)
The write-only CMDR register is accessed when eight valid command bits have been received by the bq2010. The CMDR register contains two fields:
W / R bit Command address
The W / R bit of the command register is used to select whether the received command is for a read or a write function.
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Figure 3. Typical Communication with the bq2010
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Table 6. bq2010 Command and Status Registers
Control Field Register Name Symbol CMDR FLGS1 Command register Primary status flags register Loc. (hex) 00h 01h Read / Write Write Read 7(MSB) W / R CHGS 6 AD6 BRP 5 AD5 BRM 4 AD4 CI 3 AD3 VDQ 2 AD2 n / u 1 AD1 EDV1 0(LSB) AD0 EDVF
NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0
NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0
BATID
BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0
FLGS2
DMF RST Note:
0ah 39h
DMF7 RST
DMF6 0
DMF5 0
DMF4 0
DMF3 0
DMF2 0
DMF1 0
DMF0 0
bq2010
The lower seven-bit field of CMDR contains the address portion of the register to be accessed. Attempts to write to invalid addresses are ignored.
CMDR Bits 7 6 5 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0 (LSB)
The battery removed flag (BRM) is asserted whenever the potential on the SB pin (relative to VSS) rises above MCV or falls below 0.1V. The BRM flag is asserted until the condition causing BRM is removed. The BRM values are: FLGS1 Bits 7 6 5 BRM 4 3 2 1 0 -
AD6 AD5
Primary Status Flags Register (FLGS1)
The capacity inaccurate flag (CI) is used to warn the user that the battery has been charged a substantial number of times since LMD has been updated. The CI flag is asserted on the 64th charge after the last LMD update or when the bq2010 is reset. The flag is cleared after an LMD update. The CI values are: FLGS1 Bits 7 6 5 4 CI 3 2 1 0 -
The battery replaced flag (BRP) is asserted whenever the potential on the SB pin (relative to VSS), VSB, falls from above the maximum cell voltage, MCV (2.25V), or rises above 0.1V. The BRP flag is also set when the bq2010 is reset (see the RST register description). BRP is reset when either a valid charge action increments NAC to be equal to LMD, or a valid charge action is de-
When LMD is updated with a valid full discharge After the 64th valid charge action with no LMD updates or the bq2010 is reset
bq2010
The EDVF values are: FLGS1 Bits 7 6 5 4 3 2 1 0 EDVF
The VDQ values are: FLGS1 Bits 7 6 5 4 3 VDQ 2 1 0 -
Temperature and Gas Gauge Register (TMPGG)
TMP3 TMP2
TMP1 TMP0
The first end-of-discharge warning flag (EDV1) warns the user that the battery is almost empty. The first segment pin, SEG1, is modulated at a 4Hz rate if the display is enabled once EDV1 is asserted, which should warn the user that loss of battery power is imminent. The EDV1 flag is latched until a valid charge has been detected. The EDV1 values are:
The final end-of-discharge warning flag (EDVF) is used to warn that battery power is at a failure condition. All segment drivers are turned off. The EDVF flag is latched until a valid charge has been detected. The EMPTY pin is also forced to a high-impedance state on assertion of EDVF. The host system may pull EMPTY high, which may be used to disable circuitry to prevent deep-discharge of the battery.
bq2010
The bq2010 calculates the available charge as a function of NAC, temperature, and a full reference, either LMD or PFC. The results of the calculation are available via the display port or the gas gauge field of the TMPGG register. The register is used to give available capacity in 1 16 increments from 0 to 15 16. 7 6 TMPGG Gas Gauge Bits 5 4 3 2 GG3 GG2 1 GG1 0 GG0 of the battery from full to empty. In this way the bq2010 updates the capacity of the battery. LMD is set to PFC during a bq2010 reset.
Secondary Status Flags Register (FLGS2)
Where CR is: 0 1 When charge rate falls below 2 counts / sec When charge rate is above 2 counts / sec
Nominal Available Charge Registers (NACH / NACL)
Battery Identification Register (BATID)
Last Measured Discharge Register (LMD)
0 OVLD
bq2010
DR2-0 and OVLD are set based on the measurement of the voltage at the SR pin relative to VSS. The rate at which this measurement is made varies with device activity.
Digital Magnitude Filter (DMF)
Program Pin Pull-Down Register (PPD)
Reset Register (RST)
PPU6 PPU5 PPU4 PPU3 PPU2 PPU1 PPD6 PPD5 PPD4 PPD3 PPD2 PPD1
Program Pin Pull-Up Register (PPU)
Display
Capacity Inaccurate Count Register (CPI)
bq2010
Microregulator
The bq2010 can operate directly from 3 or 4 cells. To facilitate the power supply requirements of the bq2010, an REF output is provided to regulate an external lowthreshold n-FET. A micropower source for the bq2010 can be inexpensively built using the FET and an external resistor see Figure 1.
Absolute Maximum Ratings
Symbol VCC All other pins REF VSR Parameter Relative to VSS Relative to VSS Relative to VSS Relative to VSS Minimum -0.3 -0.3 -0.3 Maximum +7.0 +7.0 +8.5 Unit V V V Current limited by R1 (see Figure 1) Minimum 100 series resistor should be used to protect SR in case of a shorted battery (see the bq2010 application note for details). Commercial Notes
TOPR Note:
Operating temperature
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Symbol VEDVF VEDV1 VSR1 VSRO VSRQ VSRD VMCV VBR Note: Parameter Final empty warning First empty warning Discharge compensation threshold SR sense range Valid charge Valid discharge Maximum single-cell voltage Battery removed / replaced Minimum 0.93 1.03 -120 -300 375 2.20 2.20 Typical 0.95 1.05 -150 2.25 0.1 2.25 Maximum 0.97 1.07 -180 +2000 -300 2.30 0.25 2.30 Unit V V mV mV µV µV V V V SB SB SR, VSR + VOS SR, VSR + VOS VSR + VOS (see note) VSR + VOS (see note) SB SB pulled low SB pulled high Notes
Default value value set in DMF register. VOS is affected by PC board layout. Proper layout guidelines should be followed for optimal performance. See "LayoutConsiderations."
bq2010
IOHLCOM LCOM source current
bq2010
Symbol tCYCH tCYCB tSTRH tSTRB tDSU tDH tDV tSSU tSH tSV tB tBR Note: Parameter Cycle time, host to bq2010 Cycle time, bq2010 to host Start hold, host to bq2010 Start hold, bq2010 to host Data setup Data hold Data valid Stop setup Stop hold Stop valid Break Break recovery Minimum 3 3 5 500 750 1.50 700 2.95 3 1 Typical Maximum 6 750 2.25 Unit ms ms ns µs µs µs ms ms µs ms ms ms Notes See note
The open-drain DQ pin should be pulled to at least VCC by the host system for proper DQ operation. DQ may be left floating if the serial interface is not used.
Serial Communication Timing Illustration
tSTRH tSTRB tDSU tDV tDH tSSU tSV tCYCH, tCYCB, tB tSH
DQ (BREAK)
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bq2010
16-Pin SOIC Narrow (SN)
16-Pin SN (SOIC Narrow)
Dimension Minimum A 0.060 A1 0.004 B 0.013 C 0.007 D 0.385 E 0.150 e 0.045 H 0.225 L 0.015 All dimensions are in inches. Maximum 0.070 0.010 0.020 0.010 0.400 0.160 0.055 0.245 0.035
bq2010
Data Sheet Revision History
Ordering Information
bq2010
Temperature Range:
Package Option:
Device:
bq2010 Gas Gauge IC