ISSUE V1.4 APPROVED Sensor Interface Contents FUNCTION
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ISSUE V1.4 APPROVED
Sensor Interface
Contents
FUNCTION
1.1. 1.1.1. 1.1.2. 1.1.3. 1.2. 1.2.1. 1.2.2. 1.2.3. 1.3. 1.3.1. 1.3.2. 1.3.3. 1.3.4. 2.1. 2.2. 2.3. 3.1. 3.2. 3.3. General Features Applications MSI-EB1 Evaluation Board Analog Components Power Supply Signal Processing Sensor Interfacing Connections Digital Components Register Block Serial Interface Logic Control Block Signal Declarations Absolute Limit Values Operating Parameters AC/DC Features Ordering Specifications PQFP44 Package Dimensions Pin-Out Assignments
ELECTRIC PARAMETERS
DESCRIPTION PACKAGE
APPLICATION CIRCUIT
MAZeT GmbH Sales office D-07745 Jena Germany Phone: +49/3641-2809-0 Fax: +49/3641-2809-12
Email: sales@MAZeT.de URL: http://www.MAZeT.de
Approvals
Compiled: Checked: Released:
Date
2001-03-16 2002-07-09 2002-07-09
MAZeT GmbH
Status: Data sheet DOC. DB99085e Sheet
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Function
1.1. General
activated working cycle, current only supplied sensor bridge only long measurement lasts. Power supply bridge circuit current mode voltage mode. Equipped with additional option recording input voltage (auto zero) voltage internal external calibration divider, allows balancing performed zero value full scale value. Since preamplifier works based chopper principle, very small signal amplitudes evaluated. chopper transforms given input signal into frequency range such that interferences transmission channel will only caused level white noise portions. consequence, noise portions prevailing frequency ranges strongly suppressed. Because small dimensions (PQFP44) little power consumption standby mode resp.), directly mounted sensor (e.g. sensor heads), sensors which connected directly supplied with current voltage. Thanks integral temperature sensing ability, preferentially employed where sensor characteristics have corrected matching temperature conditions (e.g. Hall sensors strain measuring bridges), further where integrated signal conditioning solutions required.
highly integrated sensor interface capable processing signals from four differential-output sensors input side. specifically designed interfacing with bridge sensors that deliver ratiometric output signals. input circuit which configurable terms gain, zero-point resolution amplifies, filters converts incoming analog signals into digital ones. They then made available digital interface downstream evaluation module. offers possibilities temperature compensation: on-chip integral temperature measurement that used e.g. compensate temperature behaviour connected sensors that external temperature compensation that measures response bridge resistor temperature changes against voltage divider (see section. 1.2.3. Sensor Interfacing Connections). addition integrated on-chip functionality, notably features very high signal resolution while maintaining signal stability consuming little current. designed evaluate differential sensor signals type delivered e.g. pressure sensors, hall sensors sensors working principle resistance measuring bridge (strain measuring bridges, piezo magneto-resistive sensors). These sensors
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1.1.1.
Features
Four input channels (multiplex) Bridge current voltage supplied just long selected sensor bridge takes finish measurement power design allows battery-operated mode 15-bit resolution Charge balancing excellent noise suppression Unipolar bipolar measurement 'Backrgound measurement' mode allows measurement without activation Small temperature coefficient in-chip external temperature measurement Interrupt generated excession limiting value Data output serial interface Built-in pulse counter flow meter (gas meter)
1.1.2.
Applications
Battery-supported sensor electronics (pressure, temperature, strain gauge, etc.) Data logger measuring pressure temperature water supply nets Autonomous pressure monitoring devices Weather stations meters (gas quantity meters)
1.1.3.
MSI-EB1 Evaluation Board
evaluation board provides three plug-in bases sensor modules allow individualized connection those sensors which user needs evaluate. test environment completed Windows-based graphical user screen fast easy access MCI's functionality. Features this user screen include sample configurations consecutive measurements with graphical representation results, access Evaluation-Board MSI-EB1 configurations (bits). graphical user screen ensures easy availability whole range functions parameters.
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1.2.
1.2.1.
Analog Components
Power Supply
Figure shows separate power supply diagram.
3,7V 6,6V
VBAT
3,3V±3%
µController
STAB
3,3V±3% 220n VBPx VDDA RIBx
SGND=VDDA/2
Sensors
VSSA
Figure power supply
operation, voltage supplied, preferentially from battery on-chip in-phase regulator (STAB). outputs stabilized voltage VDDA about which also powers bridge sensors. Since absolute voltage value subject relatively broad process tolerances (about ±10%), serial interface prepared calibrate approximately ±3%. regulator built-in reset function (PON) output static reset signal (high-active), soon operating voltage drops below power-fail threshold. excession this power-on threshold, reset signal will switch with certain time delay. same time, VDDA supply voltage also used reference voltage ADC, which ensures ratiometric measurement bridge signals. derivative VDDA supply voltage voltage which intended power external controller further system components. reduce retro-interference effects from controller's operating voltage, resistor about ohms isolates voltage from VDDA (regulator output voltage). With power-down mode, analog circuitry parts, including also bridge supply components, turned off. in-phase regulator will continue operate current saving stand-by mode (diminished regulation dynamics) preserve data contents digital registers, keep interface operating condition maintain power supply external components. reset circuit will also remain active. Because this leads change regulator's working point, regulator output voltage stand-by mode insignificantly differ from that normal operating mode (VDD<100mV).
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1.2.2.
Signal Processing
block diagram contained Figure required external internal signal selected input multiplexer (MUX) connected input measuring channel. Supported measuring modes are: Differential measurement Differential measurement (IPx INx)/2 (only inputs Measurement on-chip temperature sensor voltage Measurement battery voltage internal voltage divider Auto zero measurement (both inputs measuring channel internally connected AGND) Measurement different pick-offs symmetric internal calibration divider (ratiometric)
AGND SGND VDDA VSSA VBAT
Test scaler
Temp sensor
Power-ON Power-FAIL RESET
Limit value register
Voltage controller
Digital comparator Result counter
Analogue multiplexer
Preamplifier antialiasing
A/D-Converter Summator
RTC-prescaler
VBP0 VBP1 VBP2 VBP3
Bridge supply
Configuration register
MODE register Control unit Impuls counter
BUSY PULS
Time counter Realtime counter Serial interface
SDAT SCLK
Clock generator Parallel PORT
RIB1 RIB2
TEST
Figure Block diagram
measuring channel consists low-noise preamplifier (CVV) with four selectable gains, filter amplifier (FV) signal band limitation converter (ADC) with four selectable zero-point levels four selectable resolutions. Configuration measuring channel (source, sensititivity, zero-point, resolution) performed with help interface command before starting measurement. Battery voltage measurement restricted VDDA range +0.1 approximately because adequate measuring accuracy guaranteed with smaller voltages. Battery voltage measurement must calibrated supply voltage which serves reference voltage subject relatively strong exemplary variations.
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measure chip temperature, on-chip temperature sensor (TEMP) provided. Temperature measurement must calibrated, because notably sensor offset subject major variations. Since VDDA serves reference voltage, VBAT dependence (via line regulation!) must included procedure calibration. connecting capacitor pin, on-chip clock generator (CLKGEN, nominal rate) made work with lower frequency generator clock overwritten external CMOS clock that supplied this pin. clock-overwrite mode, external clock needs stopped during power-down state, order prevent unwanted current flows. When working on-chip frequency mode, should make sure that there parasitic capacity applied CLKGEN connect this pin!) series resistor works like chopper, order keep noise portions drift effects minimum. filter amplifier intended re-amplify, symmetrize limit signal band smaller than (antialiasing). Designed switched capacitor technology, uses charge balancing method. converter's integrational behaviour causes limitation bandwidth noise portions, depending integration time. bit-resolution clock frequency, integration time 13-, 9bit resolution, integration time drops factor 0.25 with each transition next smaller length correspond 9-bit resolution. conversion process consists filter settling time depending selected resolution) integration time. Conversion preceded setup time TSET selected bridge. selected stepping follows: ADC's zero-point also shifted such that corresponding input voltage span (span0 broken down from /16. (unipolar) (bipolar) (zero0. marge approximately needs deducted from these theoretical ranges both ends order account certain offset spread across entire measuring channel (already accounted specified Span values). analog testing mode, internal reference voltages switched instead various external internal sources. These reference voltages provide ratiometric input signals each span. test mode, causes pole reversal internal reference voltage. This also allows bipolar measuring ranges included testing.
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1.2.3.
Sensor Interfacing Connections
sensor connection sample diagram shown Figure with input meanings follows: VBP0: External calibration divider VBP1: Bridge voltage mode with series resistor allow temperature measurement bridge temperature coefficient described current mode), reference potential T-measurement VBP2: Bridge current mode, reference potential T-measurement VBP3: Bridge voltage mode with series resistors
VDDA
Current sources power down switches
VSSA
Figure Connection diagram power measurement bridges voltage mode current mode
Sensors which designed bridge circuits also connected. With non-ratiometric signals, should however consider that operating voltage notably temperature coefficient will reflected conversion result. should further guaranteed that common-mode level within specified limits.
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inputs rated differential measurement (IPx: positive input, INx: negative input). typical application scenario four bridge sensors, four switched supply pins (VBP0 VBP3) provided. These activated each time when channel slected measurement. This done order keep mean operating current small possible. external bridge sensors (VBP1, VBP2) supplied current voltage mode, others voltage mode only. current supply mode, current source available (BSUPPLY) provide constant current VDDA from (source STAB) pins VBP1 VBP2. Distinction between current voltage supply mode achieved different RIBx connections: short circuit with results voltage supply mode (RIBx connected with VBP). Using external resistor current sources necessary precondition small temperature coefficient. Simultaneously, adds flexibility various bridge resistors ("coarse balancing"). order minimize influence internal drift effects, current source's regulating amplifier choppered. Additionally, supply currents matched specified bridge resistor tolerances eight steps ("fine balancing", configuration interface command), proportional supply voltage VDDA ratiometric measurement will also guaranteed current supply mode. Resistance RIBx will calculated following equation: (VDDA Iout) 0.05 Iout brigde current
temperature measurement involving temperature coefficient bridge resistors, which typically lies between 2000 ppm/K 4000 ppm/K piezoresistive bridges, common-mode voltage bridge's diagonal (internal averaging inputs IP1/2 IN1/2) measured against external voltage divider (inputs IC1, IC2). compulsory precondition therefore, current supply mode must chosen with signal voltages typically range approximately mV/K bridge resistance, about 0.75mA bridge current).
1.3.
Digital Components
digital part consists register block, serial two-wire interface (TWI) logic control block.
1.3.1.
Register Block
allows reading writing digital part registers. These intended configuration, control storage measured values. normal operating mode, only certain read write operations make sense. Each register accessed register address. following table lists registers significance respective register bits selected order addresses.
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Name KONFIG ERGEB ERGSUM RTCSET GRENZ IMPZAHL ZEITZA PORT MODE RTCVT
Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009
Length bytes bytes bytes byte bytes bytes bytes byte byte bytes
Reset value 0000 0000 000000 000000 000000 0000 0000
Meaning Configuration register Result register Result register (cumulating) counter (preloadable) Limit value register Pulse counter Time counter Port register configuration register Register predivision factor
1.3.1.1. Configuration Register
K[2:0] E[1:0] O[1:0] Values A[1:0] I[2:0]
Bit(s) K[2:0]
Meaning Measuring input selection
AutoZero
E[1:0] O[1:0] A[1:0]
Span selection Zero-point (Offset) Resolution/conversion time
I[2:0]
Bridge current setting Conversion start Analog test mode Soft reset
Configuration Channel bridge (IP0, IN0) Channel bridge (IP1, IN1) Channel bridge (IP1/N1, IC1) Channel bridge (IP2, IN2) Channel bridge (IP2/N2, IC2) Channel bridge (IP3, IN3) Channel chip temperature Channel battery voltage Measures selected channel with measures zero-point with reverses calibration divider poles Span 0-3, Zero Zero bits +TSET bits +TSET bits +TSET bits +TSET Step Step Only configuration Starts foregound conversion Normal switching function Test mode channels with K[2:0], selected
Aborts running measurement
This register designed configuration triggering measuring processes. also used abort running measurement. With `1', measurement will triggered detection interface stop condition. completion measurement, will reset '0'. With SW=0, converter reconfigured. With SR=1 (bit stored), running measurement aborted defined state starting measurement restored. Besides, some test functionalities also handled this register.
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1.3.1.2. Result Counter
ERG[14:0]
Stores result single measurement. measured result (ERG) contain value between 32767 -1). measured result assigned independently selected resolution (left-adjusted results). bits that unused lower resolution mode connected level '0`. counter reset each start measurement.
1.3.1.3. Results Counter
ERGSUM[22:0]
Sums result single background measurements stores completion measurement. overflow occurs during measurement (Zout=(2 -1)), overflow will set. counter reset writing RTCSET.
1.3.1.4. Real Time Clock Counter
RTCSET[7:0]
Allows selection desired number background measurements. After each background measurement, counter decremented. This limits maximum possible number background measurements (256). Data writing into this counter starting condition so-called background measurement. Once counter reaches value, background measurements will stop. Subsequently arriving RTCINT pulses will have influence counter reading counter reset part soft reset.
1.3.1.5. Limit Value Register
OBGRZ[10:0]
UNGRZ[10:0]
Defines upper limit (OBGRZ) that lower limit (UNGRZ) measured value converted. there positive excession upper negative excession lower limiting value, running background measurement will terminated early (RTC counter unequal zero) switch power-down mode. Both limiting values OBGRZ UNGRZ completed bits each them take values between (65535) steps UNGRZ=0x000 OBGRZ=0xFFE written into this register, limit values will monitored background measurement terminated early. Bits optional changes functionality analog part. Their default value When results range (GF) result counter will ,1`.
1.3.1.6. Pulse Counter
IMPZAHL[23:0]
Counts pulses arriving PULSE input. only reset "Power thus used differential measurement. Allows writing.
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1.3.1.7. Time Counter
ZEIT[9:0]
Counts predivided pulses (RTCINT). only reset Power-On thus used differential measurement. Allows writing.
1.3.1.8. Port Configuration Register
PORT register supports configuration freely programmable eight-bit digital port. signal levels which declared this register will available outputs PB[7:0].
1.3.1.9. Mode Register
INT[1:0]
INT[1:0]
Meaning
Value
AV[1:0]
ST[1:0]
AV[1:0] ST[1:0]
Polarity signal Chopper frequency balancing steps) System settling time
Configuration interrupt (default level bit) interrupt RTCINT interrupt END/RTCINT interrupt Low-active (default high) High-active (default low) (default) steps voltage balancing highest voltage Additional measurement system settling time
This register intended configuration. only reset Power-On.
1.3.1.10.
Predivider Register
VT[15:0]
Divides pulses that arrive input RTC. writing into this register, desired division factor. content represents greatest possible division factor 32767:1. content will block pulses. predivider register only reset Power-On. actual predivider part reset writing into predivider register. Following division, pulses (RTCINT) trigger background measurements available output MODE register appropriately set) interrupt control.
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1.3.2.
Serial Interface
1.3.2.1. Features
Equipped with bi-directional (SDAT) input (SCLK), serial interface represents twowire communication port. SDAT open-drain output stage. connecting variety devices these pins serial organized. long used, lines kept high level external pull-up resistors. basic rule this serial bus, always dominant line signal which will overwrite high every case, whereas never overwritten high. data transfer rate kbit/s standard mode kbit/s fast mode.
1.3.2.2. Principle Serial Data Transfer
data which clocked with SCLK line transferred SDAT line serial bus. Data only regarded valid long clock SCLK HIGH state. data transfer byte-wise organized, beginning with MSB, i.e. each byte SDAT eight bits long. There limitation number transferable bytes. When inactive, SDTA SCLK high. data transfer enabled high-low level transition SDAT, with SCLK remaining high level (starting condition). After occurrence starting condition, seven-bit long device address (DevID) transferred. This followed which sets data transfer direction. ninth then contains expected acknowledge signal from slave master. Finally, data sent packages eight bits acknowledged with ninth bit. data transfer terminates arrival stop condition which achieved with low-high transition SDAT line. Again line carries high level when this control signal present. Figure contains schematical data transfer diagram. serial interface provides algorithms test remove transfer errors.
SDAT
SCLK
Start
Address
Data byte
Data byte
Stop
Figure Data transfer principle serial
1.3.2.3. Addressation Model
addressation performed steps. Initially, device must selected. This done sending respective device address (DevID). DevID 0010001. should unequivocally identify within destination system. this reason, must identical with DevID another device. second step, destination address register accessed needs sent (RegID). Only then actual data follows. Based this model, following protocols possible reading from, writing into, register:
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DevID
RegID
DevID
Data byte
Data byte
Reading register
DevID
RegID
Data byte
Data byte
Writing into register
Start condition Stop condition
Register address Device address
Write Read
Acknowledge Acknowledge
Figure Register write read operations
1.3.2.4. Overview Permissible Application Commands
Only those commands which quoted table below supported serial interface. Other combinations possible testing purposes (register read/write operations), guaranteed supported terms functionality.
Addressed register
KONFIG ERGEB ERGSUM RTCSET GRENZ IMPZAHL ZEITZA PORT MODE RTCVT
Read/Write
Read/Write Read Read Read/Write Read/Write Read Read Read/Write Read/Write Read/Write
Effect
Cnfigures conversion parameters, starts conversion SW=1 Reads conversion result Reads value Reads counter sets counter starting value resets ERGSUM counter Reads limit values writes limit values Reads pulse counter Reads time counter Reads writes address Reads writes configuration Reads writes division factor
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1.3.3.
Logic Control Block
implementation logic control block necessary order facilitate handshake procedure between various components. responsible sequencing control various measurements, providing power-down functionality synchronizing components with each other. control part creates clock base conversion. conversion cycle triggered KONFIG (processor measurement) RTCSET input cyclic mode. noncyclic conversion begins after module receives notice bit. cyclic time-controlled conversion triggered, conversion process will start arrival RTCINT pulse (predivided pulse) subject condition that RTCSET unequal zero, that other conversion taking place this moment limit value flag contains zero. During these so-called background measurements, BUSY signal stays high until last measurement been completed (RTC counter down zero limit value exceeded). clock base procedure itself (Figure begins with clock generator getting started powerdown state being abolished. continues turning bridge supply voltage configuring amplifier channel (span, zero, resolution), expiry bridge setup time pre-selected connecting channel predefined source, compensation preamplifier offset, turning chopper performing actual conversion expiry signal settling time. completion conversion result will available result counter. conversion triggered RTCINT pulse, ERGSUM counter will continue count too. overflow occurs RTCINTtriggered conversion, ERGSUM counter will set. Following conversion, analog components switched back power-down mode. result counter reset takes place with each start conversion. ERGSUM counter reset loading RTCSET register. BUSY state indicates either processor measurement succession background measurements and, hence, readiness read corresponding result from ERGEB ERGSUM counter. With trailing edge BUSY configuration register will zero. long BUSY signal high, access ERGEB ERGSUM counter disabled. supply operating voltage (VBAT) these registers their default state ('0') circuit remains power-down state. supply voltage (VDDA) then takes maximum value. long signal active, MISI output signals undefined.
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KONFIG START BUSY ZOUT
Signal setting conversion
Figure Clock diagram analog part control signals
1.3.4. Signal Declarations 1.3.4.1. Input
input Schmitt trigger input stage. Signals arriving accepted with their `0'-`1'transition edge. RTCINT pulse generated from pulse based relationship VT:1. '0', RTCINT pulse will generated.
1.3.4.2. Pulse Counter Input PULSE
PULSE input Schmidt trigger input stage. Signals arriving input counted with their `0'`1' edge.
1.3.4.3. BUSY Output
BUSY output high-active. enabled starting foreground measurement first series background measurements. disabled completion foreground measurement last series background measurements.
1.3.4.4. Interrupt Output
interrupt output provides interrupt pulses approximately length depending logic state INT[1:0] bits MODE register: Low-active interrupt pulse High-active interrupt pulse INT[1:0] INT[1:0] INT[1:0] INT[1:0] interrupt pulses Interrupt disablement BUSY signal (internal signal clock diagram Figure Interrupt RTCINT BUSY Interrupt pulses RTCINT BUSY
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1.3.4.5. Output
This output delivers high-active pulse when battery voltage supplied (power when regulator output voltage drops about below nominal level (power fail). output remains enabled least after reaching restoring nominal regulator output voltage.
1.3.4.6. TEST Input
This input low-active. purpose enable test mode. given application scenario, this input needs connected high level left unused (internal pull up).
1.3.4.7. Input
This input high-active. used cancel power-down state bypassing logic control block. given application, this input needs connected level left unused (internal pull down).
1.3.4.8. Input
used external clock triggering with CMOS levels (about kHz). free-running mode, input must wired, because capacitive loads will decrease frequency internal clock generator!
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Electric Parameters
2.1. Absolute Limit Values
Parameter Limits
Voltage VBAT Supply voltage Voltage other pins Power dissipation Operating temperature range Storage temperature range Lead temperature (soldering, 10sec.)
-0.3 +150°C
2.2.
Operating Parameters
Unit
Parameter
Battery voltage Battery voltage source resistance Ambient temperature level input voltage digital inputs High level input voltage digital inputs Load current Capacitor VBAT Capacitor Capacitor VDDA Bridge resistance voltage mode Bridge resistance current mode Load capacitance SDAT Clock frequency SCLK Rise/fall time SCLK Clock frequency Rise/fall time Capacitor pins AGND, SGND
12.5 t.b.d. t.b.d.
1000
t.b.d.
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2.3.
AC/DC Features
(VBAT 3.7V 7.2V, TAMB -20°C 70°C)
Symbol Parameter
Conditions Power Management
Unit
IBAT IBATPD TCVDD VCVDD VBAToff VBATon tRESET
Supply current from battery Power down supply current Regulated supply voltage Regulated supply voltage supply voltage Line regulation Load regulation Power fail level Power level Reset pulse delay after power reset pulse width case power fail
bridges With bridges Uncalibrated After calibration
VDD/( VDD/VBAT VDD/ILOAD
-400 0.91 0.95 0.923 0.96
0.94 0.97
ppm/K mV/V mV/mA
ILOAD 0.1mA ILOAD 0.1mA
Bridge Current Sources IOUT
IOUT
Source current, steps Step width Source resistance Voltage span, Span0 Sensitivity, Span0 Voltage span, Span1 Sensitivity, Span1 Voltage span, Span2 Sensitivity, Span2 Voltage span, Span3 Sensitivity, Span3 Common mode voltage Zero count, Zero0 Zero count, Zero1 Zero count, Zero2 Zero count, Zero3 Offset count Peak peak output noise Peak peak output noise Integral nonlinearity Temp. dependency gain
VOUT< 0.4V,
0.041 0,0027 10000 100000 8.63 2.88 0.96 0.32
0.060
VDDA/RIB VDDA/RIB ppm/K
µV/cnt
TCIOUT RSOURCE VSPAN VLSB VSPAN VLSB VSPAN VLSB VSPAN VLSB TCGAIN
Additional nonratiometric TCRIB= VOUT< 0.4V VINMAX-VINMIN, VINMAX-VINMIN, VINMAX-VINMIN, VINMAX-VINMIN, Span3 Span3, samp. Span2, samp. Dev. from best strait
Ratiometric True Differential Analog Channels VDD=3.3V, RADC 15Bit
µV/cnt
µV/cnt
µV/cnt
VDD-1.4 2048 4096 8192 16384 2150 4300 8600 17200
counts counts counts counts counts ppm/K
1950 3900 7800 15600
-300
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Analog Channel Internally Connected TEMPSENS, VDD=3.3V, RADC=13 VMAX VMIN VLSB VLSB f`CLK Full count count Sensitivity Auto zero count Integral nonlinearity Output count 25°C Sensitivity Auto Zero count Integral nonlinearity Input current Input current Output high level Output level Pulse length Clock frequency VBAT 6.6V, Zero3, VBAT 3.6V, Zero3, Zero3 Dev. from best strait Zero3 Zero3 Dev. from best strait Digital Inputs Outputs -2mA high Clock Generator Free running, CCLK Converter RADC tCONV tCONV EVMODE EIMODE Resolution Conversion time Conversion time Differential nonlinearity Overall error Overall error fCLK=256kHz, 15Bit fCLK=256kHz, 9Bit missing codes V-mode, average over samples I-mode, average over samples counts counts VDD-0.3
2579 1200 2.17 3900 -1000 5000 0.15 3900 -500 4096 4096 4300 1000 6000 0.25 4300
counts counts mV/cnt counts counts K/cnt counts
Analog Channel Internally Connected VBAT, VDD=3.3V, RADC=13
Total System, RADC=15Bit, Zer0, Span3, Tamb 40°C
reliability reasons, maximum battery voltage 7.2V allowed permanent operation. Parameter ratiometric (i.e. nominal value must multiplied with VDDA 3.3V)
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Description Package
3.1. Ordering Specifications
Type designation 01DF 01GF MSI-EB1 Supply version DICE (unpackaged) PQFP44 Evaluation Board with demo software, power pack, zero-modem cable
3.2.
PQFP44 Package Dimensions
Phys. dimensions (based JEDEC: MS-112AA)
Figure View PQFP44 package
Dimensions subgroup 0.80 enorm 2.60 Amax 0.25 bPmin 0.45 bPmax 13.65 HEmin 14.30 HEmax 13.65 HDmin 14.30 HDmax 0.63 LPmin
Dimensions subgroup 2.10 Amin 0.15 A1min 0.30 A1max 1.80 A2min 2.20 A2max 0.11 cmin 0.23 cmax 9.90 Dmin 10.10 Dmax 9.90 Emin 10.10 Emax
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3.3.
Pin-Out Assignments
Name Description protec-tion 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV 1.2kV PQFP Analog ground, circuitry parts (VDD/2) Negative bridge supply voltage Positive bridge supply voltage Positive supply calibration divider Positive bridge supply, bridge Positive bridge supply, bridge Positive bridge supply, bridge resistor current source resistor current source Positive input Negative input Positive input bridge Negative input brdge Input divider Positive input bridge Negative input bridge Input divider Positive input bridge Negative input bridge Clock frequency clock input Clock input interface Data input/output interface, open drain Power power fail output Real time clock Interrupt output BUSY output Power input (default low) Pulse counter input PortBit PortBit PortBit PortBit PortBit PortBit PortBit PortBit Turns digital test mode (default high) VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA ground
VBAT VDDA VSSA n.c. SGND VBP0 VBP1 VBP2 VBP3 RIB1 RIB2 SCLK SDAT BUSY PULSE TEST n.c.
Battery voltage Controlled supply voltage Controlled supply voltage controller Digital Analog
VSSA VSSA
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Page
Data sheet
VERSION
ISSUE APPROVED
Application Circuit
3.7V 6.6V 3.3V
VBAT VBP3
Bridge
SCLK
SDAT
n.c.
TEST BUSY VSSA SGND VBP1 VBP2 RIB1 RIB2 VBP0
PULSE
MAZeT
VDDA VBAT n.c. VBP3
VBP1
VBP2
100K 100K
RIB1
RIB2
100K
220n
100K
Bridge
Figure Application wiring diagram
more information, please contact:
MAZeT GmbH Herr Mahler
Str. D-07745 Jena/Germany Phone: 3641 2809-0 Telefax: 3641 2809-12 EMAIL: sales@MAZeT.de http://www.MAZeT.de
information published this document reflect state moment publishing temporary nature. MAZeT expressly reserve right make engineering changes regarding devices components described this document.
Bridge
DOC. DB99085E
Page
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