8-Bit Serial-In, Parallel-Out Shift Wide Operating Voltage Range High-
|
|
|
Top Searches for this datasheet
SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
8-Bit Serial-In, Parallel-Out Shift Wide Operating Voltage Range High-Current 3-State Outputs Drive
LSTTL Loads Power Consumption, 80-µA Typical ±6-mA Output Drive Input Current Shift Register Direct Clear
SN54HC595 PACKAGE SN74HC595 PACKAGE (TOP VIEW)
description/ordering information
'HC595 devices contain 8-bit serial-in, parallel-out shift register that feeds 8-bit D-type storage register. storage register parallel 3-state outputs. Separate clocks provided both shift storage register. shift register direct overriding clear (SRCLR) input, serial (SER) input, serial outputs cascading. When output-enable (OE) input high, outputs high-impedance state. Both shift register clock (SRCLK) storage register clock (RCLK) positive-edge triggered. both clocks connected together, shift register always clock pulse ahead storage register. ORDERING INFORMATION
PDIP SOIC -40°C 85°C SOIC SSOP CDIP -55°C 125°C LCCC PACKAGE Tube Tube Tape reel Tube Tape reel Tape reel Tape reel Tube Tube Tube ORDERABLE PART NUMBER SN74HC595N SN74HC595D SN74HC595DR SN74HC595DW SN74HC595DWR SN74HC595NSR SN74HC595DBR SNJ54HC595J SNJ54HC595W SNJ54HC595FK HC595 HC595 HC595 HC595
RCLK SRCLK SRCLR
SN54HC595 PACKAGE (TOP VIEW)
RCLK SRCLK
internal connection
TOP-SIDE MARKING SN74HC595N
SNJ54HC595J SNJ54HC595W
SNJ54HC595FK Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2003, Texas Instruments Incorporated
products compliant 38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
POST OFFICE 655303
DALLAS, TEXAS 75265
SRCLR
SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
FUNCTION TABLE INPUTS SRCLK SRCLR RCLK FUNCTION Outputs QA-QH disabled. Outputs QA-QH enabled. Shift register cleared. First stage shift register goes low. Other stages store data previous stage, respectively. First stage shift register goes high. Other stages store data previous stage, respectively. Shift-register state changed. Shift-register data stored storage register. Storage-register state changed.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
logic diagram (positive logic)
RCLK SRCLR SRCLK
numbers shown packages.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
timing diagram
SRCLK
RCLK
SRCLR
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input clamp current, VCC) (see Note Output clamp current, VCC) (see Note Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 73°C/W package 82°C/W package 57°C/W package 67°C/W package 64°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD 51-7.
recommended operating conditions (see Note
SN54HC595 Supply voltage level input Low-level voltage Input voltage Output voltage 3.15 1.35 1000 SN74HC595 3.15 1.35 1000 UNIT
High level input High-level voltage
Input transition rise/fall time
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004. this device used threshold region (from VILmax VIHmin there potential into wrong state from induced grounding, causing double clocking. Operating with inputs 1000 does damage device; however, functionally, inputs ensured while shift, count, toggle operating modes.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS QA-QH, -5.2 QA-QH, -7.8 QA-QH, QA-QH, 3.98 3.98 5.48 5.48 25°C 1.998 4.499 5.999 0.002 0.001 0.001 0.17 0.17 0.15 0.15 ±0.1 ±0.01 0.26 0.26 0.26 0.26 ±100 ±0.5 SN54HC595 ±1000 SN74HC595 3.84 3.84 5.34 5.34 0.33 0.33 0.33 0.33 ±1000 UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
fclock Clock frequency SRCLK RCLK high Pulse duration ration SRCLR before SRCLK SRCLK before RCLK Setup time SRCLR before RCLK SRCLR high (inactive) before SRCLK Hold time, after SRCLK 25°C SN54HC595 SN74HC595 UNIT
This setup time allows storage register receive stable data from shift register. clocks tied together, which case shift register clock pulse ahead storage register.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) fmax SRCLK RCLK QA-QH tPHL SRCLR QA-QH tdis QA-QH QA-QH 25°C SN54HC595 SN74HC595 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) RCLK QA-QH QA-QH QA-QH 25°C SN54HC595 SN74HC595 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS load UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
PARAMETER MEASUREMENT INFORMATION
PARAMETER tPZH tPZL tPHZ tPLZ Open Closed Open Closed Open Closed Open Closed Open Open
From Output Under Test (see Note
Test Point
tdis
LOAD CIRCUIT
High-Level Pulse
VOLTAGE WAVEFORMS PULSE DURATIONS
Reference Input Data Input
Low-Level Pulse
VOLTAGE WAVEFORMS SETUP HOLD INPUT RISE FALL TIMES
Input tPLH In-Phase Output tPHL Out-ofPhase Output tPLH tPHL
Output Control (Low-Level Enabling) tPZL Output Waveform (See Note tPZH Output Waveform (See Note
tPLZ tPHZ
VOLTAGE WAVEFORMS PROPAGATION DELAY OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES 3-STATE OUTPUTS
NOTES: includes probe test-fixture capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. Phase relationships between waveforms were chosen arbitrarily. input pulses supplied generators having following characteristics: MHz, clock inputs, fmax measured when input duty cycle 50%. outputs measured time with input transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B OCTOBER 1996
(S-CQCC-N**)
TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
TERMINALS
0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 10/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with metal lid. terminals gold plated. Falls within JEDEC MS-004
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
0.775 (19,69) 0.745 (18,92)
0.775 (19,69) 0.745 (18,92)
0.920 (23,37) 0.850 (21,59)
1.060 (26,92) 0.940 (23,88)
0.260 (6,60) 0.240 (6,10)
MS-100 VARIATION
0.070 (1,78) 0.045 (1,14)
0.045 (1,14) 0.030 (0,76)
0.020 (0,51)
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
0.430 (10,92)
14/18 ONLY vendor option
4040049/E 12/2002
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width.
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20)
Gage Plane 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,75) 0.337 (8,55)
0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI003E JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.020 (0,51) 0.014 (0,35)
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27)
0.010 (0,25)
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.291 (7,39) 0.010 (0,25)
Gage Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) 0.012 (0,30) 0.004 (0,10) PINS 0.004 (0,10)
0.410 (10,41) 0.400 (10,16)
0.462 (11,73) 0.453 (11,51)
0.510 (12,95) 0.500 (12,70)
0.610 (15,49) 0.600 (15,24)
0.710 (18,03) 0.700 (17,78) 4040000/E 08/01
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0.006 (0,15). Falls within JEDEC MS-013
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements.
Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
Other recent searches
SP-51 - SP-51 SP-51 Datasheet
SN74BCT534 - SN74BCT534 SN74BCT534 Datasheet
SN54BCT534 - SN54BCT534 SN54BCT534 Datasheet
NX7338BF-AA - NX7338BF-AA NX7338BF-AA Datasheet
MHW9227A - MHW9227A MHW9227A Datasheet
MAC3030-8 - MAC3030-8 MAC3030-8 Datasheet
FCP11N60N - FCP11N60N FCP11N60N Datasheet
AT24C02 - AT24C02 AT24C02 Datasheet
2SJ132 - 2SJ132 2SJ132 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
