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L64777 Modulator
Order Number I14031.A
This document contains proprietary information Logic Corporation. information contained herein used disclosed third parties without express written permission officer Logic Corporation. Document DB14-000121-01, First Edition, June 2000. This document describes revision Logic Corporation L64777 Modulator will remain official reference source revisions this product until rescinded update. receive product literature, visit http://www.lsilogic.com. Logic Corporation reserves right make changes products herein time without notice. Logic does assume responsibility liability arising application product described herein, except expressly agreed writing Logic; does purchase product from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties. Copyright 2000 Logic Corporation. rights reserved. TRADEMARK ACKNOWLEDGMENT Logic logo design, G10, logo design, trademarks registered trademarks Logic Corporation. other brand product names trademarks their respective companies.
Preface
This book primary reference technical manual L64777 Modulator. contains complete functional description L64777 includes complete physical electrical specifications L64777.
Audience This document assumes that have some familiarity with digital video broadcasting, modulators, related support devices. people benefit from this book are:
Organization
Engineers managers evaluating modulator possible system Engineers designing modulator into system
This document following chapters appendixes:
Chapter Introduction, introduces L64777 Modulator. Chapter Modulator Architecture, describes functional components L64777. Chapter Interfaces, describes L64777 interfaces. Chapter Register Descriptions, describes registers used configure monitor L64777. Chapter Signals, presents signal definitions L64777.
Preface
Chapter Specifications, presents electrical timing specifications L64777. also presents pinout packaging information. Appendix Programming L64777 Serial Host Interface Mode, discusses program L64777 internal registers data tables serial host interface mode. Appendix Divider Settings L64724/34 Connection, lists divider settings typical applications. also describes L64777 connection L64724. Appendix Monitoring Device Internal Signals, describes program test register (14) monitoring device internal signals.
Related Publications
Digital Broadcasting Systems Television Sound Data Services: Framing Structure, Channel Coding Modulation Cable Systems 429, September 1996. Generic Coding Moving Pictures Associated Audio, ISO/IEC 13818-1, MPEG2 Systems, November 1994. G10®-p CW900100 10-Bit Direct Digital Synthesis Digital-to-Analog Converter, Preliminary Datasheet, Logic, September 1998. L64724 Satellite Receiver Technical Manual, Logic, April 2000, order number I14030.
Conventions Used This Manual word assert means drive signal true active. word deassert means drive signal false inactive. Hexadecimal numbers indicated prefix "0x" -for example, 0x32CF. Binary numbers indicated prefix "0b" -for example, 0b0011.0010.1100.1111.
Preface
Contents
Chapter
Introduction Overview Operating Environment Modulator Architecture Introduction Modes 2.2.1 Mode 2.2.2 Mode 2.3.1 Input 2.3.2 Output Signals 2.3.3 Control Interface 2.3.4 Serial Microprocessor Interface Input Synchronization 2.4.1 Sync Acquisition Phase 2.4.2 Sync Tracking Phase FIFO Clock Conversion Sync/EF Reinsertion Unit 2.6.1 Sync Insertion Mode 2.6.2 Error Flag Insertion 2.6.3 Energy Dispersal (Scrambler) Unit Reed-Solomon Encoder 2.7.1 Forward Error Correction (FEC) 2.7.2 Error Handling Correction Convolutional Interleaver Bytes M-tuples Converter 2.10 Differential Encoder Mapping 2.11 Square Root Nyquist Filter
Chapter
2-10 2-10 2-13 2-14 2-16 2-17 2-18 2-18 2-18 2-20 2-21 2-22 2-23 2-24 2-26 2-27
Contents
2.12
2.13 2.14 2.15 Chapter
2.11.1 Filter Setup Procedure 2.11.2 Example 2.11.3 Default Filter Characteristics Global Control Module 2.12.1 Numerically Controlled Oscillator (NCO) 2.12.2 Acquisition Phase Using Frequency Measurement Unit 2.12.3 Autoacquisition Mode 2.12.4 Regulation Phase Interpolator Serial Microprocessor Interface Test Unit
2-29 2-30 2-34 2-34 2-35 2-36 2-38 2-39 2-39 2-40 2-41
Interfaces Transport Interface 3.1.1 Synchronization 3.1.2 Synchronization Methods 3.1.3 Transport Error Indicator Handling Serial Control Interface Analog Output Interface Digital Output Interface Register Descriptions Group General-Purpose Registers 4.1.1 Register 4.1.2 Register 4.1.3 Register 4.1.4 Register 4.1.5 Register 4.1.6 Register 4.1.7 Register 4.1.8 Registers 4.1.9 Registers 4.1.10 Register NCO-Related Registers 4.2.1 Register 4.2.2 Register
Chapter
4-10 4-10 4-11
Contents
4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.2.11 4.2.12 4.2.13 4.2.14 4.2.15 4.2.16 4.2.17 4.2.18 Chapter
Register Register Registers Registers Registers Registers Register Registers Registers Registers Registers Registers Register Register Register Register
4-12 4-13 4-13 4-13 4-14 4-14 4-14 4-14 4-15 4-15 4-15 4-16 4-16 4-16 4-17 4-17
Signals Overview MPEG Transport Stream Multiplexer Signals Status Information Signals Test Signals Control Signals External Signals Analog Signals Serial Microprocessor Interface Signals Specifications AC/DC Specifications 6.1.1 Electrical Ratings 6.1.2 Timing Diagrams L64777 Descriptions Lists 6.2.1 L64777 Electrical Descriptions 6.2.2 Numerical List L64777 6.2.3 Alphabetic List L64777 Package Pinout
Chapter
6-10
Contents
Appendix
Programming L64777 Serial Host Interface Mode Serial Protocol Overview Programming Slave Address Using Serial Interface Write Cycle Using Serial Interface Read Cycle Using Serial Interface Limitations Divider Settings L64724/34 Connection Overview Driver Settings Typical Applications Connecting L64777 Logic L64724 Monitoring Device Internal Signals Customer Feedback
Appendix
Appendix
Figures 2.10 2.11 2.12 2.13 2.14 2.15 2.16 L64777 Operating Environment 429-Compliant Modulation Operation Data Path Phase Frequency Detection with External Analog Output Interface Diagram Required Relation ICLK DIN/DVALIDIN FIFO Clock Conversion Sync Acquisition Phase Sync Tracking Phase FIFO Pointer Concept Transport Error Flag Insertion Scrambler Basic Serial Architecture Shift Register Initialization Sequence Code Word Structure Forward Error Correction Data Path Interleaver Block Diagram Symbol Cutting From Bytes 2-12 2-13 2-14 2-16 2-18 2-19 2-19 2-21 2-22 2-23 2-25
viii
Contents
2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 Tables
Byte Symbol Conversion Differential Encoder Mapping Pulse Shaper Structure Output Scaling Arithmetic Shift Right Square-Root Raised Cosine Filter Loop Diagram Frequency Acquisition Loop Overview Serial Base Address Analog Output Interface Diagram Filter Diagrams Logic Symbol L64777 Input Timing L64777 RESET Timing Diagram L64777 3-state Delay Timing Package 120-Pin PQFP Pinout 120-Pin PQFP (PE) Mechanical Drawing Quick Overview Serial Serial Write/Read Cycle General Call Structure Burst Write Slave (Master-Transmitter, Slave-Receiver) Single Read from Slave CATV Block Diagram Signals between L64724 L64777
2-25 2-26 2-27 2-29 2-34 2-36 2-38 2-40 6-10 6-11
Allocation Coefficient-Bits Phase Default Nyquist Filter Coefficients Group Allocation Reset Values Register Fields L64777 Absolute Maximum Ratings L64777 Recommended Operating Conditions L64777 Characteristics L64777 Preliminary Timing Parameters L64777 Description Summary L64777 Numerical List L64777 Alphabetical List Typical Settings CNT_I CNT_O
2-30 2-32 4-17
Contents
Contents
Chapter Introduction
This chapter provides introduction L64777. consists following sections:
Section 1.1, "Overview," page Section 1.2, "Operating Environment," page
Overview
L64777 chip implements modulator that digital video broadcasting (DVB)-compliant, described document 429. input MPEG-2 system layer-compliant transport stream either parallel byte-wide serial format. chip contains digital signal processing functions, digital-to-analog converters, sampling clock circuitry that generates quadrature amplitude modulation (QAM)modulated output signal baseband. Users configure device means serial interface. L64777 chip design based existing Logic L64767 device includes following major enhancements:
internal digital-to-analog converters generate in-phase quadrature baseband signals. on-chip voltage-controlled oscillator improves symbol rate support most frequently used application ranges. serial interface replaces eight-bit microprocessor interface. digital numerically controlled oscillator (NCO) interpolation mode support operation with L64724 device.
L64777 Modulator
Operating Environment
modulator intended follow either MPEG transport stream source (for example, transport multiplexer) satellite receiver, such Logic L64724 (see Figure 1.1). processes MPEG-2 systemcompliant frames input. program sync word block length, chip reinsert sync information. device handles MPEG-specific transport-packet error indication (TEI) internally. Figure L64777 Operating Environment
Analog Modulated Components
MPEG Transport MPEG Transport Stream (Digital) QPSK Satellite Receiver Transmission Network L64777 Modulator
Mixer
Cable Network
features L64777 include:
standard 429-compliant modulation operation Highly integrated global synchronization clock control On-chip support symbol rates Msymbols/s Digital interpolation mode support operation with L64724 Four-fold Nyquist filter oversampling Maskable interrupts error conditions Individual module bypass configuration modes baseband outputs both digital analog formats I2C-compatible serial interface control, setup, monitoring various chip parameters User-controllable input synchronization schemes 128, modes Reed-Solomon encoder
Introduction
Frame sync byte reinsertion Input jitter handling Reed-Solomon insertion 128-word circular FIFO buffer IEEE 1149.1 JTAG interface testing Mbytes/s parallel data input Mbits/s serial data input 11.25 Mbaud operation mode operation Easy interface most input sources ambient operation without special cooling devices Unconstrained serial mode allow modulation non-MPEG data stream
Operating Environment
Introduction
Chapter Modulator Architecture
This chapter briefly introduces standard modulator chain architecture device uses implement chain. This chapter consists following sections:
Section 2.1, "Introduction," page Section 2.2, "PLL Modes," page Section 2.3, "I/O," page Section 2.4, "Input Synchronization," page 2-10 Section 2.5, "FIFO Clock Conversion," page 2-16 Section 2.6, "Sync/EF Reinsertion Unit," page 2-17 Section 2.7, "Reed-Solomon Encoder," page 2-20 Section 2.8, "Convolutional Interleaver," page 2-23 Section 2.9, "Bytes M-tuples Converter," page 2-24 Section 2.10, "Differential Encoder Mapping," page 2-26 Section 2.11, "Square Root Nyquist Filter," page 2-27 Section 2.12, "Global Control Module," page 2-34 Section 2.13, "Interpolator," page 2-39 Section 2.14, "Serial Microprocessor Interface," page 2-40 Section 2.15, "Test Unit," page 2-41
L64777 Modulator
Introduction
L64777 implements modulator processing chain defined 429. This processing chain illustrated Figure 2.1. Figure 429-Compliant Modulation Operation
Energy Dispersal (204,188) Encoder Convol. Interleaver Byte m-tuple conversion Differential Encoder Mapping Square Root Nyquist Filter
Figure block diagram L64777 architecture. input clock drives only input synchronizing stage. OCLK, which four times symbol rate, base residual processing. numerically controlled oscillator (NCO) module allows L64777 interface with Logic L64724. this case, chip must receive L64724 PCLK clock; thus, byte_clock output from L64724 must applied ICLK. This assumes PCLK generated byte clock.
Modulator Architecture
Figure
Data Path
PCLK divided ICLK NCO* freq compare Interpolator*
Data ICLK
Input Sync Stage
Circular Buffer FIFO Word
Sync Error flag Reinsertion Energy Dispersal
(204,188) Encoder Convol. Interleaver Byte m-tuple Diff. Encoder Mapping Square Root Nyquist Filter
Introduction
Global Control Synchronization Start/Stop Signals Generation
OCLK
Symbol Clock Generation (incl. Phase Freq. Comp.)
OCLK
SCAN chain JTAG Test RAMbist
Serial Microprocessor Interface
Only used Mode
mapping supports 128, QAM. input device MPEG-2 compliant transport stream; output consists baseband signals
Modes
Connecting L64777 satellite receiver Logic satellite decoder chip requires circuits lock input output clocks. modes achieve this:
Mode uses phase/frequency detector dividers L64777 accept external VCO. Mode connects PCLK output L64724 L64734 L64777 PCLK clock input, connects byte clock output ICLK input L64777. This also called Numerically Controlled Oscillator (NCO) mode operation. This mode dedicated connection L64724 (see Appendix Divider Settings L64724/34 Connection).
PLL_MODE[1:0] pins values shown page 5-6. change during operation.
2.2.1 Mode
Figure shows phase frequency detection external voltage-controlled oscillator (VCO) loop. Choose between frequency phase detection through microprocessor interface.
Modulator Architecture
Figure
Phase Frequency Detection with External
FREQ_PHASE_COMP (From Microprocessor)
Phase Detect Load Value Frequency Detect CNT_I
current PLL_CS
CNT_O
Load Value
ICLK
OCLK From
Prescalers (CNT_I) divider (CNT_O) feedback loop generate internal operating clock (OCLK). Program 15-bit prescalers through microprocessor interface, selecting values CNT_I CNT_O that minimize CNT_O reach required ratio.
2.2.2 Mode
Mode PCLK input provides external clock. L64777 uses internal lock transport byte clock, provided ICLK. chip generates OCLK internally. Select PCLK least twice frequency internal OCLK. Appendix Divider Settings L64724/34 Connection, describes connection between L64777 L64724 Mode operation. Consecutive sync blocks have length between them. Thus, L64777 convert input block block with insertion, long size 128-byte circular input buffer sufficient insert gaps cope with possible jitter. encoder with 16-parity insertion, L64777 selects size circular input buffer with sufficient margin. When operating public synchronous networks (such synchronous digital hierarchy, SDH, plesiochronous digital hierarchy, PDH), system designer must consider possible jitter input network. design L64777 permits short-term deviations input-to-output frequency bytes before FIFO overrun condition occurs. This sufficient operations networks.
Modes
Anetworks, must prebuffer input data continuous frame rate chip input. high input jitter occurs over Awithout prebuffer, whole regulation input-to-output frame rate fails. must design size prebuffer according maximum jitter expected over asynchronous transfer mode (ATM) network.
following subsections describe input output L64777.
2.3.1 Input
Modulator accepts serial input data maximum clock frequency ICLK pin. Byte-Parallel Input mode (Parallel mode), maximum frequency ICLK MHz. DVALIDIN distinguishes between valid invalid input data DIN[7:0]. ERRORIN marks incorrect packets transport header, case preceding device passes erroneous information. input error flag transferred into TRANSPORT_ERROR_INDICATOR MPEG transport packets. Either FSTARTIN pulse SYNC_BYTE detection (0x47 MPEG transport packets) establishes input synchronization. FSTARTIN pulse marks first bit, most significant MPEG SYNC_BYTE Serial Input mode (Serial mode), SYNC_BYTE Parallel mode. FSTARTIN pulse synchronizes process forming bytes from bits Serial mode. such synchronization signal applied, input synchronizer searches programmed SYNC_BYTE occurring programmed sync length. Parallel mode, L64777 assumes byte boundaries correct compares SYNC_BYTE parallel incoming bytes. flywheel circuit stabilizes synchronization SYNC_BYTE, while synchronization external pulses feeds directly into internal control circuits (see Section 2.4, "Input Synchronization," page 2-10).
2.3.2 Output Signals
L64777 outputs components signal separate analog output interfaces (see Figure 2.4). output interface contains internal 10-bit digital-to-analog converters.
Modulator Architecture
Figure
Analog Output Interface Diagram
VDDX1 AVDD1/COMP1
Filter Output 10-Bit
Differential Output QAM_I, QAM_In AVSS1 Functional Test (Test mode selected using mode pins) VREF1 VREF2 VDDX2 AVDD2/COMP2
10-Bit Filter Output
Differential Output QAM_Q, QAM_Qn
AVSS2
On-Chip
Off-Chip
differential outputs terminate externally (the external components must provide termination both differential lines, achieves maximum linearity differential mode). L64777 component outputs available 10-bit digital format. related clock depends mode: OCLK used Mode PCLK used Mode output format programmed either two's complement, sign magnitude representation. analog Q-modulated output signals sampling rate OCLK, which four times symbol rate. input digital-to-analog conversion available also digital format DIG_I DIG_Q pins.
internal L64777 generate OCLK, OCLK input. L64777 selects OCLK based selected mode. OCLK drives Nyquist filter generates symbol-processing clock inside chip after input circular buffer. beginning sync frame output indicated FSTARTOUT signal. FSTARTOUT lets L64777 watch insertion code FIFO read side. long read pointers halted generate gaps, FSTARTOUT remains HIGH number check words plus cycle. example, FSTARTOUT symbol clock cycle long inserted; symbol clock cycles long check words inserted. signal FIRSTOUT indicates head sequence after reset with SSTARTIN signal. negative slope SSTARTIN input controls sequence reset. Note: DVALIDIN must active least ICLK cycle when SSTARTIN HIGH when SSTARTIN LOW.
2.3.3 Control Interface
external uses L64777 serial control interface control setup programmable parameters chip. This interface slavetype only, connected same serial Logic L64724. chip five hardwired MSBs takes LSBs directly from input pins SB_BASE[1:0].
SB_BASE.1 SB_BASE.0
addressing scheme L64777 complies with that Logic L64724, small, seven-bit internal address space, L64777 supports only group group registers. ignores others. Bits [2:0] within first data byte transmitted device specify group.
Modulator Architecture
Group address pointer register (APR); I2C-Compatible Serial Control Interface loads address byte into APR0 (see Appendix "Programming L64777 Serial Host Interface Mode"), programming details. Reading writing from Group causes data transfer with device address specified APR0:
APR0 zero, Serial Control Interface expects write access with data bytes load filter coefficients; does apply autoincrement APR0. APR0 zero, Serial Control Interface expects only single data byte applies autoincrement APR0.
detailed timing serial given Appendix serial runs maximum clock rate. serial control interface transfer reads writes single-byte burst mode. must access status registers with single-byte reads. division factor converting OCLK down symbol clock always four. Input synchronization works ICLK rate, either byte clock. Energy dispersal (scrambling), Reed-Solomon encoding, convolutional interleaving, byte m-tuple conversion, differential encoding, mapping operate symbol clock rate (OCLK/4). final Nyquist filter works OCLK rate. Incoming bits provided with input clock (ICLK) validation signal (DVALIDIN), which indicates rising edges ICLK that carrying valid data. These inputs feed into 128-word circular FIFO buffer. output carries continuous data stream properly locked. Figure
DVALIDIN ICLK Input Waveforms
Required Relation ICLK DIN/DVALIDIN
Invalid Data Valid Data Valid Data Invalid Data
2.3.4 Serial Microprocessor Interface
bidirectional microprocessor interface allows write confidence read-back internal registers. interaction during operation required with microprocessor, registers must configured after RESET guarantee proper operation device. default setup that requires microprocessor download built QAM. L64777, Group register acts sequential download register that feeds bytes filter coefficients. After every write, user read back last written coefficient verify tail entry coefficients shift register. L64777 uses other registers nonsequentially; these read back directly.
Input Synchronization
L64777 transport interface reads data stream from transport source, identifies position synchronization bytes, strips invalid data. transport interface operate either Parallel Serial mode. L64777 synchronize transport interface ways. both modes, works synchronously with ICLK reads signals, including input data, raising edge ICLK.
external synchronization mode, transport interface specifies position external sync byte asserting FSTARTIN HIGH during sync byte input. serial mode, interface must assert signal HIGH during first (MSB) input stream. internal synchronization mode, L64777 does require block start indication finds position programmed sync byte automatically.
transport interface also apply signal DVALIDIN, indicating valid input data, allow gaps between input bytes. avoid cyclic buffer overrun underrun, average data input rate, measured over programmed block length, must differ from nominal payload rate generated signal. circular buffer inside L64777 allows maximum 64-byte compensation input stream.
2-10
Modulator Architecture
Synchronizing modulator with input pulse SSTARTIN sets byte block boundaries with this external pulse. transport interface reinsert programmed sync byte location defined external pulse. both internal external modes, transport interface program block length value sync byte. block length must less than bytes. After L64777 achieves synchronization, either takes sync byte from FIFO, inserts sync byte into modulated stream according programmed sync byte. Only latter action eliminates error input sync byte, long modulator remains synchronized (see Section 2.6.3, "Energy Dispersal (Scrambler) Unit" more information). Given stream consisting sequence packets, sync stage searches preprogrammed sync byte (0x47). Upon meeting sync acquisition criteria, sync stage issues control strobes downstream modules. addition synchronizing L64777 SYNC_BYTEs contained input stream, L64777 forced into synchronization external sync pulses; modulator made reinsert programmed SYNC_BYTE sync pulse position. transport interface either pass transport error indicator (TEI) unchanged from input transport stream, force indicate error with ERRORIN signal. L64777 observes forced signal during sync byte input ignores rest input packet. L64777 input stage operate either Parallel Serial mode. device receives parallel input connection transport layer multiplexers frequency with input lines (CLK, lines data, FSTARTIN, DVALIDIN, required). L64777 mark MPEG frame SYNC_BYTE with pulse FSTARTIN identify beginning frame. Together with FSTARTIN, L64777 insert sync bytes error-correction information into byte frames. Figure shows FIFO clock conversion from ICLK domain OCLK domain.
Input Synchronization
2-11
Figure
FIFO Clock Conversion
INSYNC FIFO SCRAMBLER
Sync Word Block Length Serial/Parallel FSTARTIN SSTARTIN ERRORIN DIN[7:0]* Words Ser/Par Convert Sync Detector Sync Circular Buffer Err.Flg. Data Sync Insert Word Error Insert Flag Pointer Collision Alarm
Sync Word
Scrambler
ICLK domain
OCLK domain
Note that DIN[7:0] valid data, which result D[7:0] DVALIDIN HIGH
L64777 synchronizes input ICLK domain transfers OCLK domain with reserved circular buffer. uses second transfer incoming error flag further insertion into most significant (MSB) second byte sync frame, according MPEG-2 standard. L64777 also synchronizes SSTARTIN through circular buffer, allowing lock beginning long-term sequence SYNC_BYTE location next sync block. this activated after reset, generated sequences free. When using L64777 with L64724, select Parallel mode, which supported with external synchronization pulses. L64724 Mode (204 cycle frames with DVALIDIN during check bytes). transport stream indicates frames with errors. single-line transmission connection serial input L64777 device generally requires synchronizing SYNC_BYTE within
2-12
Modulator Architecture
bitstream. microprocessor interface selects internal synchronization, L64777 looks 8-bit sync pattern repeated DIN[0] input data stream with given period bytes. MPEG-2 transmission, 0x47 204. values programmable chip accommodate applications based MPEG MPEG-derived standards. Parallel operation requires byte-aligning SYNC_BYTE achieve data-dependant synchronization. serial input, L64777 searches SYNC_BYTE possible positions automatically detects byte-alignment. L64777, sync algorithm fixed procedure with programmable values order achieve required functionality lowest possible gate count, select from three values track steps, which number flywheel repetitions required declare states SYNCOK loss-of-sync. There phases sync algorithm procedure: sync acquisition phase, sync tracking phase.
2.4.1 Sync Acquisition Phase
sync acquisition phase, number sync detections required sync loss programmable from designation number track steps. After error-free consecutive detections sync byte correct locations, L64777 declares synchronization; mismatch occurs, goes back search state. Validating detection sync word three times ensures probability false alarm equal (2-8)3 6*10-8. Validating detection sync word five times insures probability false alarm equal (2-8)5 9*10-13. Figure shows states occurring sync acquisition phase. Figure Sync Acquisition Phase
State
Input Synchronization
2-13
abbreviations illustration indicate following states:
sync pattern research state. When detected, transition leads state detected, transition maintains state retest state. Period bytes after detection state detection retested. detected again, transition leads state detected, transition leads back state again tests detection after period correct detection occurs, transition leads sync tracking phase. not, transition leads back
2.4.2 Sync Tracking Phase
sync tracking phase checks detection correct location (i.e., every bytes). mismatches tolerated, last mismatch L64777 declares loss-of-sync goes back state look synchronization. Figure shows states occurring sync tracking phase. Figure
From State
Sync Tracking Phase
State
abbreviations illustration indicate following states:
synchronized state. mismatches occur, transition maintains this state. wrong word detected location where expected, transition leads state tests detection after interval bytes since last detection test. detected, transition leads back synchronized state not, transition leads
2-14
Modulator Architecture
again test detection after period detected, transition leads back synchronized state not, transition leads back look another sync location.
review transitions sync acquisition sync tracking phases:
Transition occurs when word detected. Transition occurs when word detected. Transition occurs when word detected exactly bytes after last detection test. Transition occurs when word been detected bytes after last detection test. This transition activates declaration loss-of-sync.
L64777 activates output SYNCOK state This allows easy measurement synchronization conditions from outside monitoring during normal operation. microprocessor interface also provides SYNCOK information. this interface, L64777 read actual status glitch trap (which detects sync losses between sync status reads). SYNCOK also generate interrupts, SYNCOK interrupt masked (see Section 4.2.1, "Register 12," page 4-10). order subset device with random data (without frame structure), bypass synchronization mechanism setting unconstrained register (see Section 4.1.10, "Register 11," page 4-9).
Input Synchronization
2-15
FIFO Clock Conversion
L64777 uses dual-ported implement circular buffer FIFO function. circular buffer write pointer driven ICLK read pointer driven Symbol clock, OCLK/4. device does prevent collisions pointers; rather, PLL-VCO follow-up time proper initial setup pointer distance must guarantee this. FIFO initialization, L64777 loads user-programmable pointer distance cycles (the FIFO delay value Register Group into read address pointer (after each microprocessor delay register access) sets write address pointer zero (see Figure 2.9). After this initialization, both pointers free, OCLK ICLK frequency relationship determines read write pointers advance. allow outside watching asynchronous pointers, alarm comparator indicates when both pointers equal. Because both counters Gray Code counters which changes occur only bit) spikes glitches asynchronous signals minimized. When specifying microprocessor download value read pointer initialization, must Gray Code. write pointer also Gray Code counter-driven; initializes zero when read counter loaded. Figure FIFO Pointer Concept
Read Pointer
Circular Buffer Words
Zero
Properly programmed delay values Gray Code guarantee that read pointer directly opposite write pointer most time; this increases system immunity against frequency swings, which might occur during phases unstable input signal. Smaller distances also reduce system delay.
2-16
Modulator Architecture
hexidecimal address sequence read (underlined) write pointers L64777 download through microprocessor interface starts with beginning read pointer value. write pointer start value always fixed zero. Every time L64777 accesses FIFO delay value microprocessor interface (FDEL, Section 4.1.3, "Register page 4-5), pointers reset these values. L64777 programmed FIFO Autoreset mode (see Section 4.1.7, "Register page 4-7), forces pointers value FDEL register read side zero write side after every FIFO collision. Attention: only legal load values read pointer Gray Code numbers with even parity, which means even number (underlined above table). Therefore, FIFO delay increment only steps two. device achieves maximum delay with value 0x41; optimum (center) distance overrun underruns 0x60.
Sync/EF Reinsertion Unit
following subsections describe Sync/EF modes, error flag insertion, scrambler.
Sync/EF Reinsertion Unit
2-17
2.6.1 Sync Insertion Mode
Sync/EF unit inserts sync words that mode programmed (see Section 4.1.2, "Register page 4-4). Sync insertion useful work against errors sync bytes, even sync already inserted stream. bitstream contains sync bytes that device uses synchronization, regenerated sync bytes conceal single errors synchronization pattern. unsynchronized states L64777 bypasses data bits without modification sync byte. After establishes synchronization states S5), device inserts regenerated sync pattern based programming Register
2.6.2 Error Flag Insertion
next processing task error flag handling MPEG-2 transport packets. ERRORIN indicates decoder error first byte frame, L64777 sets TRANSPORT_ERROR_INDICATOR MPEG-2 packet. This second byte packet (see Figure 2.10). there error indication, L64777 passes TRANSPORT_ERROR_INDICATOR transparently. Figure 2.10 Transport Error Flag Insertion
Errorin FstartIn Din[0] SYNC_BYTE (0x47) Start transport packet .don't care /Error.
2.6.3 Energy Dispersal (Scrambler) Unit
function Scrambler specified serial domain Digital Broadcasting Systems Television Sound Data Services: Framing Structure, Channel Coding Modulation Cable Systems. energy dispersal module (scrambler) operates Parallel mode based algorithm serial domain. Figure 2.11 illustrates basic serial architecture Scrambler.
2-18
Modulator Architecture
Figure 2.11 Scrambler Basic Serial Architecture
Shift_Enable Initial Load
Shift Register
Control
Bitstream
Scrambled Bitstream
scrambler block consists major modules: generate pseudo-random binary sequence (PRBS) that modifies incoming data stream, other control module that properly aligns data with PRBS. PRBS descrambler module produces characterized following generator polynomial: initialization, choose specific value 15-tap shift register (see Figure 2.12). Figure 2.12 Shift Register Initialization Sequence
L64777 uses special sync word (0xB8), generated inverting every eighth transport sync word (0x47), align descrambler with incoming data stream. L64777 applies first PRBS first data following inverted sync byte freezes scrambler register contents during gaps check words. During following noninverted sync words, descrambler sequence generator kept operation does modify data stream. L64777 resets descrambler sequence after every inverted sync word.
Sync/EF Reinsertion Unit
2-19
SSTARTIN input signal preset phase inverted SYNC_BYTE whole scrambler sequence. microprocessor switch scrambler module through Register (see Section 4.1.4, "Register page 4-5). selected microprocessor control applies sequence Start, Run, Disable modes, depending programmed sync block length values Register (see page 4-6).
Reed-Solomon Encoder
Reed-Solomon (RS) error correction codes systematic operate bytes rather than single-bit data streams. codes expressed convention numbers, first indicating total code word length (N), second indicating number message bytes (K). difference between these numbers number check bytes. uses this generator polynomial codes:
where (checkbytes), root binary primitive polynomial:
data byte (d7, d6,.d1, identified with element (256), finite field with elements. error-correcting power code related number redundant check symbols code words. general, code with check symbols code word correct byte errors code word. Higher redundancy allows more errors corrected. devices have specific lexicon associated with their ability correct transmission messages; terms used variables Reed-Solomon Core follows:
2-20
Modulator Architecture
Check Bytes encoder generates appends check bytes incoming message according Reed-Solomon error-correction encoding. decoder uses check bytes locate correct errors transmission. Detection Power Detection power minimum value maximum value
Message Length message comprised multiple bytes. size message varies depending code word length check bytes used, where Symbol Size symbol size bits fixed. Code Word Length This number message bytes number check bytes Number Error Corrections This variable maximum number error corrections performed decoder. maximum value
2.7.1 Forward Error Correction (FEC)
requires encoder that appends redundant check information message before transmission. bytes with indeterminate number bits referred symbols. message symbols following redundant check symbols make code words. check symbols redundant because they derived from message appended message. Check symbols also referred "redundant check bytes," sometimes "correction bytes." Figure 2.13 illustrates code word. Figure 2.13 Code Word Structure
Code Word Bytes Message Bytes Redundant Check Bytes
Reed-Solomon Encoder
2-21
code word block bytes that includes message symbols check bytes (R). check bytes, symbols, some fraction message symbols. large number check symbols allows decoder correct large number transmission errors. redundant check symbols message allow decoder receiving transmission line detect transmission errors reconstruct original message content. Figure 2.14 shows block diagram basic encoder decoder functions transmission system. Figure 2.14 Forward Error Correction Data Path
Encoder Message Data Message Check Bytes Code Word Channel Decoder Code Word Check Bytes Message Corrected Message Data
After generating code word, encoder transmits decoder. decoder compares bitstream message data encoding check bytes detect transmission errors. L64777 reconstruct original message precisely from check symbols, long code word more than byte errors, where number redundant check bytes.
2.7.2 Error Handling Correction
error occurs when transmitted received vice versa. byte error occurs when more bits byte have errors. example, byte with only error counted byte error, byte with errors (all bits inverted) also counted byte error. long code word more than byte errors, decoder corrects errors. achieve encoding lowest possible gate count power consumption, check byte parameters encoder L64777 fixed according standard. When encoder switched off, data feeds through without check-word insertion internal delay clock cycles.
2-22
Modulator Architecture
Convolutional Interleaver
Figure 2.15 block diagram convolutional interleaver system, which rearranges ordering sequence symbols deterministic manner. periodic interleaver following characteristics:
minimum separation interleaver output symbols symbols that separated less than symbols interleaver input. burst errors inserted channel results single errors deinterleaver output.
scheme also referred convolutional interleaver/ deinterleaver (based Forney approach). Figure 2.15 Interleaver Block Diagram
Encoder CHANNEL Decoder
L64777 interleaver performs periodic interleaving with fixed parameters: desired interleaving depth, defined
values interleaver L64777 are: 204, switch interleaver. fully transparent with intrinsic delay three clock cycles. main modules configured RAM-based delay lines implement proper delay individual data bytes, controller handle generate strobes needed subsequent modules data path.
Convolutional Interleaver
2-23
interleaver must recover block boundaries, SSTARTIN indicates them internal strobes; also resets interleaver sequence. program interleaver that data into interleaver before very first arrival SSTARTIN negative slope zero. This eases operation verification debugging during development when interleaver completely initialized with zero values. must apply fresh reset feed zeros after active SSTARTIN slope. interleaver deinterleaver, sequence, output original byte stream after delay
Delay
L64777, Delay 2244 clock cycles. Thus, delay from time first input byte first valid output byte maximum delay path interleaver half this value, which 1122 valid clock cycles. mode, interleaver inserts invalid cycles eight-byte sequence, which proportionally increases delay time. zero delay path interleaver delivers data with propagation delay three clock cycles. This equal delay interleaver when off.
Bytes M-tuples Converter
This unit cuts down bytes slices bits. programming parameter, mSize (see Section 4.1.2, "Register page 4-4), must order oldest byte first. Digital Broadcasting Systems Television Sound Data Services: Framing Structure, Channel Coding Modulation Cable Systems detailed specification. When cutting six-bit symbols, cuts three bytes into four symbols. case four-bit symbols trivial (eight bits split into sets four bits each). Figure 2.16 outlines basic principle symbol cutting bytes. Modes similar.
2-24
Modulator Architecture
Figure 2.16 Symbol Cutting From Bytes
Byte Byte Byte
Symbol
Symbol
Symbol
Symbol
Symbol
Symbol
Symbol
Symbol
Symbol
Symbol
general control unit feeds packets eight bytes valid indicator convertor. Thus, conversion shown Figure 2.17. Figure 2.17 Byte Symbol Conversion
Byte Byte Byte Byte
Byte Byte Byte Byte Byte Byte
Byte Byte Byte Byte Byte
Time
Byte Byte Byte Byte Byte Byte Byte
Time
Bytes M-tuples Converter
Byte Byte Byte Byte Byte Byte Byte Byte
Byte-to-Symbol Conversion
2-25
2.10 Differential Encoder Mapping
This block performs differential encoding mapping QAM, specified Digital Broadcasting Systems Television Sound Data Services: Framing Structure, Channel Coding Modulation Cable Systems, baseline document, extensions. mapping taken from document 1190. encoder performs differential encoding most significant bits each symbol, shown block diagram Figure 2.18 specified equations 2.2. Figure 2.18 Differential Encoder Mapping
From Interleaver Byte M-tuple Differential Encoder Mapping Q[3:0] I[3:0]
clarify underlying concepts Figure 2.18, here examples: bits bits [1:0]. bits bits [3:0].
Equation Equation
Mapping performs table look-up concatenation least significant bits each symbol with differentially generated bits mode, mapping block differential encoder maps 6-tuples 3-bit values output. mode, maps 4-tuples 2-bit values. lower modes, aligns output values stuffs least-significant (LSB) with ones.
2-26
Modulator Architecture
Differential encoding infinite error propagation. switch independently from mapping function (see Register page 4-8).
2.11 Square Root Nyquist Filter
This pulse-shaper module implements programmable square-root raised cosine filtering function with default roll-off factor. precision internal Nyquist filter computations, width output data bus, sufficient modulations 256. filter operates four times oversampling rate. Figure 2.19 illustrates structure pulse shaper. Figure 2.19 Pulse Shaper Structure
From Coefficient Register (Register
offset
adder Numbers represent coefficient word width structures
QS[19:0] IS[19:0], Shifter
Note that bits channel result length each coefficient register (211) plus length (24) plus number stages 25). total number coefficients (there coefficient each four phases multiplied structure, which contains multipliers). Each branches filter, realized polyphase structures. Each filter consists four filter branches, which compute 1-phase filter results symbol rate. Thus, L64777 Nyquist filter module generates desired pulse shape combining outputs four identical filter branches
Square Root Nyquist Filter
2-27
oversampling factor four, filter executes above sequence four times symbol rate mode). Each multiply accumulator (MAC)-structure contains multipliers whose outputs desired result. pulse shaper module connects input each multiplier delayed version filter input data; other multiplier input connected four coefficient registers through multiplexer. pulse shaper clocks delay line IData QData with symbol clock rate. coefficient multiplier width described below. pulse shaper interprets data two's complement. Each MACstructure contains additional input adder array allow addition 11-bit value compensate offset. pulse shaper treats these offset coefficients like regular coefficients, except that adds them directly outputs. There offset coefficient each phase. shifter block adjusts internally generated filter result accommodate limited range internal D/A-converter. standard mapping after reset five-bit shift right, which means IS[5] I[0], IS[6] I[1] shifter treats Q-branch accordingly. applying value different from zero BITS_TO_SHIFT[3:0] input shifter (using Register shifter connects that lowest bits truncated, while more significant bits hooked outputs. BITS_TO_SHIFT input assume maximum value thus mapping IS[15] I[0], IS[16] I[1], filter output value limited maximum positive negative values before shifting, user's responsibility download coefficients appropriate shifting value avoid output overflow underflow. Figure 2.20 illustrates output scaling arithmetic shift right.
2-28
Modulator Architecture
Figure 2.20 Output Scaling Arithmetic Shift Right
BITS_TO_SHIFT[3:0]
Shifter IS[19:0]
I[9:0]
Shifter QS[19:0]
Q[9:0]
shifter treats value BITS_TO_SHIFT[3:0] like coefficient, value available separately every phase. This means that hardware filter multiplexed such that there same coefficient registers channel, each MACs switches between four banks coefficients cyclically, driven OCLK. Setting coefficients zero (except center coefficient, which offers bypass mode filter. interpolator following Nyquist filter receives 12-bit resolution Mode Program shifter accordingly make increase precision available interpolator; example: rather than
2.11.1 Filter Setup Procedure
filter module loaded with filter coefficients sequentially, with four blocks bytes PHASE_0, PHASE_1, PHASE_2, PHASE_3 registers (Register Group same data controls data path parallel. Also, filter loaded with four BITS_TO_SHIFT 11-bit offset value each phase. specified within bytes each phase, shown Table 2.1. complete setup sequence consists bytes four phases. filter organizes coefficient registers each register bank described below, using coefficient enumeration shown block diagram. Note that meaningful operation performed while filter being programmed, since coefficients being shifted while ones programmed
Square Root Nyquist Filter
2-29
shown Figure 2.18, filter shifts four coefficient register banks (Register sequentially, starting with register proceeding down this configuration, shifts bank first, then bytes bank bank and, finally, bank Table shows exact allocation bits within each bank.
2.11.2 Example
Assuming filter configuration bits located host microprocessor array bytes addressed with 195], filter coefficients place phase coefficients registers 48], phase 97], phase 146], phase [147 195]. download this array, microprocessor must write bytes [195 down sequentially into address register, highest array address first. After write cycles, four coefficient register banks completely configured. During configuration, filter operational save gates avoiding double buffering coefficient registers. different modes, filter must load appropriate sets coefficients shifter values. default coefficients square-root raised cosine filter. filter sets coefficients Table after reset, overwrite them with external programming through I2C-compatible interface. Table
c0.7 c1.7 c2.7 c3.7 c4.7 c5.7
Allocation Coefficient-Bits Phase
c0.6 c1.6 c0.10 c2.6 c3.6 c2.10 c4.6 c5.6 c4.10 c0.5 c1.5 c0.9 c2.5 c3.5 c2.9 c4.5 c5.5 c4.9 c0.4 c1.4 c0.8 c2.4 c3.4 c2.8 c4.4 c5.4 c4.8 c0.3 c1.3 c2.3 c3.3 c4.3 c5.3 c0.2 c1.2 c1.10 c2.2 c3.2 c3.10 c4.2 c5.2 c5.10 c0.1 c1.1 c1.9 c2.1 c3.1 c3.9 c4.1 c5.1 c5.9 c0.0 c1.0 c1.8 c2.0 c3.0 c3.8 c4.0 c5.0 c5.8
2-30
Modulator Architecture
Table
c6.7 c7.7 c8.7 c9.7 c10.7 c11.7 c12.7 c13.7 c14.7 c15.7 c16.7 c17.7 c18.7 c19.7 c20.7 c21.7 c22.7
Allocation Coefficient-Bits Phase (Cont.)
c6.6 c7.6 c6.10 c8.6 c9.6 c8.10 c10.6 c11.6 c10.10 c12.6 c13.6 c12.10 c14.6 c15.6 c14.10 c16.6 c17.6 c16.10 c18.6 c19.6 c18.10 c20.6 c21.6 c20.10 c22.6 c6.5 c7.5 c6.9 c8.5 c9.5 c8.9 c10.5 c11.5 c10.9 c12.5 c13.5 c12.9 c14.5 c15.5 c14.9 c16.5 c17.5 c16.9 c18.5 c19.5 c18.9 c20.5 c21.5 c20.9 c22.5 c6.4 c7.4 c6.8 c8.4 c9.4 c8.8 c10.4 c11.4 c10.8 c12.4 c13.4 c12.8 c14.4 c15.4 c14.8 c16.4 c17.4 c16.8 c18.4 c19.4 c18.8 c20.4 c21.4 c20.8 c22.4 c6.3 c7.3 c8.3 c9.3 c10.3 c11.3 c12.3 c13.3 c14.3 c15.3 c16.3 c17.3 c18.3 c19.3 c20.3 c21.3 c22.3 c6.2 c7.2 c7.10 c8.2 c9.2 c9.10 c10.2 c11.2 c11.10 c12.2 c13.2 c13.10 c14.2 c15.2 c15.10 c16.2 c17.2 c17.10 c18.2 c19.2 c19.10 c20.2 c21.2 c21.10 c22.2 c6.1 c7.1 c7.9 c8.1 c9.1 c9.9 c10.1 c11.1 c11.9 c12.1 c13.1 c13.9 c14.1 c15.1 c15.9 c16.1 c17.1 c17.9 c18.1 c19.1 c19.9 c20.1 c21.1 c21.9 c22.1 c6.0 c7.0 c7.8 c8.0 c9.0 c9.8 c10.0 c11.0 c11.8 c12.0 c13.0 c13.8 c14.0 c15.0 c15.8 c16.0 c17.0 c17.8 c18.0 c19.0 c19.8 c20.0 c21.0 c21.8 c22.0
Square Root Nyquist Filter
2-31
Table
c23.7 c24.7 c25.7 c26.7 c27.7 c28.7 c29.7 c30.7 offset.7
Allocation Coefficient-Bits Phase (Cont.)
c23.6 c22.10 c24.6 c25.6 c24.10 c26.6 c27.6 c26.10 c28.6 c29.6 c28.10 c30.6 offset.6 c30.10 c23.5 c22.9 c24.5 c25.5 c24.9 c26.5 c27.5 c26.9 c28.5 c29.5 c28.9 c30.5 offset.5 c30.9 c23.4 c22.8 c24.4 c25.4 c24.8 c26.4 c27.4 c26.8 c28.4 c29.4 c28.8 c30.4 offset.4 c30.8 c23.3 c24.3 c25.3 c26.3 c27.3 c28.3 c29.3 c30.3 offset.3 shift.3 c23.2 c23.10 c24.2 c25.2 c25.10 c26.2 c27.2 c27.10 c28.2 c29.2 c29.10 c30.2 offset.2 offset.10 shift.2 c23.1 c23.9 c24.1 c251 c25.9 c26.1 c271 c27.9 c28.1 c29.1 c29.9 c30.1 offset.1 offset.9 shift.1 c23.0 c23.8 c24.0 c25.0 c25.8 c26.0 c27.0 c27.8 c28.0 c29.0 c29.8 c30.0 offset.0 offset.8 shift.0
Table
Default Nyquist Filter Coefficients
Phase0 Phase1 Phase2 Phase3
2-32
Modulator Architecture
Table
Default Nyquist Filter Coefficients (Cont.)
Phase0 -191 -191 Phase1 -184 Phase2 Phase3 -184
Square Root Nyquist Filter
2-33
default offset value four phases shift shifter default, bits.
2.11.3 Default Filter Characteristics
Figure 2.20 shows characteristics L64777 default filter. Figure 2.21 Square-Root Raised Cosine Filter
Magnitude Response (dB) Magnitude Response (dB)
-100 -100 -150 -150
Normalized Frequency (Nyquist 1)== Normalized frequency (Nyquist
Phase (degrees) Phase (degrees)
-2000 -2000 -4000 -4000
-6000 -6000 -8000 -8000
Normalized Frequency (Nyquist 1)== Normalized frequency (Nyquist
2.12 Global Control Module
L64777 interface supports serial parallel input modes input interface. global control generates clocking input output interfaces; also controls data path. contains necessary logic chain processing units together.
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Modulator Architecture
global control manages output data stream that continuous gaps between symbols), assuming that incoming data rate constant average). achieve this, must derive output clock OCLK from input transport stream rate. module consists independent clock dividers ICLK OCLK. dividers 15-bit binary counters that have count sequence length that programmable through Registers through default values written external microprocessor are: OCLK divider ICLK divider QAM.
2.12.1 Numerically Controlled Oscillator (NCO)
Mode generates internal clocking (OCLK, SCLK) control information interpolator. locked ICLK clock operates with processing clock PCLK provided from L64724. PCLK must least twice fast necessary OCLK. lock loop with jitter, program with frequency close ideal value obtained from formulae given other modes. phase loop second step does fine regulation (see Figure 2.22). find required initial frequency, device supports modes: frequency measurement unit, automated frequency acquisition. These described following sections.
Global Control Module
2-35
Figure 2.22 Loop Diagram
Frequency Measurement Unit NPCLK, N_COUNT, NP_COUNT, NM_COUNT Step Correction Threshold
ICLK
Serial
Virtual FIFO Automatic Frequency Acquisition
Byte Clock Phase Loop CNT_I Divider EXOR CNT_O Divider OCLK Interpolator Ctrl
phase_gain enable_phase_loop Step (for Frequency Selection)
2.12.2 Acquisition Phase Using Frequency Measurement Unit
During acquisition phase, bases measurement assumption that byte clock ICLK input duration either PCLK cycles that input stays within these bounds duration measurement. program duration multiples 256-byte clock cycles REF_DUR register (see Section 4.2.7, "Registers 22," page 4-14). control register (see Section 4.2.3, "Register 14," page 4-12) control start measurement, Measurement Done register indicates successful completion. Register enables interrupt, measurement generates After completion measurement, host reads number byte clock cycles found with appropriate length (from NM_COUNT, N_COUNT, NP_COUNT-see Sections 4.2.10 through 4.2.12), well value (from N_PCLK-see Section 4.2.9).
2-36
Modulator Architecture
host computes following formulae initial step phase where indicates average value.
Equation
from this:
Equation Sync length initial step QAMmode valid bytes
above formulae:
reading from NM_COUNT register. reading from N_COUNT register. reading from NP_COUNT register. reading from N_PCLK register. Sync length number ICLK cycles between sync bytes (for example, 204). Valid bytes number valid bytes during sync interval (for example, 188). ld(QAMmode) number bits symbol.
encoder enabled mode interface L64724 programmed Mode factor sync length valid bytes becomes one. order accurate initial step, measurement must long duration. recommended duration
general OCLK frequency calculated OCLK PCLK
step
Above, step Start measurement toggling "start measurement" (bit control register control register enabled interrupt (through Register 14), interrupt indicates completion.
Global Control Module
2-37
2.12.3 Autoacquisition Mode
ease usage phase automatic frequency acquisition. Enable regulation NCO_LOOP_ENABLE (bit AUTO_ACQUI (bit control register. Figure 2.23 outlines parameter usage during automatic frequency acquisition. Figure 2.23 Frequency Acquisition Loop Overview
init step init step (reg measurement duration (Registers threshold reset virtual FIFO
runs ENABLE_NCO_LOOP (Register
step step virtual FIFO nco_gain reset virtual FIFO (Registers
wait until measurement duration elapsed (Register step update indication will reset upon read register
abs(virt FIFO) threshold
below_thres
below_thres runs AUTO_ACQUI threshold threshold/2 (Register NCO_GAIN NCO_GAIN/2 (Registers
AUTO_ACQUI_RUNNING NCO_GAIN false true
measurement duration measurement duration
(Registers
2-38
Modulator Architecture
Note that virtual FIFO, which indicates FIFO under- over-run, internal location. NCO_GAIN reached smallest possible value AUTO_ACQUISITION terminates. AUTO_ACQUI_RUNNING (Register sets zero, indicating termination. enabled, issue interrupt this condition. This procedure updates step until contents virtual FIFO zero during measurement duration. ENABLE_NCO_LOOP AUTO_ACQUI set, also possible parameters loop through microprocessor interface frequency acquisition fully controlled microprocessor. monitoring purposes, possible read current step NCO_GAIN using microprocessor interface.
2.12.4 Regulation Phase
When ENABLE_PHASE_LOOP control register (Register loop starts running phase compare between divided reference divided feedback clock. must counters CNT_I CNT_O according rules applied other modes Registers through phase loop relatively small gain, which adjusted address achieves phase lock only initial frequency already close desired range.
2.13 Interpolator
Mode interpolator retimes output samples that Nyquist filter calculated. interpolator clocked with PCLK generates output samples PCLK sampling grid. interpolator takes required retiming information from NCO. PCLK least twice frequency original OCLK obtained formula Mode square-root raised cosine filter also compensates sin(x)/x frequency characteristic digital-toanalog converter with faster sampling grid.
Interpolator
2-39
Another consideration that interpolator receives 12-bit input from Nyquist filter. shifter Nyquist filter accordingly (for example: Mode shifter value (which defined filter coefficients Register Group Mode shifter value
2.14 Serial Microprocessor Interface
external microprocessor controls modes operation, QAM. also controls mode input synchronization, that whether lock synchronization sync bytes input pulses. microprocessor interface downloads filter coefficients delay value proper FIFO initialization. microprocessor interface uses I2C-compatible serial control protocol. signal behavior described Appendix interface slave-only master serial bus. base address component composed fixed five-bit address selectable bits, which through SB_BASE[1:0] (see Figure 2.24). Application these bits must static basis ensure proper operation. Figure 2.24 Serial Base Address
L64777 output pins microprocessor interface provide error indications (for example, FIFO alarm signal). following interface signals used: Serial control line Serial data access
INT_n Interrupt, open drain output same type two-wire serial interface available Logic L64724.
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Modulator Architecture
Attention:
internal microprocessor registers doublebuffered, they influence processing modes L64777 asynchronously during operation. Thus, mode changes place chip undefined state until SSTARTIN pulse synchronously resets sequences data path. When FIRSTOUT pulse grants sequence reset output, chip becomes fully operational again. normal chip initialization procedure follows: Reset after power-up. Initialize microprocessor registers. Apply negative slope SSTARTIN reset sequences beginning next sync block. Apply negative slope SSTARTIN after mode changes from microprocessor interface wait FIRSTOUT.
Also, serial interface requires clock internal operation, either through OCLK input from internal program device. Furthermore, there lower limit this clock: frequency must least eight times that SCL.
2.15 Test Unit
L64777 supports:
Full scan test BIST RAMs JTAG boundary scan Digital-to-analog conversion test tests
Select L64777 test modes through FTMODE pins. default values normal operation are: FTMODE 000, SCAN_ENABLE cleared, outputs high-impedance.
Test Unit
2-41
guarantee proper operation L64777 printed circuit board environment, additional IEEE 1149.1 JTAG module included device, which operates following pins:
TRSTn (output)
Special test modes applicable further functional testing, test digital-to-analog converters.
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Modulator Architecture
Chapter Interfaces
following chapter describes interfaces chip interface operation modes. consists following sections:
Section 3.1, "Transport Interface," page Section 3.2, "Serial Control Interface," page Section 3.3, "Analog Output Interface," page Section 3.4, "Digital Output Interface," page
Transport Interface
task transport interface read data stream from transport source, identify position synchronization bytes, strip invalid data. transport interface operate either parallel serial mode.
3.1.1 Synchronization
L64777 synchronize transport interface ways. both modes, works synchronously with ICLK reads signals, including input data, raising edge ICLK.
external synchronization mode, transport interface specifies position external sync byte asserting FSTARTIN HIGH during synch byte input. serial mode, interface must assert signal HIGH during first (MSB) input stream. internal synchronization mode, L64777 does require block start indication finds position programmed sync byte automatically.
L64777 Modulator
3.1.2 Synchronization Methods
transport interface also apply signal DVALIDIN, indicating valid input data, allow gaps between input bytes. avoid cyclic buffer overrun underrun, average data input rate, measured over programmed block length, must differ from nominal payload rate generated signal. circular buffer inside L64777 allows maximum 64-byte compensation input stream. Synchronizing modulator with input pulse SSTARTIN sets byte block boundaries with this external pulse. transport interface reinsert programmed sync byte location defined external pulse. both internal external modes, transport interface program block length value sync byte. block length must less than bytes. After L64777 achieves synchronization, inserts sync byte into modulated stream according programmed sync byte. This advantage eliminating error input sync byte long modulator remains synchronized.
3.1.3 Transport Error Indicator Handling
transport interface either pass transport error indicator (TEI) unchanged from input transport stream, force indicate error with ERRORIN signal. L64777 observes forced signal during sync byte input ignores rest input packet.
Serial Control Interface
L64777 uses serial control interface control setup programmable parameters chip. This interface slave-type only, connected same serial Logic L64724.
Interfaces
chip five hardwired MSBs takes LSBs directly from input pins SB_BASE[1:0].
SB_BASE.1 SB_BASE.0
addressing scheme L64777 complies with that Logic L64724, but, small 7-bit internal address space, L64777 supports only group group location [2:0] within first data byte transmitted device specifies group. Group address pointer register (APR); Serial Control Interface loads following data byte APR0. Reading writing from Group causes data transfer with device address specified APR0:
APR0 zero, Serial Control Interface expects write access with data bytes load filter coefficients; does apply autoincrement APR0. APR0 zero, Serial Control Interface expects only single data byte applies autoincrement APR0.
L64777 ignores Group Groups does apply reading writing from them. detailed timing serial given Appendix serial designed maximum clock rate. serial control interface transfer reads writes single-byte burst mode. must read access status registers single-byte read.
Analog Output Interface
L64777 puts component signal separate analog output interfaces (see Figure 3.1). output interface contains internal 10-bit digital-to-analog converters.
Analog Output Interface
Figure
Analog Output Interface Diagram
VDDX1 AVDD1/COMP1
Filter Output 10-Bit
Differential Output QAM_I, QAM_In AVSS1 Functional Test (Test mode selected using mode pins) Vref1 Vref2 VDDX2 AVDD2COMP2
10-Bit Filter Output
Differential Output QAM_Q, QAM_Qn
AVSS2
On-Chip
Off-Chip
Figure shows typical application interfacing with outputs L64777 DACs.
Interfaces
Figure
Filter Diagrams
µF/16
QAM_I R169
QAM_IN
AD8048AR µF/16
-5VA
µF/16
QAM_Q
QAM_QN
AD8048AR µF/16
-5VA
Analog Output Interface
device separate differential outputs component. differential outputs terminate externally (that external components must provide termination both differential lines, achieves maximum linearity differential mode).
Digital Output Interface
L64777 component outputs available 10-bit digital format. Depending mode, either OCLK PCLK related clock. output format programmed either two's complement, sine magnitude representation.
Interfaces
Chapter Register Descriptions
This chapter describes registers used configure monitor L64777. sections this chapter are:
Section 4.1, "Group General-Purpose Registers," page Section 4.2, "NCO-Related Registers," page 4-10
Group General-Purpose Registers
registers listed Table described subsequently comprise Group registers. These registers configure monitor operations L64777. (Note that L64777 does Groups 3-7.) filter coefficient register sequential input register, which sequentially shifts bytes filter coefficients. Therefore, external microprocessor must make exactly accesses that register. verify filter coefficients, read back contents Register after writing each coefficient. This does influence shift register shift operation. remaining registers either loaded read back random. address specified writing into Group Address Pointer register. registers L64777 8-bit. Table provides overview allocations L64777 registers. Note that column indicates read-only register; indicates read/write register.
L64777 Modulator
Table
Bit7 FCOEFF.7 SERIN RESERVED SMAG SYNC_ LENGTH.7 SYNC_ BYTE.7 AUTORESET ICNT_O.7
Group Allocation
Bit6 FCOEFF.6 NEWSYNC FDEL.6 RESERVED SYNC_ LENGTH.6 SYNC_ BYTE.6 PLL_INV ICNT_O.6 Bit5 FCOEFF.5 EXTSYNC FDEL.5 IQ_EX SYNC_ LENGTH.5 SYNC_ BYTE.5 IRAM_OFF ICNT_O.5 ICNT_O.13 ICNT_I.5 ICNT_I.13 UNCONSTR. INPUT FIFO_ ALARM_ STORE MEASURE_ DONE Bit4 FCOEFF.4 PLLSET FDEL.4 RESERVED SYNC_ LENGTH.4 SYNC_ BYTE.4 FIFO_OFF ICNT_O.4 ICNT_O.12 ICNT_I.4 ICNT_I.12 GAP.4 ERF_ STORE STEP_ UPDATE Bit3 FCOEFF.3 FREQ_PHA FDEL.3 SCR_OFF SYNC_ LENGTH.3 SYNC_ BYTE.3 DIFF_OFF ICNT_O.3 ICNT_O.11 ICNT_I.3 ICNT_I.11 GAP.3 EVENT Bit2 FCOEFF.2 MSIZE.2 FDEL.2 RS_OFF SYNC_ LENGTH.2 SYNC_ BYTE.2 MAP_OFF ICNT_O.2 ICNT_O.10 ICNT_I.2 ICNT_I.10 GAP.2 Bit1 FCOEFF.1 MSIZE.1 FDEL.1 INT_OFF SYNC_ LENGTH.1 SYNC_ BYTE.1 AMPL ICNT_O.1 ICNT_O.9 ICNT_I.1 ICNT_I.9 GAP.1 MASK_ SYNCOK Bit0 FCOEFF.0 MSIZE.0 FDEL.0
RESERVED SYNC_ LENGTH.0 SYNC_ BYTE.0
RESERVED ICNT_O.0 ICNT_O.8 ICNT_I.0 ICNT_I.8 GAP.0
RESERVED ICNT_O.14 ICNT_I.7 ICNT_I.6
RESERVED I_ICNT_I.14 TRACKSTEPS.1 SYNCOK TRACKSTEPS.0 SYNCOK_ STORE BELOW_ THRES
MASK_ERF
MASK_FIFO _ALARM
RESERVED
AUTO_ ACQ_STATE ACQ_STATE ACQ_STATE ACQUI_ RUNNING FIFO_INT
START AUTO_ ENABLE_ MASK_NCO MASK_ACQ EN_PHASE RESERVED MEASUREACQUISITIO NCO_LOOP _IRQ _IRQ _LOOP MENT N_ON TEST.7 INISTEP.7 TEST.6 INISTEP.6 TEST.5 INISTEP.5 TEST.4 INISTEP.4 TEST.3 INISTEP.3 TEST.2 INISTEP.2 TEST.1 INISTEP.1 INISTEP.9
TEST.0 INISTEP.0 INISTEP.8 INISTEP.16
INISTEP.15 INISTEP.14 INISTEP.13 INISTEP.12 INISTEP.11 INISTEP.10
INISTEP.23 INISTEP.22 INISTEP.21 INISTEP.20 INISTEP.19 INISTEP.18 INISTEP.17
NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN. NCO_GAIN.
Register Descriptions
Table
Bit7
Group Allocation (Cont.)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
REF_DUR.7 REF_DUR.6 REF_DUR.5 REF_DUR.4 REF_DUR.3 REF_DUR.2 REF_DUR.1 REF_DUR.0 REF_DUR. REF_DUR REF_DUR. REF_DUR. REF_DUR. REF_DUR. REF_DUR.9 REF_DUR.8
PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. N_PCLK.7 N_PCLK.6 N_PCLK.5 N_PCLK.4 N_PCLK.3 N_PCLK.2 N_PCLK.1 N_PCLK.0
NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. NM_COUNT. N_COUNT.7 N_COUNT.6 N_COUNT.5 N_COUNT.4 N_COUNT.3 N_COUNT.2 N_COUNT.1 N_COUNT.0 N_COUNT. N_COUNT. N_COUNT. N_COUNT. N_COUNT. N_COUNT. N_COUNT. N_COUNT. N_COUNT. N_COUNT. N_COUNT. N_COUNT.9 N_COUNT.8 N_COUNT. N_COUNT. N_COUNT.
NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. NP_COUNT. CUR_STEP.7 CUR_STEP.6 CUR_STEP.5 CUR_STEP.4 CUR_STEP.3 CUR_STEP.2 CUR_STEP.1 CUR_STEP.0 CUR_STEP. CUR_STEP. CUR_STEP. CUR_STEP. CUR_STEP. CUR_STEP. CUR_STEP.9 CUR_STEP.8 CUR_STEP. CUR_STEP. CUR_STEP. CUR_STEP. CUR_STEP. CUR_STEP. CUR_STEP. CUR_STEP. CUR_UPD.7 CUR_UPD.6 CUR_UPD.5 CUR_UPD.4 CUR_UPD.3 CUR_UPD.2 CUR_UPD.1 CUR_UPD.0 CUR_UPD. CUR_UPD. CUR_UPD. CUR_UPD. CUR_UPD. CUR_UPD. CUR_UPD.9 CUR_UPD.8
FIFO_FULL. FIFO_FULL. FIFO_FULL. FIFO_FULL. FIFO_FULL. FIFO_FULL. FIFO_FULL. FIFO_FULL.0 PH_GAIN.7 PH_GAIN6 PH_GAIN.5 PH_GAIN.4 PH_GAIN.3 PH_GAIN.2 PH_GAIN.1 PH_GAIN.0 EXT_GAP.0 THRESHOLD.0
EXT_GAP.7 EXT_GAP.6 EXT_GAP.5 EXT_GAP.4 EXT_GAP.3 EXT_GAP.2 EXT_GAP.1 THRESHOLD.7 THRESHOLD.6 THRESHOLD.5 THRESHOLD.4 THRESHOLD.3 THRESHOLD.2 THRESHOLD.1
Group General-Purpose Registers
4.1.1 Register
FCOEFF
FCOEFF
Filter Coefficient Shift [7:0] Writing this location shifts 196-byte filter coefficient shift register forward puts this entry queue. Reading this location shows last entry coefficient shift register without shifting reset values fields this register
4.1.2 Register
SERIN NEWSYNC EXTSYNC PLLSET FREQ_PHASE MSIZE
SERIN
Serial/Parallel Input Setting When this L64777 uses DIN[0] serial input considers ICLK clock. When this L64777 uses DIN[7:0] parallel input ICLK byte clock. reset value NEWSYNC Insertion When this L64777 inserts sync word (NEWSYNC, Section 2.6.1) into data stream. When this L64777 leaves data stream unchanged. reset value Synchronization Setting When this L64777 synchronizes positive pulses FSTARTIN pin. When this L64777 synchronizes SYNC_BYTE input stream. reset value Divider Setting When this L64777 forces load dividers. When this L64777 runs dividers normally. reset value
NEWSYNC
EXTSYNC
PLLSET
FREQ_PHASE Frequency/Phase Compare When this L64777 uses frequency compare external control. When this L64777 uses phase compare. reset value
Register Descriptions
MSIZE
Symbol Size This value indicates size symbols: 0b000 0b001 0b010 0b011 0b100 0b101 0b110 0b111 bit. reset value 0b101
[2:0]
4.1.3 Register
FDEL
FDEL
Reserved This reserved.
FIFO Delay [6:0] This parameter indicates FIFO delay value Gray Code. Writing this location loads ICLK address counter with OCLK-driven address counter FDEL value. FIFO automatically reset, L64777 also uses this value OCLK-driven address. reset value 0b110 0000.
4.1.4 Register
SMAG IQ_EX SCR_OFF RS_OFF INT_OFF
SMAG
Sign Magnitude When this L64777 outputs two's complement Nyquist filter. When this L64777 inverts sign output sign magnitude representation. reset value Reserved These bits reserved.
Group General-Purpose Registers
IQ_EX
Channel Exchange When this L64777 exchanges channels Nyquist filter input. When this L64777 leaves data stream unchanged. reset value Scrambler When this L64777 stops scrambler delays data this module three clock cycles. When this scrambler runs normally. reset value Reed-Solomon When this L64777 stops Reed Solomon (RS) encoder delays data this module clock cycles. When this L64777 runs encoder normally. reset value Interleaver When this L64777 stops interleaver delays data this module three clock cycles. When this L64777 runs interleaver DVB-compliant mode. reset value
SCR_OFF
RS_OFF
INT_OFF
4.1.5 Register
SYNC_LENGTH
SYNC_LENGTH Sync Block Length [7:0] This register specifies distance between consecutive SYNC_BYTE values. Legal register values range from sync block length. reset value 0b1011 1011.
4.1.6 Register
SYNC_BYTE
SYNC_BYTE Sync Reference Pattern [7:0] This register specifies sync reference pattern. reset value 0b0100 0111.
Register Descriptions
4.1.7 Register
AUTORESET PLL_INV IRAM_OFF FIFO_OFF DIFF_OFF MAP_OFF AMPL
AUTORESET Automatic Reset Setting When this L64777 loads FIFO address counters with initial values register after detection FIFO alarm (pointer collision). When this FIFO address counters remain unchanged after pointer collision until external microcontroller intervenes. reset value PLL_INV Phase Detector Setting When this L64777 exchanges reference feedback inputs frequency phase detector. When this exchange takes place. reset value Interleaver When this L64777 switches interleaver after reset initializes with values (not with incoming data stream). interleaver resumes normal operation soon first sequence start from SSTARTIN (pin comes data stream. This setting useful getting well-defined chip output sequence. When this L64777 uses interleaver DVB-compliant mode input data stream. reset value FIFO When this L64777 switches FIFO input stage clocks input data stream through three internal registers from ICLK OCLK domain. When this L64777 uses normal FIFO processing delay. reset value This mode requires ICLK exactly same signal OCLK. must connect these pins each other. Differential Encoding When this L64777 switches differential encoding off. When this L64777 encodes according standard. reset value
IRAM_OFF
FIFO_OFF
Note:
DIFF_OFF
Group General-Purpose Registers
MAP_OFF
Mapping When this L64777 stops mapping. When this L64777 uses DVB-compliant mapping. reset value Oscillator Amplitude This controls amplitude on-chip oscillator. When this L64777 low-power mode with higher jitter. When this L64777 high-power mode with lower jitter. normal operation, this Reserved This reserved.
AMPL
4.1.8 Registers
ICNT_O
ICNT_O
Reserved This reserved.
Initial OCLK Value [14:0] This 15-bit initial value OCLK feedback division. reset value other bits
4.1.9 Registers
ICNT_I
ICNT_I
Reserved This reserved.
Initial ICLK Value [14:0] This 15-bit initial value ICLK reference division. reset value other bits
Register Descriptions
4.1.10 Register
UNCONST. INPUT
TRACKSTEPS
TRACKSTEPS Steps Sync [7:6] This value indicates number steps acquire synchronization declare loss sync sync pattern missing this number events: 0b00 0b01 0b11 reset value 0b00. UNCONST. INPUT Unconstrained Input default setting this which indicates that frame structure with sync byte required after every (block length bytes. this data stream accepted. reset value Code Bytes [4:0] This number bytes inserted code each sync block. value there modification incoming data stream. maximum value bytes insert. This control generates gaps incoming stream code insertion. each block, readout FIFO stops specified number bytes. This determines value FDEL (Register parameter determines number bytes inserted into symbol stream, read from FIFO. These bytes come from encoder; thus, setting must proprietary mode). reset value 0b10000.
Group General-Purpose Registers
NCO-Related Registers
4.2.1 Register
SYNCOK SYNCOK _STORE
FIFO_ALARM MASK_SYNC MASK_FIFO ERF_STORE NCO_EVENT MASK_ERF _STORE _ALARM
SYNCOK
State SYNCOK This value reflects actual state SYNCOK pin. This signal slow enough sampled external microcontroller. When this sync achieved. When this sync achieved. reset value
SYNCOK_STORE This read-only faulty SYNCOK condition detected since last read. this indicates that sync lock status continues positive. reset value FIFO_ALARM_STORE This read-only FIFO alarm condition detected since last read. this FIFO alarm condition detected. reset value ERF_STORE Error Flag Store This read-only error flag inserted since last read. this error flag inserted. reset value NCO_EVENT this measurement complete AUTO ACQUISITION terminated. reset value Error Flag Mask this error flag insertion MPEG transport packet does generate interrupt. this error flag insertion does generate interrupt. reset value
MASK_ERF
4-10
Register Descriptions
MASK_SYNCOK this missing SYNCOK does generate interrupt. this missing SYNCOK generates interrupt. reset value MASK_FIFO_ALARM this FIFO alarm (pointer collision) does generate interrupt. this FIFO alarm (pointer collision) generates interrupt. reset value
4.2.2 Register
BELOW_ THRES MEASUREMENT_ DONE STEP_ UPDATE AUTO_ACQUI_ RUNNING ACQ_STATE
Reserved This reserved.
BELOW_THRES FIFO CONTENT THRESHOLD When this virtual FIFO content below equal threshold programmed Register During AUTO_ACQUISITION, threshold dynamically changed. reset value MEASUREMENT_DONE this indicates that measurement data gained during byte clock probe valid that measurement complete. reset value STEP_UPDATE this indicates step update since last reading register. This relevant only during acquisition mode. reset value AUTO_ACQUI_RUNNING this indicates that internal frequency acquisition running. reset value ACQ_STATE
Internal Acquisition State [2:0] This indicates many auto acquisition loops have taken place since initiation auto acquisition mode. reference duration length ACQ_STATE input packets, threshold divided ACQ_STATE times. reset value 0b111.
NCO-Related Registers
4-11
4.2.3 Register
START_ MEASUREMENT FIFO_INT
AUTO_ ENABLE_ MASK_NCO_ MASK_ACQ_ EN_PHASE_ ACUISITION NCO_LOOP LOOP
Reserved This reserved.
START_MEASUREMENT transition from 0-to-1 starts measurement byte clock connected ICLK input. MEASUREMENT_ DONE status register (13) indicates measurement. reset value ENABLE_NCO_ LOOP Setting this allows step update loop based FIFO fullness. REF_DUR parameter adjust update frequency. reset value MASK_NCO_IRQ Setting this enables interrupt MEASUREMENT_DONE event. Even case disabled interrupt, status indicated correctly. reset value AUTO_ACQUISITION_ON 1-to-0 transition this starts internal procedure regulate frequency. reset value Setting this activates autoacquisition mode. MASK_ACQ_IRQ this transition from AUTO_ACQUI_RUNNING register causes interrupt. interrupt visible NCO_EVENT register clears upon reading register reset value EN_PHASE_LOOP Setting this enables phase acquisition loop, after Autofrequency Acquisition completed mode operation. reset value
4-12
Register Descriptions
FIFO_INT
FIFO Interrupt This enables generation interrupt response FIFO alarm. reset value
4.2.4 Register
TEST
TEST
Reserved Test [7:0] This register reserved Logic production testing; each field must zero. reset value
4.2.5 Registers
INIT_STEP
INIT_STEP
[23:0] This value initial step parameter. loaded into when most significant portion written. These NCO-related register fields; they used only Mode. Bits reset other bits reset
4.2.6 Registers
NCO_GAIN
NCO_GAIN
Loop Bandwidth Adjustment [15:0] L64777 this parameter adjust loop bandwidth. value becomes valid writing most significant portion. These NCO-related register fields; they used only Mode reset other bits reset
NCO-Related Registers
4-13
4.2.7 Registers
REF_DUR
REF_DUR
Duration Between Step Updates [15:0] This parameter determines duration between step updates multiples sync length. These NCO-related register fields; they used only Mode resets other bits reset
4.2.8 Registers
PROB_DUR
PROB_DUR
Byte Clock Duration [15:0] This parameter determines duration byte clock measurement units ICLK cycles. These NCO-related register fields; they used only Mode reset value
4.2.9 Register
N_PCLK
N_PCLK
PCLK Cycles [7:0], This number PCLK cycles during ICLK byte clock. value this register valid only MEASUREMENT_DONE control register set. These NCO-related register fields; they used only Mode reset value
4.2.10 Registers
NM_COUNT
NM_COUNT
[23:0] This value number cycles found within duration PCLK cycles. value this
4-14
Register Descriptions
register valid only MEASUREMENT_DONE control register set. These NCO-related register fields; they used only Mode reset value
4.2.11 Registers
N_COUNT
N_COUNT
ICLK Cycles [23:0] This value number ICLK cycles found within duration PCLK cycles. value this register valid only MEASUREMENT_DONE control register set. These NCO-related register fields; they used only Mode reset value
4.2.12 Registers
NP_COUNT
NP_COUNT
[23:0] This value number ICLK cycles found within duration PCLK cycles. value this register valid only MEASUREMENT_DONE control register set. These NCO-related register fields; they used only Mode reset value
4.2.13 Registers
CUR_STEP
CUR_STEP
Current Loop Step [23:0] This value indicates current loop step. differs from programmed update step autoacquisition enabled. registers read-only. These NCO-related register fields; they used only Mode reset value
NCO-Related Registers
4-15
4.2.14 Registers
CUR_UPD
CUR_UPD
Current Loop Update Step [15:0] This value indicates current loop update step. differs from programmed update step autoacquisition enabled. registers read-only. These NCO-related register fields; they used only Mode reset value
4.2.15 Register
FIFO_FULL
FIFO_FULL
FIFO Fullness Indicator [7:0] This value sign representation virtual FIFO fullness used loop regulation. These NCO-related register fields; they used only Mode reset value
4.2.16 Register
PH_GAIN
PH_GAIN
Phase Regulation Gain [7:0] This value sets gain used during phase regulation. real value applied multiplied four. These NCO-related register fields; they used only Mode reset value 0b0001 0000.
4-16
Register Descriptions
4.2.17 Register
EXT_GAP
EXT_GAP
Bytes [7:0] This value indicates number bytes applied input. These NCO-related register fields; they used only Mode reset value 0b0100 0110.
4.2.18 Register
THRESHOLD
THRESHOLD FIFO Measurement Threshold [7:0] This value sets threshold virtual FIFO measurement, which used initial value autoacquisition. These NCO-related register fields; they used only Mode reset value 0b0111 0011 Table shows reset values register fields. Table
Bit7
Reset Values Register Fields
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
NCO-Related Registers
4-17
Table
Bit7
Reset Values Register Fields (Cont.)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
4-18
Register Descriptions
Chapter Signals
This chapter defines signals L64777. consists following sections:
Section 5.1, "Overview," page Section 5.2, "MPEG Transport Stream Multiplexer Signals," page Section 5.3, "Status Information Signals," page Section 5.4, "Test Signals," page Section 5.5, "Control Signals," page Section 5.6, "External Signals," page Section 5.7, "Analog Signals," page Section 5.8, "Serial Microprocessor Interface Signals," page
Overview
Figure shows L64777 interface signals their respective groupings. Within each category, signals described alphabetical order signal mnemonic.
L64777DVB Modulator
Figure
Logic Symbol L64777
Serial Microprocessor Interface SB_BASE[1:0]
INT_n
DIN[7:0] DVALIDIN ERRORIN MPEG FSTARTIN ICLK SCLK SSTARTIN L64777 Modulator
AVDD1 AVDD2 AVSS1 AVSS2 COMP1 COMP2 IREF1 IREF2 QAM_I QAM_IN QAM_Q QAM_QN VDDX_I VDDX_Q VREF_I VREF_Q
Analog
DIG_I[9:0] DIG_Q[9:0] FIFOALARM FIRSTOUT FSTARTOUT SYNCOK TESTPINS[11:0]
Status Information Test
PLL_MODE[1:0]
OCLK
PCLK
Control Signals
External Signals
Signals
PLL_OUT_CS
RESET_n
MPEG Transport Stream Multiplexer Signals
DIN[7:0] Modulator Parallel/Serial Data Input Serial data enters L64777 DIN[0]; parallel data enters DIN[7:0]. modulator samples DIN[7:0] positive edge ICLK. DIN[7:0] input accepts data with number invalid bits between. modulator disregards invalid bits bytes does take them into input FIFO. Clock Enable Input Input When DVALIDIN active (HIGH), L64777 accepts data from DIN[7:0] continuous basis. When DVALIDIN LOW, data input internal FIFO internal data processing stops, encoder does accept input from DIN[7:0] pins. DVALIDIN functions independently modulator. Error Detection Flag Input ERRORIN asserted flag uncorrectable errors. L64777 checks ERRORIN status first frame; then, required (HIGH error bit), copies value that MPEG error-indication bit. External Sync Input Input FSTARTIN asserted mark beginning MPEG transport packet hardwired signal. incoming bitstream contains unique sync words, this pulse must applied L64777. L64777 forces synchronization with FSTARTIN pulses into chip; does flywheel-stabilize synchronization sync word detection mode. sync insertion mode, L64777 regenerates DVB-defined sync information inserts into Modulator. Modulator Input Clock Input ICLK positive-edge-triggered clock. L64777 clocks DIN[7:0], DVALIDIN, ERRORIN, FSTARTIN SSTARTIN rising edge ICLK. ICLK either byte clock clock, depending control register (Register setup parallel/serial mode.
DVALIDIN
ERRORIN
FSTARTIN
ICLK
MPEG Transport Stream Multiplexer Signals
SCLK
Modulator Symbol Clock Output Output SCLK clock output synchronous internally processed symbols bytes; identical OCLK/4. L64777 uses SCLK determine phase Nyquist filter output. rising edge SCLK followed Phase falling edge transition Phase Phase 4-fold oversampling mode. Sync Sequence Start Input SSTARTIN asserted mark beginning new, fully reset sequence hardwired signal. L64777 evaluates SSTARTIN negative slope restarts internal sequences next Block/Frame start following negative SSTARTIN slope. SSTARTIN applied, internal sequences free after reset.
SSTARTIN
Status Information Signals
DIG_I[9:0] Digital Component Output This port provides modulator I-component output digital format. Depending mode, either OCLK PCLK related clock. Digital Component Output This port provides modulator Q-component output digital format. Depending mode, either OCLK PCLK related clock. FIFO Collision Detected Output this alarm occurs, FIFO control detected equal pointers read write access. detected collision most probably indicates unlocked external PLL-VCO circuitry. L64777 synchronizes this signal with SCLK-driven flip-flops output. First Block Sequence Output FIRSTOUT occurs together with FSTARTOUT indicates head sync block that just-reset sequences, controlled SSTARTIN. FIRSTOUT acceptance SSTARTIN negative slope delayed internal processing modules.
DIG_Q[9:0]
FIFOALARM
FIRSTOUT
Signals
FSTARTOUT Frame Start Output Output FSTARTOUT asserted during first symbol every sync frame. width FSTARTOUT reflects number bytes that parameter inserts. one-cycle width indicates inserted gaps; width means inserted bytes Reed-Solomon gap. FSTARTOUT applied only sync word detection mode. FSTARTIN pulses force synchronization, FSTARTOUT constantly LOW. SYNCOK SYNC Detection/Phase Monitoring Output internal sync mode, this indicates undisturbed synchronization status when HIGH. This signal asserted when number track steps required synchronization fulfilled. FSTARTIN pulses force synchronization, SYNCOK constantly LOW.
Test Signals
FTMODE[2:0] Functional Test These must tied IDDTN[3] NT_OUT[4] Test Mode IDDTN production test pin. Nand Tree Output NT_OUT production test pin. Input Input Output
SCAN_ENABLE[5] Scan Enable This enables scan chain shift. TNn[11]
Input
Test Output Enable Input switches 3-state buffers high-impedance mode testing. Test Reset Reset JTAG unit. Test Mode Select selects JTAG unit test mode. Test Data Output JTAG unit data output. Input Input Output
TRSTn[10] TMS[9] TDO[8]
Test Signals
TDI[7] TCK[6]
Test Data Input JTAG unit data input. Test Mode Clock JTAG test mode clock.
Input Input
Control Signals
OCLK Encoder Out/Processing Clock Bidirectional OCLK positive-edge-triggered clock. L64777 internally processes data based fraction OCLK (for example: scrambler, interleaver, Reed-Solomon encoder) references data outputs FSTARTOUT) OCLK. Input
PLL_MODE[1:0] Select Mode select mode: 0b00 0b01 external usage 0b11 usage RESET_n
Reset Input This resets internal data paths. Reset timing asynchronous device clocks. Reset affects configuration registers filter coefficients, which must downloaded again after reset.
External Signals
PCLK Processing Clock: Mode Input PCLK output L64724 provides this clock, which drives digital signal processing interpolation NCO. When using Mode leave this open.
PLL_OUT_CS Current Source 3-State Output This charge pump external pass control frequency. comparator frequency- phase-sensitive. normally 3-state level drives positive negative current, required. Depending configuration, current source inverted.
Signals
Analog Signals
AVDD1 Analog Input: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Analog Input: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Analog Input: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Analog Input: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Compensation Output: Comp. Analog Output usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Compensation Output: Comp. Analog Output usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Reference Current: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Reference Current: Component Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Symbol Modulation Analog Output QAM_I positive differential analog in-phase output signal modulator.
AVDD2
AVSS1
AVSS2
COMP1
COMP2
IREF1
IREF2
QAM_I
Analog Signals
QAM_IN
Symbol Modulation Inverted Analog Output QAM_IN corresponding inverted differential part QAM_I. Symbol Modulation Analog Output QAM_Q positive differential analog quadrature output signal modulator. Inverted Differential QAM_Q Analog Output QAM_QN corresponding inverted differential part QAM_Q. Isolated Power: Digital-to-Analog Converter, Channel usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Isolated Power: Digital-to-Analalog Converter, Channel usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Reference Voltage Input: Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998). Reference Voltage Input: Analog Input usage value, Logic datasheet G10®-p CW900100 10-bit Direct Digital Synthesis Digitalto-Analog Converter (September 1998).
QAM_Q
QAM_QN
VDDX_I
VDDX_Q
VREF_I
VREF_Q
Serial Microprocessor Interface Signals
INT_n Interrupt Request Output L64777 asserts INT_n when interrupt enabled interrupt condition occurs. INT_n open drain output that requires external pull-up resistor operation.
Signals
SB_BASE[1:0] Serial Base Address Input external microprocessor must apply these signals static signals device because they determine LSBs serial base address. Serial Clock Line Input conjunction with SDA, controls microprocessor interface according protocol described Appendix Serial Data Access Bidirectional conjunction with SCL, controls microprocessor interface according protocol described Appendix
Serial Microprocessor Interface Signals
5-10
Signals
Chapter Specifications
This chapter provides information about electrical ratings, pins, packaging L64777. consists following sections:
Section 6.1, "AC/DC Specifications," page Section 6.2, "Pin Descriptions Lists," page Section 6.3, "Package Pinout," page 6-10
AC/DC Specifications
This section lists electrical requirements, provides timing characteristics, shows timing diagrams, lists timing values L64777 decoder.
6.1.1 Electrical Ratings
tables this section specify electrical requirements L64777 decoder. Table provides L64777 absolute maximum electrical temperature ratings. Table provides L64777 recommended operating conditions. Table lists characteristics L64777.
L64777 Modulator
Table
Symbol TSTG
L64777 Absolute Maximum Ratings
Parameter Supply LVTTL Input Voltage Compatible Inputs Input Current Storage Temperature Range (Plastic) Operating Junction Temperature Range Limits -0.3 -1.0 -1.0 +150 +125 Unit
Table
Symbol
L64777 Recommended Operating Conditions
Parameter Supply Ambient Temperature Limits Unit
3.14 3.45
When studying values Table 6.3, note that L64777 follows Logic G10-p process, which characterized 0.35-micron gate length. Table L64777 Characteristics
Condition1 3.14 -4.0 Max, VOUT 3.45 Units
Symbol Parameter Supply Voltage Input Voltage Input Voltage HIGH Output Voltage HIGH Output Voltage Current 3-State Leakage w/Pulldown
Specifications
Table
L64777 Characteristics (Cont.)
Condition1 Max, Max, Max, ICLK max, MODE PCLK -215 -215 -384 -384 Units
Symbol Parameter Input Current Leakage Input Current Leakage w/Pullup Input Current Leakage w/Pulldown Quiescent Supply Current Dynamic Supply Current
Specified ambient temperature over specified range.
6.1.2 Timing Diagrams L64777
Figure illustrates input timing. Figure Input Timing
ICLK Inputs
Figure illustrates reset timing L64777. Figure L64777 RESET Timing Diagram
RESET
Figure illustrates 3-state delay timing L64777 bus.
AC/DC Specifications
Figure
L64777 3-state Delay Timing
DATA
numbers column Table refer timing parameters preceding figures. parameters this table apply output load Table
L64777 Preliminary Timing Parameters
Description Clock Cycle OCLK Clock Pulse Width HIGH OCLK Clock Pulse Width OCLK Clock Cycle ICLK Clock Pulse Width HIGH ICLK Clock Pulse Width ICLK Input Setup Time ICLK Input Hold ICLK Reset Pulse Width HIGH Wake-up Time after RESET (used initialization during microprocessor configuration access) 18.5 1280 Unit ICLK cycles with DVALIDIN HIGH OCLK cycles
Parameter tCYCLE tPWH tPWL tI_CYCLE tI_PWH tI_PWL tI_S tI_H tRWH
2560 tTDLY Delay from
Specifications
Descriptions Lists
following subsections provide descriptions electrical pins, well numerical alphabetic listings L64777 pins.
6.2.1 L64777 Electrical Descriptions
Table summarizes electrical properties pins L64777. table provides signal types both output input pins, drive capacity outputs. Table L64777 Description Summary
Drive (mA) Active HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
Mnemonic AVDD1 AVDD2 AVSS1 AVSS2 COMP1 COMP2 DIG_I[9:0] DIG_Q[9:0] DIN[7:0] DVALIDIN ERRORIN FIFOALARM FIRSTOUT FSTARTIN FSTARTOUT
Description Supply Supply Analog Supply Supply Compensation Output Compensation Output Digital Output Digital Output Data Input Data Enable Input Error Flag Input FIFO Alarm Output Beginning Sequence Frame Start Input Frame Start Output
Type Analog Input Analog Input Analog Input Analog Input Analog Output Analog Output Output Output Input Input Input Output Output Input Output
Descriptions Lists
Table
L64777 Description Summary (Cont.)
Drive (mA) Active HIGH LOW/ HIGH HIGH LOW/ HIGH HIGH HIGH 3-state HIGH
Mnemonic FTMODE[2:0] ICLK IDDTN INT_n IREF1 IREF2 NT_OUT OCLK PCLK PLL_MODE[1:0] PLL_OUT_CS QAM_I QAM_In QAM_Q QAM_QN RESET_n SB_BASE[1:0]
Description
Type
Functional Test Mode Input w/Pulldown Ground Input Clock Test Interrupt Request Reference Current Input Reference Current Input Nand Tree Clock Output External Clock Input Clock Input Mode Select Mode Current Source Positive Output Channel Negative Output Channel Positive Output Channel Negative Output Channel Chip Reset Serial Base Address Selector Analog Input Input w/Pullup Open Drain, Driving Analog Input Analog Input Output Bidirectional input Input w/Pulldown 3-state Current Source Analog Output Analog Output Analog Output Analog Output Input Input w/Pulldown
Specifications
Table
L64777 Description Summary (Cont.)
Drive (mA) Active HIGH HIGH LOW/ HIGH Opendrain HIGH HIGH HIGH HIGH HIGH
Mnemonic SCAN_ENABLE SCLK SSTARTIN SYNCOK TRSTn VDDX_I VDDX_Q VREF_I VREF_Q
Description Scan Enable Serial Control Line
Type Input w/Pulldown Input V-tolerant)
Symbol Clock Output Output Serial Data Access Bidirectional V-tolerant)
Sequence Start Input Input Sync Detection Flag JTAG Test Clock JTAG Test Data JTAG Test Data JTAG Test Mode Select 3-State Mode JTAG Test Reset Supply Digital Part Supply Digital Part Voltage Reference Voltage Reference Output Input w/Pulldown Input w/Pulldown Output Input w/Pulldown Input w/Pullup Input w/Pulldown Analog Input Analog Input Analog Analog
Also compatible.
Descriptions Lists
6.2.2 Numerical List L64777
Table
Signal QAM_I QAM_IN AVDD1 IREF1 COMP1 VREF_I AVSS VDDX_I VDDX_Q AVSS2 VREF_Q COMP2 IREF2 AVDD2 QAM_QN QAM_Q PLL_OUT_CS
L64777 Numerical List
Signal PLL_MODE.0 PLL_MODE.1 IDDTN RESET_N DIG_Q.0 DIG_Q.1 DIG_Q.2 DIG_Q.3 DIG_Q.4 DIG_Q.5 DIG_Q.6 DIG_Q.7 DIG_Q.8 DIG_Q.9 OCLK Signal TRSTN INT_N FIFOALARM FIRSTOUT SYNCOK FSTARTOUT DIN.7 DIN.6 DIN.5 DIN.4 ICLK DIN.3 DIN.2 DIN.1 DIN.0 DVALIDIN ERRORIN FSTARTIN SSTARTIN Signal NT_OUT SCAN_ENABLE FTMODE.0 FTMODE.1 FTMODE.2 SB_BASE.0 SB+BASE.1 PCLK SCLK DIG_I.0 DIG_I.1 DIG_I.2 DIG_I.3 DIG_I.4 DIG_I.5 DIG_I.6 DIG_I.7 DIG_I.8 DIG_I.9
pins connected.
Specifications
6.2.3 Alphabetic List L64777
Table
Signal AVDD1 AVDD2 AVSS AVSS2 COMP1 COMP2 DIG_I.0 DIG_I.1 DIG_I.2 DIG_I.3 DIG_I.4 DIG_I.5 DIG_I.6 DIG_I.7 DIG_I.8 DIG_I.9 DIG_Q.0 DIG_Q.1 DIG_Q.2 DIG_Q.3 DIG_Q.4 DIG_Q.5 DIG_Q.6 DIG_Q.7 DIG_Q.8 DIG_Q.9 DIN.0 DIN.1 DIN.2 DIN.3
L64777 Alphabetical List
Signal DIN.4 DIN.5 DIN.6 DIN.7 DVALIDIN ERRORIN FIFOALARM FIRSTOUT FSTARTIN FSTARTOUT FTMODE.0 FTMODE.1 FTMODE.2 ICLK IDDTN INT_N IREF1 IREF2 NT_OUT OCLK PCLK PLL_MODE.0 Signal PLL_MODE.132 PLL_OUT_CS QAM_I QAM_IN QAM_Q QAM_QN RESET_N SB+BASE.1 SB_BASE.0 SCAN_ENABLE SCLK SSTARTIN SYNCOK TRSTN Signal VDD77 VDD86 VDD91 VDDX_I VDDX_Q VREF_I VREF_Q
pins connected.
Descriptions Lists
Package Pinout
Figure Package 120-Pin PQFP Pinout
DIG_I.9 DIG_I.8 DIG_I.7 DIG_I.6 DIG_I.5 DIG_I.4 DIG_I.3 DIG_I.2 DIG_I.1 DIG_I.0 SCLK PCLK SB_BASE.1 SB_BASE.0 FTMODE.2 FTMODE.1 FTMODE.0 SCAN_ENABLE NT_OUT
6-10
PLL_MODE.0 PLL_MODE.1 IDDTN RESET_N DIG_Q.0 DIG_Q.1 DIG_Q.2 DIG_Q.3 DIG_Q.4 DIG_Q.5 DIG_Q.6 DIG_Q.7 DIG_Q.8 DIG_Q.9 OCLK
QAM_I QAM_IN AVDD1 IREF1 COMP1 VREF_I AVSS1 VDDX_I VDDX_Q AVSS2 VREF_Q COMP2 IREF2 AVDD2 QAM_QN QAM_Q PLL_OUT_CS
View L64777
SSTARTIN FSTARTIN ERRORIN DVALIDIN DIN.0 DIN.1 DIN.2 DIN.3 ICLK DIN.4 DIN.5 DIN.6 DIN.7 FSTARTOUT SYNCOK FIRSTOUT FIFOALARM INT_N TRSTN
Specifications
Figure provides mechanical drawing 120-pin PQFP L64777. Figure 120-Pin PQFP (PE) Mechanical Drawing
Important:
This drawing latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
Package Pinout
6-11
Figure
120-Pin PQFP (PE) Mechanical Drawing (Cont.)
Important:
This drawing latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
6-12
Specifications
Appendix Programming L64777 Serial Host Interface Mode
This appendix discusses program L64777 internal registers data tables serial host interface mode. This chapter intended primarily system programmers developing software drivers using serial bus. This appendix contains following sections:
Section A.1, "Serial Protocol Overview," page A-1, provides high-level overview serial protocol. Section A.2, "Programming Slave Address Using Serial Interface," page A-4, shows slave address formed transmitted. Section A.3, "Write Cycle Using Serial Interface," page A-4, shows example serial write cycle. Section A.4, "Read Cycle Using Serial Interface," page A-5, shows example serial read cycle. Section A.5, "Limitations," page A-7, shows limitations L64777
Serial Protocol Overview
multimaster serial interface 1-bit lines-SDA (Serial Data) (Serial Clock)-that connected shown Figure A.1. External pullup resistors hold logic value when operation.
L64777 Modulator
Figure
Quick Overview Serial
Serial Compliant Device
Serial Compliant Device
serial interface, data transfers synchronized serial clock input line. serial data clock have maximum frequency kHz. pins SB_BASE[1:0] input LSB's slave address required serial protocol. slave address definition shown below:
7-Bit Slave Address L64777 Serial SB_BASE1 SB_BASE0
master always generates clock cycle start stop conditions. Figure gives overview read write cycles using serial protocol.
Programming L64777 Serial Host Interface Mode
Figure
Start Condition
Serial Write/Read Cycle
Stop Condition
Write Cycle
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Master-Transmitter, Slave-Receiver (Master transmits slave address)
Cycle: Slave
Master-Transmitter, Slave-Receiver (Master transmits data slave)
Cycle: Slave
Read Cycle (burst)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
Master-Transmitter, Slave-Receiver (Master transmits slave address)
Cycle: Slave
Master-Receiver, Slave-Transmitter (Slave transmits data master)
Cycle: Master
Single-Read Cycle
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Master-Transmitter, Slave-Receiver (Master transmits slave address)
Cycle: Slave
Master-Receiver, Slave-Transmitter (Slave transmits data master)
Cycle: Master
Stop Condition
Start Condition: master (which drives SCL) indicates start cycle pulling when HIGH. Stop Condition: master (which drives SCL) indicates cycle releasing HIGH when HIGH. Data Transfer: data changes line happen only when clock LOW, except special cases outlined above indicate cycle Start/Stop. Acknowledge: receiver always generates acknowledge. case single read, master-receiver does generate that generate Stop condition indicated above).
Serial Protocol Overview
Programming Slave Address Using Serial Interface
general call (master does start condition followed eight 0's) address used address every device serial bus. device that requires information supplied through this general call structure must acknowledge cycle. second byte following meaning when (see Figure A.3): 0b0000 0110 (0x6): Reset write programmable part slave address hardware from SB_BASE pins. General Call Structure
Figure
General Call Address. Start Condition Acknowledge Cycle
Write Cycle Using Serial Interface
Figure shows timing burst, single-write cycle. following cycles must take place write cycle: master starts cycle with start condition. master transmits 7-bit slave address. master transmits (the bit) indicate write cycle. addressed slave acknowledges reception slave address driving cycle. master sends 8-bit Group address (0x0) indicate that Address Programming register (APR) loaded. (The master accesses Group only load APR.) master then sends 8-bit data, which initializes address pointer register (APR0).
Programming L64777 Serial Host Interface Mode
master generates another start condition. master repeats steps address appropriate group write more data bytes. master terminates cycle issuing stop condition. Figure
Start Condition
Burst Write Slave (Master-Transmitter, Slave-Receiver)
Start Condition Stop Condition
(Slave) (Slave) (Slave) (Slave) (Slave) (Slave) (Slave)
7-bit Slave Address
8-bit Group Address 8-bit Data
7-bit Slave Address
8-bit Group Address 8-bit Data
8-bit Data
Read Cycle Using Serial Interface
Figure shows timing burst, single read cycle. following cycles must take place read cycle: master starts cycle issuing start condition. master transmits 7-bit slave address. master sets indicate write cycle. addressed slave acknowledges reception slave address driving cycle. master sends 8-bit Group address (0x0) indicate that loaded. (The master accesses Group only load APR.)
Read Cycle Using Serial Interface
master then sends 8-bit data, which initializes base pointer (APR0/1). master repeats start condition. master transmits 7-bit slave address. master sets indicate write cycle. addressed slave acknowledges reception driving cycle. master transmits number group that wishes read, which slave acknowledges. master issues another start condition. master transmits 7-bit slave address. master sets indicate read cycle. slave drives acknowledge. slave starts transmitting data, first. master provide acknowledge driving during cycle. case single read, master does drive during cycle after reception first byte. slave responds this relinquishing control waiting master issue stop condition. burst reads, master drives each byte receives during cycle, except last byte. master terminates cycle issuing stop condition.
Programming L64777 Serial Host Interface Mode
Figure
Start Condition
Single Read from Slave
Start Condition Start Condition Stop Condition
(Slave) (Slave) (Slave) (Slave) (Slave) (Slave) (Master)
7-bit Slave Address
8-bit Group Address 8-bit Data
7-bit Slave Address
8-bit Group Address
7-bit Slave Address 8-bit Data
Limitations
access internal registers either bursts single-byte operation. must access status registers single-byte read write. After stop condition, user must program desired next access address. rely expected location after last access.
Limitations
Programming L64777 Serial Host Interface Mode
Appendix Divider Settings L64724/34 Connection
This appendix lists divider settings typical applications. also describes L64777 connection L64724 contains following sections:
Section B.1, "Overview," page Section B.2, "PLL Driver Settings Typical Applications," page Section B.3, "Connecting L64777 Logic L64724," page
Overview
modulator last stage digital CATV transmitter system. Figure shows block diagram typical CATV transmitter. Figure
Video Source
CATV Block Diagram
MPEG-2 Transport Decoder Modulator Mixer Power Amplifier Source CATV
Satellite Receiver Antenna
Modulator
Mixer Power Amplifier Source
CATV
L64777 Modulator
modulator programmed configuration operational modes through Serial Microprocessor interface. L64777 synchronizes with input data, derives operating clock (based operational mode), carries clock conversion with appropriate FIFO management, inserts sync error flags, performs scrambling, encoding, convolutional interleaving. Signal frequencies symbol clock (SCLK) operating clock (OCLK) outputs L64777 indicate appropriate locking internal timing system with respect incoming data rates when input from MPEG source L64724 satellite receiver. relationship among SCLK, OCLK, input data rate described following subsections. same serial host controls both L64724 L64777, hold L64777 reset until L64724 been programmed.
Driver Settings Typical Applications
Table lists L64777's driver settings Mode Table Typical Settings CNT_I CNT_O
Frequency Phase Comparator 0.92 0.87 0.87 0.86
ICLK 7.32 5.17 4.33 3.42
mode
rate Mbyte/s /Mbit/s 6.75/54.0 4.76/38.1 3.99/31.9 3.15/25.2
CNT_I CNT_O (decimal) (decimal)
OCLK 29.30 27.56 27.69 27.34
Note that above settings assume block length bytes with invalid bytes effective input rate attained, considering number cycles with valid data.
Divider Settings L64724/34 Connection
Connecting L64777 Logic L64724
L64777 connected satellite receiver device L64724. L64724 uses interpolation-based digital receiver. Thus, outputs transport-rate byte clock with granularity L64724 internal processing clock, PCLK. Logic L64724 Satellite Receiver Technical Manual (April 2000). digital generates this byte clock, which consists clock cycles having length PCLK cycles. Usually, rate byte clock exactly that received transport stream rate. ease interfacing, L64724 supports modes byte-clock generation. Mode synchronous parallel interface (SPI) best suited interconnection with L64777. this mode, L64724 outputs 204-byte clock cycles, together with indication valid data bytes. Connect byte clock ICLK input L64777, reference generating output sampling rate (OCLK); connect PCLK output L64724 PCLK input L64777. keep loop bandwidth possible, L64777 provides digital interpolation scheme lock byte clock mode Figure provides simplified illustration signals between L64724 L64777. Figure
L64724 PCLK
Signals between L64724 L64777
L64777 PCLK
BCLKOUT
ICLK
DVALIDOUT
DVALIDIN
CO(7:0)
DIN(7:0)
Connecting L64777 Logic L64724
When input L64777 from L64724 satellite selected center frequency baud rate, parameters programmed into L64777 are: Operational Mode mode (Mode Block Length bytes bytes I-Counter (0x6) O-Counter (0x20) After synchronization: OCLK Baud rate oversampling 1/(symbol size) SCLK OCLK/4 where: oversampling symbol size mode (log level base Note that PLL_SET (Register must before downloading counter parameters, must cleared after completion. This applies Mode programming.
Divider Settings L64724/34 Connection
Appendix Monitoring Device Internal Signals
programming test register (14) allows monitoring device's internal signals. Depending programming test register bits (Register 15), following signals observable DIG_Q[9:0] pins: TEST[3:0] 0b0000: 0b0001: 0b0010: 0b0011: 0b0100: 0b0101: 0b0110: 0b0111: 0b1000: 0b1001: 0b1010: 0b1011: 0b1100: 0b1101: 0b1110: 0b1111: test.4: test.5: test.6: Nyquist filter output interpolator out
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