Addendum Number A000692 Product Code L64364 ATMizer ATM-SAR Chip Revis

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Addendum Number A000692 Product Code L64364 ATMizer ATM-SAR Chip Revis

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L64364 ATMizer® ATM-SAR Chip Addendum
Addendum Number A000692 Product Code L64364 ATMizer ATM-SAR Chip Revision Date Code Order Number Manual R14008 This addendum contains changes L64364 ATMizer ATM-SAR Chip Technical Manual LX100 version. LX100 operates maximum frequency MHz. LX100 functionally same previous version (LX80), however, some timing values change when SYS_CLK input MHz. following tables show timing changes.
Copyright 2000 Logic Corporation. rights reserved.
Table
Secondary Timing
LX80 14.7 12.8 LX100 Units
Signal Timing SB_CLKO period SB_CLKO duty cycle (SYS_PLL SB_CLKO duty cycle (SYS_PLL SB_CLKO phase delay (SYS_CLK_PCI SYS_PLL SB_CLKO phase delay (SYS_CLK_PCI SYS_PLL SB_D[31:0] input setup time SB_D[31:0] input hold time SB_D[31:0] output valid SB_D[31:0] output hold time SB_D[31:0] output float SB_A[21:2] output valid SB_A[21:2] output hold time SB_A[21:2] output float SB_WEn[3:0] output valid SB_WEn[3:0] output hold time SB_WEn[3:0] output float SB_OEn[3:0] output valid SB_OEn[3:0] output hold time SB_OEn[3:0] output float (Sheet
Reference Clock PCI_CLK SYS_CLK SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO
LX80 12.5
LX100 10.0
L64364 ATMizer ATM-SAR Chip Addendum
Table
Secondary Timing (Cont.)
LX80 10.5 LX100 Units
Signal Timing SB_PCSn[4:0] output valid SB_PCSn[4:0] output hold time SB_PCSn[4:0] output float SB_REQn input setup time SB_REQn input hold time SB_GNTn output valid SB_RDYn setup time1 SB_RDYn hold time1
Reference Clock SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO SB_CLKO
LX80
LX100
(Sheet While SB_RDYn asynchronous input, these times provided choose make inputs synchronous.
L64364 ATMizer ATM-SAR Chip Addendum
Table
Miscellaneous Timing
LX80 80.0 40.0 50.0 LX100 100.0 Units
Signal Timing SYS_CLK frequency (SYS_PLL SYS_CLK duty cycle (SYS_PLL SYS_CLK frequency (SYS_PLL SYS_CLK duty cycle (SYS_PLL SE_DI input setup time SE_DI input hold time SE_ACK input setup time SE_ACK input hold time JTAG_TCLK frequency JTAG_TCLK duty cycle JTAG_TDI setup time JTAG_TDI hold time JTAG_setup time JTAG_hold time JTAG_TDO output delay JTAG_TRSTn pulse width
Reference Clock SE_CLK SE_CLK SE_CLK SE_CLK JTAG_TCLK JTAG_TCLK JTAG_TCLK JTAG_TCLK JTAG_TCLK JTAG_TCLK
LX80
LX100
L64364 ATMizer ATM-SAR Chip Addendum
Table
Characteristics
Condition 3.135 4.75 -0.5 -0.5 -0.5 operation operation -214 -115 3.465 5.25 0.55 1040 Units
Symbol Parameter VILP VIHP VOLP VOHP VILS VIHS IILP IIHP Supply Voltage clamp diode voltage Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage Input Secondary Voltage Input High Secondary Voltage Output Secondary Voltage Output High Secondary Voltage Input other signals Voltage Input High other signals Voltage Output other signals Voltage Output High other signals Input current Input current pins with pull-ups Input current high Input current high pins with pull-downs 3-state leakage current Dynamic supply current
L64364 ATMizer ATM-SAR Chip Addendum
Notes
L64364 ATMizer ATM-SAR Chip Addendum
Notes
L64364 ATMizer ATM-SAR Chip Addendum
Notes
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Printed Order R14008.AD1 Doc. DB05-000058-00
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L64364 ATMizer ATM-SAR Chip Addendum

Addendum Number A000692 Product Code L64364 ATMizer ATM-SAR Chip Revis

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